A method for testing impedance performance of an internal circuit of a meter box body and related equipment

Abstract

The application is suitable for the technical field of loop impedance test, and provides a method for testing the loop impedance performance inside an electric meter box body and related equipment, which comprises the following steps: collecting synchronous current phasor, synchronous voltage phasor and pre-fault latched phasor of the electric meter box, determining the fault time and the target unit length impedance of each conductor, and calculating Kirchhoff current residual according to the synchronous current phasor; when the Kirchhoff current residual exceeds the setting value, it is determined that there is an internal fault in the electric meter box, and the contact resistance and temperature rise value of each contact point in the phase busbar and N busbar inside the electric meter box are determined to determine the internal contact point fault number; when the Kirchhoff current residual does not exceed the setting value, it is determined that there is an external fault in the electric meter box, and the external fault distance, transition resistance and fault starting angle are calculated. The application solves the technical problem of the ranging deviation introduced by the single loop in the shared PEN area in the prior art, can close-loop root-finding on the embedded processor in the electric meter box, and outputs the fault positioning result within several cycles after the fault.

Description

Technical Field

[0001] This invention relates to the field of loop impedance testing technology, and in particular to a method and related equipment for testing the internal loop impedance performance of an electric meter box. Background Technology

[0002] Low-voltage meter boxes are the end-point metering and branch line collection points of the distribution network in the transformer area. For a long time, fault location has relied on manual inspection: maintenance personnel carry clamp meters and insulation resistance meters to measure section by section and conduct contact temperature measurement on each terminal in the box one by one. On average, the inspection takes several hours, which is difficult to meet the requirements of rapid power restoration.

[0003] Existing technology transplants the single-ended impedance method for distance measurement of medium-voltage feeders to low-voltage outgoing lines. However, the length of low-voltage outgoing lines is less than 500 meters, and the conductor impedance is mainly resistance with a much lower X / R ratio than that of medium-voltage lines. Under full load, the resistance change corresponding to the temperature rise of the conductor core can reach 20%. The medium-voltage method neither corrects for this temperature rise nor uses the zero-sequence compensation coefficient based on the premise of a zero-sequence path to the ground. This is fundamentally mismatched with the actual circuit of a low-voltage TN system where the neutral point is directly grounded and the fault current returns through the N conductor or PE conductor, resulting in a large location error. Moreover, the measurement point of the existing technology is located at the beginning of the feeder, making it impossible to distinguish whether the fault occurs inside the meter box or outside the box. The deterioration of contact resistance and series arcing faults at the inlet terminals, phase busbars, N busbars, front-end wiring, and outgoing terminals inside the box are important components of low-voltage metering unit repairs. The fault current for such faults does not increase but decreases. The medium-voltage transplant method not only cannot identify these faults but also incorrectly converts them to a certain distance value outside the box. Two outgoing lines from the same meter box share the same PEN trunk line or are laid in parallel. There is a common impedance coupling between the two circuits. The existing single-circuit method does not address this, which introduces ranging deviation in the shared PEN area. Summary of the Invention

[0004] This invention provides a method and related equipment for testing the impedance performance of the internal circuit of an electric meter box. This invention solves the technical problem of ranging deviation introduced by a single circuit in a shared PEN distribution area in the prior art. It can perform closed-loop root calculation on an embedded processor in the box and output the fault location result within a few cycles after the fault.

[0005] In a first aspect, embodiments of this application provide a method for testing the internal circuit impedance performance of an electric meter box, including: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source. This yields the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, and determines the fault time and the target impedance per unit length of each conductor. Simultaneously, the Kirchhoff current residual is calculated by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor. When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault. The voltage difference phasor and the current phasor flowing through the section are extracted from each contact section of the phase bus and N bus in the meter box. The contact resistance of each contact is calculated by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. The internal contact fault number is determined by combining the temperature rise value of each contact. When the Kirchhoff current residual does not exceed the set value, it is determined to be an external fault. The external fault distance, transition resistance and fault initiation angle are calculated based on the synchronous current phasor, the synchronous voltage phasor, the pre-fault latched phasor and the target unit length impedance.

[0006] Optionally, in a first implementation of the first aspect of the present invention, the method of synchronously acquiring the incoming current, two outgoing currents, metering branch currents, phase voltages, and N-bus voltage of the meter box using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter for synchronous clock source acquisition, thereby obtaining the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, and determining the fault time and the target impedance per unit length of each conductor, while simultaneously calculating the Kirchhoff current residual by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor, includes: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage to busbar voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source, to obtain synchronous current phasors and synchronous voltage phasors. The fault time is determined based on the current mutation in the synchronous current phasor, and a full-cycle Fourier transform is performed on the steady-state cycle before the fault time to obtain the latched phasor before the fault. Based on the steady-state current RMS value in the latched phasor before the fault and the temperature measurement value of each return terminal, the initial unit length impedance of each conductor is corrected to obtain the target unit length impedance of each conductor. The Kirchhoff current residual is obtained by subtracting the sum of the incoming current in the synchronous current phasor from the sum of the two outgoing currents and the metering branch current.

[0007] Optionally, in a second implementation of the first aspect of the present invention, when the Kirchhoff current residual exceeds the set value, it is determined to be an in-box fault, and along the detection section of each contact point of the phase bus and N bus in the meter box, the voltage difference phasor and the current phasor flowing through the section are extracted. The contact resistance of each contact point is calculated by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. The in-box contact fault number is determined by combining the temperature rise value of each contact point, including: When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault and the contact resistance of each contact point corresponding to the phase bus and N bus is extracted, and the temperature rise value of each contact point is read synchronously. The contact resistance of each contact point is compared with the resistance reference value of the corresponding contact point, and the temperature rise value is compared with the temperature rise threshold. When the contact resistance is greater than the resistance reference value or the temperature rise value is greater than the temperature rise threshold, the corresponding box contact fault number is output.

[0008] Optionally, in a third implementation of the first aspect of the present invention, the step of determining an external fault when the Kirchhoff current residual does not exceed the set value, and calculating the external fault distance, transition resistance, and fault initiation angle based on the synchronization current phasor, the synchronization voltage phasor, the pre-fault latched phasor, and the target unit length impedance, includes: When the Kirchhoff current residual does not exceed the set value, it is determined to be an external fault and the fault type is determined according to the synchronous current phasor. The fault type includes single-phase, two-phase, three-phase fault, phase-PE grounding fault and N line disconnection. Calculate the fault loop impedance per unit length, the double-loop coupling impedance per unit length, and the coupling segment length based on the fault type and the target unit length impedance; Based on the quotient of the pre-fault voltage phasor and the pre-fault current phasor in the pre-fault latched phasor, the product of the unit length impedance of the fault circuit and the outgoing line arch length is subtracted to obtain the terminal equivalent load impedance. The external fault distance, transition resistance, and fault initiation angle are calculated based on the fault circuit unit length impedance, the double-loop coupling unit length impedance, the coupling section length, the end equivalent load impedance, the synchronous current phasor, and the synchronous voltage phasor.

[0009] Optionally, in a fourth implementation of the first aspect of the present invention, the calculation of the external fault distance, transition resistance, and fault initiation angle based on the fault loop unit length impedance, the double-loop coupling unit length impedance, the coupling segment length, the end equivalent load impedance, the synchronous current phasor, and the synchronous voltage phasor includes: The fault loop voltage is calculated based on the synchronous voltage phasor, the synchronous current phasor, the double-loop coupling unit length impedance, and the current fault distance and coupling segment length. Based on the fault circuit voltage, the synchronous current phasor, the fault circuit impedance per unit length, and the equivalent load impedance at the end, a quadratic equation with the fault distance as the only unknown is established, and the fault distance outside the box and the transition resistance are obtained by solving it. The fault initiation angle is calculated based on the fundamental phase of the fault phase in the pre-fault latched phasor and the fault time.

[0010] Optionally, in a fifth implementation of the first aspect of the present invention, the step of establishing a quadratic equation with the fault distance as the only unknown based on the fault circuit voltage, the synchronous current phasor, the fault circuit impedance per unit length, and the equivalent load impedance at the end, and solving for the external fault distance and transition resistance, includes: Add the product of the unit length impedance of the fault circuit and the outgoing line filing length to the equivalent load impedance at the end to obtain the total impedance at the end of the circuit; subtract the product of the outgoing line current of the fault circuit and the total impedance at the end of the circuit from the voltage of the fault circuit to obtain the auxiliary quantity of the fault branch. The voltage of the fault circuit The fault circuit output current The impedance per unit length of the fault circuit The total impedance at the end of the circuit and the auxiliary quantity of the fault branch According to the coefficient of the quadratic term coefficient of the first term constant term Establish a quadratic equation in one variable ,in The distance from the fault point to the outgoing port, The conjugate of the auxiliary quantity of the faulty branch; By performing closed-form root-finding on the quadratic equation, the external fault distance and transition resistance can be obtained.

[0011] Secondly, embodiments of this application provide a device for testing the internal circuit impedance performance of an electric meter box, comprising: The acquisition module is used to synchronously acquire the incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage of the meter box, using the N-bus sampling point as a unified potential reference and connecting it to the same multi-channel A / D for synchronous acquisition with a common clock source. This yields the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, and determines the fault time and the target impedance per unit length of each conductor. Simultaneously, the module calculates the Kirchhoff current residual by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor. The box-in-box fault location module is used to determine that when the Kirchhoff current residual exceeds the set value, it is a box-in-box fault. It also extracts the voltage difference phasor and the current phasor flowing through the segment along the detection section of each contact point of the phase bus and N bus in the meter box. It calculates the contact resistance of each contact point by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. Combined with the temperature rise value of each contact point, it determines the box-in-box contact fault number. The external fault location module is used to determine an external fault when the Kirchhoff current residual does not exceed the set value, and to calculate the external fault distance, transition resistance and fault initiation angle based on the synchronous current phasor, the synchronous voltage phasor, the fault pre-latch phasor and the target unit length impedance.

[0012] Optionally, in a first implementation of the second aspect of the present invention, the acquisition module is specifically used for: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage to busbar voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source, to obtain synchronous current phasors and synchronous voltage phasors. The fault time is determined based on the current mutation in the synchronous current phasor, and a full-cycle Fourier transform is performed on the steady-state cycle before the fault time to obtain the latched phasor before the fault. Based on the steady-state current RMS value in the latched phasor before the fault and the temperature measurement value of each return terminal, the initial unit length impedance of each conductor is corrected to obtain the target unit length impedance of each conductor. The Kirchhoff current residual is obtained by subtracting the sum of the incoming current in the synchronous current phasor from the sum of the two outgoing currents and the metering branch current.

[0013] Optionally, in a second implementation of the second aspect of the present invention, the in-box fault location module is specifically used for: When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault and the contact resistance of each contact point corresponding to the phase bus and N bus is extracted, and the temperature rise value of each contact point is read synchronously. The contact resistance of each contact point is compared with the resistance reference value of the corresponding contact point, and the temperature rise value is compared with the temperature rise threshold. When the contact resistance is greater than the resistance reference value or the temperature rise value is greater than the temperature rise threshold, the corresponding box contact fault number is output.

[0014] Optionally, in a third implementation of the second aspect of the present invention, the external fault location module further includes: The type analysis unit is used to determine an external fault when the Kirchhoff current residual does not exceed the set value, and to determine the fault type according to the synchronous current phasor. The fault types include single-phase, two-phase, three-phase faults, phase-PE grounding faults, and N-line disconnection. The first calculation unit is used to calculate the fault circuit impedance per unit length, the double-loop coupling impedance per unit length, and the coupling segment length based on the fault type and the target unit length impedance. The second calculation unit is used to subtract the product of the fault circuit unit length impedance and the outgoing line filing length from the quotient of the fault voltage phasor and the fault current phasor in the fault latched phasor to obtain the terminal equivalent load impedance. The fault analysis unit is used to calculate the external fault distance, transition resistance, and fault initiation angle based on the unit length impedance of the fault loop, the unit length impedance of the double-loop coupling, the length of the coupling section, the equivalent load impedance at the end, the synchronous current phasor, and the synchronous voltage phasor.

[0015] Optionally, in a fourth implementation of the second aspect of the present invention, the fault analysis unit is specifically used for: The fault loop voltage is calculated based on the synchronous voltage phasor, the synchronous current phasor, the double-loop coupling unit length impedance, and the current fault distance and coupling segment length. Based on the fault circuit voltage, the synchronous current phasor, the fault circuit impedance per unit length, and the equivalent load impedance at the end, a quadratic equation with the fault distance as the only unknown is established, and the fault distance outside the box and the transition resistance are obtained by solving it. The fault initiation angle is calculated based on the fundamental phase of the fault phase in the pre-fault latched phasor and the fault time.

[0016] Thirdly, embodiments of this application provide a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the steps of the above-described method for testing the internal circuit impedance performance of the meter box body.

[0017] Fourthly, embodiments of this application provide a readable storage medium storing a computer program that, when executed by a processor, implements the steps of the above-described method for testing the internal circuit impedance performance of the meter box body.

[0018] Fifthly, embodiments of this application provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps of the above-described method for testing the internal circuit impedance performance of the meter box body.

[0019] In one scheme provided by the aforementioned method and related equipment for testing the impedance performance of the internal circuit of an electric meter box, the incoming current, the two outgoing currents, and the metering branch current are all connected to the same multi-channel A / D converter for synchronous acquisition using a common clock source. This invention enables the current phasors of all branches within the box to be acquired synchronously under the same clock reference, thereby allowing the difference between the phasors of the incoming current and the sum of the currents of all outgoing branches to be calculated. When a fault occurs inside the electric meter box, the fault current flows out of the main circuit at a certain node within the box between the incoming and outgoing sides, and the difference between the two, i.e., the Kirchhoff current residual, will inevitably exceed the setting value. When a fault occurs outside the box, all currents flow through the outgoing current transformer, and the residual falls within the setting value, thus achieving a precise boundary between inside and outside the box. For faults inside the box, this invention extracts each segment along the phase busbar and N busbar segment by segment. The real part of the product of the voltage difference across the two ends and the conjugate product of the current flowing through it is divided by the square of the current magnitude to obtain the contact resistance of each segment. The discrimination process of this invention does not take the increase of the fault current as a premise. It also applies to the two types of fault current that are unique to the box, namely contact resistance deterioration and series arc, where the fault current does not increase but decreases. The location result is accurate to the contact number level. For external faults, the existing medium-voltage transplantation method uses the zero-sequence compensation coefficient to handle grounding faults. However, the low-voltage neutral point is directly grounded and the fault current returns through the N conductor or PE conductor. There is no zero-sequence path to the ground in the sense of medium voltage. This coefficient has no physical correspondence in the low-voltage scenario. This invention changes to summing the target unit length impedance of the fault phase conductor and the corresponding return conductor according to the determined fault type. The model corresponds one-to-one with the actual return conductor of the low-voltage TN system, eliminating the inherent model bias when the medium-voltage method is transplanted to low voltage. Low-voltage conductors have a low X / R ratio and their impedance is mainly resistance. Under full load, the resistance change caused by the temperature rise of the conductor core is the dominant source of error in this scenario. This invention uses terminal temperature measurements and steady-state current RMS values ​​to calculate the conductor core temperature through a first-order thermal model, and then corrects the resistance per unit length according to the conductor material temperature coefficient, incorporating this error into the correction. Medium-voltage methods do not address this issue. When two outgoing lines share a PEN trunk line or are laid in parallel, the voltage drop generated by the current in the healthy circuit at the coupling section simultaneously enters the measured voltage of the faulty circuit. This invention uses this voltage drop as an iterative decoupling term to successively remove it from the measured voltage, solving the ranging deviation introduced by a single circuit in a shared PEN area in existing technologies. The equivalent load impedance at the end is directly calculated from the measured voltage and current phasors before the fault, so that all coefficients of the quadratic equation are composed of actual measurements inside the box, without any typical value estimation. Under the physical constraint that the transition resistance is a pure real number, the present invention reduces the transition resistance to a quadratic equation about the fault distance. The root can be found in closed form on the embedded processor inside the box, and the fault location result can be output within a few cycles after the fault. Attached Figure Description

[0020] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of a system for testing the internal circuit impedance performance of an electric meter box in one embodiment of the present invention. Figure 2 This is a schematic flowchart of a method for testing the internal circuit impedance performance of an electric meter box body according to an embodiment of the present invention; Figure 3 yes Figure 2 A schematic diagram of the implementation process of step S101; Figure 4 yes Figure 2 A schematic diagram of the implementation process of step S102; Figure 5 yes Figure 2 A schematic diagram of the implementation process of step S103; Figure 6 yes Figure 2 A schematic diagram of the implementation process of step S104; Figure 7 This is a schematic diagram of a device for testing the internal circuit impedance performance of an electric meter box body according to an embodiment of the present invention. Figure 8 This is a schematic diagram of the structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that, as used in this specification and the appended claims, the term "and / or" refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0024] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0025] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0026] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0027] To illustrate the technical solution of the present invention, specific embodiments are described below.

[0028] To address the problems mentioned above in the background art, this application proposes a method and related equipment for testing the internal circuit impedance performance of an electricity meter box. The method for testing the internal circuit impedance performance of an electricity meter box provided by this invention can be applied to applications such as... Figure 1The internal circuit impedance performance testing system of the meter box shown includes: a synchronous measurement and fault recording device 1, which uses the N busbar sampling point inside the meter box as a potential reference, and employs the same multi-channel analog-to-digital converter and the same clock source to synchronously acquire three-phase voltage, incoming current, two outgoing currents, branch current inside the box, N-PE voltage, and terminal temperature; and is used to identify the fault time, latch the steady-state quantity before the fault, and measure the parameters required for output temperature correction; and a fault demarcation device 2, which determines whether the fault is inside the meter box or outside the box based on the Kirchhoff current residual between the incoming current and the current of each outgoing branch; when the fault is determined to be inside the box, the fault information is transmitted to the contact positioning and dual-circuit ranging device 3 for contact measurement. Level positioning: When a fault is determined to be outside the box, the fault phase and synchronization quantity measurements are transmitted to the contact positioning and dual-circuit ranging device 3 for outgoing line fault ranging; the contact positioning and dual-circuit ranging device 3 is used to extract the equivalent contact resistance between adjacent sampling points for faults inside the box and determine the fault contact point by combining terminal temperature rise; it is used to identify the fault type of faults outside the box, establish the common impedance coupling and decoupling term between the two outgoing lines according to the actual return path combination fault circuit impedance of the low-voltage TN system, calculate the fault distance and transition resistance outside the box, and perform DC component self-checking according to the fault initiation angle; the positioning result communication device 4 is used to send the fault contact number inside the box, or the fault distance, transition resistance, fault initiation angle, fault type and judgment confidence flag bit outside the box to the intelligent fusion terminal of the distribution area through the existing communication channel of the meter box body.

[0029] In one embodiment, such as Figure 2 As shown, a method for testing the internal circuit impedance performance of an electric meter box is provided, and this method is applied to... Figure 1 Taking the internal circuit impedance performance testing system of the meter box as an example, the following steps are included: S101: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source. This yields the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, and determines the fault time and the target impedance per unit length of each conductor. Simultaneously, the Kirchhoff current residual is calculated by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor. S102: When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault. The voltage difference phasor and the current phasor flowing through the section are extracted from each contact section of the phase busbar and N busbar in the meter box. The contact resistance of each contact is calculated by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. The internal contact fault number is determined by combining the temperature rise value of each contact. S103: When the Kirchhoff current residual does not exceed the set value, it is determined to be an external fault. The external fault distance, transition resistance and fault initiation angle are calculated based on the synchronous current phasor, synchronous voltage phasor, pre-fault latched phasor and target unit length impedance.

[0030] In this embodiment, the incoming current, the two outgoing currents, and the metering branch current are all connected to the same multi-channel A / D converter for synchronous acquisition using a common clock source. This embodiment ensures that the current phasors of all branches within the box are acquired synchronously under the same clock reference. This allows the difference between the phasors of the incoming current and the sum of the currents of all outgoing branches to be calculated. When a fault occurs inside the meter box, the fault current flows out of the main circuit at a certain node within the box between the incoming and outgoing sides. The difference between the two, i.e., the Kirchhoff current residual, will inevitably exceed the setting value. When a fault occurs outside the box, all current flows through the outgoing current transformer, and the residual falls within the setting value, thus achieving a precise boundary between inside and outside the box. For faults inside the box, this embodiment extracts the product of the voltage difference between the two ends of each segment and the conjugate product of the current flowing through each segment along the phase busbar and the N busbar. Dividing the real part by the square of the current modulus yields the contact resistance of each segment. In this embodiment, the discrimination process does not rely on an increase in fault current. It also applies to the unique fault modes inside the enclosure, such as contact resistance deterioration and series arcing, where the fault current decreases instead of increasing. The location result is accurate to the contact number level. For external enclosure faults, the existing medium-voltage transfer method uses a zero-sequence compensation coefficient to handle grounding faults. However, in low-voltage systems, the neutral point is directly grounded, and the fault current returns through the N conductor or PE conductor. There is no zero-sequence path to the ground in the sense of medium voltage, and this coefficient has no physical correspondence in low-voltage scenarios. In this embodiment, the target unit length impedance of the fault phase conductor and the corresponding return conductor is summed separately according to the determined fault type. The model corresponds one-to-one with the actual return conductor of the low-voltage TN system, eliminating the inherent model bias when the medium-voltage method is transferred to low voltage. Low-voltage conductors have a low X / R ratio and their impedance is mainly resistance. Under full load, the resistance change caused by the temperature rise of the conductor core is the dominant error source in this scenario. In this embodiment, the conductor core temperature is calculated using a first-order thermal model based on the terminal temperature measurement value and the steady-state current RMS value. Then, the resistance per unit length is corrected according to the conductor material temperature coefficient, incorporating this error into the correction. Medium-voltage methods do not address this issue. When two outgoing lines share a PEN trunk line or are laid in parallel, the voltage drop generated by the current in the healthy circuit at the coupling section simultaneously enters the measured voltage of the faulty circuit. In this embodiment, this voltage drop is used as an iterative decoupling term to be successively removed from the measured voltage, eliminating the systematic ranging bias introduced by the single-circuit method in the shared PEN area. The equivalent load impedance at the end is directly calculated from the measured voltage and current phasors before the fault, so that all coefficients of the quadratic equation are composed of actual measurements inside the box, without any typical value estimation. In this embodiment, after eliminating the transition resistance under the physical constraint that the transition resistance is a pure real number, it is reduced to a quadratic equation about the fault distance. The root can be found in closed form on the embedded processor inside the box, and the location conclusion is output within a few cycles after the fault.

[0031] In one embodiment, such as Figure 3 As shown, step S101 specifically includes the following steps: S201: The incoming current, two outgoing currents, metering branch current, phase voltage, and N bus to bus voltage of the meter box are synchronously acquired using the N bus sampling point as a unified potential reference and connected to the same multi-channel A / D for common clock source acquisition, so as to obtain synchronous current phasors and synchronous voltage phasors. S202: Determine the fault time based on the current mutation in the synchronous current phasor, and perform a full-cycle Fourier transform on the steady-state cycle before the fault time to obtain the latched phasor before the fault. S203: Based on the steady-state current RMS value in the latched phasor before the fault and the temperature measurement value of each return terminal, the initial unit length impedance of each conductor is corrected to obtain the target unit length impedance of each conductor. S204: Subtract the sum of the incoming current in the synchronous current phasor and the sum of the two outgoing currents and the metering branch current to obtain the Kirchhoff current residual.

[0032] In this embodiment, a multi-channel acquisition link with a unified reference and clock is established inside the meter box. The fixed sampling point on the N busbar inside the box is used as the unified zero potential point for all voltage quantities. Voltage taps for phases A, B, and C are set on the three-phase busbars, and an independent voltage sampling channel from the N busbar to the PE busbar is also provided. Current transformers are installed on the A, B, and C phases and the N conductor on the incoming line side. Current transformers or Rogowski coils are installed on the first and second outgoing lines. Current sampling channels are set for the remaining metering branches according to the metering branch topology inside the box. All current and voltage channels are then connected to the same multi-channel synchronous A / D converter, and the same sampling clock simultaneously triggers sampling in each channel, ensuring that each channel's sampling point has the same time reference. This avoids phase deviations between the two outgoing and incoming lines due to asynchronous sampling. For example, the sampling rate can be set to 6.4 kHz, corresponding to 50 Under Hz power frequency conditions, 128 sampling points are collected per cycle. Temperature sensors are installed at the incoming terminal block, the first outgoing terminal block, the second outgoing terminal block, and the N busbar, while the ambient temperature inside the enclosure is also collected, thus forming synchronous raw data. This acquisition structure unifies the three-phase voltage reference to the N busbar sampling point and ensures that the current quantities of the incoming line, the two outgoing lines, and the metering branch share the same A / D converter and clock source, providing a common time reference for cross-loop phasor calculations.

[0033] In this embodiment, a point-by-point abrupt change detection is established for each continuously acquired instantaneous current value, according to... Calculate the current change between the current sampling point and the in-phase sampling point of the previous complete cycle, where This approach aims to minimize the impact of normal power frequency cycle components on sudden change detection. When the current surge at three consecutive sampling points in the same current channel exceeds the set value, fault location is initiated. For example, the set value can be set to 5% of the rated current of the corresponding channel, with a minimum threshold of 0.5 A. Linear interpolation is performed between the first exceeding sampling point and its preceding sampling point. The intersection of the interpolation curve and the set value is determined as the fault time. Simultaneously, the starting point of the power frequency cycle at that time is recorded. Based on 6.4 kHz sampling, interpolation within the sampling interval improves the accuracy of fault time determination. After determining the fault time, the last complete steady-state cycle before the fault, unaffected by the fault transient, is selected from the cyclic buffer. A full-cycle Fourier transform is performed on the synchronous voltage and synchronous current of this cycle to extract the fundamental phasor and corresponding fundamental phase of each phase voltage, the fundamental current phasor of the two outgoing lines, and the effective value of the steady-state current. Simultaneously, the terminal temperature measurements and ambient temperature corresponding to this cycle are latched, thus obtaining the latched phasor before the fault.

[0034] In this embodiment, the initial unit length impedance is corrected for temperature based on the latched steady-state current RMS value and terminal temperature measurement results, wherein the core temperature is determined according to a first-order thermal model. Make an estimate, The thermal time constant is retrieved according to the parameters established based on the conductor cross-section, material, and laying method; after obtaining the core temperature, it is then... The resistance component is corrected, with the temperature coefficient of copper conductors taken as 0.00393 / ℃ and aluminum conductors as 0.00403 / ℃. The reactance component remains unchanged from its base value and is not corrected with temperature, thus forming the target impedance per unit length for the phase conductor, neutral conductor, protective conductor, and PEN conductor, respectively. After obtaining the synchronous current phasors corresponding to the same complete cycle, the incoming lines flow into the enclosure and the outgoing lines and metering branches flow out of the enclosure according to the unified current direction specification. For the faulty phase, the difference between the incoming current phasor and the sum of the current phasors of the two outgoing lines and all metering branches is calculated. This is used as the Kirchhoff current residual. Since the current phasors involved in the calculation come from the same A / D converter and the same sampling clock, the phasors maintain a unified phase reference. The resulting residual can mainly reflect whether the current flows out of the box from the nodes between the incoming line measurement point and each outgoing line and metering branch measurement point, rather than a false residual formed by the channel time scale difference. At the same time, the setting value used for subsequent fault boundary between inside and outside the box can be set to the larger value between 5% of the rated current and 0.5 A, so that the Kirchhoff current residual can be directly used as the input quantity for the next stage to determine whether the fault is inside the meter box or outside the box.

[0035] In one embodiment, such as Figure 4 As shown, step S102 specifically includes the following steps: S301: When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault and the contact resistance of each contact point corresponding to the phase busbar and N busbar is extracted, and the temperature rise value of each contact point is read synchronously. S302: Compare the contact resistance of each contact point with the corresponding contact point's resistance reference value, and compare the temperature rise value with the temperature rise threshold value. S303: When the contact resistance is greater than the resistance reference value or the temperature rise value is greater than the temperature rise threshold, output the corresponding box contact fault number.

[0036] In this embodiment, the Kirchhoff current residual corresponding to the current fault is compared with the setting value. The setting value can follow the previous criterion and be the larger of 5% of the rated current and 0.5 A. When the Kirchhoff current residual exceeds the setting value, it indicates that the current conservation relationship between the incoming current and the two outgoing currents and the metering branch current can no longer be satisfied with the normal node current conservation relationship in the box. That is, there is a part of the current flowing out through the N bus, PE bus, box body or other abnormal conductive path between the sampling position of the incoming current and the sampling positions of each outgoing current or metering branch current. Therefore, the current fault is determined to be an internal fault in the box, and the entry into the external fault distance calculation channel is stopped. Instead, the contact level impedance detection is performed according to the contact topology relationship pre-established in the meter box. During contact testing, voltage sampling positions can be set for each contact to be tested on the phase busbar and N busbar according to the actual connection sequence of the incoming terminal, front terminal, rear terminal, N-row pressure contacts, and outgoing terminal. The conductive connection segment between two adjacent voltage sampling positions is defined as a contact testing segment. Simultaneously, the current phasor flowing through this segment is obtained from the synchronous current channel corresponding to that testing segment, thus ensuring that the voltage across the contact and the contact current originate from the same sampling moment. For the first... Each contact detection segment obtains the phasor of the potential difference between its two ends. and the current phasor flowing through this section and in accordance with Calculate the equivalent contact resistance of the detection section, where Indicates the first Contact resistance of each detection segment, To take the real part of a complex number, It represents the conjugate of the current phasor. Since this calculation extracts the real part of the impedance from the complex power relationship between voltage and current, it can mainly reflect the resistive degradation caused by loose contact, oxidation, or reduced contact area, without requiring a significant increase in the fault current.

[0037] Simultaneously, the temperature of the terminal temperature sensor installed at the corresponding contact point or thermally coupled to that contact point is read, along with the ambient temperature inside the enclosure. This ensures that each contact point has a corresponding data record of "contact point number - contact resistance - terminal temperature - ambient temperature," preventing mismatches between temperature and contact resistance values ​​at different locations. Temperature sensors can be primarily placed on the incoming terminal blocks, the two outgoing terminal blocks, and the N busbar. For locations requiring further subdivision, such as the terminals before and after the meter, additional temperature sensors can be added based on the number of contacts inside the enclosure. The calculated contact resistance of each contact point is compared one by one with the resistance benchmark value established during normal operation or acceptance testing. A single, uniform resistance value cannot be used to cover all terminals, as the conductor cross-section, crimping structure, and connection materials may differ between terminals. To ensure a clear margin for error, a contact resistance greater than three times the corresponding benchmark value can be considered a resistance anomaly condition, while a temperature rise of more than 25 K relative to the ambient temperature inside the enclosure can be considered a thermal anomaly condition. These two conditions are assessed in parallel. The reason for using parallel criteria is that when a contact first becomes loose, oxidized, or the contact area decreases, the resistance value may have already increased significantly. However, due to thermal inertia, the terminal temperature rise has not yet been fully established. At this time, abnormal contact resistance can be used to identify the fault in advance. Conversely, under continuous current-carrying conditions, some crimped parts may have already formed obvious local heating, and the contact resistance calculated by the current cycle is affected by load fluctuations or sampling disturbances. Therefore, the temperature rise criterion can also serve as a supplement. Thus, as long as the contact resistance of a certain contact reaches the corresponding abnormal resistance condition, or the terminal temperature rise of that contact reaches the thermal abnormality condition, the contact can be added to the fault candidate set, and the corresponding box-side contact fault number can be output according to the pre-established contact number mapping table. For example, the fault location can be specified to the incoming terminal, the front terminal of the meter, the rear terminal of the meter, the N-row crimped contact, or the outgoing terminal, instead of just outputting the general "fault inside the meter box". When multiple adjacent contacts simultaneously reach abnormal conditions, a joint review can be conducted based on the degree of deviation of each contact's contact resistance from its own reference value and the temperature rise. The contact with the most significant abnormality will be prioritized, while the remaining abnormal contacts will be retained as associated fault information.

[0038] In one embodiment, such as Figure 5 As shown, step S103 specifically includes the following steps: S401: When the Kirchhoff current residual does not exceed the set value, it is determined to be an external fault and the fault type is determined according to the synchronous current phasor. The fault types include single-phase, two-phase, three-phase faults, phase-PE grounding faults, and N-line disconnection. S402: Calculate the unit length impedance of the fault loop, the unit length impedance of the double-loop coupling, and the length of the coupling segment based on the fault type and the target unit length impedance; S403: Based on the quotient of the voltage phasor and the current phasor before the fault in the latched phasor before the fault, subtract the product of the unit length impedance of the fault circuit and the outgoing line filing length to obtain the equivalent load impedance at the end. S404: Calculate the external fault distance, transition resistance, and fault initiation angle based on the fault loop unit length impedance, double-loop coupling unit length impedance, coupling section length, end equivalent load impedance, synchronous current phasor, and synchronous voltage phasor.

[0039] In this embodiment, the Kirchhoff current residual is used as the boundary between internal and external faults. It is compared with the larger of 5% and 0.5 A of the rated current to form a setting value. When the Kirchhoff current residual does not exceed this setting value, it indicates that the incoming current, the two outgoing currents, and the metering branch current basically satisfy the current conservation relationship inside the meter box. This confirms that the abnormal current does not form a significant current shunting between the sampling boundaries inside the box, marking the current fault as an external fault and entering the fault type analysis process. The three-phase current mutation is calculated using the A, B, and C phase synchronous current phasors obtained from the first complete cycle after the fault, and combined with... The zero-sequence current component is obtained. A single-phase fault is identified when only one phase current exhibits a significant abrupt change; a two-phase fault is identified when two phases exhibit simultaneous significant abrupt changes while the other phase remains essentially in its pre-fault state; and a three-phase fault is identified when all three phases exhibit corresponding abrupt changes. For single-phase faults where the faulty phase has been identified, the zero-sequence current is then combined with the synchronous current of conductor N, according to... A PE return current discrimination value is generated. When its magnitude exceeds the preset current threshold, it indicates that there is a fault current that returns through the PE conductor and grounding path instead of through the N conductor. Therefore, it is further determined to be a phase-PE grounding fault. When its magnitude does not exceed the threshold, it is handled as a phase-N return current. For example, this current threshold can be set to the larger of 5% of the rated current and 0.5 A. For N line disconnection, the three-phase voltage imbalance, N bus voltage to PE bus voltage, and three-phase current change status are used together for judgment. When the three-phase voltage imbalance exceeds 4%, the N bus voltage to PE bus voltage increases significantly, and the current of each phase does not increase synchronously, it is determined that the N conductor is open or disconnected. At this time, since the fault mechanism is neutral point drift rather than the formation of a low-resistance fault loop along the outgoing line, the N line disconnection and corresponding neutral point drift status are directly output, and the external distance calculation is not continued.

[0040] After obtaining the fault types that can enter the ranging channel, this embodiment constructs a fault loop unit length impedance consistent with the actual return path based on the target unit length impedance of the phase conductor, neutral conductor, protective conductor, and PEN conductor formed by S203. Specifically, for phase-N faults, the sum of the phase conductor unit length impedance and the neutral conductor unit length impedance is used; for phase-PE grounding faults, the sum of the phase conductor unit length impedance and the protective conductor unit length impedance is used; for two-phase short circuits, twice the phase conductor unit length impedance is used; and for three-phase short circuits, the phase conductor unit length impedance is used. This avoids continuing to use the zero-sequence compensation method based on the medium-voltage ground zero-sequence path. Simultaneously... The unit length impedance and coupling section length of the double-circuit coupling are determined based on the actual laying structure of the two outgoing lines. When the two outgoing lines share the PEN trunk, the temperature-corrected unit length impedance of the PEN conductor is used as the unit length impedance of the double-circuit coupling, and the documented length of the shared PEN section is used as the coupling section length. When the two single-core conductors are laid in parallel in the same pipe or trench, the corresponding coupling impedance is obtained according to the documented parallel laying parameters, and the actual parallel section length is used as the coupling section length. When the two outgoing lines use independent multi-core cables and there is no common conductor coupling that needs to be compensated, the unit length impedance of the double-circuit coupling can be set to zero.

[0041] In this embodiment, the load state at the end of the fault circuit is directly determined using the voltage and current phasors latched from the last steady-state cycle before the fault, according to... The equivalent load impedance at the end is obtained, where The corresponding outgoing line's archiving length is used, while the temperature condition is the pre-fault latched temperature, ensuring that the terminal load parameters correspond to the actual operating conditions before the fault. The fault distance calculation process incorporates the fault circuit unit length impedance, double-circuit coupling unit length impedance, coupling section length, terminal equivalent load impedance, and post-fault synchronous current and voltage phasors. Corrections are made for the coupling voltage drop generated by the healthy circuit current in the shared PEN section or parallel laying section. The calculation was performed using... Initial command Then, the corrected fault loop voltage, fault loop current, fault loop impedance per unit length, and equivalent load at the end are substituted into the existing quadratic equation. Candidate fault distances are obtained through closed-form root-finding, retaining valid roots that fall within the corresponding outgoing line filing length range and whose back-substituted transition resistance is non-negative. If both sets of roots satisfy the above conditions, the residuals between the healthy loop voltage reconstructed using each candidate distance and the actual synchronization voltage are further compared. The result with the smaller residual is selected, and the obtained fault distance is used to update the coupling voltage drop for recalculation until the change in fault distance between two adjacent faults is less than 0.01 m, thus obtaining the converged external fault distance and transition resistance. The fault initiation angle is calculated using the fault time determined by S202, the corresponding power frequency cycle start point, and the fundamental phase of the fault phase latched before the fault, i.e., according to... Determine the voltage phase corresponding to the time of the fault occurrence, and combine it with the obtained fault distance and transition resistance to form the final external fault location result.

[0042] In one embodiment, such as Figure 6 As shown, step S404 specifically includes the following steps: S501: Calculate the fault loop voltage based on the synchronous voltage phasor, synchronous current phasor, double-loop coupling unit length impedance, and the current fault distance and coupling segment length; S502: Based on the fault circuit voltage, synchronous current phasor, fault circuit impedance per unit length, and equivalent load impedance at the end, establish a quadratic equation with the fault distance as the only unknown, and solve it to obtain the fault distance outside the box and the transition resistance. S503: Calculate the fault initiation angle based on the fundamental phase of the fault phase and the fault time in the latched phasor before the fault.

[0043] In this embodiment, the faulty circuit is defined as the outgoing line that has experienced a fault, and the other outgoing line is defined as the healthy circuit. The outgoing current phasors of the faulty circuit, the outgoing current phasors of the healthy circuit, and the faulty phase voltage phasors within the enclosure are obtained from the synchronous sampling results of the first complete cycle after the fault. The voltage measured in the faulty circuit includes not only the voltage drop generated by the faulty circuit's own conductor, but also, when the two outgoing lines share a PEN trunk or have parallel laying coupling, the additional voltage drop generated by the healthy circuit current across the common impedance or coupling impedance. Therefore, this portion of the coupling voltage drop is first subtracted based on the current fault distance. The first... The fault circuit voltage used in this calculation is denoted as... ,according to Perform calculations, where The fault phase voltage was acquired synchronously. To ensure the proper output current of the circuit, For double-loop coupling, the unit length impedance is... The length of the coupling segment. The fault distance obtained in the previous round is used as the actual length used in the coupling voltage drop calculation. Since the fault point may be located inside or after the coupling section, the length actually used in the calculation is the smaller of the current fault distance and the coupling section length. The fault distance is not yet available in the initial calculation, so it can be set as follows: That is, first ignore the coupling voltage drop to obtain the initial distance, and then use the initial distance to recalculate the fault loop voltage, thus forming an iterative relationship of "fault distance - coupling voltage drop - fault loop voltage - updated fault distance".

[0044] In this embodiment, after obtaining the fault circuit voltage corresponding to the current iteration, the total impedance at the end of the fault circuit is obtained by combining the unit length impedance of the fault circuit, the outgoing line filing length, and the equivalent load impedance at the end. Then, the auxiliary quantity of the fault branch is constructed by combining the fault circuit voltage and the outgoing line current. Furthermore, utilizing the physical condition that the transition resistance is a real number, the transition resistance is eliminated from the complex fault circuit relationship, making the fault distance the only unknown in the equation to be solved, ultimately forming a quadratic equation in one variable concerning the fault distance. During the solution stage, the quadratic equation is solved in a closed-form form, and real roots within the range of 0 to the outgoing line filing length are retained from the candidate solutions. The candidate fault distances are then used to calculate the transition resistance, and roots with negative transition resistances that do not meet the actual physical conditions of the fault are eliminated. When both candidate roots satisfy the distance range and transition resistance conditions, the candidate root that results in the smaller residual in the reconstruction of the healthy circuit voltage is selected as the fault distance for this round. The fault distance is then returned to S501 to redetermine the actual length involved in the double-loop coupling correction and update the fault loop voltage. This calculation is repeated until the difference between two adjacent fault distances is less than 0.01 m. The current fault distance is then determined as the converged external fault distance, and its corresponding transition resistance is used as the final transition resistance. Based on the fault phase identified in S401, the fundamental phase of the fault phase within the last complete steady-state cycle before the fault is retrieved from the pre-fault latched phasor, while simultaneously obtaining the fault time determined in S202. And the starting time of the power frequency cycle in which the fault occurred. The fundamental phase of the fault phase before the fault is denoted as ,according to Calculate the fault initiation angle, where The fault position on the time axis is converted into the instantaneous electrical angle of the corresponding fault phase voltage by using the power frequency angular frequency. To avoid fault moment identification errors being directly transmitted to the fault initiation angle, the DC component of the short-circuit current can be inversely calculated using the already obtained external fault distance and line impedance, and then checked against the actual DC component obtained by synchronous sampling. When the deviation between the two exceeds 15%, the current result is marked as fault moment location abnormal or impedance parameter mismatch, and the process is returned to the fault moment identification process for re-determination. Then, the fault distance, transition resistance, and fault initiation angle are recalculated, and the final outputs are the external fault distance, transition resistance, and fault initiation angle.

[0045] In one embodiment, step S502 specifically includes the following steps: Add the product of the unit length impedance of the fault circuit and the outgoing line filing length to the equivalent load impedance at the end to obtain the total impedance at the end of the circuit; subtract the product of the outgoing line current of the fault circuit and the total impedance at the end of the circuit from the voltage of the fault circuit to obtain the auxiliary quantity of the fault branch. The voltage of the fault circuit The fault circuit output current The impedance per unit length of the fault circuit The total impedance at the end of the circuit and the auxiliary quantity of the fault branch According to the coefficient of the quadratic term coefficient of the first term constant term Establish a quadratic equation in one variable ,in The distance from the fault point to the outgoing port, The conjugate of the auxiliary quantity of the faulty branch; By performing closed-form root-finding on the quadratic equation, the external fault distance and transition resistance can be obtained.

[0046] In this embodiment, the fault loop voltage after iterative correction is obtained. And call the fault loop unit length impedance corresponding to the current fault type. Fault circuit outgoing line filing length and the equivalent load impedance at the end The total impedance at the end of the circuit is obtained by series-equivalent connection of the total impedance of the line with the equivalent load impedance at the end. Subsequently, the outgoing current of the fault circuit was obtained through synchronous acquisition. Calculate the auxiliary quantity of the faulty branch. This allows complex quantities in the equation that are independent of the fault distance to be uniformly classified into... .

[0047] In this embodiment, when establishing the distance equation, the distance from the fault point to the outgoing port of the meter box is set as follows: Then the voltage at the fault point can be expressed as The impedance observed from the fault point to the end of the line is Therefore, the load-side current can be determined by the fault point voltage and the impedance, and the fault branch current can be obtained by subtracting the load-side current from the fault circuit outgoing current; after processing, the fault branch current contains... The relevant linear terms cancel each other out, so that its numerator consists only of known quantities, and in combination with the fault point, satisfies... and transition resistance To accommodate the physical constraint of real numbers, the transition resistance is eliminated from the distance calculation equation, and finally, the solution is based on the coefficients of the quadratic term. coefficient of the first term and constant terms Establish based solely on fault distance A quadratic equation with unknowns ,in Indicates the auxiliary quantity of the faulty branch The conjugate of . After processing, the fault distance does not need to be determined by searching meter by meter along the outgoing line or by multivariate joint iteration, but can be directly determined by . Perform closed-form root finding. After obtaining two candidate roots, discard those that do not belong to the given path. The root of the range is found, and the remaining candidate distances are substituted back into the original fault loop relationship, according to... Find the corresponding transition resistance, where For the calculated Candidate roots are discarded because negative transition resistance does not meet the physical conditions of an actual faulty branch. If both roots satisfy the distance range and non-negative transition resistance conditions, the healthy loop voltage is reconstructed using the two candidate distances, and the one with the smaller residual difference from the actual synchronously measured voltage is selected as the current fault distance. This fault distance is then returned to the double-loop coupling voltage correction process to recalculate the fault loop voltage. Then, the above quadratic equation is re-established. Iteration stops when the difference between two consecutive calculated fault distances is less than 0.01 m, and the finally converged equation is... As the distance to external faults, the non-negative value obtained by substituting it back is... As the corresponding transition resistance, this completes the closed-loop solution process from the known synchronous phasor and line impedance parameters to the external fault distance and transition resistance.

[0048] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0049] In one embodiment, a device 700 for testing the internal circuit impedance performance of an electricity meter box is provided. This device 700 corresponds one-to-one with the method for testing the internal circuit impedance performance of the electricity meter box in the above embodiments. Figure 7 As shown, the internal circuit impedance performance testing device 700 of the meter box includes: The acquisition module 701 is used to synchronously acquire the incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus-to-bus voltage of the meter box, using the N-bus sampling point as a unified potential reference and connecting it to the same multi-channel A / D for synchronous acquisition with a common clock source. This process yields the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, determines the fault time, and identifies the target impedance per unit length of each conductor. Simultaneously, the Kirchhoff current residual is calculated by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor. The box-in-box fault location module 702 is used to determine that when the Kirchhoff current residual exceeds the set value, it is a box-in-box fault. It extracts the voltage difference phasor and the current phasor flowing through the segment along the detection section of each contact point of the phase bus and N bus in the meter box. It calculates the contact resistance of each contact point by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. It determines the box-in-box contact fault number by combining the temperature rise value of each contact point. The external fault location module 703 is used to determine an external fault when the Kirchhoff current residual does not exceed the set value, and to calculate the external fault distance, transition resistance and fault initiation angle based on the synchronous current phasor, synchronous voltage phasor, pre-fault latched phasor and target unit length impedance.

[0050] Optionally, the acquisition module 701 is specifically used for: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage to busbar voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source, to obtain synchronous current phasors and synchronous voltage phasors. The fault time is determined by the current mutation in the synchronous current phasor, and the full-cycle Fourier transform is performed on the steady-state cycle before the fault time to obtain the latched phasor before the fault. Based on the steady-state current RMS value in the latched phasor before the fault and the temperature measurement value of each return terminal, the initial unit length impedance of each conductor is corrected to obtain the target unit length impedance of each conductor. The Kirchhoff current residual is obtained by subtracting the sum of the incoming current in the synchronous current phasor from the sum of the two outgoing currents and the metering branch current.

[0051] Optionally, the in-box fault location module 702 is specifically used for: When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault and the contact resistance of each contact point corresponding to the phase busbar and the N busbar is extracted, and the temperature rise value of each contact point is read synchronously. The contact resistance of each contact point is compared with the corresponding contact point's resistance reference value, and the temperature rise value is compared with the temperature rise threshold value. When the contact resistance is greater than the resistance reference value or the temperature rise value is greater than the temperature rise threshold, the corresponding box contact fault number will be output.

[0052] Optionally, the external fault location module 703 also includes: The type analysis unit is used to determine the external fault when the Kirchhoff current residual does not exceed the set value, and to determine the fault type based on the synchronous current phasor. The fault types include single-phase, two-phase, three-phase faults, phase-PE grounding faults, and N-line disconnection. The first calculation unit is used to calculate the fault circuit impedance per unit length, the double-loop coupling impedance per unit length, and the coupling segment length based on the fault type and the target unit length impedance. The second calculation unit is used to obtain the equivalent load impedance at the end by subtracting the product of the unit length impedance of the fault circuit and the outgoing line filing length from the quotient of the pre-fault voltage phasor and the pre-fault current phasor in the pre-fault latched phasor. The fault analysis unit is used to calculate the external fault distance, transition resistance, and fault initiation angle based on the fault loop unit length impedance, double-loop coupling unit length impedance, coupling section length, end equivalent load impedance, synchronous current phasor, and synchronous voltage phasor.

[0053] Optionally, the fault analysis unit is specifically used for: Calculate the fault loop voltage based on the synchronous voltage phasor, synchronous current phasor, double-loop coupling unit length impedance, and current fault distance and coupling segment length. Based on the fault circuit voltage, synchronous current phasor, fault circuit impedance per unit length, and equivalent load impedance at the end, a quadratic equation with fault distance as the only unknown is established, and the fault distance outside the box and the transition resistance are obtained by solving it. The fault initiation angle is calculated based on the fundamental phase of the fault phase in the latched phasor before the fault and the fault time.

[0054] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0055] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0056] This application also provides a computer device, such as... Figure 8As shown, the computer device includes: at least one processor, a memory, and a computer program stored in the memory and executable on the at least one processor. When the processor executes the computer program, it implements the steps in any of the above method embodiments, or when the processor executes the computer program, it implements the functions of each module / unit in the above device embodiments.

[0057] For example, the computer program may be divided into one or more modules / units, which are stored in the memory and executed by the processor to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the computer device.

[0058] Those skilled in the art will understand that Figure 8 The computer device described is merely an example and does not constitute a limitation on the computer device. It may include more or fewer components than shown, or combine certain components, or different components. For example, the computer device may also include input / output devices, network access devices, buses, etc.

[0059] The aforementioned processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), or field-programmable gate arrays (FPGAs). Programmable Gate Array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0060] The memory can be an internal storage unit of the computer device, such as a hard drive or RAM. The memory can also be an external storage device of the computer device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory can include both internal and external storage units of the computer device.

[0061] This application also provides a readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the various method embodiments described above.

[0062] This application provides a computer program product that, when run on an electronic device, enables the electronic device to implement the steps described in the various method embodiments above.

[0063] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of this application can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0064] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0065] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0066] In the embodiments provided in this application, it should be understood that the disclosed apparatus / devices and methods can be implemented in other ways. For example, the apparatus / device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0067] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0068] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for testing the internal circuit impedance performance of an electric meter box, characterized in that, include: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source. This yields the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, and determines the fault time and the target impedance per unit length of each conductor. Simultaneously, the Kirchhoff current residual is calculated by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor. When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault. The voltage difference phasor and the current phasor flowing through the section are extracted from each contact section of the phase bus and N bus in the meter box. The contact resistance of each contact is calculated by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. The internal contact fault number is determined by combining the temperature rise value of each contact. When the Kirchhoff current residual does not exceed the set value, it is determined to be an external fault. The external fault distance, transition resistance and fault initiation angle are calculated based on the synchronous current phasor, the synchronous voltage phasor, the pre-fault latched phasor and the target unit length impedance.

2. The method for testing the internal circuit impedance performance of the meter box as described in claim 1, characterized in that, The process involves synchronously acquiring the incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage of the meter box using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source. This yields the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, determining the fault time and the target impedance per unit length of each conductor. Simultaneously, the Kirchhoff current residual is calculated by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor, including: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage to busbar voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source, to obtain synchronous current phasors and synchronous voltage phasors. The fault time is determined based on the current mutation in the synchronous current phasor, and a full-cycle Fourier transform is performed on the steady-state cycle before the fault time to obtain the latched phasor before the fault. Based on the steady-state current RMS value in the latched phasor before the fault and the temperature measurement value of each return terminal, the initial unit length impedance of each conductor is corrected to obtain the target unit length impedance of each conductor. The Kirchhoff current residual is obtained by subtracting the sum of the incoming current in the synchronous current phasor from the sum of the two outgoing currents and the metering branch current.

3. The method for testing the internal circuit impedance performance of the meter box as described in claim 2, characterized in that, When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault. The voltage difference phasor and the current phasor flowing through each contact section of the phase busbar and N busbar within the meter box are extracted. The contact resistance of each contact is calculated by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. Combined with the temperature rise of each contact, the internal fault number is determined, including: When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault and the contact resistance of each contact point corresponding to the phase bus and N bus is extracted, and the temperature rise value of each contact point is read synchronously. The contact resistance of each contact point is compared with the resistance reference value of the corresponding contact point, and the temperature rise value is compared with the temperature rise threshold. When the contact resistance is greater than the resistance reference value or the temperature rise value is greater than the temperature rise threshold, the corresponding box contact fault number is output.

4. The method for testing the internal circuit impedance performance of the meter box as described in claim 3, characterized in that, When the Kirchhoff current residual does not exceed the set value, it is determined to be an external fault. The external fault distance, transition resistance, and fault initiation angle are calculated based on the synchronous current phasor, the synchronous voltage phasor, the pre-fault latched phasor, and the target unit length impedance, including: When the Kirchhoff current residual does not exceed the set value, it is determined to be an external fault and the fault type is determined according to the synchronous current phasor. The fault type includes single-phase, two-phase, three-phase fault, phase-PE grounding fault and N line disconnection. Calculate the fault loop impedance per unit length, the double-loop coupling impedance per unit length, and the coupling segment length based on the fault type and the target unit length impedance; Based on the quotient of the pre-fault voltage phasor and the pre-fault current phasor in the pre-fault latched phasor, the product of the unit length impedance of the fault circuit and the outgoing line arch length is subtracted to obtain the terminal equivalent load impedance. The external fault distance, transition resistance, and fault initiation angle are calculated based on the fault circuit unit length impedance, the double-loop coupling unit length impedance, the coupling section length, the end equivalent load impedance, the synchronous current phasor, and the synchronous voltage phasor.

5. The method for testing the internal circuit impedance performance of the meter box as described in claim 4, characterized in that, The calculation of the external fault distance, transition resistance, and fault initiation angle based on the fault circuit unit length impedance, the double-loop coupling unit length impedance, the coupling section length, the end equivalent load impedance, the synchronous current phasor, and the synchronous voltage phasor includes: The fault loop voltage is calculated based on the synchronous voltage phasor, the synchronous current phasor, the double-loop coupling unit length impedance, and the current fault distance and coupling segment length. Based on the fault circuit voltage, the synchronous current phasor, the fault circuit impedance per unit length, and the equivalent load impedance at the end, a quadratic equation with the fault distance as the only unknown is established, and the fault distance outside the box and the transition resistance are obtained by solving it. The fault initiation angle is calculated based on the fundamental phase of the fault phase in the pre-fault latched phasor and the fault time.

6. The method for testing the internal circuit impedance performance of the meter box body as described in claim 5, characterized in that, The process involves establishing a quadratic equation with the fault distance as the sole unknown based on the fault circuit voltage, the synchronous current phasor, the fault circuit impedance per unit length, and the equivalent load impedance at the end, and solving for the external fault distance and transition resistance, including: Add the product of the unit length impedance of the fault circuit and the outgoing line filing length to the equivalent load impedance at the end to obtain the total impedance at the end of the circuit; subtract the product of the outgoing line current of the fault circuit and the total impedance at the end of the circuit from the voltage of the fault circuit to obtain the auxiliary quantity of the fault branch. The voltage of the fault circuit The fault circuit output current The impedance per unit length of the fault circuit The total impedance at the end of the circuit and the auxiliary quantity of the fault branch According to the coefficient of the quadratic term coefficient of the first term constant term Establish a quadratic equation in one variable ,in The distance from the fault point to the outgoing port, The conjugate of the auxiliary quantity of the faulty branch; By performing closed-form root-finding on the quadratic equation, the external fault distance and transition resistance can be obtained.

7. A device for testing the internal circuit impedance performance of an electric meter box, characterized in that, The steps for performing the test method for the internal circuit impedance performance of the meter box body as described in any one of claims 1 to 6 include: The acquisition module is used to synchronously acquire the incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage of the meter box, using the N-bus sampling point as a unified potential reference and connecting it to the same multi-channel A / D for synchronous acquisition with a common clock source. This yields the synchronous current phasor, synchronous voltage phasor, and pre-fault latched phasor of the meter box, and determines the fault time and the target impedance per unit length of each conductor. Simultaneously, the module calculates the Kirchhoff current residual by subtracting the incoming current from the sum of the two outgoing currents and the metering branch current in the synchronous current phasor. The box-in-box fault location module is used to determine that when the Kirchhoff current residual exceeds the set value, it is a box-in-box fault. It also extracts the voltage difference phasor and the current phasor flowing through the segment along the detection section of each contact point of the phase bus and N bus in the meter box. It calculates the contact resistance of each contact point by dividing the real part of the conjugate product of the voltage difference phasor and the current phasor by the square of the current magnitude. Combined with the temperature rise value of each contact point, it determines the box-in-box contact fault number. The external fault location module is used to determine an external fault when the Kirchhoff current residual does not exceed the set value, and to calculate the external fault distance, transition resistance and fault initiation angle based on the synchronous current phasor, the synchronous voltage phasor, the fault pre-latch phasor and the target unit length impedance.

8. The meter box internal circuit impedance performance testing device as described in claim 7, characterized in that, The acquisition module is specifically used for: The incoming current, two outgoing currents, metering branch current, phase voltage, and N-bus voltage to busbar voltage of the meter box are synchronously acquired using the N-bus sampling point as a unified potential reference and connected to the same multi-channel A / D converter with a common clock source, to obtain synchronous current phasors and synchronous voltage phasors. The fault time is determined based on the current mutation in the synchronous current phasor, and a full-cycle Fourier transform is performed on the steady-state cycle before the fault time to obtain the latched phasor before the fault. Based on the steady-state current RMS value in the latched phasor before the fault and the temperature measurement value of each return terminal, the initial unit length impedance of each conductor is corrected to obtain the target unit length impedance of each conductor. The Kirchhoff current residual is obtained by subtracting the sum of the incoming current in the synchronous current phasor from the sum of the two outgoing currents and the metering branch current.

9. The meter box internal circuit impedance performance testing device as described in claim 8, characterized in that, The in-box fault location module is specifically used for: When the Kirchhoff current residual exceeds the set value, it is determined to be an internal fault and the contact resistance of each contact point corresponding to the phase bus and N bus is extracted, and the temperature rise value of each contact point is read synchronously. The contact resistance of each contact point is compared with the resistance reference value of the corresponding contact point, and the temperature rise value is compared with the temperature rise threshold. When the contact resistance is greater than the resistance reference value or the temperature rise value is greater than the temperature rise threshold, the corresponding box contact fault number is output.

10. The meter box internal circuit impedance performance testing device as described in claim 9, characterized in that, The external fault location module also includes: The type analysis unit is used to determine an external fault when the Kirchhoff current residual does not exceed the set value, and to determine the fault type according to the synchronous current phasor. The fault types include single-phase, two-phase, three-phase faults, phase-PE grounding faults, and N-line disconnection. The first calculation unit is used to calculate the fault circuit impedance per unit length, the double-loop coupling impedance per unit length, and the coupling segment length based on the fault type and the target unit length impedance. The second calculation unit is used to subtract the product of the fault circuit unit length impedance and the outgoing line filing length from the quotient of the fault voltage phasor and the fault current phasor in the fault latched phasor to obtain the terminal equivalent load impedance. The fault analysis unit is used to calculate the external fault distance, transition resistance, and fault initiation angle based on the unit length impedance of the fault loop, the unit length impedance of the double-loop coupling, the length of the coupling section, the equivalent load impedance at the end, the synchronous current phasor, and the synchronous voltage phasor.

11. The meter box body internal circuit impedance performance testing device as described in claim 10, characterized in that, The fault analysis unit is specifically used for: The fault loop voltage is calculated based on the synchronous voltage phasor, the synchronous current phasor, the double-loop coupling unit length impedance, and the current fault distance and coupling segment length. Based on the fault circuit voltage, the synchronous current phasor, the fault circuit impedance per unit length, and the equivalent load impedance at the end, a quadratic equation with the fault distance as the only unknown is established, and the fault distance outside the box and the transition resistance are obtained by solving it. The fault initiation angle is calculated based on the fundamental phase of the fault phase in the pre-fault latched phasor and the fault time.

12. A computer device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method for testing the internal circuit impedance performance of the meter box body as described in any one of claims 1 to 6.

13. A readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the method for testing the internal circuit impedance performance of the meter box body as described in any one of claims 1 to 6.

14. A computer program product, characterized in that, The computer program product includes a computer program that, when executed by a processor, implements the steps of the method for testing the internal circuit impedance performance of the meter box body as described in any one of claims 1 to 6.

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