Silicon photonic quantum waveguide array chip for high-density integration and parameter optimization method

Abstract

The application relates to the technical field of silicon light quantum chip integration, and discloses a silicon light quantum waveguide array chip for high-density integration and a parameter optimization method. The chip comprises a silicon-based substrate, a buried oxygen layer, a silicon waveguide core layer, an upper cladding layer and a plurality of quantum light transmission waveguides. The silicon waveguide core layer is arranged above the buried oxygen layer and forms the plurality of quantum light transmission waveguides through etching. The upper cladding layer is arranged above the silicon waveguide core layer and the quantum light transmission waveguides. A non-uniform spacing region, a non-symmetrical propagation constant mismatch region and a local isolation auxiliary structure region arranged between different adjacent waveguides form a low crosstalk structure. Compared with the prior art, the application can preferentially allocate the chip transverse space to a crosstalk sensitive region, reduce area waste caused by a unified large spacing design, supplementally inhibit a high-risk region, reduce additional loss caused by a continuous isolation structure, and improve the crosstalk inhibition capability and manufacturing adaptability of the waveguide array under the condition of high-density layout as a whole.

Description

Technical Field

[0001] This invention relates to the field of silicon photonic quantum chip integration technology, and in particular to a silicon photonic quantum waveguide array chip and parameter optimization method for high-density integration. Background Technology

[0002] With the continuous development of silicon-based photonic integration technology, more and more functions such as optical transmission, beam splitting and combining, modulation, filtering, delay, and routing are being integrated onto a single chip. Relying on mature CMOS manufacturing processes, silicon photonic chips have advantages such as high integration density, small size, low power consumption, and ease of mass production, and have been widely used in high-speed optical communication, on-chip optical interconnects, optical sensing, and quantum information processing. In quantum photonic chips, multiple silicon photonic waveguides typically undertake tasks such as single-photon transmission, path coding, quantum interference, entangled state distribution, and multi-channel quantum state processing. Therefore, the integration density and transmission quality of the waveguide array directly affect the overall performance of the on-chip quantum information system.

[0003] As chip integration scales increase and the spacing between adjacent waveguides decreases, factors such as waveguide evanescent field overlap, mode coupling, and local refractive index perturbations can easily lead to crosstalk between adjacent waveguides. For traditional optical communication systems, crosstalk mainly manifests as optical power leakage; however, in quantum photonic chips, even small non-target couplings can increase the probability of path errors, decrease quantum state fidelity, reduce interference visibility, and cause deviations in quantum measurement results. Therefore, high-density silicon optical waveguide arrays not only need to control optical power crosstalk but also need to consider comprehensive performance aspects such as quantum state preservation capability, phase consistency, and manufacturing tolerance.

[0004] Currently, methods for reducing crosstalk in silicon photonic waveguides mainly include increasing the spacing between adjacent waveguides, using asymmetric waveguide structures, setting up isolation structures, and introducing active compensation methods such as thermal tuning or electro-optic tuning. Among these, increasing the waveguide spacing can reduce mode coupling, but it will significantly increase the chip area, which is not conducive to high-density integration; using asymmetric waveguides of fixed size can create propagation constant mismatch, but it is difficult to meet the crosstalk requirements of different functional regions; isolation slots or subwavelength structures can reduce mode overlap, but continuously setting up isolation structures may increase scattering loss and increase manufacturing complexity; although active compensation methods have a certain degree of adjustability, they require additional driving circuits and power consumption, and are prone to introducing thermal crosstalk, which will have a certain impact on the long-term stable operation of on-chip quantum systems.

[0005] Further analysis reveals that most existing technologies optimize for single structural parameters, typically employing uniform waveguide spacing, fixed propagation constant mismatch, or a single isolation structure. Using the same optimization strategy for different locations, coupling lengths, and quantum functional regions makes it difficult to achieve a comprehensive balance between chip area, crosstalk level, quantum performance, and manufacturing tolerance. In crosstalk-sensitive locations such as the quantum interference region, long-distance parallel transmission region, and path coding region, these design methods are prone to insufficient local crosstalk suppression or increased overall layout area, limiting the further integration of high-density silicon photonic quantum chips.

[0006] Therefore, it is necessary to propose a low-crosstalk silicon photonic quantum waveguide array chip for high-density integration and its parameter optimization method. By using non-uniform waveguide spacing design, asymmetric propagation constant mismatch design, local isolation auxiliary structure, and parameter co-optimization strategy, the waveguide array structure can be jointly optimized. While maintaining high integration density, it helps to reduce crosstalk between adjacent waveguides, improve quantum state transmission stability, and enhance the structure's adaptability to manufacturing deviations. Summary of the Invention

[0007] To address the aforementioned shortcomings of existing technologies, this invention proposes a silicon photonic quantum waveguide array chip and parameter optimization method for high-density integration. The aim is to improve the crosstalk suppression capability and manufacturing adaptability of waveguide arrays under high-density layout conditions through non-uniform waveguide spacing, asymmetric propagation constant mismatch, local isolation auxiliary structure, and parameter synergistic optimization.

[0008] The technical solution of this invention is implemented as follows: A silicon photonic quantum waveguide array chip for high-density integration includes a silicon substrate, a buried oxide layer, a silicon waveguide core layer, and an upper cladding layer arranged from bottom to top, and multiple quantum optical transmission waveguides formed in the silicon waveguide core layer. The multiple quantum optical transmission waveguides are arranged side-by-side along the chip plane, forming at least two sets of adjacent quantum optical transmission waveguides. A non-uniform spacing region is provided between adjacent quantum optical transmission waveguides, and at least two sets of adjacent quantum optical transmission waveguides in the non-uniform spacing region have different center-to-center spacings. At least one set of adjacent quantum optical transmission waveguides is provided with an asymmetric propagation constant mismatch region, causing the adjacent quantum optical transmission waveguides to have different propagation constants. At least one set of adjacent quantum optical transmission waveguides is provided with a locally isolated auxiliary structure region. The non-uniform spacing region, the asymmetric propagation constant mismatch region, and the locally isolated auxiliary structure region between different adjacent quantum optical transmission waveguides constitute a low crosstalk structure for the high-density integrated silicon photonic quantum waveguide array.

[0009] Preferably, the asymmetric propagation constant mismatch region is formed by changing at least one of the waveguide width, etching depth, cladding perturbation structure, or lateral perturbation structure of the adjacent quantum optical transmission waveguide, and the local isolation auxiliary structure region includes at least one of the following: shallow etched grooves, low refractive index isolation grooves, subwavelength perturbation structures, or lateral microgrooves arranged in sections along the light propagation direction.

[0010] Preferably, the three regions—the non-uniform spacing region, the asymmetric propagation constant mismatch region, and the local isolation auxiliary structure region—are arranged in an overlapping or segmented configuration according to crosstalk sensitivity in the light propagation direction, and the front and rear positions of the three regions are not fixed.

[0011] Preferably, in the non-uniform spacing region, the center-to-center spacing of each adjacent quantum optical transmission waveguide is set to different values ​​according to the crosstalk sensitivity.

[0012] Preferably, the asymmetric propagation constant mismatch region is formed by the difference in width, etching depth, cladding disturbance, or lateral disturbance between adjacent waveguides.

[0013] Preferably, the local isolation auxiliary structure region is segmented along the light propagation direction and is only deployed in crosstalk sensitive areas.

[0014] Preferably, the crosstalk sensitivity is determined by the coupling coefficient of adjacent waveguides, the equivalent parallel coupling length, and the quantum function weight.

[0015] This invention also discloses a parameter optimization method for high-density integrated silicon photonic quantum waveguide array chips, comprising the following steps: S1. Establish an initial waveguide array model based on the chip application requirements. The initial waveguide array model includes the number of input waveguides, operating wavelength, core layer thickness, initial waveguide width, manufacturing constraint parameters, and low crosstalk performance constraint parameters. S2. Based on the initial waveguide array model, calculate the coupling coefficient, equivalent parallel coupling length, and quantum function weight of each adjacent quantum optical transmission waveguide, and determine the crosstalk sensitivity of each adjacent waveguide pair according to the coupling coefficient, equivalent parallel coupling length, and quantum function weight, so as to obtain the optimization priority of each adjacent waveguide pair. S3. Based on the crosstalk sensitivity of each adjacent waveguide pair, the center spacing between each adjacent waveguide is non-uniformly configured, and the waveguide width, etching depth, cladding perturbation structure or lateral perturbation structure of the adjacent waveguide pairs with crosstalk sensitivity higher than the threshold are further adjusted to form a propagation constant mismatch. S4. For adjacent waveguide pairs that still do not meet the preset crosstalk requirements after the propagation constant mismatch adjustment, a local isolation auxiliary structure is set in the corresponding area, and the position, size and distribution of the local isolation auxiliary structure are jointly optimized. S5. Calculate the crosstalk value, path error probability, quantum state fidelity, interference visibility and insertion loss based on the structure of the optimized waveguide array, and determine whether the preset low crosstalk constraint is met. S6. Based on satisfying the preset low crosstalk constraint, verify the manufacturing tolerance of waveguide width deviation, etching depth deviation and local isolation auxiliary structure size deviation; if the manufacturing tolerance verification result does not meet the preset requirements, return to step S3 or step S4 to continue parameter optimization. S7. Repeat steps S3 to S6 until the optimized waveguide array simultaneously meets the low crosstalk constraint and manufacturing tolerance requirements. S8. Output the final waveguide array layout and corresponding structural parameters.

[0016] Preferably, the non-uniform configuration includes increasing or decreasing the center spacing of adjacent waveguides according to crosstalk sensitivity, and ensuring that the center spacing is not less than the minimum manufacturing spacing.

[0017] Preferably, the manufacturing tolerance verification includes perturbation analysis of waveguide width deviation, etching depth deviation, or local isolation auxiliary structure size deviation.

[0018] Preferably, the final waveguide array layout outputs the center-to-center spacing between adjacent waveguides, waveguide width, propagation constant mismatch parameters, and local isolation auxiliary structure parameters.

[0019] Compared with the prior art, the present invention has the following beneficial effects: By using non-uniform waveguide spacing design, the lateral space of the chip can be preferentially allocated to crosstalk-sensitive areas, reducing the area waste caused by uniform large spacing design; By using asymmetric propagation constant mismatch design, non-target coupling between adjacent waveguides can be weakened without significantly increasing the physical spacing between waveguides; By deploying local isolation auxiliary structures in segments, high-risk areas can be supplemented and suppressed, and the additional losses caused by continuous isolation structures can be reduced. By introducing low crosstalk constraints and manufacturing tolerance verification, the optimized waveguide array can be made more suitable for on-chip quantum information transmission in high-density silicon photonic quantum chips. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall structure of the low crosstalk silicon photonic quantum waveguide array chip of the present invention; Figure 2 This is a schematic diagram of the non-uniform waveguide spacing self-optimization structure of the present invention; Figure 3 This is a schematic diagram of the combined structure of asymmetric propagation constant mismatch and local isolation of the present invention; Figure 4This is a flowchart of the waveguide array parameter optimization method of the present invention; Figure 5 This is a curve comparing the key performance indicators of the present invention before and after optimization. Detailed Implementation

[0021] The present invention will now be clearly and completely described with reference to the accompanying drawings in the embodiments of the present invention.

[0022] The chip structure of this invention includes a silicon substrate 1, a buried oxide layer 2, a silicon waveguide core layer 3, an upper cladding layer 4, multiple quantum optical transmission waveguides 5, a non-uniform spacing region 6, an asymmetric propagation constant mismatch region 7, and a local isolation auxiliary structure region 8. The silicon waveguide core layer 3 is disposed above the buried oxide layer 2, and multiple quantum optical transmission waveguides 5 are formed by etching. The upper cladding layer 4 covers the silicon waveguide core layer 3 and the quantum optical transmission waveguides 5, and is used to stabilize the refractive index environment around the waveguides. The multiple quantum optical transmission waveguides 5 are arranged side-by-side along the chip plane and can be used for on-chip transmission of single photons, weakly coherent light, path-coded quantum states, or phase-coded quantum states. This invention sets a non-uniform center spacing between different adjacent waveguide pairs, so that the center spacing of at least two sets of adjacent quantum optical transmission waveguides 5 is different. For waveguide pairs with high crosstalk sensitivity, long equivalent parallel coupling length, or located in the quantum interference region or path coding region, a larger center spacing can be set; for waveguide pairs with low crosstalk risk or short parallel coupling length, a smaller center spacing can be set while meeting manufacturing constraints.

[0023] In the asymmetric propagation constant mismatch region 7, the present invention creates a propagation constant mismatch between adjacent waveguides by making at least one group of adjacent quantum optical transmission waveguides have different waveguide widths, etching depths, local cladding perturbation structures, or lateral perturbation structures. This propagation constant mismatch weakens the phase matching condition between adjacent waveguides, helping to reduce non-target coupling. For regions where a high risk of crosstalk still exists after spacing adjustment and propagation constant mismatch, the present invention provides a local isolation auxiliary structure between adjacent quantum optical transmission waveguides. This local isolation auxiliary structure can be at least one of shallow etched grooves, low-refractive-index isolation grooves, subwavelength perturbation structures, or lateral microgrooves, and is preferably segmented along the light propagation direction to reduce mode overlap while minimizing the additional scattering loss and process complexity that continuous isolation structures may introduce.

[0024] This invention employs a parameter optimization control module to generate waveguide array structural parameters during the chip design phase. This module determines structural parameters such as the center-to-center spacing d_i between adjacent waveguides, waveguide width w_i, propagation constant mismatch Δβ_i, local isolation slot width g_i, and local isolation slot length s_i, based on the waveguide number N, operating wavelength λ, core layer thickness h, initial waveguide width w_0, minimum manufacturing pitch d_min, maximum array width W_max, manufacturing width deviation Δw, etching depth deviation Δh, and quantum functionality requirements of different regions. The parameter optimization method includes: establishing an initial waveguide array model; calculating the crosstalk sensitivity between adjacent waveguides; jointly optimizing the waveguide center-to-center spacing, waveguide width, propagation constant mismatch, and local isolation structure according to low crosstalk constraints; verifying manufacturing tolerances; iteratively updating relevant structural parameters when constraints are not met; and outputting the final waveguide array layout and structural parameters.

[0025] In one alternative implementation, the propagation constant of the i-th waveguide can be expressed as: β_i=(2πn_(eff,i)) / λ, Where n_(eff,i) is the effective refractive index of the i-th waveguide at the target operating wavelength, which can be obtained through mode solving or equivalent refractive index calculation. The propagation constant mismatch between adjacent waveguides can be expressed as: Δβ_i = |β_i - β_(i+1) |, To comprehensively evaluate the crosstalk risk of adjacent waveguide pairs, crosstalk sensitivity can be used: R_i=q_i κ_i L_i, Where κ_i represents the coupling coefficient of the i-th pair of adjacent waveguides, L_i represents the equivalent parallel coupling length, and q_i represents the quantum function weight of the corresponding region. The coupling coefficient reflects the coupling strength between adjacent waveguides, the equivalent parallel coupling length reflects the coupling distance, and the quantum function weight reflects the sensitivity of the region to crosstalk. Therefore, the product of these three factors can be used to characterize the overall crosstalk risk of adjacent waveguide pairs. Parameters such as d_i, w_i, Δβ_i, g_i, and s_i can be adjusted according to the magnitude of R_i.

[0026] The following constraints may be adopted during the optimization process of this invention: C_i≤C_th, P_err≤P_th, F≥F_th, V≥V_th, IL≤IL_th, d_max≥d_i≥d_min, Where C_i represents the crosstalk value of the i-th pair of adjacent waveguides, P_err represents the path error probability, F represents the quantum state fidelity, V represents the interference visibility, IL represents the insertion loss, C_th, P_th, F_th, V_th, and IL_th are the corresponding thresholds, d_min is the minimum manufacturing spacing, and d_max is the maximum manufacturing spacing. These constraints allow structural optimization to consider not only ordinary power crosstalk but also quantum state transmission quality and manufacturing feasibility.

[0027] like Figure 1 As shown, the low crosstalk silicon quantum waveguide array of the present invention includes a silicon substrate 1, a buried oxide layer 2, a silicon waveguide core layer 3, an upper cladding layer 4, and multiple quantum optical transmission waveguides 5. The silicon substrate 1 serves as the chip structure, the buried oxide layer 2 is disposed on top of the silicon substrate 1, the silicon waveguide core layer 3 is disposed on top of the buried oxide layer 2, and multiple quantum optical transmission waveguides 5 are formed by etching. The upper cladding layer 4 covers the silicon waveguide core layer 3 and the multiple quantum optical transmission waveguides 5 to form a relatively stable refractive index environment. Figure 1 W1 to W5 in the diagram represent five quantum optical transmission waveguides, and d1 to d4 are the center-to-center distances between adjacent W1 to W5, serving as an example of a multi-channel waveguide array. In practical applications, the number of quantum optical transmission waveguides can be expanded to N depending on the chip's functional requirements.

[0028] Figure 1 The top view of the chip schematically shows the input coupling region, the output coupling region, and the waveguide array main body region located between them. The waveguide array main body region includes a non-uniform spacing region 6, an asymmetric propagation constant mismatch region 7, and a local isolation auxiliary structure region 8. It should be noted that the above three regions can be overlapped or segmented in the optical propagation direction according to the crosstalk sensitivity. For example, the local isolation auxiliary structure region 8 can be set in a high-risk local position within the non-uniform spacing region 6 or the asymmetric propagation constant mismatch region 7. Figure 1 The cross section C-C' in the figure is used to show the hierarchical relationship between the silicon substrate 1, the buried oxide layer 2, the silicon waveguide core layer 3, the upper cladding layer 4, and the quantum optical transmission waveguide 5, illustrating that the waveguide array can be formed on a silicon-based photonic integration platform.

[0029] like Figure 2 As shown, in this embodiment, the crosstalk sensitivity R_i of each pair of adjacent waveguides is calculated according to step S3. Subsequently, the control module determines the corresponding center spacing d_i sequentially according to the magnitude of R_i, and generates... Figure 2The non-uniform spacing distribution is shown. For an adjacent waveguide pair consisting of the i-th waveguide and the (i+1)-th waveguide, the center-to-center spacing is denoted as d_i. The system can determine the crosstalk sensitivity R_i based on the equivalent parallel coupling length L_i, coupling coefficient κ_i, quantum function weight q_i, and initial crosstalk level of the adjacent waveguide pair. When R_i is high, it indicates that the adjacent waveguide pair is more sensitive to crosstalk, and the corresponding center-to-center spacing d_i can be appropriately increased; when R_i is low, d_i can be appropriately decreased under the condition that it is not less than the minimum manufacturing spacing d_min, and the total array width W_total should not exceed the maximum array width W_max. Figure 2 The bar chart below is used to represent the non-uniform spacing distribution of different adjacent waveguide pairs, illustrating that different waveguide pairs can use different center spacings.

[0030] like Figure 3 As shown, in the asymmetric propagation constant mismatch region 7, this invention enables at least one set of adjacent quantum optical transmission waveguides to have different structural parameters. After completion... Figure 2 After the spacing optimization shown, for waveguide pairs where the crosstalk sensitivity R_i is still higher than the preset crosstalk sensitivity threshold R_th, the control module continues to adjust the waveguide width w_i or the etching depth to form... Figure 3 The region of propagation constant mismatch is shown.

[0031] Taking the first quantum optical transmission waveguide 5a and the second quantum optical transmission waveguide 5b as examples, they can have different waveguide widths w_1 and w_2, respectively, and can also form different effective refractive indices through different etching depths, cladding perturbation structures, or lateral perturbation structures. Therefore, a propagation constant mismatch Δβ is formed between the propagation constant β_1 of the first quantum optical transmission waveguide 5a and the propagation constant β_2 of the second quantum optical transmission waveguide 5b. This propagation constant mismatch can weaken the phase matching condition between adjacent waveguides, thereby helping to reduce non-target energy transfer.

[0032] See also Figure 3 When certain local areas still have a high risk of crosstalk after completing the non-uniform spacing design and propagation constant mismatch design, a local isolation auxiliary structure region 8 can be set between adjacent quantum optical transmission waveguides. The local isolation auxiliary structure region 8 can be at least one of shallow etched grooves, low refractive index isolation grooves, subwavelength perturbation structures, or lateral microgrooves. Compared with continuous isolation structures, the local isolation auxiliary structure region 8 is preferably arranged in segments along the optical propagation direction and only set in local locations with high crosstalk risk, so as to reduce additional scattering loss and process complexity while reducing mode overlap. Figure 3 The magnified section A is used to show the waveguide width difference and the positional relationship of the isolation auxiliary structure, while the schematic section B is used to show the hierarchical relationship between the local isolation auxiliary structure region 8 and the silicon substrate 1, buried oxide layer 2, silicon waveguide core layer 3 and upper cladding layer 4.

[0033] like Figure 4 As shown, the parameter optimization method of the present invention includes steps S1 to S8: S1 represents the design requirements input. Based on the chip application scenario, the following parameters are input: waveguide number N, operating wavelength λ, core layer thickness h, initial waveguide width w_0, minimum manufacturing pitch d_min, maximum manufacturing pitch d_max, maximum array width W_max, manufacturing width deviation Δw, etching depth deviation Δh, as well as crosstalk threshold C_th, path error probability threshold P_th, quantum state fidelity threshold F_th, interference visibility threshold V_th, and insertion loss threshold IL_th. These parameters serve as input conditions for subsequent structural modeling and optimization calculations.

[0034] S2 establishes the initial waveguide array model. Based on the input parameters, an initial waveguide array layout with equal spacing and width is established, and the functional divisions of the input coupling region, parallel transmission region, quantum interference region, path selection region, and output coupling region are completed (see [link to relevant documentation]). Figure 2 This step can extract information such as the initial center spacing, initial waveguide width, adjacent waveguide pair index i, and equivalent parallel coupling length L_i, providing a basic model for subsequent crosstalk analysis.

[0035] S3 involves crosstalk analysis and sensitivity assessment. Based on the initial waveguide array model, the coupling coefficient κ_i, equivalent parallel coupling length L_i, and quantum function weight q_i of adjacent waveguides are calculated, and the crosstalk sensitivity R_i is obtained. In this step, the coupling coefficient κ_i reflects the coupling strength between adjacent waveguides, the equivalent parallel coupling length L_i reflects the coupling distance, and the quantum function weight q_i reflects the sensitivity of different regions to crosstalk. By combining these factors, the optimization priority of different adjacent waveguide pairs can be determined.

[0036] S4 is a joint parameter optimization. Based on the crosstalk sensitivity ranking results, it jointly updates the waveguide center spacing, propagation constant mismatch, and local isolation structure. According to the crosstalk sensitivity R_i and preset design constraints, it jointly optimizes the adjacent waveguide center spacing d_i, waveguide width w_i, propagation constant mismatch Δβ_i, local isolation slot width g_i, and local isolation slot length s_i. For waveguide pairs with high crosstalk sensitivity, d_i can be increased first, and w_i or Δβ_i can be adjusted accordingly. For regions where local high-risk coupling still exists, local isolation auxiliary structures corresponding to g_i and s_i can be further set. For waveguide pairs with low crosstalk sensitivity, the spacing can be appropriately reduced while ensuring d_i ≥ d_min, to improve the layout area utilization.

[0037] S5 is the low crosstalk constraint verification. The key performance parameters of the waveguide array are recalculated using the optimized structural parameters, including crosstalk value C_i, path error probability P_err, quantum state fidelity F, interferometric visibility V, and insertion loss IL. If any of these parameters satisfy C_i≤C_th, P_err≤P_th, F≥F_th, V≥V_th, and IL≤IL_th, the subsequent manufacturing tolerance verification can proceed; if any parameter fails to meet the constraint, the process returns to S4 to readjust the structural parameters.

[0038] S6 is for manufacturing tolerance verification. While meeting the low crosstalk constraint, perturbation analysis is performed on manufacturing deviations such as waveguide width, etching depth, isolation trench size, and cladding thickness to evaluate the impact of manufacturing errors on crosstalk performance and quantum transmission performance. This step can use perturbation sampling methods for Δw, Δh, g_i, and s_i to recalculate C_i, P_err, F, V, and IL. If a manufacturing deviation causes a performance indicator to exceed a preset range, the process returns to the parameter optimization step.

[0039] S7 is the iterative optimization. Based on the verification results of S5 and S6, the parameters d_i, w_i, Δβ_i, g_i, and s_i are updated, and crosstalk analysis, joint parameter optimization, low crosstalk constraint verification, and manufacturing tolerance verification are repeated. By repeatedly executing S3 to S6, a relatively balanced combination of structural parameters can be obtained among area constraints, low crosstalk constraints, and manufacturing tolerance constraints.

[0040] S8 outputs the final waveguide array layout and parameters. Once the waveguide array meets preset area constraints, low crosstalk constraints, and manufacturing tolerance requirements, the final waveguide array layout and corresponding structural parameters are output. These structural parameters may include the center-to-center distance d_i between adjacent waveguides, the width w_i of each waveguide, the propagation constant mismatch Δβ_i, the width g_i of the local isolation slot, and the length s_i of the local isolation slot. The output results can serve as the basis for subsequent chip layout design, process verification, and manufacturing document generation.

[0041] Finish Figure 4 After the optimization process shown, the final waveguide array was used for simulation verification, and the results were obtained. Figure 5 The results are shown. Figure 5 As shown, this invention can compare the key performance indicators of the traditional equal-spacing and equal-width scheme with the optimized waveguide array scheme of this invention under a set of example design parameters. Figure 5 Taking a five-channel waveguide array as an example, the trends of crosstalk value C_i, insertion loss IL, quantum state fidelity F, interference visibility V, and path error probability P_err as a function of channel number are shown. Figure 5The results shown illustrate the changing trends of key indicators before and after optimization, and do not limit the specific values ​​of this invention under different process platforms, different numbers of waveguides, or different chip sizes. This exemplary comparison can be used to demonstrate that this invention has certain technical effects in reducing crosstalk between adjacent waveguides, reducing the probability of path errors, and improving the quality of on-chip quantum state transmission.

[0042] In one embodiment, the chip operating wavelength can be 1550 nm, and the silicon waveguide core layer thickness can be determined based on the SOI process platform. The system generates an initial equidistant waveguide array based on the input / output ports and functional area division, and calculates the coupling coefficient κ_i and equivalent parallel coupling length L_i of adjacent waveguides. When an adjacent waveguide pair is located in the quantum interference region or path coding region, a higher quantum function weight q_i can be set; when an adjacent waveguide pair is only located in the short-distance connection region, a lower quantum function weight q_i can be set. The system generates different center spacings d_i accordingly, and further applies propagation constant mismatch Δβ_i or local isolation auxiliary structure region 8 to high-risk regions. After low crosstalk constraint verification and manufacturing tolerance verification, a waveguide array layout that meets the design requirements can be output.

Claims

1. A silicon photonic quantum waveguide array chip for high-density integration, characterized in that, The array includes a silicon substrate (1), a buried oxide layer (2), a silicon waveguide core layer (3), and an upper cladding layer (4) arranged from bottom to top, and multiple quantum optical transmission waveguides (5) formed in the silicon waveguide core layer (3); the multiple quantum optical transmission waveguides (5) are arranged side by side along the chip plane and form at least two sets of adjacent quantum optical transmission waveguides; a non-uniform spacing region (6) is provided between adjacent quantum optical transmission waveguides, and at least two sets of adjacent quantum optical transmission waveguides in the non-uniform spacing region (6) have different center spacings; at least one set of adjacent quantum optical transmission waveguides is provided with an asymmetric propagation constant mismatch region (7) that makes the adjacent quantum optical transmission waveguides have different propagation constants; a local isolation auxiliary structure region (8) is provided between at least one set of adjacent quantum optical transmission waveguides; wherein, the non-uniform spacing region (6), the asymmetric propagation constant mismatch region (7), and the local isolation auxiliary structure region (8) between different adjacent quantum optical transmission waveguides constitute a low crosstalk structure of a high-density integrated silicon photonic quantum waveguide array.

2. The silicon photonic quantum waveguide array chip for high-density integration according to claim 1, characterized in that, The asymmetric propagation constant mismatch region (7) is formed by changing at least one of the waveguide width, etching depth, cladding perturbation structure or lateral perturbation structure of the adjacent quantum optical transmission waveguide. The local isolation auxiliary structure region (8) includes at least one of the following: shallow etching groove, low refractive index isolation groove, subwavelength perturbation structure or lateral microgroove arranged in sections along the optical propagation direction.

3. The silicon photonic quantum waveguide array chip for high-density integration according to claim 1, characterized in that, The three regions—the non-uniform spacing region (6), the asymmetric propagation constant mismatch region (7), and the local isolation auxiliary structure region (8)—are configured to overlap or be segmented in the direction of light propagation according to crosstalk sensitivity, and the front and rear positions of the three regions are not fixed.

4. The silicon photonic quantum waveguide array chip for high-density integration according to claim 1, characterized in that, In the non-uniform spacing region (6), the center spacing of each adjacent quantum optical transmission waveguide is set to different values ​​according to the crosstalk sensitivity.

5. The silicon photonic quantum waveguide array chip for high-density integration according to claim 1, characterized in that, The asymmetric propagation constant mismatch region (7) is formed by the difference in width, etching depth, cladding disturbance or lateral disturbance between adjacent waveguides.

6. The silicon photonic quantum waveguide array chip for high-density integration according to claim 3, characterized in that, The local isolation auxiliary structure region (8) is segmented along the direction of light propagation and is only deployed in crosstalk sensitive areas.

7. The silicon photonic quantum waveguide array chip for high-density integration according to claim 3, characterized in that, The crosstalk sensitivity is determined by the coupling coefficient of adjacent waveguides, the equivalent parallel coupling length, and the quantum function weight.

8. A parameter optimization method for high-density integrated silicon photonic quantum waveguide array chips, implemented using the chip described in any one of claims 1-7, characterized in that... Includes the following steps: S1. Establish an initial waveguide array model based on the chip application requirements. The initial waveguide array model includes the number of input waveguides, operating wavelength, core layer thickness, initial waveguide width, manufacturing constraint parameters, and low crosstalk performance constraint parameters. S2. Based on the initial waveguide array model, calculate the coupling coefficient, equivalent parallel coupling length, and quantum function weight of each adjacent quantum optical transmission waveguide, and determine the crosstalk sensitivity of each adjacent waveguide pair according to the coupling coefficient, equivalent parallel coupling length, and quantum function weight, so as to obtain the optimization priority of each adjacent waveguide pair. S3. Based on the crosstalk sensitivity of each adjacent waveguide pair, the center spacing between each adjacent waveguide is non-uniformly configured, and the waveguide width, etching depth, cladding perturbation structure or lateral perturbation structure of the adjacent waveguide pairs with crosstalk sensitivity higher than the threshold are further adjusted to form a propagation constant mismatch. S4. For adjacent waveguide pairs that still do not meet the preset crosstalk requirements after the propagation constant mismatch adjustment, a local isolation auxiliary structure is set in the corresponding area, and the position, size and distribution of the local isolation auxiliary structure are jointly optimized. S5. Calculate the crosstalk value, path error probability, quantum state fidelity, interference visibility and insertion loss based on the structure of the optimized waveguide array, and determine whether the preset low crosstalk constraint is met. S6. Based on satisfying the preset low crosstalk constraint, verify the manufacturing tolerance of waveguide width deviation, etching depth deviation and local isolation auxiliary structure size deviation; if the manufacturing tolerance verification result does not meet the preset requirements, return to step S3 or step S4 to continue parameter optimization. S7. Repeat steps S3 to S6 until the optimized waveguide array simultaneously meets the low crosstalk constraint and manufacturing tolerance requirements. S8. Output the final waveguide array layout and corresponding structural parameters.

9. The parameter optimization method according to claim 8, characterized in that, The non-uniform configuration includes increasing or decreasing the center spacing of adjacent waveguides according to crosstalk sensitivity, and ensuring that the center spacing is not less than the minimum manufacturing spacing.

10. The parameter optimization method according to claim 8, characterized in that, The manufacturing tolerance verification includes perturbation analysis of waveguide width deviation, etching depth deviation, or local isolation auxiliary structure size deviation.

11. The parameter optimization method according to claim 8, characterized in that, The final waveguide array layout outputs the center-to-center spacing between adjacent waveguides, waveguide width, propagation constant mismatch parameters, and local isolation auxiliary structure parameters.

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