A computer memory overclocking method, system, electronic device and storage medium

Abstract

The application discloses a computer memory overclocking method and system, electronic equipment and storage medium. The method comprises the following steps: in response to a memory overclocking start instruction, starting a memory reference code (MRC) module to perform training on the memory, the training comprising multiple training stages; recording the training progress through a preset CMOS bit, setting a corresponding mark after passing through each training stage, and then entering the next training stage; when the training fails, determining a failure node, recording the current training parameters to a buffer area, amplifying the training data domain by a preset ratio according to the parameters of the last training, and re-executing the training from the failure node; when all the training stages are passed, completing the overclocking and normally starting; and when the number of training reaches a preset threshold, exiting the training. The application can inherit the historical training parameters and continue the training from the failure node when the training fails, automatically expand the training data domain, improve the success rate and stability of the high-frequency memory overclocking, and reduce the difficulty of the overclocking operation.

Description

Technical Field

[0001] This invention relates to the field of computer hardware technology, and in particular to a method, system, electronic device, and computer-readable storage medium for overclocking computer memory. Background Technology

[0002] Memory overclocking refers to adjusting parameters such as the memory's operating frequency, timings, and voltage to make the memory run at a frequency higher than its nominal specifications, thereby improving the overall performance of the computer. Currently, computer memory overclocking is generally performed according to the specifications provided by the memory manufacturer. For example, after enabling the Extreme Memory Profile (XMP) function, the Memory Reference Code (MRC) module in the motherboard firmware initializes and trains the memory according to the XMP configuration file to ensure that the memory runs stably at the target frequency and completes the boot process.

[0003] During training, the MRC module needs to scan within a certain voltage and timing range to train a sufficiently wide data domain (i.e., a parameter window that allows the memory to operate stably), thus enabling the memory to stably pass through each training stage. However, the inventors have discovered in practice that the existing technology has at least the following technical problems: Firstly, existing memory overclocking methods have significant limitations on the compatibility of computer components, resulting in low training success rates and high overclocking difficulty at high frequencies. Secondly, in existing technologies, when a training phase fails, the entire training process can usually only be re-executed from the initial state. The training progress and training parameters already obtained cannot be effectively inherited, resulting in a long overclocking process and a low success rate. Third, existing overclocking operations require a high level of expertise from operators, making them difficult for ordinary users to perform, failing to meet the needs of special customer groups, and failing to fully utilize the computer's performance.

[0004] Therefore, how to improve the success rate of the training phase and reduce the difficulty of overclocking during memory overclocking has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a computer memory overclocking method, system, electronic device and computer-readable storage medium to solve the technical problems of low training success rate, high overclocking difficulty and high professional requirements of memory overclocking at high frequency in the prior art.

[0006] In a first aspect, embodiments of the present invention provide a method for overclocking computer memory, comprising: In response to a memory overclocking startup command, the memory reference code (MRC) module is initiated to train the memory. This training includes multiple sequential training phases. During training, the training progress is recorded using preset CMOS bits. Each time a training phase is completed, a flag corresponding to the completed phase is set in the CMOS bits, and the process proceeds to the next training phase. When the current training phase fails, it is designated as a failure node. The current training parameters are recorded in a preset buffer, and the training data domain is amplified according to a preset ratio, referencing the previous training failure node and parameters stored in the buffer. Referring to the failed nodes and training parameters of the previous training session stored in the buffer, the training data domain is enlarged according to a preset ratio, including: obtaining the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure stored in the buffer; expanding the scanning range of the training parameters according to a preset ratio based on the difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure, to obtain the enlarged training data domain; re-executing training from the failed node based on the enlarged training data domain; completing memory overclocking and booting up normally when all training stages are successfully completed; and exiting training when the number of training iterations reaches a preset training iteration threshold.

[0007] In one possible implementation, the step of starting the MRC module to perform memory training in response to the memory overclocking start command includes: generating the memory overclocking start command when the memory limit configuration XMP function is detected to be enabled; starting the MRC module and performing memory training on the memory based on the target memory parameters in the XMP configuration file.

[0008] In one possible implementation, recording the training progress using preset CMOS bits includes: allocating corresponding bits in the CMOS bits to each of the plurality of training stages; when any training stage is successfully completed, setting the bit corresponding to that training stage to a valid state as a marker corresponding to the completed training stage.

[0009] In one possible implementation, the training data domain includes at least one of a reference voltage scan range and a timing scan range; the difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure has a corresponding relationship with the preset ratio: the larger the difference, the larger the preset ratio; the smaller the difference, the closer the current training parameters are to the hardware physical boundary of the memory, and the smaller the preset ratio; when expanding the scan range of the training parameters according to the preset ratio, the boundary of the scan range is expanded or reduced in a minimum adjustment unit of ±4, and the boundary of the expanded training data domain does not exceed the hardware physical boundary of the memory.

[0010] In one possible implementation, the training count threshold is preset by the user based on the target frequency of the memory, wherein the higher the target frequency, the larger the training count threshold.

[0011] In one possible implementation, re-executing training from the failed node based on the amplified training data domain includes: reading the flags set in the CMOS bits to determine the training phases that have been passed; skipping the passed training phases and re-executing training based on the amplified training data domain starting from the training phase corresponding to the failed node.

[0012] In one possible implementation, the method further includes: before each re-execution of training, counting the number of training iterations; when the number of training iterations reaches the training iteration threshold and the training still fails, exiting the training and outputting a training failure message.

[0013] Secondly, embodiments of the present invention provide a computer memory overclocking system, comprising: The training module, in response to a memory overclocking start command, initiates the memory reference code (MRC) module to train the memory, wherein the training includes multiple training stages performed sequentially. The recording module, during training, records the training progress using preset CMOS bits. Each time a training stage is completed, a marker corresponding to the completed training stage is set in the CMOS bits, and the process proceeds to the next training stage. The retraining module, when the current training stage fails, identifies the current training stage as a failure node, records the current training parameters in a preset buffer, and, referring to the previous training failure node and training parameters stored in the buffer, amplifies the training data according to a preset ratio. The training data domain, wherein the reference to the failed nodes and training parameters of the previous training stored in the buffer, is amplified according to a preset ratio, including: obtaining the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure stored in the buffer; expanding the scanning range of the training parameters according to a preset ratio based on the difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure, to obtain the amplified training data domain, and re-executing training from the failed node based on the amplified training data domain; a control module, used to complete memory overclocking and normal power-on when all training stages are successfully completed; and to exit training when the number of training times reaches a preset training time threshold.

[0014] Thirdly, embodiments of the present invention provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the computer memory overclocking method as described in any of the first aspects.

[0015] Fourthly, embodiments of the present invention provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the computer memory overclocking method as described in any of the first aspects.

[0016] The technical solutions provided in the embodiments of the present invention have at least the following beneficial effects compared with the prior art: (1) The training progress is recorded in stages by the preset CMOS bits. After the training fails, the training can continue from the failure node without having to start the entire training process from the beginning, thus shortening the training time. (2) When training fails, the training parameters are recorded in the buffer, and the training data domain is enlarged according to the preset ratio based on the failure node and training parameters of the previous training, so that the training parameters can be iteratively optimized and the memory can complete the training within a wider parameter range, thereby improving the success rate and stability of memory overclocking training at high frequency. (3) Users can set a training number threshold based on memory frequency. When the threshold is reached, the training will be terminated in time. The entire overclocking process is completed automatically. Users do not need to have professional overclocking knowledge, which reduces the difficulty of overclocking and improves the user experience. Attached Figure Description

[0017] Figure 1 This is a structural block diagram of the computer memory overclocking system provided in an embodiment of the present invention; Figure 2 This is a flowchart of a computer memory overclocking method provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a CMOS bit marker provided in an embodiment of the present invention; Figure 4 This is a magnified schematic diagram of the training data domain provided in an embodiment of the present invention. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] First, the relevant terms involved in the embodiments of the present invention will be explained: XMP (Extreme Memory Profile) refers to a configuration file pre-written by the memory manufacturer, containing parameters such as target frequency, timings, and voltage. MRC (Memory Reference Code) refers to the code module in the motherboard firmware used for memory initialization and training. Training refers to the process by which the MRC module scans and calibrates parameters such as memory read / write timings and reference voltages during the boot process to determine the parameters that enable the memory to work stably. CMOS bits refer to readable and writable storage bits in the Complementary Metal-Oxide-Semiconductor (CMOS) memory area of ​​the motherboard, and their stored contents can be retained after the computer is powered off and restarted. The buffer is a storage area reserved by the MRC module during training to record training parameters and training status. The training data domain refers to the scanning range of training parameters during the training process, including the reference voltage scanning range and / or timing scanning range. The wider the data domain, the larger the parameter window that can be stably operated in memory.

[0020] Example 1: Figure 1 This is a structural block diagram of a computer memory overclocking system provided in an embodiment of the present invention.

[0021] like Figure 1 As shown, the computer memory overclocking system 100 includes: a training module 110, a recording module 120, a retraining module 130, and a control module 140.

[0022] The training module 110 is used to start the memory reference code (MRC) module to perform training on the memory 200 in response to the memory overclocking start command. The training includes multiple training phases performed in sequence, such as initialization phase, read training phase, write training phase, reference voltage training phase, etc.

[0023] The recording module 120 is used to record the training progress through preset CMOS bits during the training process. After each training stage is passed, a mark corresponding to the passed training stage is set in the CMOS bits, and the next training stage is entered.

[0024] The retraining module 130 is used to determine the current training stage as a failure node when training fails in the current training stage, record the current training parameters in a preset buffer, and expand the training data domain according to a preset ratio by referring to the previous training failure node and training parameters stored in the buffer. The expansion of the training data domain according to the preset ratio by referring to the previous training failure node and training parameters stored in the buffer includes: obtaining the training parameters stored in the buffer at the time of the previous training failure and the training parameters at the time of the current training failure; expanding the scanning range of the training parameters according to the preset ratio based on the difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure, obtaining the expanded training data domain, and re-executing training from the failure node based on the expanded training data domain.

[0025] The control module 140 is used to complete memory overclocking and power on normally when all training stages have passed, and to exit training when the number of training sessions reaches the preset training session threshold.

[0026] It should be noted that the training module 110, recording module 120, retraining module 130 and control module 140 mentioned above can be implemented by the motherboard firmware (such as the MRC module in BIOS or UEFI) executing the corresponding logic. The division of each module is only exemplary. In actual implementation, they can be merged or further split as needed. Any implementation method that can achieve the above functions should fall within the protection scope of this invention.

[0027] Example 2: Figure 2 A flowchart illustrating a computer memory overclocking method provided in an embodiment of the present invention. Figure 2 As shown, the method includes the following steps: Step S101: In response to the memory overclocking start command, the MRC module is started to train the memory. Specifically, when the user enables the memory's XMP function in the motherboard firmware settings interface, a memory overclocking start command is generated; after the MRC module starts, it reads the target memory parameters (target frequency, target timings, target voltage, etc.) from the XMP configuration file and performs memory training based on the target memory parameters. The training includes multiple training phases performed sequentially, such as an initialization phase, a read training phase, a write training phase, and a reference voltage training phase.

[0028] Step S102: Execute the current training phase and determine whether the current training phase has passed.

[0029] Step S103: If the current training stage is successful, set the flag corresponding to the successful training stage in the CMOS bit, and determine whether all training stages have been successful; if all have been successful, complete the memory overclocking and boot normally; if not all have been successful, proceed to the next training stage and return to step S102.

[0030] Specifically, such as Figure 3 As shown, in this embodiment, each training stage in the multiple training stages is assigned a corresponding bit in the CMOS bit, for example, bits 0 to 7 correspond to stages 1 to 8 respectively; when any training stage is successfully trained, the bit corresponding to that training stage is set to a valid state (e.g., set to 1) as a marker corresponding to the successfully trained stage. Figure 3 Bits 0 to 2 are set to 1, indicating that stages 1 to 3 have been completed; bit 3 is 0, and its corresponding stage 4 is the current training stage. When stage 4 training fails, stage 4 is identified as a failure node. Since the stored content of the CMOS bits can be retained after the computer is powered off and restarted, the training progress can still be restored based on the CMOS bits even after the system restarts following a training failure.

[0031] Step S104: If the current training phase fails, the failure node is identified, and the current training parameters are recorded in the buffer. Specifically, when the current training phase fails, the current training phase is identified as the failure node, and the training parameters used in this training (including reference voltage, timing parameters, etc.) and the failure node information are recorded in a preset buffer for reference in subsequent training; the buffer can also store the failure node and training parameters from the previous training.

[0032] Step S105: Referencing the parameters from the previous training iteration, expand the training data domain according to a preset ratio. Specifically, obtain the training parameters stored in the buffer from the time of the previous training failure and the training parameters from the time of this training failure. Based on the difference between the two, expand the scanning range of the training parameters according to a preset ratio to obtain the expanded training data domain. For example... Figure 4 As shown, the solid rectangle represents the original training data domain, and the dashed rectangle represents the training data domain enlarged by a preset ratio. The training data domain includes at least one of a reference voltage scan range and a timing scan range. For example, the preset ratio could be 1.2, meaning that after each training failure, the upper and lower limits of the reference voltage scan range are expanded by 20%, and / or the timing scan range is expanded by 20%, thereby rescanning within a larger parameter range to train a sufficiently wide data domain, enabling the memory to pass the training phase faster and more stably.

[0033] Furthermore, the training parameters at the time of the previous training failure, the training parameters at the time of the current training failure, and the parameters at the time of the final training success are all limited by the physical hardware boundaries of the memory. As the training data domain is successively enlarged, the scanning range of the training parameters gradually approaches the physical hardware limit, effectively covering the physical limit. In extreme overclocking scenarios, the closer the training parameters are to the physical hardware limit, the higher the training success rate. Moreover, the parameter values ​​that are successfully trained are usually the boundary values ​​that are closest to the physical hardware limit, thereby improving the stability and success rate of subsequent parameter training.

[0034] Correspondingly, there is a relationship between the difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure and the preset ratio: when the difference between the two failed training parameters is large, it indicates that there is still a large margin between the current scanning range and the physical boundary of the hardware, and a larger preset ratio can be used to quickly expand the scanning range and approach the physical boundary; when the difference is small, it indicates that the current training parameters are close to the physical boundary of the hardware, and a smaller preset ratio can be used to avoid the scanning range from exceeding the physical boundary and causing the training to be invalid, and the boundary of the enlarged training data domain does not exceed the physical boundary of the memory.

[0035] Specifically, in each training phase, each training node at the corresponding frequency has a specific preset default value as a reference. The bytes of each training node include the left boundary (Left), right boundary (Right), width (Width), and center value (Center) of the training interval. When the training result is successful, the corresponding parameter value that finally takes effect is generated, and the process moves to the next training node. When the training fails, the boundaries of the existing failed training parameters of the failed node are marked, and the CMOS marker bit is recorded. When training restarts from the failed node, the training interval is expanded or shrunk in increments of ±4 units until the node parameters are successfully trained, and then the process moves to the next training node to continue execution.

[0036] Next, it is determined whether the number of training iterations has reached the preset training iteration threshold: if not, training is re-executed from the failed node, i.e., returning to step S102; if it has reached the threshold, training is exited. Specifically, before each re-execution of training, the number of training iterations already executed is counted; when the number of training iterations already executed has not reached the training iteration threshold, the flag set in the CMOS bit is read to determine the passed training stage, the passed training stage is skipped, and training is re-executed from the training stage corresponding to the failed node, based on the amplified training data domain; when the number of training iterations already executed has reached the training iteration threshold and training still fails, training is exited, and a training failure prompt message can be output, such as prompting the user that the current memory quality or platform configuration cannot stably run at the target frequency, suggesting reducing the target frequency or replacing the components.

[0037] The training count threshold can be preset by the user based on the target memory frequency; the higher the target frequency, the larger the training count threshold. For example, when the target frequency does not exceed 6000MT / s, the training count threshold can be set to 3 times; when the target frequency is between 6000MT / s and 7200MT / s, the training count threshold can be set to 5 times; and when the target frequency is higher than 7200MT / s, the training count threshold can be set to 8 times. Therefore, users can adjust the training count appropriately according to the memory frequency, balancing overclocking success rate with time cost and exiting the program in a timely manner.

[0038] Application Example: Taking DDR5 memory overclocked to 7200MT / s on a motherboard platform as an example. After the user enables XMP, the MRC module performs training according to the XMP configuration file. The training includes eight training stages, from stage 1 to stage 8. The user sets the training count threshold to 5 times based on the target frequency. During training, stages 1 to 3 pass sequentially, and the recording module sets bits 0 to 2 in the CMOS to 1. If the first training in stage 4 (writing training stage) fails, the retraining module identifies stage 4 as the failure node, records the current training parameters in the buffer, and expands the reference voltage scan range at a ratio of 1.2 based on the previous training parameters, and re-executes training from stage 4. If the second training in stage 4 passes, the recording module sets bit 3 to 1 and continues to execute subsequent stages. If it fails again, the above process of expanding the training data domain and retraining is repeated until all training stages pass and the system boots up normally, or the training count reaches 5 times and then training exits. After repeated debugging and verification, the method of this embodiment significantly improved the memory overclocking success rate of the 7200MT / s high-frequency band on the platform, and the overclocking process did not require users to manually adjust the training parameters, simplifying the overclocking difficulty.

[0039] Example 3: This embodiment of the invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the computer memory overclocking method described in any of the above embodiments. The electronic device is, for example, a desktop computer, a laptop computer, a server, or a motherboard testing device.

[0040] Example 4: This embodiment of the invention also provides a computer-readable storage medium storing a computer program thereon. When the computer program is executed by a processor, it implements the steps of the computer memory overclocking method described in any of the above embodiments. The computer-readable storage medium is, for example, a motherboard firmware storage chip (e.g., SPI Flash), a read-only memory (ROM), a random access memory (RAM), or other media capable of storing program code.

[0041] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. The terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0042] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A method for overclocking computer memory, characterized in that, The method includes: In response to the memory overclocking start command, the memory reference code MRC module is started to perform training on the memory, wherein the training includes multiple training phases performed sequentially; During the training process, the training progress is recorded through preset CMOS bits. Each time a training stage is completed, a flag corresponding to the completed training stage is set in the CMOS bits, and the next training stage is started. When training fails in the current training phase, the current training phase is identified as a failure node. The current training parameters are recorded in a preset buffer. Referring to the previous training failure node and training parameters stored in the buffer, the training data domain is enlarged according to a preset ratio. This enlargement of the training data domain, referring to the previous training failure node and training parameters stored in the buffer, includes: obtaining the training parameters stored in the buffer at the time of the previous training failure and the training parameters at the time of the current training failure; expanding the scanning range of the training parameters according to the preset ratio based on the difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure, to obtain an enlarged training data domain; and re-executing training from the failure node based on the enlarged training data domain. When all training stages are successfully completed, memory overclocking is completed and the system boots up normally; when the number of training iterations reaches the preset training iteration threshold, training is terminated.

2. The computer memory overclocking method according to claim 1, characterized in that, The step of starting the MRC module to perform memory training in response to the memory overclocking startup command includes: When the memory overclocking startup command is generated when the memory limit configuration XMP function is detected to be enabled; The MRC module is started, and training is performed on the memory based on the target memory parameters in the XMP configuration file.

3. The computer memory overclocking method according to claim 1, characterized in that, The method of recording training progress using preset CMOS bits includes: The corresponding bits in the CMOS bits are allocated to each of the plurality of training stages; When any training stage is successfully completed, the corresponding bit is set to a valid state as a marker for the completed training stage.

4. The computer memory overclocking method according to claim 1, characterized in that, The training data domain includes at least one of a reference voltage scan range and a timing scan range; The difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure has a corresponding relationship with the preset ratio: the larger the difference, the larger the preset ratio; the smaller the difference, the closer the current training parameters are to the hardware physical boundary of the memory, and the smaller the preset ratio. When expanding the scanning range of the training parameters according to the preset ratio, the boundary of the scanning range is expanded or reduced in a minimum adjustment unit of plus or minus 4. The boundary of the magnified training data domain does not exceed the hardware physical boundary of the memory.

5. The computer memory overclocking method according to claim 1, characterized in that, The training count threshold is preset by the user based on the target frequency of the memory, wherein the higher the target frequency, the larger the training count threshold.

6. The computer memory overclocking method according to claim 1, characterized in that, The re-execution of training from the failed node based on the amplified training data domain includes: Read the flags set in the CMOS bits to determine the training phase that has been completed; Skip the completed training phases and start training again from the training phase corresponding to the failed node, based on the amplified training data domain.

7. The computer memory overclocking method according to any one of claims 1 to 6, characterized in that, The method further includes: Before each re-execution of training, the number of training sessions already performed is counted; When the number of training iterations reaches the training iteration threshold and the training still fails, the training is terminated and a training failure message is output.

8. A computer memory overclocking system, characterized in that, include: A training module is used to start the memory reference code (MRC) module to perform training on the memory in response to a memory overclocking start command, wherein the training includes multiple training phases performed sequentially. The recording module is used to record the training progress through preset CMOS bits during the training process. Each time a training stage is passed, a flag corresponding to the passed training stage is set in the CMOS bits, and the next training stage is entered. The retraining module is used to determine the current training stage as a failure node when training fails in the current training stage, record the current training parameters in a preset buffer, and expand the training data domain according to a preset ratio by referring to the previous training failure node and training parameters stored in the buffer. The step of expanding the training data domain according to the preset ratio by referring to the previous training failure node and training parameters stored in the buffer includes: obtaining the training parameters stored in the buffer at the time of the previous training failure and the training parameters at the time of the current training failure; expanding the scanning range of the training parameters according to the preset ratio based on the difference between the training parameters at the time of the previous training failure and the training parameters at the time of the current training failure to obtain an expanded training data domain; and re-executing training from the failure node based on the expanded training data domain. The control module is used to complete memory overclocking and power on normally when all training stages are successfully completed; and to exit training when the number of training sessions reaches a preset training session threshold.

9. An electronic device, characterized in that, The system includes a memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor, when executing the computer program, implements the computer memory overclocking method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the computer memory overclocking method as described in any one of claims 1 to 7.

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