A microcontroller-based digital-analog hybrid signal processing method and related device

Abstract

The application provides a microcontroller-based digital-analog hybrid signal processing method and related equipment. The method comprises the following steps: generating a global timing reference based on a microcontroller-based timer; collecting an analog original signal by using an analog-to-digital converter of the microcontroller, and locking a corresponding analog signal timing stamp from the global timing reference at a starting trigger moment of collecting the analog original signal; receiving a digital communication original signal by using a communication peripheral of the microcontroller, and locking a corresponding digital signal timing stamp from the global timing reference at an interrupt response moment of receiving the digital communication original signal; and performing timing alignment processing on the analog original signal and the digital communication original signal based on the analog signal timing stamp and the digital signal timing stamp, to obtain a timing-aligned digital-analog hybrid signal. The application can improve the time consistency of the digital-analog hybrid signal and the data fusion analysis reliability.

Description

Technical Field

[0001] This application relates to the field of signal processing technology, specifically to a microcontroller-based method and related equipment for heterogeneous digital-analog signal processing. Background Technology

[0002] In modern industrial control and IoT scenarios, signal processing systems based on embedded microcontrollers are widely used. To comprehensively sense and control the operating status of equipment, the system typically needs to simultaneously acquire analog raw signals from sensors and digital communication signals transmitted via a bus, and perform comprehensive processing and fusion analysis on these two heterogeneous data to support upper-level decision control.

[0003] When processing heterogeneous signals, different peripherals within a system typically operate on independent clock cycles. After receiving data at the application layer, software logic sequentially timestamps the data for subsequent analysis. However, in a multi-tasking system, this application-layer marking method is susceptible to system scheduling mechanisms and interrupt preemption, causing random delays in time recording. This results in significant deviations in the timing matching of data from different channels, reducing the reliability of multi-source data fusion analysis. Summary of the Invention

[0004] The embodiments of this application provide a microcontroller-based method and related equipment for processing heterogeneous digital and analog signals, aiming to improve the time consistency of heterogeneous digital and analog signals and the reliability of data fusion analysis.

[0005] In a first aspect, embodiments of this application provide a microcontroller-based method for heterogeneous digital-analog signal processing, applied to a microcontroller, the method comprising:

[0006] A global timing reference is generated based on the timer of the microcontroller;

[0007] The analog-to-digital converter of the microcontroller is used to acquire the original analog signal, and at the trigger moment of acquiring the original analog signal, the corresponding analog signal timing stamp is latched from the global timing reference.

[0008] Using the communication peripherals of the microcontroller, the original digital communication signal is received, and at the interrupt response time of receiving the original digital communication signal, the corresponding digital signal timing stamp is latched from the global timing reference;

[0009] Based on the analog signal timing stamp and the digital signal timing stamp, the analog original signal and the digital communication original signal are time-aligned to obtain a time-aligned analog-digital heterogeneous signal.

[0010] In the above embodiments, a global timing reference is generated based on a timer, and the timing stamps of analog and digital signals are latched at the start trigger time of the analog-to-digital converter and the interrupt response time of the communication peripheral device, respectively. Based on this, the timing of the original analog signal and the original digital communication signal is aligned, eliminating the random delay caused by the application layer time stamp being affected by scheduling and interrupt preemption, and improving the time consistency of the analog-to-digital heterogeneous signals and the reliability of data fusion analysis.

[0011] In one embodiment, before performing timing alignment processing on the analog raw signal and the digital communication raw signal based on the analog signal timing stamp and the digital signal timing stamp, the method further includes performing filtering processing on the analog raw signal, the filtering processing including:

[0012] The simulated original signal is stored in the corresponding signal sliding window;

[0013] By removing extreme value data within the signal sliding window, a set of effective sampling points including multiple effective sampling points is obtained.

[0014] Based on the average value of the data in the set of valid sampling points, the confidence weight of each valid sampling point in the set of valid sampling points is determined, and based on the confidence weight, the valid sampling points in the set of valid sampling points are weighted and summed to obtain the global weighted mean.

[0015] Based on the data standard deviation of the effective sampling point set, determine the current dynamic hysteresis threshold of the signal sliding window;

[0016] Delete the target valid sampling point from the set of valid sampling points, where the difference between the voltage value of the target valid sampling point and the global weighted mean is greater than the dynamic hysteresis threshold.

[0017] In the above embodiments, the simulated original signal is stored in a signal sliding window, extreme value data is removed and then the signal is weighted and summed according to the confidence level. The dynamic hysteresis threshold is determined based on the standard deviation to delete peak points. This can suppress random noise and sudden interference, improve the stability of the simulated original signal and the data basis for subsequent timing alignment.

[0018] In one embodiment, before performing timing alignment processing on the analog original signal and the digital communication original signal based on the analog signal timing stamp and the digital signal timing stamp, the method further includes performing compensation processing on the analog original signal, the compensation processing including:

[0019] After deleting the target valid sampling points from the set of valid sampling points, the remaining valid sampling points in the set of valid sampling points are used as target simulated sampling points respectively;

[0020] Obtain the digital reference state of the original digital communication signal;

[0021] If the digital reference state is in a stable state, obtain the real-time zero-point offset and real-time temperature change of the analog-to-digital converter.

[0022] Determine the temperature drift compensation amount corresponding to the real-time temperature change;

[0023] The voltage value of the target simulated sampling point is compensated using the temperature drift compensation amount and the real-time zero-point offset.

[0024] In the above embodiments, when the digital reference state is stable, temperature drift compensation is performed by combining real-time zero-point offset and real-time temperature change, which can correct the long-term deviation and temperature drift error of the analog-to-digital converter, reduce the impact of analog sampling drift on heterogeneous signal fusion analysis, and improve the authenticity of analog signals.

[0025] In one embodiment, before performing timing alignment processing on the analog original signal and the digital communication original signal based on the analog signal timing stamp and the digital signal timing stamp, the method further includes performing a correction process for the digital communication original signal, the correction process including:

[0026] Based on the target simulated sampling points after the compensation process, determine the effective value of the simulated sampling in the current period, and obtain the effective value of the simulated sampling in the previous period of the current period.

[0027] Based on the current period's effective value of the analog sample, the previous period's effective value of the analog sample, and the sampling period of the analog-to-digital converter, the real-time gradient of the analog signal is determined.

[0028] Obtain the data change amount of the original digital communication signal in the current period;

[0029] If the real-time change gradient of the analog signal is less than the preset maximum mutation threshold, and the amount of data change is greater than the preset data mutation limit, the valid digital data of the original digital communication signal in the current period is determined to be abnormal communication data.

[0030] The abnormal communication data is corrected using the valid digital data from the two previous cycles of the original digital communication signal in the current cycle.

[0031] In the above embodiments, the real-time gradient is calculated based on the compensated target analog sampling points, and abnormal communication data with stable analog signals but abrupt changes in digital data is corrected. This can identify and repair communication errors, maintain the continuity of the original digital communication signal, and improve the reliability of the digital signal before timing alignment.

[0032] In one embodiment, after obtaining the time-aligned digital-analog heterogeneous signal, the method further includes:

[0033] The real-time occupancy rate of the microcontroller in the current period is calculated, and the sampling flow of the analog-to-digital converter collecting the analog raw signal and the communication frame flow of receiving the digital communication raw signal in the current period are extracted.

[0034] Based on the real-time occupancy rate, the sampling traffic, and the communication frame traffic, the overall system load score of the microcontroller is determined.

[0035] If the overall system load score is greater than a preset first load threshold, the sampling rate of the analog-to-digital converter and the filtering order of the signal sliding window used to remove the extreme value data are reduced, and the alignment task that performs the timing alignment processing is adjusted to a preset first priority.

[0036] If the overall system load score is less than a preset second load threshold, the sampling rate of the analog-to-digital converter and the filtering order of the signal sliding window used to remove the extreme value data are increased, and the alignment task is adjusted to a preset second priority, where the second load threshold is less than the first load threshold and the second priority is lower than the first priority.

[0037] In one embodiment, before performing time alignment processing on the analog original signal and the digital communication original signal based on the analog signal time stamp and the digital signal time stamp, the method further includes:

[0038] Obtain the communication protocol type, effective byte length, and link load traffic of the original digital communication signal;

[0039] Based on the communication protocol type, the effective byte length, and the link load traffic, the compensation delay of the original digital communication signal is determined;

[0040] Using the compensation delay and the digital signal timing stamp, a corrected digital timing stamp is generated;

[0041] Determine the absolute value of the deviation between the analog signal timing stamp and the corrected digital timing stamp;

[0042] If the absolute value of the deviation is greater than a preset deviation threshold, the clock division parameter corresponding to the communication peripheral is adjusted based on the absolute value of the deviation.

[0043] In the above embodiments, the compensation delay is calculated based on the communication protocol type, effective byte length and link load traffic, a corrected digital timing stamp is generated, and the clock division parameters of the communication peripheral are adjusted when the deviation exceeds the threshold. This can correct the timing deviation caused by bus transmission and improve the alignment accuracy between the analog signal timing stamp and the digital signal timing stamp.

[0044] In one embodiment, after obtaining the time-aligned digital-analog heterogeneous signal, the method further includes:

[0045] The current voltage drift of the analog original signal is obtained, the current communication bit error rate of the digital communication original signal is obtained, and the task blocking duration of the microcontroller in the current cycle is determined.

[0046] The current voltage drift, the current communication bit error rate, and the task blocking duration are compared with the corresponding preset fault tolerance thresholds to obtain a comprehensive fault judgment result.

[0047] In a preset repair instruction library, a target state repair instruction corresponding to the comprehensive fault determination result is determined, wherein the repair instruction library includes at least one of an analog-to-digital conversion zero-point calibration instruction, a communication port reset instruction, and a chip task restart instruction;

[0048] Execute the target state repair command.

[0049] Secondly, embodiments of this application provide a microcontroller-based heterogeneous digital-analog signal processing system, applied to a microcontroller, the system comprising:

[0050] A global timing reference generation module is used to generate a global timing reference based on the timer of the microcontroller;

[0051] The analog signal acquisition and latching module is used to acquire analog raw signals using the analog-to-digital converter of the microcontroller, and latch the corresponding analog signal timing stamp from the global timing reference at the start trigger time of acquiring the analog raw signals;

[0052] The digital signal receiving and latching module is used to receive the original digital communication signal using the communication peripheral of the microcontroller, and latch the corresponding digital signal timing stamp from the global timing reference at the interrupt response time of receiving the original digital communication signal;

[0053] The signal timing alignment module is used to perform timing alignment processing on the original analog signal and the original digital communication signal based on the analog signal timing stamp and the digital signal timing stamp, so as to obtain a timing-aligned analog-digital heterogeneous signal.

[0054] Thirdly, embodiments of this application provide a microcontroller, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the microcontroller-based heterogeneous digital-analog signal processing method as described in any of the preceding claims.

[0055] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the microcontroller-based heterogeneous digital-analog signal processing method as described in any of the preceding claims.

[0056] Understandably, the microcontroller-based heterogeneous digital-analog signal processing system provided in the second aspect, the microcontroller provided in the third aspect, and the computer-readable storage medium provided in the fourth aspect are all used to execute the method provided in this application. Therefore, the beneficial effects they can achieve can be referred to the beneficial effects in the corresponding methods, and will not be repeated here. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0058] Figure 1 This is a block diagram of the overall hardware architecture of the microcontroller provided in the embodiments of this application;

[0059] Figure 2 This is an overall flowchart of the microcontroller-based heterogeneous digital-analog signal processing method provided in the embodiments of this application;

[0060] Figure 3 This is a schematic diagram of the core steps of the microcontroller-based heterogeneous digital-analog signal processing method provided in the embodiments of this application;

[0061] Figure 4 This is a flowchart of the filtering process for analog raw signals provided in an embodiment of this application;

[0062] Figure 5 This is a schematic diagram of the load-aware dynamic resource scheduling logic provided in the embodiments of this application;

[0063] Figure 6 This is a flowchart of the fault self-diagnosis and self-healing process provided in the embodiments of this application;

[0064] Figure 7 This is a schematic diagram of the structure of a microcontroller-based heterogeneous digital-analog signal processing system provided in an embodiment of this application. Detailed Implementation

[0065] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, in the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0066] In a first aspect, embodiments of this application provide a microcontroller-based method for heterogeneous digital-analog signal processing. This method can be executed by a microcontroller-based heterogeneous digital-analog signal processing system, which runs on the microcontroller and coordinates with its on-chip and off-chip peripherals to complete analog signal acquisition, digital communication reception, and timing alignment.

[0067] First, refer to Figure 1 The overall hardware architecture of the microcontroller in the embodiments of this application will be described. For example... Figure 1 As shown, the hardware architecture includes an analog sensor signal input terminal and a multi-protocol communication signal input terminal, both of which serve as external signal sources for the system.

[0068] The microcontroller main control unit serves as the core processing platform. This main control unit can integrate a floating point unit (FPU) and an analog-to-digital converter (ADC). It can also integrate a direct memory access (DMA) controller and a system tick timer (SysTick).

[0069] The analog conditioning module, connected to the microcontroller's main control unit, amplifies and filters the analog sensor signals before sending them to the analog-to-digital converter. The clock synchronization module, also connected to the microcontroller's main control unit, provides a global timing reference. The storage buffer module, connected to the microcontroller's main control unit, buffers sampled data and communication frame data. The multi-protocol communication module, connected to the microcontroller's main control unit, receives and transmits digital communication signals using multiple protocols.

[0070] The output terminals of the microcontroller main control unit are connected to the Controller Area Network (CAN) data output interface and the Recommended Standard 485 (RS485) fused data output interface, respectively. These interfaces are used to forward the processed fused data to the outside.

[0071] Reference Figure 2 This paper provides an overview of the overall workflow of the microcontroller-based heterogeneous digital-analog signal processing method provided in the embodiments of this application. For example... Figure 2 As shown, the overall workflow of this method includes the following sequentially executed processing stages: system initialization and clock calibration, analog signal acquisition and adaptive filtering, digital multi-protocol parsing and fault tolerance, and analog-digital bidirectional cross-calibration. It also includes two-level microsecond-level timing synchronization alignment, dynamic load scheduling adaptation, fault diagnosis and self-healing processing, and multi-protocol adaptive fusion forwarding.

[0072] The system initialization and clock calibration correspond to step S101; the analog signal acquisition and adaptive filtering correspond to step S102 and subsequent filtering processing; and the digital multi-protocol parsing and fault tolerance correspond to step S103 and digital signal correction processing.

[0073] Analog-digital bidirectional cross-calibration corresponds to compensation and correction processing; secondary microsecond-level timing synchronization alignment corresponds to step S104 and delay compensation; load dynamic scheduling adaptation corresponds to load-aware dynamic resource scheduling steps.

[0074] The fault diagnosis and self-healing process corresponds to the fault determination and repair instruction execution steps; the multi-protocol adaptive fusion forwarding corresponds to the protocol selection and forwarding output after timing alignment. The following is an explanation of each stage.

[0075] Specifically, refer to Figure 3 The microcontroller-based heterogeneous digital-analog signal processing method may include:

[0076] S101. A microcontroller-based timer generates a global timing reference.

[0077] In this embodiment, the microcontroller may be a single-chip embedded processor that integrates a central processing unit core, ADC, DMA controller, timer and various communication peripherals, such as the STM32 series microcontroller.

[0078] The global timing reference is a unified time reference that is continuously incremented by the microcontroller timer at a fixed resolution, used to provide the same time coordinates for acquired events and communication events.

[0079] In some embodiments of this application, in step S101, an 8MHz external crystal oscillator can be used as the input reference source of the phase-locked loop (PLL), and the PLL can multiply the frequency to 168MHz as the main clock of the microcontroller.

[0080] Based on this, the microcontroller's SysTick timer can be configured to bind its timing clock source to the 168MHz master clock. The SysTick timer's reload count value can be set to increment the timing output every 168 clock cycles, thereby obtaining a continuously incrementing timing value sequence with a resolution of 1 microsecond.

[0081] The SysTick timer starts running immediately after the microcontroller is powered on and runs continuously. Its overload cycle is configured in full-scale cyclic mode, ensuring that the timing value monotonically increases. This sequence of timing values ​​constitutes the global timing reference. The analog-to-digital converter and communication peripherals inside the microcontroller use this global timing reference as the sole reference for the timing of events in subsequent operations.

[0082] S102. Using the analog-to-digital converter of the microcontroller, the original analog signal is acquired, and at the start trigger moment of acquiring the original analog signal, the corresponding analog signal timing stamp is latched from the global timing reference.

[0083] The analog raw signal is a continuous voltage signal output by the sensor and sent to the analog-to-digital converter via a signal conditioning circuit; the signal conditioning circuit may include an instrumentation amplifier and a second-order low-pass filter.

[0084] In some embodiments of this application, in step S102, the sampling start trigger signal of the analog-to-digital converter can be hardware-bound to the timing beat of the timer. At the instant each sampling conversion starts, the hardware circuit immediately reads the current timing value of the global timing reference and writes the value into a dedicated register for storage, serving as the timing stamp of the analog signal corresponding to this acquisition.

[0085] Since the latching action is performed by hardware and does not depend on the execution of software instructions in the processor core, it is not affected by task scheduling latency and processor load fluctuations.

[0086] Meanwhile, after the analog-to-digital converter (ADC) completes the sampling conversion, the direct memory access controller (DMC) operates in circular cache mode, sequentially moving the conversion result from the ADC's data register to the on-chip circular buffer. Circular cache mode allows the buffer to be rewritten from its starting address when it is full, without requiring processor core intervention to reconfigure the address shifting.

[0087] In some embodiments of this application, a fixed-length microsecond-level synchronous monitoring time window can be divided based on a global timing reference, for example, every 2 milliseconds is a synchronous monitoring time window period.

[0088] Within each synchronous monitoring time window, the maximum voltage fluctuation value of each analog-to-digital converter external channel can be extracted from the on-chip circular buffer moved by the direct memory access controller, and the timestamp of the first voltage fluctuation of each external channel exceeding the preset fluctuation detection threshold is latched as the channel fluctuation timestamp.

[0089] Simultaneously, the voltage fluctuation of the internal reference voltage channel integrated on the microcontroller within the synchronous monitoring time window can be read as the internal reference fluctuation; the error register of the communication peripheral can also be read to count the cumulative number of error flags within the synchronous monitoring time window as the communication error count.

[0090] Furthermore, the time difference between the actual trigger time of the direct memory access controller transmission completion interrupt and the theoretical trigger time calculated based on the sampling rate can be calculated as the transmission residual. This multi-dimensional data will serve as input for subsequent determination of the nature of interference sources.

[0091] S103. Using the microcontroller's communication peripherals, receive the original digital communication signal, and at the interrupt response time of receiving the original digital communication signal, latch the corresponding digital signal timing stamp from the global timing reference.

[0092] Communication peripherals may include a CAN bus interface and an Ethernet Media Access Controller (MAC) interface. Communication peripherals may also include a Universal Asynchronous Receiver / Transmitter (UART) interface for receiving digital communication frames.

[0093] In some embodiments of this application, in step S103, a receive completion interrupt can be configured for the communication peripheral, so that an interrupt request is triggered immediately after the communication peripheral completes the reception of each frame of raw digital communication signal. At the interrupt response entry point, the hardware immediately reads the current timing value of the global timing reference and saves this value as the digital signal timing stamp corresponding to this frame. Considering that the hardware latching action of the interrupt response has the highest priority, this operation is executed before any subsequent processing steps such as protocol parsing and data buffering in any interrupt service routine, thereby ensuring that the digital signal timing stamp records the physical time of arrival of the communication frame rather than the time when the software processing is completed.

[0094] In some embodiments of this application, the raw digital communication signal received by the communication peripheral can be organized using a unified and general frame structure. This unified and general frame structure includes, in sequence, a frame header field, a microsecond timestamp field, a channel identifier field, a data type field, a valid data field, a cyclic redundancy check (CRC) field, and a frame trailer field.

[0095] The frame header field identifies the start boundary of a data frame. The microsecond timestamp field records the global timing reference reading corresponding to the frame's generation at the sending end. The channel identifier field indicates which communication channel the data frame originates from, and the data type field distinguishes the physical meaning category of the valid data.

[0096] The valid data field carries the actual transmitted service values, the cyclic redundancy check field is used to verify the integrity of the data within the frame, and the frame tail field is used to identify the end boundary of a frame. Through this unified and universal frame structure, the raw digital communication signals of different communication protocol types present a consistent data organization format at the application layer.

[0097] In some embodiments of this application, when the cyclic redundancy check (CRC) field of the original digital communication signal fails the check, the frame can be marked as an abnormal frame, and the values ​​in its valid data field will not be directly used for subsequent processing. For this abnormal frame, the most recent frame with the same channel identifier as the abnormal frame that has passed the check can be extracted from the historical communication data buffer. The valid data of this successful frame can be used as the zero-order hold value to replace the original valid data of the abnormal frame in subsequent processing, thus avoiding data loss throughout the entire communication cycle due to a single frame check failure.

[0098] S104. Based on the analog signal timing stamp and the digital signal timing stamp, perform timing alignment processing on the original analog signal and the original digital communication signal to obtain the timing-aligned analog-digital heterogeneous signal.

[0099] Timing alignment is a process that pairs and associates the original analog signal with the original digital communication signal under a unified time coordinate, based on the analog signal timing stamp and the digital signal timing stamp. The fused data set after pairing is the timing-aligned heterogeneous digital-analog signal.

[0100] In some embodiments of this application, in step S104, the time difference between the analog signal time stamp and the digital signal time stamp can be calculated, and it can be determined whether the time difference falls within a preset alignment tolerance window. If the time difference falls within the alignment tolerance window, the corresponding analog original signal and digital communication original signal are determined to be paired data at the same physical moment and merged into a set of time-aligned heterogeneous digital-analog signals. If the time difference exceeds the alignment tolerance window, the pairing combination with the smallest time difference is searched in adjacent sampling periods according to the order of the time stamps to complete the alignment matching. Through the above processing, analog original signals and digital communication original signals from different sources and with different acquisition cycles are unified under the same time coordinate system to form time-aligned heterogeneous digital-analog signals.

[0101] In some embodiments of this application, after obtaining the time-aligned heterogeneous digital-analog signal, multi-protocol adaptive fusion forwarding can be performed. This forwarding process selects a forwarding protocol based on the link connectivity status, load level, and application scenario of each communication peripheral, and outputs the time-aligned heterogeneous digital-analog signal to the outside.

[0102] Specifically, it can detect the link connectivity and load level of the CAN bus interface, MAC interface, and UART interface in real time.

[0103] When the application scenario involves close-range real-time data interaction and the Controller Area Network (CAN) bus interface link is connected, forwarding should be prioritized through the CAN bus interface. When the application scenario involves remote monitoring and the Ethernet Media Access Controller Interface (MTA) link is connected, forwarding can be done through the Ethernet MTA controller interface.

[0104] When in local debugging mode, data can be forwarded in Modbus protocol format via the serial asynchronous transceiver interface. The selection process for the aforementioned forwarding protocol can be dynamically executed based on the link status in each output cycle to ensure the availability of the converged data output path.

[0105] Through the above steps, analog sampling events and digital communication frames are paired under the same global timing reference to form a heterogeneous digital-analog signal that can be used for subsequent fusion analysis and forwarding.

[0106] In some embodiments, the analog raw signal may be filtered before participating in timing alignment to reduce the impact of random noise, power supply ripple coupling interference, and transient spike pulses on subsequent alignment.

[0107] Reference Figure 4 The filtering process includes writing the raw sampled data of the analog-to-digital converter (i.e., the raw ADC sampled input) into a signal sliding window, performing extreme value elimination and confidence weighting calculation, and outputting the global weighted mean.

[0108] Then, the dynamic hysteresis threshold is determined based on the adaptive coefficient for the operating condition. The adaptive coefficient for the operating condition is denoted as... When the signal is in steady-state operation, Take 1.5; when the signal is in a transient change condition, Set the value to 2.5. Then, based on the dynamic hysteresis threshold, remove residual spike interference data, and finally output the effective filtered data.

[0109] The following details each step in the filtration process, which includes:

[0110] S201. Store the original analog signal into the corresponding signal sliding window.

[0111] The signal sliding window is a first-in-first-out data queue in the on-chip buffer, which stores the sampled values ​​output by the analog-to-digital converter in the order of sampling time. The capacity can be configured to 16, 32 or 64 levels.

[0112] In some embodiments of this application, in step S201, after each sampling conversion by the analog-to-digital converter, the conversion result is written to the tail of the signal sliding window in chronological order. If the signal sliding window is full, the earliest written sample value at the head of the queue is removed to make room for the new sample value. Through this first-in-first-out cyclic writing method, the signal sliding window always maintains analog original signal sampling data containing the most recent consecutive cycles, providing a temporally continuous data basis for subsequent extreme value elimination and weighted calculation.

[0113] S202. Remove extreme value data within the signal sliding window to obtain a set of effective sampling points including multiple effective sampling points.

[0114] In some embodiments of this application, in step S202, all sampling points within the signal sliding window can be sorted according to their voltage values. Then, several sampling points at the beginning and end of the sorted window are marked as extreme values ​​and discarded. The number of discarded points is determined by the current filter order of the signal sliding window. For example, a 32-order window can discard two extreme sampling points at the beginning and end. After discarding the extreme values, the remaining sampling points constitute the set of valid sampling points.

[0115] S203. Based on the average value of the data in the set of valid sampling points, determine the confidence weight of each valid sampling point in the set of valid sampling points, and based on the confidence weight, perform a weighted summation of the valid sampling points in the set of valid sampling points to obtain the global weighted mean.

[0116] Confidence weights are used to characterize the reliability of each valid sampling point relative to the data average; the smaller the deviation from the data average, the higher the confidence weight.

[0117] In some embodiments of this application, in step S203, the arithmetic mean of the voltage values ​​of all valid sampling points in the valid sampling point set can be calculated first as the data average, and the data standard deviation of the valid sampling point set can be calculated simultaneously. Then, for each valid sampling point in the valid sampling point set, its confidence weight is determined using the inverse proportional normalization method of deviation. The specific calculation formula is as follows:

[0118]

[0119] in, For the first The voltage values ​​of each valid sampling point, in this formula This is the average of the data. Let be the standard deviation of the set of valid sampling points. This formula assigns a confidence weight closer to 1 to valid sampling points whose voltage values ​​deviate less from the data average, and a confidence weight closer to 0 to valid sampling points whose deviations are greater.

[0120] After determining the confidence weights of all valid sampling points, the global weighted mean can be calculated using the weighted truncated mean formula:

[0121]

[0122] in, The global weighted mean. The total number of valid sampling points in the set of valid sampling points. For the first The confidence weight of each valid sampling point For the first The voltage values ​​of each valid sampling point are used to calculate the global weighted mean.

[0123] S204. Based on the data standard deviation of the effective sampling point set, determine the current dynamic hysteresis threshold of the signal sliding window.

[0124] The dynamic hysteresis threshold is an anomaly detection boundary determined in real time based on the standard deviation of the data. The threshold narrows when the signal is stable and widens when the signal fluctuates greatly.

[0125] In some embodiments of this application, in step S204, the standard deviation of the effective sampling point set can be calculated first:

[0126]

[0127] in, The standard deviation of the effective set of sampling points. For the first Voltage values ​​at each valid sampling point The global weighted mean. This represents the total number of valid sampling points.

[0128] Then, the dynamic hysteresis threshold is determined by multiplying the adaptive coefficient of the operating condition by the standard deviation of the data:

[0129]

[0130] in, The dynamic hysteresis threshold. For the adaptive coefficient of the working condition, This represents the standard deviation of the effective set of sampling points. When the signal is in a steady-state condition... A value of 1.5 is set to tighten the dynamic hysteresis threshold, making it easier to identify small-amplitude spike interference; when the signal is in a transient change condition, A value of 2.5 is set to appropriately relax the dynamic hysteresis threshold, avoiding misjudging normal signal transitions as interference. The operating condition can be determined based on the trend of the data standard deviation over multiple consecutive signal sliding window periods. If the data standard deviation is consistently lower than the preset steady-state judgment threshold, it is judged as a steady-state operating condition; otherwise, it is judged as a transient change operating condition.

[0131] S205. Delete the target valid sampling point from the set of valid sampling points. The difference between the voltage value of the target valid sampling point and the global weighted average value is greater than the dynamic hysteresis threshold.

[0132] In some embodiments of this application, in step S205, each valid sampling point in the valid sampling point set can be traversed, and the absolute value of the difference between the voltage value of the valid sampling point and the global weighted average value can be calculated. If the absolute value is greater than the dynamic hysteresis threshold, the valid sampling point is marked as a target valid sampling point and deleted from the valid sampling point set. After all traversals are completed, only sampling points whose voltage values ​​deviate from the global weighted average value by no more than the dynamic hysteresis threshold are retained in the valid sampling point set. These sampling points are the high-quality analog signal data after filtering, which can be used in subsequent timing alignment processing.

[0133] Through steps S201 to S205, extreme value data and residual spike interference can be eliminated while preserving the effective variation trend of the original analog signal, providing a stable data foundation for subsequent compensation and timing alignment.

[0134] In some embodiments of this application, before performing filtering, a multi-channel mutation synchronization index can be calculated based on the channel mutation timestamps of each external channel latched within the synchronous monitoring time window. The multi-channel mutation synchronization index refers to the difference between the maximum and minimum values ​​of the channel mutation timestamps among all external channels whose voltage mutations exceed the mutation detection threshold within the same synchronous monitoring time window. This difference reflects the temporal dispersion of mutation events in each channel. The calculation formula is:

[0135]

[0136] in, For the first The timestamp of the channel mutation when the voltage change of the first external channel exceeds the mutation detection threshold. It serves as an indicator of multi-channel mutation synchronization.

[0137] When the microcontroller is configured with only a single external analog-to-digital converter channel, the multi-channel mutation synchronization index does not participate in subsequent judgments; the filtering process is directly executed based on the judgment logic dominated by the four-dimensional homologous distortion index. When the microcontroller is configured with two or more external analog-to-digital converter channels, the multi-channel mutation synchronization index and the four-dimensional homologous distortion index jointly participate in the determination of the nature of the interference source.

[0138] In some embodiments of this application, after filtering, a four-dimensional homogeneous distortion index can be constructed using multi-dimensional data collected within the synchronous monitoring time window. This index is used to determine the physical source of voltage surges within the current synchronous monitoring time window, specifically distinguishing between real mechanical events and environmental electromagnetic interference. Based on the determination result, it is decided whether to retain or discard the filtered sampling data.

[0139] The four-dimensional homologous distortion index is a joint distortion assessment value constructed by integrating four dimensions: the intensity of external channel voltage surges, communication error counts, internal reference fluctuations, and transmission residuals. This value degenerates into a pure amplitude index when only the external analog channel experiences a surge while the other three dimensions show no abnormal response. When any digital domain or internal chip domain probe is triggered, the four-dimensional homologous distortion index increases, reflecting the multi-domain synchronous coupling characteristics of the surge event. The calculation formula is:

[0140]

[0141] in, This is the four-dimensional homology distortion index. This represents the maximum voltage surge value across all external channels within the current synchronous monitoring time window. This represents the daily noise floor standard deviation of the external channel voltage signal. For communication error counting, This is the internal benchmark fluctuation. This represents the daily noise floor standard deviation of the internal reference voltage channel. To transmit residuals, This serves as the normal operating baseline for transmitting residual values. , , These are the communication coupling coefficient, power coupling coefficient, and bus coupling coefficient, respectively. It is a natural constant.

[0142] As can be seen from the above formula, when there is no abnormal response in the communication error count, internal reference fluctuation, and transmission residual, the four-dimensional homologous distortion index mainly characterizes the intensity of external channel voltage change; when any of the above digital domain or chip internal domain probes responds, the four-dimensional homologous distortion index increases, which is used to characterize the multi-domain coupling characteristics of the change event.

[0143] Based on the four-dimensional homology distortion index and the multi-channel mutation synchronization index, a three-level classification judgment is performed at the end of each synchronization monitoring time window:

[0144] The first operating condition is a real mechanical event. The judgment criteria are: the maximum voltage change value of the external channel exceeds the change detection threshold, the four-dimensional homogeneous distortion index is less than the preset distortion index threshold, and the multi-channel change synchronization index is greater than the preset mechanical propagation delay threshold. At this time, the filtering order of the signal sliding window is temporarily reduced to the minimum value, the change waveform data is retained, and a mechanical characteristic event mark is added to the data within the synchronization monitoring time window.

[0145] The second operating condition is environmental electromagnetic interference. The judgment criteria are: the four-dimensional homogeneous distortion index is greater than the preset distortion index threshold, and the multi-channel mutation synchronization index is less than the preset electromagnetic synchronization threshold; in single-channel mode, the multi-channel mutation synchronization index is not included in the judgment. In this case, all analog-to-digital converter sampling data within the synchronization monitoring time window are marked as contaminated data and removed. The global weighted average value within the previous synchronization monitoring time window is used for zero-order hold replacement, and an error register clearing operation is performed on the communication peripherals.

[0146] The third scenario is an uncertain mixed event. The criteria are: the four-dimensional homology distortion index slightly exceeds the distortion index threshold, and the multi-channel mutation synchronization index is in the fuzzy range between the electromagnetic synchronization threshold and the mechanical propagation delay threshold. In this case, the sampled data within the synchronization monitoring time window is retained, and the confidence weight corresponding to the data within this window is reduced to 50% of the original value for subsequent weighted fusion calculations; if the same conditions are met for three consecutive subsequent synchronization monitoring time windows, the process is upgraded to the second scenario.

[0147] After filtering, compensation processing can be performed on the retained analog sampled data to correct systematic deviations caused by analog-to-digital converter zero-point offset and temperature variations. Specifically, before timing alignment processing of the original analog and digital communication signals based on analog and digital signal time stamps, compensation processing for the original analog signals is performed. This compensation processing includes:

[0148] S301. After deleting the target valid sampling points from the set of valid sampling points, the remaining valid sampling points in the set of valid sampling points are used as target simulation sampling points respectively.

[0149] In some embodiments of this application, in step S301, after the deletion operation of the target valid sampling points is completed in step S205, all remaining valid sampling points in the set of valid sampling points can be directly marked as target analog sampling points one by one. Each target analog sampling point retains its original voltage value and the corresponding analog signal timing stamp information so that the voltage value can be corrected point by point in subsequent compensation calculations.

[0150] S302. Obtain the digital reference state of the original digital communication signal.

[0151] Digital reference state is used to characterize the stability of the original digital communication signal within the current time period, and can include stable and unstable states.

[0152] In some embodiments of this application, in step S302, the variation amplitude of the payload data of the original digital communication signal over the most recent consecutive communication cycles can be statistically analyzed. Specifically, the payload values ​​of the original digital communication signal in the most recent consecutive frames can be extracted, the range or standard deviation of these values ​​can be calculated, and the range or standard deviation can be compared with a preset stability judgment threshold. If the range or standard deviation does not exceed the stability judgment threshold, the digital reference state is determined to be stable, indicating that the current reference data transmitted by the digital communication link has high reliability and is suitable as a reference for analog signal compensation.

[0153] S303. If the digital reference state is stable, obtain the real-time zero offset and real-time temperature change of the analog-to-digital converter.

[0154] The real-time zero offset is the offset voltage output by the analog-to-digital converter when its input is shorted to the reference ground potential in the current operating state; the real-time temperature change is the difference between the current temperature reading and the reference temperature.

[0155] In some embodiments of this application, in step S303, when the digital reference state is stable, the zero-point offset calibration value stored in the internal calibration register of the analog-to-digital converter can be read, or the input channel of the analog-to-digital converter can be switched to the internal reference ground channel during the sampling interval to perform a zero-point sampling, and the sampling result can be used as the real-time zero-point offset. At the same time, the current temperature value of the on-chip temperature sensor of the microcontroller can be read, and it can be subtracted from the reference temperature value recorded during the power-on initialization phase to obtain the real-time temperature change.

[0156] S304. Determine the temperature drift compensation amount corresponding to the real-time temperature change.

[0157] In some embodiments of this application, in step S304, the real-time temperature change can be multiplied by a pre-calibrated temperature drift coefficient to obtain the temperature drift compensation amount. The temperature drift coefficient is a constant obtained during factory calibration or power-on initialization self-learning phase by recording the output change of the analog-to-digital converter within a known temperature range and performing linear fitting. Its physical meaning is the sampling voltage offset caused by a unit temperature change. The temperature drift compensation amount can be calculated as follows:

[0158]

[0159] in, This is the temperature drift compensation amount. This is the temperature drift coefficient. This represents the real-time temperature change.

[0160] S305. The voltage value of the target simulation sampling point is compensated by using the temperature drift compensation amount and the real-time zero offset amount.

[0161] In some embodiments of this application, in step S305, voltage compensation calculation can be performed point-by-point for each target analog sampling point in the effective sampling point set according to the following formula:

[0162]

[0163] in, The voltage value at the target simulated sampling point after compensation is given in this formula. The target is to simulate the original voltage value of the sampling point. This is the real-time zero-point offset. This is the temperature drift coefficient. This represents the real-time temperature change. After the compensation calculation is completed, the voltage value of each target analog sampling point is updated to the compensated value. This value has eliminated the systematic errors caused by zero-point offset and temperature drift, and can be used in subsequent timing alignment and digital-analog signal cross-calibration processes.

[0164] Through steps S301 to S305, when the digital reference state is stable, the voltage value of the target analog sampling point can be corrected by using the real-time zero offset and the real-time temperature change, so that the analog signal has a more stable amplitude reference before entering timing alignment.

[0165] After completing the compensation processing of the original analog signal, the continuous variation characteristics of the compensated analog signal can be used to identify and correct any abnormal communication data that may appear in the original digital communication signal. Specifically, before performing timing alignment processing on the original analog signal and the original digital communication signal based on the analog signal timing stamp and the digital signal timing stamp, a correction process for the original digital communication signal is also performed. This correction process includes:

[0166] S401. Based on the target simulated sampling points after compensation processing, determine the effective value of the simulated sampling in the current period, and obtain the effective value of the simulated sampling in the previous period.

[0167] In some embodiments of this application, in step S401, the voltage value of the target simulated sampling point after compensation processing within the current sampling period can be used as the effective value of the simulated sampling in the current period. If there are multiple target simulated sampling points within the current period, their weighted average or the last sampled value can be used as the effective value of the simulated sampling in the current period. Simultaneously, the effective value of the simulated sampling saved in the previous period can be read from the historical data buffer. The historical data buffer sequentially stores the effective values ​​of the simulated sampling for the most recent several periods, in units of sampling periods. The result is written to the buffer after each period of compensation processing is completed.

[0168] S402. Based on the RMS value of the analog sample in the current period, the RMS value of the analog sample in the previous period, and the sampling period of the analog-to-digital converter, determine the real-time gradient of the analog signal.

[0169] The real-time gradient of the analog signal is the rate of change of the effective value of the analog sample per unit time between adjacent sampling periods, used to characterize the current degree of change of the monitored physical quantity.

[0170] In some embodiments of this application, in step S402, the real-time gradient of the analog signal can be obtained by dividing the difference between the effective value of the analog sample in the current period and the effective value of the analog sample in the previous period by the sampling period of the analog-to-digital converter. The calculation formula is as follows:

[0171]

[0172] in, This represents the valid value of the simulated sample for the current period. This is the effective value of the simulated sample from the previous period. The sampling period of the analog-to-digital converter. This is to simulate the real-time changing gradient of the signal.

[0173] S403. Obtain the data change of the original digital communication signal in the current cycle.

[0174] In some embodiments of this application, in step S403, the payload value of the received digital communication raw signal in the current cycle can be extracted from the receive buffer of the communication peripheral. Then, the payload value of the previous cycle is read from the historical communication data buffer. The two are subtracted and the absolute value is taken to obtain the data change of the digital communication raw signal in the current cycle.

[0175] S404. If the real-time change gradient of the analog signal is less than the preset maximum mutation threshold, and the amount of data change is greater than the preset data mutation limit, the valid digital data of the original digital communication signal in the current period shall be determined as abnormal communication data.

[0176] The maximum mutation threshold and data mutation limit are used to limit the normal gradient of analog signals and the normal jump amplitude of digital communication data, respectively. Both can be obtained in advance through engineering calibration.

[0177] In some embodiments of this application, in step S404, the real-time gradient of the analog signal can be compared with the maximum abrupt change threshold, and the amount of data change can be compared with the data abrupt change limit. When the real-time gradient of the analog signal is less than the maximum abrupt change threshold, it indicates that the monitored physical quantity is in a state of gradual change within the current period, and there are no physical conditions for drastic abrupt changes. If the amount of data change is greater than the data abrupt change limit, the digital communication link reports a large data jump that is inconsistent with the physical reality, and this jump lacks the support of physical signals. When both of the above conditions are met simultaneously, the valid digital data of the original digital communication signal in the current period can be determined as abnormal communication data.

[0178] S405. Correct abnormal communication data by using the valid digital data of the original digital communication signal in the first two cycles of the current cycle.

[0179] In some embodiments of this application, in step S405, the valid digital data of the previous cycle and the valid digital data of the previous two cycles can be read from the historical communication data buffer, and the abnormal communication data can be corrected using a second-order timing interpolation formula. The correction calculation formula is as follows:

[0180]

[0181] in, For the valid digital data of the previous period, The significant figures are from the first two periods. This is the corrected digital data. The formula, based on the principle of linear extrapolation, uses the changing trends of the data from the previous two periods to predict a reasonable value for the current period, replacing the original value of the abnormal communication data. After correction, the corrected digital data is written into the communication data record of the current period, replacing the original abnormal communication data. This restores the continuity and physical rationality of the original digital communication signal in the time series, for use in subsequent timing alignment processing.

[0182] Through steps S401 to S405, when the analog signal changes smoothly but the digital communication data changes abnormally, the abnormal communication data can be corrected, so that the original digital communication signal can maintain the continuity of the time series before entering the timing alignment.

[0183] In some embodiments, before the timing alignment process in step S104, delay compensation and clock fine-tuning can be performed on the digital signal timing stamp to ensure that the original digital communication signal participates in alignment under a unified time coordinate. Specifically, before performing timing alignment processing on the analog original signal and the digital communication original signal based on the analog signal timing stamp and the digital signal timing stamp, the process further includes:

[0184] S501. Obtain the communication protocol type, effective byte length, and link load traffic of the original digital communication signal.

[0185] Communication protocol types include one of the following: Controller Area Network Bus Protocol, Serial Asynchronous Receiver / Transmitter Protocol, and Ethernet Protocol. Different communication protocol types correspond to different physical layer transmission characteristics and frame structure overhead.

[0186] In some embodiments of this application, in step S501, after the communication peripheral completes the reception of a frame of digital communication raw signal, the communication protocol type can be parsed from the frame header identifier field, and the effective byte length can be counted from the frame length field or the payload area. The link load traffic can be obtained by counting the product of the number of interruptions triggered when the communication peripheral completes reception in the most recent observation period and the amount of data in each frame, and then normalizing it to a value between 0 and 1.

[0187] S502. Based on the communication protocol type, effective byte length, and link load traffic, determine the compensation delay of the original digital communication signal.

[0188] The compensation delay is a time correction calculated based on the inherent transmission characteristics of the communication link, used to offset the time overhead between the original digital communication signal being sent from the transmitting end and the timing stamp of the digital signal latched by the communication peripheral interrupt response.

[0189] In some embodiments of this application, in step S502, a corresponding delay fitting model can be selected according to the communication protocol type to calculate the compensation delay. The calibration coefficients in the delay fitting model can be obtained through self-learning calibration during the microcontroller power-on initialization phase.

[0190] Specifically, during the power-on initialization phase, test frames of known length can be sent sequentially to each communication peripheral, and the time difference between sending the test frame and receiving the interrupt response upon completion can be recorded. For the same communication protocol type, multiple sets of test frames with different effective byte lengths can be sent, and the delay data for each set can be statistically analyzed.

[0191] For serial asynchronous transceiver protocols, multiple sets of effective byte lengths and corresponding delay data can be linearly fitted to obtain the single-byte transmission delay coefficient and fixed protocol overhead delay. For controller area network bus protocols, the average delay from multiple tests can be taken as the fixed transmission delay.

[0192] For the Ethernet protocol, test frames can be sent under different link load conditions to obtain the dynamic delay coefficient and the basic transmission delay. After self-learning calibration is completed, the calibration coefficients are written to the parameter storage area for use during the runtime phase.

[0193] During operation, when the communication protocol type is a serial asynchronous transceiver protocol, the compensation delay is linearly related to the effective byte length, and the calculation formula is as follows:

[0194]

[0195] in, This refers to the compensation delay corresponding to the serial asynchronous transceiver protocol. Valid byte length, This is the single-byte transmission delay factor. Delay for fixed protocol overhead, and All of these are constants obtained through self-learning calibration during the power-on initialization phase.

[0196] When the communication protocol type is Controller Area Network Bus protocol, since the frame structure length is fixed and the bus arbitration delay is stable, the compensation delay is a fixed value, and the calculation formula is as follows:

[0197]

[0198] in, Compensation delay for the Controller Area Network Bus protocol. The fixed transmission delay corresponding to the bus baud rate is fixed through initialization calibration.

[0199] When the communication protocol is Ethernet, the compensation delay is positively correlated with the link load traffic, and the calculation formula is as follows:

[0200]

[0201] in, This is the compensation delay for the Ethernet protocol. The current link load traffic, This is the maximum load threshold for the link. This refers to the dynamic delay coefficient in the Ethernet delay model. This represents the basic transmission delay for Ethernet. This dynamic delay coefficient is independently determined by the communication coupling coefficient in the four-dimensional homogeneous distortion index.

[0202] S503. Generate a corrected digital timing stamp using compensation delay and digital signal timing stamp.

[0203] In some embodiments of this application, in step S503, the digital signal timing stamp can be added to the compensation delay to obtain the corrected digital timing stamp. The calculation formula is as follows:

[0204]

[0205] in, To correct the digital time stamp, For digital signal timing stamps, This is the compensation delay calculated based on the communication protocol type. This corrected digital timing stamp will replace the original digital signal timing stamp in subsequent timing alignment processing.

[0206] S504. Determine the absolute value of the deviation between the analog signal timing stamp and the corrected digital timing stamp.

[0207] In some embodiments of this application, in step S504, the absolute value of the deviation can be obtained by subtracting the analog signal timing stamp from the corrected digital timing stamp and taking the absolute value. The calculation formula is as follows:

[0208]

[0209] in, The absolute value of the deviation. For analog signal timing stamps, To correct the digital time stamp.

[0210] S505. If the absolute value of the deviation is greater than the preset deviation threshold, adjust the clock division parameter corresponding to the communication peripheral based on the absolute value of the deviation.

[0211] The deviation threshold is a preset upper limit for the timing alignment accuracy, for example, it can be set to 5 microseconds; the clock division parameter is the configuration value of the division coefficient of the communication peripheral's working clock.

[0212] In some embodiments of this application, in step S505, when the absolute value of the deviation is greater than the deviation threshold, the clock division parameters of the communication peripheral can be fine-tuned based on the absolute value of the deviation. Specifically, the clock cycle correction amount can be calculated using the product of the convergence adjustment coefficient and the absolute value of the deviation, and applied to the current clock cycle of the communication peripheral. The adjustment formula is:

[0213]

[0214] in, The adjusted clock period, The current clock cycle of the communication peripheral. This is the convergence adjustment coefficient in the clock fine-tuning formula, and its value is a positive number between 0 and 1. This is the absolute value of the deviation. This convergence adjustment coefficient is independently determined from the power coupling coefficient in the four-dimensional homogeneous distortion index.

[0215] The convergence adjustment coefficient is set to less than 1, ensuring that the adjustment amplitude is less than the absolute value of the deviation itself, thereby gradually converging the timing deviation without causing overshoot oscillation. The absolute value of the deviation and the clock division parameter adjustment are repeatedly performed in each scheduling cycle until the absolute value of the deviation converges to within the deviation threshold.

[0216] Once the absolute value of the deviation is determined to be no more than the deviation threshold for multiple consecutive times (e.g., 10 times), the current compensation delay parameters and clock division parameters can be written to a non-volatile memory area for persistence. Subsequent runtime cycles can then directly call the persisted parameters without executing the deviation determination and clock fine-tuning process again.

[0217] In some embodiments of this application, when the timing stamp of the latched analog signal or digital signal changes significantly due to clock jitter or abnormal interrupt response of the global timing reference, timing gradient interpolation can be used to correct the abnormal timing stamp.

[0218] Specifically, the average gradient of the time stamp increment over the most recent consecutive sampling periods can be calculated, and this average gradient can be used as the expected increment of the time stamp in the current period.

[0219] When the increment between the actual latched time stamp and the previous period's time stamp deviates from the expected increment by more than the preset gradient deviation tolerance, the time stamp is determined to be an abnormal time stamp. In this case, a corrected time stamp can be generated by adding the expected increment to the previous period's time stamp, and this corrected time stamp can replace the abnormal time stamp in subsequent deviation absolute value calculation and timing alignment processing.

[0220] Through steps S501 to S505, a corrected digital timing stamp can be generated based on the communication protocol type, effective byte length, and link load traffic. When the deviation exceeds the threshold, the clock division parameters of the communication peripheral can be adjusted to reduce the impact of communication link transmission delay on timing alignment accuracy.

[0221] After obtaining the time-aligned analog-digital heterogeneous signal, the sampling rate, filter order, and alignment task priority can be adjusted according to the microcontroller's operating load to match the operating parameters with the current load state.

[0222] Reference Figure 5 The logic of load-aware dynamic resource scheduling is explained.

[0223] like Figure 5 As shown, load-aware dynamic resource scheduling uses the utilization rate of the microcontroller processor core (CPU load), the sampling flow of the analog-to-digital converter (ADC load), and the communication frame flow of the communication peripherals (communication load) as load inputs.

[0224] Based on the above load inputs and a comprehensive load score, the current operating condition can be divided into high load, normal load, and low load modes. In high load mode, the sampling rate is reduced, the filter order is decreased, and the alignment task priority is increased; in normal load mode, standard parameters are maintained; and in low load mode, high-precision parameter configuration is enabled.

[0225] The adjustment results of the three modes are combined to form a dynamic parameter adaptive output, namely the updated sampling rate, filter order, and task priority parameters.

[0226] The following details each step of load-aware dynamic resource scheduling. Specifically, after obtaining the time-aligned heterogeneous digital-analog signals, the process also includes:

[0227] S601: Calculate the real-time occupancy rate of the microcontroller in the current cycle, and extract the sampling flow of the analog raw signal collected by the analog-to-digital converter and the communication frame flow of the received digital communication raw signal in the current cycle.

[0228] In some embodiments of this application, in step S601, the real-time occupancy rate can be obtained by reading the cumulative running time of the operating system's idle tasks in the current cycle, subtracting it from the total time of the current cycle, and then dividing by the total time. For example, if the total time of the current cycle is 10 milliseconds and the cumulative running time of the idle tasks is 3 milliseconds, then the real-time occupancy rate is 70%. Simultaneously, the total number of sampling points moved from the analog-to-digital converter to the on-chip buffer by the direct memory access controller in the current cycle can be counted, divided by a preset full-scale sampling rate value for normalization, and the sampling rate can be obtained. Similarly, the product of the number of interrupts triggered upon completion of communication peripheral reception in the current cycle and the number of valid bytes per frame can be counted, divided by a preset full-scale communication frame rate value for normalization, and the communication frame rate can be obtained.

[0229] S602. Based on real-time occupancy rate, sampling traffic, and communication frame traffic, determine the overall system load score of the microcontroller.

[0230] The overall system load score is a comprehensive quantitative value obtained by weighting real-time occupancy, sampling traffic and communication frame traffic according to preset weights, which is used to characterize the current overall load level of the microcontroller.

[0231] In some embodiments of this application, in step S602, the real-time occupancy rate, sampling traffic, and communication frame traffic can be linearly weighted and summed using preset weights to obtain a comprehensive system load score. The calculation formula is as follows:

[0232]

[0233] in, To provide a comprehensive load score for the system, For real-time occupancy rate, For sampling flow rate, For communication frame traffic, , , The weights are preset and their sum is 1. The values ​​of the weights are determined based on the degree of impact of each dimension on the system's operational stability in the specific application scenario. For example, in communication-intensive scenarios, the weights can be appropriately increased. The value of can be appropriately increased in high-speed sampling scenarios. The value of .

[0234] S603. If the overall system load score is greater than the preset first load threshold, reduce the sampling rate of the analog-to-digital converter and the filtering order of the signal sliding window used to remove extreme data, and adjust the alignment task for performing timing alignment processing to the preset first priority.

[0235] In some embodiments of this application, in step S603, when the overall system load score is greater than the first load threshold, the following parameter adjustments can be performed.

[0236] First, reduce the sampling rate of the analog-to-digital converter from the current configuration value to a preset low sampling rate level, reducing the number of sampling conversions per unit time. Second, switch the filtering order of the signal sliding window from the current configuration value to a lower order level, for example, from 64th order to 16th order.

[0237] Third, the scheduling priority of the alignment task in the Free Real-Time Operating System (FreeRTOS) is elevated to the first priority. This adjustment reduces the computational burden of data handling and filtering, and allows the timing alignment process to gain priority execution rights from the processor core under high load conditions.

[0238] S604. If the overall system load score is less than the preset second load threshold, increase the sampling rate of the analog-to-digital converter and the filtering order of the signal sliding window used to remove extreme data, and adjust the alignment task to the preset second priority. The second load threshold is less than the first load threshold, and the second priority is lower than the first priority.

[0239] In some embodiments of this application, in step S604, when the overall system load score is less than the second load threshold, the following parameter adjustments can be performed.

[0240] First, increase the sampling rate of the analog-to-digital converter from the current configuration value to a preset high sampling rate level to obtain denser analog signal time-domain data. Second, switch the filtering order of the signal sliding window from the current configuration value to a higher order level, such as switching from order 32 to order 64.

[0241] Third, the scheduling priority of the alignment task in the real-time operating system is reduced to the second priority. Through the above adjustments, the microcontroller can improve signal processing accuracy by utilizing idle computing resources under low load conditions.

[0242] Through steps S601 to S604, the overall system load score can be determined based on real-time occupancy rate, sampling traffic, and communication frame traffic, and the sampling rate, filtering order, and alignment task priority can be adjusted accordingly.

[0243] After obtaining the time-aligned analog-digital heterogeneous signals, online judgment and repair can be performed on analog drift, communication errors and task blocking that occur during long-term operation of the microcontroller.

[0244] Reference Figure 6 The process of fault self-diagnosis and self-healing is explained. For example... Figure 6 As shown, the fault self-healing process includes three branches: analog fault, digital fault, and system fault.

[0245] The analog fault branch addresses voltage drift, spike interference, and sensor disconnection, and performs analog-to-digital conversion zero-point calibration and sampling parameter enhancement. The digital fault branch addresses communication errors, data packet loss, and port lag, and performs timing data interpolation fault tolerance and communication port reset.

[0246] The system fault branches correspond to clock skew anomalies, direct memory access controller (DMA) transfer anomalies, and task scheduling anomalies, and perform task restarts and clock base recalibration. After each branch is completed, the fault type, occurrence time, and repair operations are recorded in the fault log storage area.

[0247] The following details the steps involved in fault self-diagnosis and self-healing. Specifically, after obtaining the time-aligned heterogeneous digital-analog signal, the process also includes:

[0248] S701: Obtain the current voltage drift of the analog original signal, obtain the current communication bit error rate of the digital communication original signal, and determine the task blocking duration of the microcontroller in the current cycle.

[0249] The current voltage drift, current communication bit error rate, and task blocking duration are used to characterize the magnitude of the analog sampling channel's deviation from the reference voltage, the proportion of abnormal frames in the digital communication link, and the waiting time for critical signal processing tasks to be executed by the processor, respectively.

[0250] In some embodiments of this application, in step S701, the voltage value output by the analog-to-digital converter in the current sampling period can be subtracted from a pre-stored reference voltage value, and the absolute value can be taken to obtain the current voltage drift. The reference voltage value is the reference voltage recorded during the power-on initialization phase or after the most recent successful calibration. The calculation formula is:

[0251]

[0252] Among them, in this formula This represents the output voltage value of the analog-to-digital converter during the current sampling period. For reference voltage value, This represents the current voltage drift.

[0253] Meanwhile, the number of frames that were determined to be abnormal after the communication peripheral received an interruption and were detected by cyclic redundancy check within the most recent observation period can be counted. Dividing this number by the total number of frames received within that observation period yields the current communication bit error rate. The calculation formula is:

[0254]

[0255] in, The number of abnormal frames. This represents the total number of received frames. This represents the current communication error rate.

[0256] In addition, the cumulative time that a critical signal processing task has been in a blocked state in the current cycle can be read through the task status query interface provided by the real-time operating system, which can be used as the task blocking duration.

[0257] S702. The current voltage drift, current communication error rate, and task blocking duration are compared with the corresponding preset fault tolerance thresholds to obtain a comprehensive fault judgment result.

[0258] In some embodiments of this application, in step S702, the current voltage drift amount can be compared with a preset voltage drift tolerance threshold. If the current voltage drift amount is greater than the voltage drift tolerance threshold, an analog signal drift fault is recorded in the comprehensive fault determination result. The current communication bit error rate can be compared with a preset bit error rate tolerance threshold. If the current communication bit error rate is greater than the bit error rate tolerance threshold, a digital communication bit error fault is recorded in the comprehensive fault determination result. The task blocking duration can be compared with a preset blocking duration tolerance threshold. If the task blocking duration is greater than the blocking duration tolerance threshold, a task scheduling blocking fault is recorded in the comprehensive fault determination result. The comparisons of the three dimensions are performed independently, and finally, all triggered fault types are summarized into a comprehensive fault determination result.

[0259] S703. In the preset repair instruction library, determine the target state repair instruction corresponding to the comprehensive fault judgment result. The repair instruction library includes at least one of the following: analog-to-digital conversion zero-point calibration instruction, communication port reset instruction, and chip task restart instruction.

[0260] The repair instruction library is a set of mapping relationships between fault types and repair operations; among them, the analog-to-digital conversion zero-point calibration instruction is used to update the real-time zero-point offset, the communication port reset instruction is used to reset the communication peripheral status, and the chip task restart instruction is used to resume the scheduling and execution of blocked tasks.

[0261] In some embodiments of this application, in step S703, the corresponding target state repair instruction can be searched one by one in the repair instruction library according to the fault type recorded in the comprehensive fault determination result. If the comprehensive fault determination result includes an analog signal drift fault, an analog-to-digital conversion zero-point calibration instruction is matched; if it includes a digital communication bit error fault, a communication port reset instruction is matched; if it includes a task scheduling blocking fault, a chip task restart instruction is matched. When the comprehensive fault determination result contains multiple fault types, multiple target state repair instructions can be determined simultaneously.

[0262] S704, Execute the target state repair command.

[0263] In some embodiments of this application, in step S704, the corresponding repair operations can be executed sequentially according to the type of the target state repair instruction.

[0264] When the target state repair command is an analog-to-digital converter zero-point calibration command, the input channel of the analog-to-digital converter can be switched to the internal reference ground channel, a sampling conversion can be performed, the conversion result can be updated to a new real-time zero-point offset, and the value can be written to the calibration parameter storage area.

[0265] When the target state repair instruction is a communication port reset instruction, it can disable the receive enable of the communication peripheral, clear residual data in the receive buffer, and perform a soft reset operation on the communication peripheral hardware registers. After the reset is complete, the communication parameters are reconfigured and the receive enable is enabled again.

[0266] When the target state repair instruction is a chip task restart instruction, the target task in a blocked state can be deleted through the task management interface of the real-time operating system, releasing the stack and control block resources it occupies. The task is then recreated with the same task parameters and initial priority and added to the ready queue. After execution, the fault type, occurrence time, and executed repair instructions can be written to the fault log storage area.

[0267] Through steps S701 to S704, the voltage drift, communication error rate, and task blocking duration can be summarized into a comprehensive fault judgment result, and the corresponding target state repair instruction can be executed according to the repair instruction library.

[0268] Secondly, such as Figure 7 As shown, embodiments of this application provide a microcontroller-based heterogeneous digital-analog signal processing system, applied to a microcontroller, the system comprising:

[0269] The global timing reference generation module is used to generate a global timing reference based on the microcontroller's timer.

[0270] The analog signal acquisition and latching module is used to acquire analog raw signals using the analog-to-digital converter of the microcontroller, and latch the corresponding analog signal timing stamp from the global timing reference at the start trigger moment of acquiring the analog raw signal;

[0271] The digital signal receiving and latching module is used to receive the original digital communication signal using the communication peripherals of the microcontroller, and latch the corresponding digital signal timing stamp from the global timing reference at the interrupt response time of receiving the original digital communication signal.

[0272] The signal timing alignment module is used to perform timing alignment processing on the original analog signal and the original digital communication signal based on the analog signal timing stamp and the digital signal timing stamp, so as to obtain the timing aligned digital-analog heterogeneous signal.

[0273] Thirdly, embodiments of this application provide a microcontroller, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the microcontroller-based heterogeneous digital-analog signal processing method as described in any of the above embodiments.

[0274] Specifically, in one implementation, the microcontroller can be implemented using an STM32F407 series chip. This microcontroller integrates a processor core, non-volatile memory, random access memory, direct memory access controller, analog-to-digital converter, timers, and communication peripherals. The processor core executes embedded firmware stored in the non-volatile memory, coordinating with the analog-to-digital converter, direct memory access controller, timers, and communication peripherals. This enables the acquisition of analog raw signals, reception of digital communication raw signals, timing stamp latching, timing alignment processing, filtering processing, compensation processing, correction processing, dynamic resource scheduling, and fault repair processing.

[0275] Fourthly, embodiments of this application provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the microcontroller-based heterogeneous digital-analog signal processing method as described in any of the above embodiments.

[0276] Fifthly, embodiments of this application provide a computer program product, including a computer program that is executed by a processor to implement the microcontroller-based heterogeneous digital-analog signal processing method as described in any of the above embodiments.

[0277] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. Furthermore, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for processing heterogeneous digital and analog signals based on a microcontroller, characterized in that, Applied to a microcontroller, the method includes: A global timing reference is generated based on the timer of the microcontroller; The analog-to-digital converter of the microcontroller is used to acquire the original analog signal, and at the trigger moment of acquiring the original analog signal, the corresponding analog signal timing stamp is latched from the global timing reference. Using the communication peripherals of the microcontroller, the original digital communication signal is received, and at the interrupt response time of receiving the original digital communication signal, the corresponding digital signal timing stamp is latched from the global timing reference; Based on the analog signal timing stamp and the digital signal timing stamp, the analog original signal and the digital communication original signal are time-aligned to obtain a time-aligned analog-digital heterogeneous signal.

2. The microcontroller-based heterogeneous digital-analog signal processing method as described in claim 1, characterized in that, Before performing timing alignment processing on the analog original signal and the digital communication original signal based on the analog signal timing stamp and the digital signal timing stamp, the method further includes performing filtering processing on the analog original signal, the filtering processing including: The simulated original signal is stored in the corresponding signal sliding window; By removing extreme value data within the signal sliding window, a set of effective sampling points including multiple effective sampling points is obtained. Based on the average value of the data in the set of valid sampling points, the confidence weight of each valid sampling point in the set of valid sampling points is determined, and based on the confidence weight, the valid sampling points in the set of valid sampling points are weighted and summed to obtain the global weighted mean. Based on the data standard deviation of the effective sampling point set, determine the current dynamic hysteresis threshold of the signal sliding window; Delete the target valid sampling point from the set of valid sampling points, where the difference between the voltage value of the target valid sampling point and the global weighted mean is greater than the dynamic hysteresis threshold.

3. The microcontroller-based heterogeneous digital-analog signal processing method as described in claim 2, characterized in that, Before performing timing alignment processing on the analog original signal and the digital communication original signal based on the analog signal timing stamp and the digital signal timing stamp, the method further includes performing compensation processing on the analog original signal, the compensation processing including: After deleting the target valid sampling points from the set of valid sampling points, the remaining valid sampling points in the set of valid sampling points are used as target simulated sampling points respectively; Obtain the digital reference state of the original digital communication signal; If the digital reference state is in a stable state, obtain the real-time zero-point offset and real-time temperature change of the analog-to-digital converter. Determine the temperature drift compensation amount corresponding to the real-time temperature change; The voltage value of the target simulated sampling point is compensated using the temperature drift compensation amount and the real-time zero-point offset.

4. The microcontroller-based heterogeneous digital-analog signal processing method as described in claim 3, characterized in that, Before performing timing alignment processing on the analog original signal and the digital communication original signal based on the analog signal timing stamp and the digital signal timing stamp, the method further includes performing a correction process for the digital communication original signal, the correction process including: Based on the target simulated sampling points after the compensation process, determine the effective value of the simulated sampling in the current period, and obtain the effective value of the simulated sampling in the previous period of the current period. Based on the current period's effective value of the analog sample, the previous period's effective value of the analog sample, and the sampling period of the analog-to-digital converter, the real-time gradient of the analog signal is determined. Obtain the data change amount of the original digital communication signal in the current period; If the real-time change gradient of the analog signal is less than the preset maximum mutation threshold, and the amount of data change is greater than the preset data mutation limit, the valid digital data of the original digital communication signal in the current period is determined to be abnormal communication data. The abnormal communication data is corrected using the valid digital data from the two previous cycles of the original digital communication signal in the current cycle.

5. The microcontroller-based heterogeneous digital-analog signal processing method as described in claim 2, characterized in that, After obtaining the time-aligned digital-analog heterogeneous signal, the process further includes: The real-time occupancy rate of the microcontroller in the current period is calculated, and the sampling flow of the analog-to-digital converter collecting the analog raw signal and the communication frame flow of receiving the digital communication raw signal in the current period are extracted. Based on the real-time occupancy rate, the sampling traffic, and the communication frame traffic, the overall system load score of the microcontroller is determined. If the overall system load score is greater than a preset first load threshold, the sampling rate of the analog-to-digital converter and the filtering order of the signal sliding window used to remove the extreme value data are reduced, and the alignment task that performs the timing alignment processing is adjusted to a preset first priority. If the overall system load score is less than a preset second load threshold, the sampling rate of the analog-to-digital converter and the filtering order of the signal sliding window used to remove the extreme value data are increased, and the alignment task is adjusted to a preset second priority, where the second load threshold is less than the first load threshold and the second priority is lower than the first priority.

6. The microcontroller-based heterogeneous digital-analog signal processing method as described in claim 1, characterized in that, Before performing time alignment processing on the original analog signal and the original digital communication signal based on the analog signal time stamp and the digital signal time stamp, the process further includes: Obtain the communication protocol type, effective byte length, and link load traffic of the original digital communication signal; Based on the communication protocol type, the effective byte length, and the link load traffic, the compensation delay of the original digital communication signal is determined; Using the compensation delay and the digital signal timing stamp, a corrected digital timing stamp is generated; Determine the absolute value of the deviation between the analog signal timing stamp and the corrected digital timing stamp; If the absolute value of the deviation is greater than a preset deviation threshold, the clock division parameter corresponding to the communication peripheral is adjusted based on the absolute value of the deviation.

7. The microcontroller-based heterogeneous digital-analog signal processing method as described in claim 1, characterized in that, After obtaining the time-aligned digital-analog heterogeneous signal, the process further includes: The current voltage drift of the analog original signal is obtained, the current communication bit error rate of the digital communication original signal is obtained, and the task blocking duration of the microcontroller in the current cycle is determined. The current voltage drift, the current communication bit error rate, and the task blocking duration are compared with the corresponding preset fault tolerance thresholds to obtain a comprehensive fault judgment result. In a preset repair instruction library, a target state repair instruction corresponding to the comprehensive fault determination result is determined, wherein the repair instruction library includes at least one of an analog-to-digital conversion zero-point calibration instruction, a communication port reset instruction, and a chip task restart instruction; Execute the target state repair command.

8. A microcontroller-based heterogeneous digital-analog signal processing system, characterized in that, The system, applied to a microcontroller, includes: A global timing reference generation module is used to generate a global timing reference based on the timer of the microcontroller; The analog signal acquisition and latching module is used to acquire analog raw signals using the analog-to-digital converter of the microcontroller, and latch the corresponding analog signal timing stamp from the global timing reference at the start trigger time of acquiring the analog raw signals; The digital signal receiving and latching module is used to receive the original digital communication signal using the communication peripheral of the microcontroller, and latch the corresponding digital signal timing stamp from the global timing reference at the interrupt response time of receiving the original digital communication signal; The signal timing alignment module is used to perform timing alignment processing on the original analog signal and the original digital communication signal based on the analog signal timing stamp and the digital signal timing stamp, so as to obtain a timing-aligned analog-digital heterogeneous signal.

9. A microcontroller, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the microcontroller-based heterogeneous digital-analog signal processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program, which, when executed by a processor, implements the steps of the microcontroller-based heterogeneous digital-analog signal processing method according to any one of claims 1 to 7.

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