A method and system for SLC NAND dynamic array reconfiguration

Abstract

The application relates to the technical field of solid-state storage, and discloses an SLC NAND dynamic array reconstruction method and system, the method comprising the following steps: acquiring the erasing times and historical programming time consumption of a physical block, performing feature extraction and state classification to obtain an initial wear degree; acquiring a charge retention amount according to the initial wear degree, judging a potential failure risk, and regressing to predict a remaining service period; comparing the remaining service period with a scheduling decision threshold to generate a data migration instruction; extracting target data according to the data migration instruction and matching the target data to be written into a target physical block to obtain an array reconstruction result. The method can realize forward-looking control of single-cell flash memory wear, and improves data reliability and storage system operation efficiency.

Description

Technical Field

[0001] This invention relates to the field of solid-state storage technology, and in particular to a method and system for dynamic array reconfiguration of SLC NAND. Background Technology

[0002] Currently, in the field of solid-state storage technology, ensuring the reliability of single-cell flash memory is a key aspect of preventing data corruption and mitigating the risk of storage failure, and has become a key research area in application-specific integrated circuit design and storage system management.

[0003] In one existing technology, wear leveling is primarily used to ensure the lifespan of flash memory media. This relies mainly on fixed erase counts or a single threshold for evaluation, such as using an instantaneous status response mode to perform data migration tasks and judging the health of physical blocks by the number of simple erases. However, this approach is clearly insufficient in complex workload environments. Fixed rules cannot adapt to the dynamic changes in the aging rate of physical blocks, and single-index evaluation is easily affected by differences in read / write frequencies and charge leakage. It is also affected by cell insulation degradation and increased write time, which can easily lead to difficulties in ensuring data reliability during storage. Furthermore, it lacks the ability to proactively predict and reconstruct potential physical failures. Especially in scenarios with high-frequency, intensive writes and accelerated block degradation, it is difficult to avoid data read errors caused by management lags, resulting in low system efficiency.

[0004] In summary, existing technologies are insufficient to proactively manage the wear and tear process of single-cell flash memory, and cannot meet the core requirement of long-term data reliability in solid-state storage technology when facing complex workloads. Summary of the Invention

[0005] This invention provides a method and system for dynamic array reconfiguration of SLC NAND to achieve proactive control of the wear process of single-cell flash memory, meeting the core requirement of long-term reliability of stored data in solid-state storage technology when facing complex workloads.

[0006] Firstly, in order to solve the above-mentioned technical problems, the present invention provides an SLC NAND dynamic array reconfiguration method, comprising: Obtain the number of erases and historical programming time for physical blocks in a single-level cell flash memory; Based on the number of erasures and the historical programming time, feature extraction and state classification are performed to obtain the initial wear level of the physical block; The charge retention amount is obtained based on the initial wear level. If the charge retention amount is less than the preset capacity warning threshold, it is determined that the physical block has a potential failure risk. Regression prediction processing is performed based on the initial wear level and the charge retention amount to obtain the remaining service life. If the charge retention amount is not less than the capacity warning threshold, it is determined that the physical block is in normal condition. If the physical block has a potential failure risk, the remaining service life is compared with a preset scheduling decision threshold; if the remaining service life is less than the scheduling decision threshold, a data migration instruction for the physical block is generated; if the remaining service life is not less than the scheduling decision threshold, a regular monitoring instruction is generated. The target data within the physical block is extracted according to the data migration instruction to obtain the data to be reconstructed; the target physical block is matched in the single-level cell flash memory according to the data to be reconstructed, and the data to be reconstructed is written into the target physical block to obtain the array reconstruction result.

[0007] In a second aspect, the present invention provides an SLC NAND dynamic array reconfiguration system, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the SLC NAND dynamic array reconfiguration method as described above.

[0008] Thirdly, the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the SLC NAND dynamic array reconfiguration method as described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention obtains the number of erases and historical programming time of physical blocks in a single-level cell flash memory, constructs a state feature vector and performs node splitting and purity evaluation processing. After gain determination and multi-dimensional classification determination, a voting matrix is ​​generated and the initial wear degree is obtained. This invention breaks through the limitation that the traditional single erase count index cannot reflect the difference in the actual aging speed of physical blocks under complex workloads. It integrates the dual-dimensional wear characteristics of erase accumulation and programming time to accurately quantify the health status of blocks, solves the problem that fixed threshold evaluation is easily affected by the difference in read and write frequency and charge leakage, which leads to misjudgment of wear degree, and provides an accurate state classification basis for the dynamic reconstruction of flash arrays.

[0010] (2) This invention reads the voltage distribution offset characteristics based on the initial wear degree and fits the distribution curve to obtain the charge retention amount. It extracts the charge loss rate by combining the resting time and calculates the risk assessment value with the voltage drift amount. When the risk exceeds the standard and the charge retention amount is lower than the capacity warning threshold, it determines the potential failure risk. Then, it extracts the distribution morphology feature vector and inputs it into the regression prediction model to obtain the degradation rate and extrapolates the limit erase threshold to determine the remaining service life. It breaks through the limitation of traditional passive response management lacking the ability to predict physical failure in advance. It quantifies the remaining usable life by nonlinear mapping of charge retention decay trajectory and multidimensional degradation characteristics. It accurately identifies the hidden degradation block where the number of erases has not reached the threshold but the charge retention capacity has significantly decreased. It makes up for the defects of existing methods that cannot predict risks before physical blocks completely fail and the timing of migration is inaccurate.

[0011] (3) This invention combines physical block read / write frequency and dynamic wear rate to compensate and correct the remaining service life. When the remaining service life is less than the scheduling decision threshold, the migration priority is evaluated and a data migration instruction is generated. The instruction is parsed to extract the target data and the data to be reconstructed is obtained through redundancy check error correction and fragment splicing. The target physical blocks with low erase / write cycles are selected in the free page mapping table and a page programming sequence is generated. After state distribution prediction and verification, charge injection is performed to complete the array reconstruction. A full-link dynamic array reconstruction system is constructed from multi-dimensional wear assessment, remaining life prediction, risk prospective judgment to active data migration and secure writing. It breaks through the limitations of traditional wear leveling strategies that rely on real-time state response and management that lags behind the actual degradation process. It takes into account the early identification of potential failure blocks and the reliable reconstruction of data on healthy media. It effectively improves the long-term data reliability and storage system operation efficiency of single-level cell flash memory under complex workloads and meets the core requirements of solid-state storage technology for forward-looking life management and data integrity assurance. Attached Figure Description

[0012] Figure 1 This is a schematic diagram of a SLC NAND dynamic array reconstruction method provided in the first embodiment of the present invention; Figure 2 This is a schematic diagram of charge retention decay and failure risk determination provided in the first embodiment of the present invention; Figure 3 This is a schematic diagram of the threshold voltage distribution after array reconstruction provided in the first embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Reference Figure 1 The first embodiment of the present invention provides a method for reconfiguring an SLC NAND dynamic array, comprising the following steps: S101, obtain the number of erases and historical programming time of physical blocks in a single-level cell flash memory; S102, perform feature extraction and state classification processing based on the number of erasures and the historical programming time to obtain the initial wear degree of the physical block; S103, obtain the corresponding charge retention amount according to the initial wear level. If the charge retention amount is less than the preset capacity warning threshold, it is determined that the physical block has a potential failure risk. Regression prediction processing is performed according to the initial wear level and the charge retention amount to obtain the remaining service life. If the charge retention amount is not less than the capacity warning threshold, it is determined that the physical block is in normal condition. S104, if the physical block has a potential failure risk, compare the remaining service life with a preset scheduling decision threshold; if the remaining service life is less than the scheduling decision threshold, generate a data migration instruction for the physical block; if the remaining service life is not less than the scheduling decision threshold, generate a regular monitoring instruction. S105, extract the target data within the physical block according to the data migration instruction to obtain the data to be reassembled; match the target physical block in the single-level cell flash memory according to the data to be reassembled, and write the data to be reassembled into the target physical block to obtain the array reconstruction result.

[0015] In step S101, the number of erases and the historical programming time of the physical blocks in the single-level cell flash memory are obtained.

[0016] It's important to note that the erase count for a physical block records the total number of erase operations performed on that block since it was manufactured. The flash memory controller has a dedicated erase counter register. Each time a block erase command is executed on a physical block, the flash memory controller automatically increments the counter value at the corresponding physical address and writes the updated value back to the non-volatile memory area where the register resides, ensuring the count is not lost after power failure. To obtain the erase count, the microprocessor sends a status read command to the target physical block via the flash memory interface. This command includes the physical block address of that block. The flash memory controller responds by returning a data frame containing multi-byte status information. The hexadecimal erase count field is parsed from the data frame and converted to a decimal value to obtain the erase count. The read precision is one complete program erase cycle, measured in units of erasures (k).

[0017] Historical programming time refers to the actual time required to complete a single-page data programming operation for a physical block over a past period. The flash memory controller contains a high-precision timer that resets to zero and starts counting each time a page programming operation begins, stopping when the programming completion signal is triggered. The count result multiplied by the timer's clock cycle yields the raw programming time, measured in microseconds. The timer's clock source is typically an internal oscillator with a frequency of 1 MHz and a timing resolution of 1 microsecond. To obtain historical programming time, the flash memory controller's runtime log buffer is read. This buffer stores the most recently completed programming operation records in a first-in, first-out (FIFO) manner. Each record contains the physical page address, programming start timestamp, and time value. After extracting the most recent programming time values ​​for the target physical block, the arithmetic mean of these time values ​​is calculated as the historical programming time for that physical block.

[0018] It should be noted that there is a physical relationship between the number of erases and the programming time. As the number of erases increases, the accumulation of trap charges in the tunnel oxide layer of the floating gate transistor leads to a decrease in electron injection efficiency, and the programming time gradually increases. Combining the number of erases and the historical programming time into an ordered set of values ​​can serve as the basic input for subsequent feature extraction and state classification processing.

[0019] In step S102, feature extraction and state classification are performed based on the number of erasures and the historical programming time to obtain the initial wear level of the physical block, including: A state feature vector is constructed based on the number of erasures and the historical programming time. Perform node splitting and purity evaluation processing on the state feature vector to obtain the node splitting gain value; If the node split gain value is greater than the preset gain determination threshold, then multi-dimensional classification and determination processing is performed on the state feature vector to obtain a voting matrix; if the node split gain value is not greater than the gain determination threshold, then the classification and determination processing is terminated. The initial wear level of the physical block is obtained by performing majority voting statistics based on the voting matrix.

[0020] It should be noted that, firstly, a state feature vector is constructed based on the number of erases and the historical programming time. The number of erases for the target physical block is read from the flash controller's status register, and the arithmetic mean of the most recent programming times for that physical block is extracted from the runtime log cache as the historical programming time. These two values, the number of erases and the historical programming time, are arranged in chronological order to form a one-dimensional array of length 2, which serves as the state feature vector for that physical block. The unit for the number of erases is times, and the value typically ranges from 0 to 10. 5The programming time is measured in microseconds, typically ranging from 200 to 800. The state feature vector is normalized using min-max normalization, mapping it to a dimensionless interval of 0 to 1, resulting in a normalized state feature vector. The normalization baseline range starts from the initial erase count of 0 at the time of manufacture and the historical lowest programming time of 200 microseconds, ending at the maximum erasable count and programming time limit specified in the flash memory datasheet. The maximum erasable count is obtained from the flash memory chip's datasheet, typically 100,000 times. The programming time limit is set as the programming timeout threshold determined by the flash memory controller, typically 1000 microseconds.

[0021] Next, node splitting and purity evaluation are performed on the state feature vectors to obtain the node splitting gain value. The classification process here uses a classification and regression tree model, which constructs decision rules by recursively splitting the training dataset into binary trees. The training dataset is constructed by performing cyclic erasure programming operations on 100 physical blocks under a constant temperature of 25℃. After each cycle, the number of erasures, programming time, and number of error bits during readback verification are recorded. When the number of error bits continuously exceeds the error correction engine's upper limit, the block is marked as having reached the end of its lifespan. The proportion of error bits in each cycle relative to the error correction upper limit is used as the classification criterion: below 30% is marked as slight wear, 30% to 60% as moderate wear, and 60% to 100% as severe wear. Approximately 5000 samples were collected and divided into training and validation sets in a 7:3 ratio.

[0022] Secondly, the classification and regression tree model uses the Gini coefficient as a node purity evaluation metric during training. Starting from the root node, the model traverses both dimensions of the state feature vector: the number of erases and the programming time, trying all possible split points in each dimension. For a candidate split point, the model divides the training samples within the current node into a left and right subset, calculates the Gini coefficient for each subset, and uses the proportion of samples in the left and right subsets as weights to calculate the sum of the weighted Gini coefficients corresponding to that split point. Subtracting the sum of the weighted Gini coefficients from the node's Gini coefficient before splitting yields the node split gain value. The model selects the split point with the largest node split gain value among all candidate split points as the optimal split point for the current node and assigns samples to the left and right child nodes accordingly. The child nodes continue the above splitting process until all samples within the node belong to the same label category or the number of samples within the node is less than the preset minimum number of split samples (3), ultimately forming a complete binary decision tree. During model training, the maximum tree depth is set to 4 layers, the minimum number of split samples is 3, and there is no limit on the minimum number of leaf nodes, in order to balance the model's generalization ability and the risk of overfitting.

[0023] Subsequently, the node split gain value is compared with a preset gain determination threshold. The gain determination threshold determines whether to continue the classification determination process, and this threshold is set based on the statistical characteristics of the Gini coefficient gain. The Gini coefficient gain ranges from 0 to 1. When the gain value approaches 0, it indicates that the class distribution of samples within the current node is nearly uniform, and further splitting will not help improve classification purity. Therefore, the gain determination threshold is set to 0.05. If the node split gain value of the current node is greater than 0.05, it indicates that the split has sufficient classification discrimination. Then, according to the child node path after the split of the classification and regression tree model, the state feature vector to be determined is sent to the corresponding child node for multidimensional classification determination processing.

[0024] The multidimensional classification process is as follows: the state feature vector starts from the root node and is passed down layer by layer according to the segmentation rules of each node. At each internal node, the model determines whether to proceed to the left or right child node based on the node's segmentation dimension and threshold, continuing until a leaf node is reached. This leaf node stores the sample distribution of various wear level labels that fell into it during training. The model reads the sample distribution of this leaf node and records the votes for each label, thus constructing a voting matrix. Each row of the voting matrix corresponds to the current decision tree's judgment result, and each column corresponds to the three categories: slight wear, moderate wear, and severe wear. The matrix elements represent the number of training samples for the corresponding category within the leaf node. If the node split gain of the current node is not greater than 0.05, further splitting is considered negligible in terms of contribution to classification accuracy, and the classification process is terminated. The label category with the largest number of samples in the current node is directly used as the initial wear level judgment result.

[0025] Then, majority voting statistics are performed based on the voting matrix to obtain the initial wear level of the physical block. The majority voting statistics process involves iterating through each category column of the voting matrix, summing the element values ​​of each column to obtain the total votes for the slight wear category, the moderate wear category, and the severe wear category. The values ​​of these three total votes are compared, and the category with the highest total votes is selected as the final classification result for that state feature vector. If two categories have the same number of votes, the category with the more severe wear level is prioritized; that is, severe wear takes precedence over moderate wear, and moderate wear takes precedence over slight wear, thus ensuring the conservatism of the physical block lifetime assessment. The final output initial wear level is one of the three category labels: slight wear, moderate wear, or severe wear. This label reflects the wear stage of the physical block under the current number of erases and programming time, providing a classification basis for subsequent dynamic array reconstruction.

[0026] In step S103, the charge retention amount is obtained according to the initial wear level. If the charge retention amount is less than a preset capacity warning threshold, it is determined that the physical block has a potential failure risk, and regression prediction processing is performed based on the initial wear level and the charge retention amount to obtain the remaining service life. If the charge retention amount is not less than the capacity warning threshold, it is determined that the physical block is in normal condition, including: The voltage distribution offset characteristics of the physical block are read based on the initial wear level; Based on the voltage distribution offset characteristics, a distribution curve fitting process is performed to obtain the charge retention amount; The attenuation trajectory fitting process is performed based on the charge retention amount and the pre-acquired resting time to obtain the charge loss rate; The risk assessment value is obtained by performing a product operation on the charge loss rate and the pre-acquired voltage drift. The risk assessment value is compared with a preset risk benchmark threshold; if the risk assessment value is greater than the risk benchmark threshold, the operation of comparing the charge retention amount with the capacity warning threshold is triggered; if the risk assessment value is not greater than the risk benchmark threshold, the physical block is determined to be in normal condition.

[0027] It should be noted that the voltage distribution offset characteristics of physical blocks are read based on the initial wear level. Physical blocks belonging to the same initial wear level are used as a statistical set. A read reference voltage scan command is sequentially sent through the flash memory controller, increasing from 0V to 4.5V in 25mV increments. At each step, the number of memory cells turned on in that block is recorded. A measured threshold voltage distribution curve is plotted with voltage value on the horizontal axis and the number of turned-on cells on the vertical axis. This curve is compared with the threshold voltage distribution curve of a new flash memory chip at the time of manufacture, and the voltage difference at the peak positions of the two curves is calculated, i.e., the voltage distribution offset characteristic, in mV. Slight wear corresponds to an offset within 50mV, moderate wear between 50mV and 150mV, and severe wear between 150mV and 300mV. These ranges were obtained by performing 100,000 cycles of full lifecycle wear testing on 20 chips, with data recorded every 1000 cycles.

[0028] Next, the charge retention is obtained by performing distribution curve fitting based on the voltage distribution offset characteristics. Specifically, a Gaussian mixture model is used to perform multi-peak fitting on the threshold voltage distribution curve. Each storage cell of a single-level flash memory stores one bit, and its threshold voltage distribution curve is composed of the superposition of two independent Gaussian peaks, corresponding to the peak value in the erase state and the peak value in the programming state, respectively. As wear intensifies, the position of the Gaussian peak in the programming state shifts towards lower voltages, while the peak width gradually widens. The Gaussian mixture model fitting process decomposes the measured threshold voltage distribution curve into two Gaussian components, each described by three parameters: peak position, peak width, and weight. After fitting, the peak position parameter of the Gaussian component in the programming state is extracted and denoted as... The minimum reliable read threshold voltage defined in the flash memory datasheet is denoted as... Due to wear causing a negative drift in the programmed threshold voltage, the voltage offset... The charge retention, or the equivalent number of electrons n currently stored on the floating gate, is physically related to the capacitance-voltage equation. Therefore, charge retention .in, This is the coupling capacitance between the control gate and the floating gate, obtained by consulting the flash memory chip datasheet; a typical value is... Farad; q is the charge of a single electron, which is coulomb.

[0029] Secondly, the charge loss rate is obtained by performing attenuation trajectory fitting processing based on the charge retention amount and the pre-acquired resting time. The resting time refers to the natural resting time elapsed since the last data write to the physical block until the current moment. This time is recorded by the real-time clock module inside the flash memory controller. Each time a page programming operation is performed on the physical block, the real-time clock module writes the timestamp of that moment into the physical block's metadata area. Upon reading, the timestamp field in the metadata area is parsed and subtracted from the current clock module's time value; the difference is the resting time, expressed in hours. The attenuation trajectory fitting processing uses a power-law attenuation model to describe the charge loss pattern on the floating gate over time. The power-law attenuation model assumes that the attenuation of the charge retention amount follows a power-law relationship with time, specifically in the form of… Where n(t) is the charge retention after t hours of rest, n0 is the manufacturer's nominal initial charge, and α is the decay exponent. The fitting process uses multiple sets of charge retention data pairs under different resting times as input. These data pairs originate from historical records collected at different time points from the same physical block. Using charge retention as the vertical axis variable and resting time as the horizontal axis variable, the decay exponent parameter of the power-law decay model is solved using the least squares method. The charge loss rate is obtained by converting the decay exponent α with the current charge retention, i.e., λ = α × n(t) / t, with the unit being the charge loss per hour. The power-law decay model is valid only if the resting time exceeds 24 hours. For resting times less than 24 hours, the linear decay slope between the charge retention and the manufacturer's nominal initial charge is directly used as the charge loss rate. The manufacturer's nominal initial charge is obtained by consulting the flash memory chip specifications, with a typical value such as 500 electrons. If the actual operating temperature of the flash memory exceeds 85°C, the power-law model's description of high-temperature accelerated loss will become nonlinear. In this case, the Arrhenius acceleration model should be used for correction calculation.

[0030] Subsequently, a risk assessment value is obtained by multiplying the charge loss rate with the pre-acquired voltage drift. The voltage drift is acquired in real time by reading the temperature sensor and voltage reference source embedded in the flash memory chip. The temperature sensor, integrated on the substrate of the flash memory chip, measures the chip junction temperature through a bandgap reference circuit, outputting a temperature value with an accuracy of ±2℃. The flash memory controller periodically reads the temperature value at a sampling frequency of 1Hz. The voltage reference source provides a stable internal reference voltage, and the flash memory controller simultaneously reads the difference between the current supply voltage and the internal reference voltage as the voltage drift. When the temperature value exceeds the normal operating temperature range of 0℃ to 70℃ specified in the flash memory datasheet, the voltage drift reading is multiplied by a margin factor of 1.5 to reflect the accelerating effect of temperature on charge loss. The charge loss rate read at the current moment is directly multiplied by the voltage drift, and the product result is the risk assessment value. The dimension of this product is electron-volts per hour, which means the energy dissipation rate of charge loss per unit voltage drift amplitude, and can be used as a comprehensive engineering indicator of flash memory data retention risk.

[0031] The preset risk baseline threshold is calibrated using a reliability test report provided by the flash memory chip manufacturer. The report describes a 1000-hour accelerated aging test of data retention capability on samples from the same batch of chips under nine different operating conditions: 25°C, 60°C, and 85°C, and 90%, 100%, and 110% of the nominal voltage. The bit error rate (BER) data for each physical block is recorded every 24 hours, along with the charge loss rate and voltage drift of each physical block. The risk assessment value at the corresponding sampling time is calculated, aligning the BER data with the risk assessment value on the timeline.

[0032] The product values ​​corresponding to the moment when the bit error rate first exceeds the error correction capability of the error correction engine under all operating condition combinations are selected. The minimum value among these values ​​is then multiplied by a safety margin coefficient of 0.7 to determine the risk baseline threshold. The safety margin coefficient of 0.7 is used to compensate for individual differences in batch production. If the risk assessment value is greater than the risk baseline threshold, it indicates that the current physical block is in a high-risk range for data retention, posing a risk of data loss, and triggering an operation to compare the charge retention amount with the capacity warning threshold.

[0033] The capacity warning threshold is a boundary value for the charge retention amount used to determine whether a physical block has a potential failure risk. Based on the data retention failure characteristics specified in the flash memory datasheet, this embodiment sets it to the number of electrons corresponding to the data retention failure threshold, with a typical value of 80 electrons. When the charge retention amount is lower than this threshold, the physical block is determined to have a potential failure risk. If the risk assessment value is not greater than the risk benchmark threshold, the physical block is determined to be in normal condition, and the current array mapping relationship and refresh strategy remain unchanged.

[0034] In one implementation, the step of performing regression prediction processing based on the initial wear level and the charge retention amount to obtain the remaining service life includes: Based on the initial wear level and the charge retention amount, distribution feature extraction processing is performed to obtain a distribution morphology feature vector; The distribution morphology feature vector is input into a pre-trained regression prediction model to perform nonlinear mapping processing, thereby obtaining the degradation rate value. A linear extrapolation calculation is performed based on the degradation rate value and the initial wear level to obtain the ultimate erase / write threshold. The remaining service life is determined based on the stated write / erase threshold.

[0035] It should be noted that the initial wear level is a discrete category label, with three values: slight wear, moderate wear, and severe wear. Converted to one-hot encoded form, slight wear corresponds to the vector [1,0,0], moderate wear to [0,1,0], and severe wear to [0,0,1]. Charge retention is a continuous value describing the number of equivalent electrons currently stored on the floating gate. This value is subjected to min-max normalization, with the lower bound being the number of electrons corresponding to the data retention failure threshold defined in the flash memory specification, and the upper bound being the number of electrons in the initial programmed state defined in the flash memory specification. The typical value for the number of electrons corresponding to the data retention failure threshold is 80, and the typical value for the number of electrons in the initial programmed state is 500. The one-hot encoded three-dimensional wear category vector is concatenated with the normalized charge retention value to form a one-dimensional array of length 4, which is the distribution feature vector.

[0036] Next, the distribution feature vector is input into a pre-trained regression prediction model to perform nonlinear mapping processing, obtaining the degradation rate value. The regression prediction model adopts a support vector regression model, and the kernel function is a radial basis function. Nonlinear mapping is achieved by finding the optimal regression hyperplane in the high-dimensional feature space. The components of each dimension of the input vector are mapped by the kernel function and then weighted and combined with the support vectors to finally output a continuous degradation rate prediction value.

[0037] Secondly, the training dataset construction process for the regression prediction model is as follows: Samples were collected from a full-lifecycle accelerated aging test platform for flash memory chips. The test platform used 10 flash memory chips from the same batch to perform cyclic erase programming operations at a high temperature of 85℃. After each cycle, the number of erases, threshold voltage distribution, and the number of error bits after readback verification of the written data for each physical block were recorded. The lifespan termination criterion was used when the number of error bits first exceeded 80% of the error correction limit of the flash memory controller's error correction code engine. The corresponding number of erases at this point was recorded as the actual lifespan termination erase count.

[0038] For each physical block, several sampling points are selected at equal erase intervals throughout its lifecycle. The initial wear level category and charge retention value corresponding to each sampling point are recorded as input features, and the degradation rate corresponding to that sampling point is used as the regression label. The degradation rate d=N end / (N end -N cur ), where N end N represents the number of erase / write cycles until the actual end of the device's lifespan. cur The current erase / write count for this sampling point is represented by the degradation rate, which characterizes the equivalent lifetime consumed per erase / write cycle. It should be noted that the training samples were taken from an 85°C high-temperature accelerated aging environment. However, in actual applications, the operating temperature of flash memory is usually lower than this value. To eliminate the influence of temperature differences on the degradation rate calibration results, during training, the equivalent lifetime consumption at 85°C was converted to the corresponding value at the actual operating temperature using the Arrhenius acceleration model before being used as the regression label. The actual operating temperature was read by the temperature sensor embedded in the flash memory chip. Approximately 800 valid samples were collected from 10 chips in this manner and randomly divided into training and validation sets at a ratio of 7:3.

[0039] Subsequently, during the training of the support vector regression model, the kernel width coefficient γ and the error penalty parameter C are determined through a grid search on the training set. The candidate values ​​for γ during the grid search range from 2... -8 to 2 8 As the value increases progressively by powers of 2, the range of candidate values ​​for C also increases from 2... -8 to 2 8The parameters are incremented sequentially by powers of 2. For each candidate parameter combination, a support vector regression model is trained on the training set, and the root mean square error (RMSE) between the predicted values ​​and the true labels is calculated on the validation set. The optimal hyperparameter combination is selected, minimizing the RMSE on the validation set. After fixing the optimal hyperparameters, the model is retrained once using all the training set data to obtain the final regression prediction model. An ε-insensitive loss function is used to measure the prediction error during model training, with ε set to 0.1 times the standard deviation of the validation set labels. The morphological feature vector is input into the trained support vector regression model, which outputs a continuous degradation rate value. This value represents the equivalent lifetime consumed per erase / write cycle under the current wear state and charge retention capability, and is a dimensionless ratio.

[0040] The linear extrapolation calculation process involves reading the accumulated erase counts of the current physical block directly from the erase count register of the flash memory controller. The maximum number of erase cycles specified in the flash memory chip datasheet is taken as the manufacturer's nominal lifetime limit. The current accumulated erase counts are subtracted from the manufacturer's nominal lifetime limit to obtain an estimated upper limit for the remaining erase cycles. This estimated upper limit for the remaining erase cycles is then divided by the degradation rate to obtain the equivalent remaining erase / write cycles, i.e., the ultimate erase / write threshold. The physical meaning of this ultimate erase / write threshold is the number of standardized erase / write cycles that the physical block can withstand under the current degradation rate.

[0041] Subsequently, the remaining service life is determined based on the write limit threshold. The average daily write / erase count for this physical block over the past 7 days, as recorded by the flash controller, is obtained. The average daily write / erase count is calculated by dividing the total write / erase count over 7 days by 7. The write limit threshold is then divided by the average daily write / erase count; the quotient is the remaining service life, expressed in days. The remaining service life represents the number of days the physical block is expected to maintain normal data storage functionality under the current usage intensity and wear / degradation trend.

[0042] like Figure 2 As shown in the figure, this graph illustrates the decay trajectory of the physical block charge retention amount as a function of resting time and the failure risk assessment results. The curve clearly shows that after fitting the floating gate charge loss law to the power-law decay model, the charge retention amount, which was initially at a relatively high level (approximately...), decreases. The charge retention was effectively tracked as the resting time accumulated, exhibiting a rapid decline followed by a stabilization trajectory. Specifically, in the first 200 hours of resting, the charge retention decreased from approximately [missing value]. Sharply down to about It then enters a slow decay phase, and at approximately 500 hours (the current state marked by the red dot), the charge retention drops to... It has fallen below the preset capacity warning threshold. (Red dashed line) Triggers potential failure risk assessment. This result intuitively demonstrates that the proposed solution's multi-dimensional degradation feature fusion mechanism—which integrates reading voltage distribution offset characteristics, performing Gaussian mixture model distribution curve fitting to obtain charge retention, combining resting time to perform attenuation trajectory fitting to extract charge loss rate, and calculating risk assessment values ​​with voltage drift—can accurately identify failure risks in the latent degradation stage where the charge retention capability has significantly decreased even though the number of physical block erasures has not reached the lifetime limit. This provides a solid quantitative data foundation for subsequent regression prediction processing to obtain the remaining service life and generate data migration instructions or routine monitoring instructions.

[0043] In step S104, if the physical block has a potential failure risk, the remaining service life is compared with a preset scheduling decision threshold; if the remaining service life is less than the scheduling decision threshold, a data migration instruction for the physical block is generated; if the remaining service life is not less than the scheduling decision threshold, a regular monitoring instruction is generated, including: The read / write frequency of the physical block is obtained, and a multivariate linear fitting process is performed based on the read / write frequency and the number of erases to obtain the dynamic wear rate; Based on the dynamic wear rate, a compensation calculation is performed on the remaining service life to obtain the corrected remaining service life; The remaining correction period is compared with a preset scheduling decision threshold; If the remaining correction period is less than the scheduling decision threshold, the attributes of the data block to be processed and the capacity of the receiving area are extracted in advance and priority evaluation is performed to obtain the migration priority. Data migration instructions for the physical block are generated based on the migration priority.

[0044] It should be noted that read / write frequency refers to the frequency with which a physical block is accessed by the host within the past 24 hours. The flash memory controller maintains a 32-bit access counter and a 16-bit timestamp register for each physical block. The counter increments with each read / write operation, and the timestamp is updated to the current clock value. During a read operation, the counter value is divided by the actual duration of the statistical window and then multiplied by 86400 to obtain the daily read / write frequency, expressed as times per day. The number of erases is read directly from the erase count register. A binary linear regression equation is constructed using read / write frequency as the first independent variable, the number of erases as the second independent variable, and dynamic wear rate as the dependent variable.

[0045] Secondly, the fitting coefficients of the binary linear regression equation were offline calibrated using historical operating datasets and then embedded in the flash memory controller firmware. The historical operating datasets were collected by selecting 10 flash memory chips from the same batch and running them continuously for 90 days in a real-world operating environment. During this period, the flash memory controller recorded the read / write frequency, erase count increment, and charge retention decay of each physical block every 24 hours. The charge retention decay was measured using the same method as the charge retention data acquisition method described above, obtained by periodically executing a read reference voltage scan command on the physical block and fitting a Gaussian mixture model. The 24-hour decay was the difference between two consecutive measurements. Dividing the 24-hour decay by the initial programmed state electron count of the flash memory cell (500) yielded the equivalent wear rate caused by the combined effects of read / write interference and erase wear within those 24 hours. This equivalent wear rate was used as the dependent variable label. Approximately 1800 valid samples were extracted from the 90-day operating data of the 10 chips in this manner. Each sample contained three values: read / write frequency, erase count, and equivalent wear rate. 1800 sets of samples are input into the least squares fitting solver. The solver outputs three fitting parameters for the bivariate linear regression equation: the intercept coefficient, the read / write frequency coefficient, and the erase count coefficient. These three fitting parameters are written into the non-volatile configuration area of ​​the flash memory controller. During online operation, the flash memory controller reads the read / write frequency and erase count of the current physical block, multiplies these two values ​​by the read / write frequency coefficient and the erase count coefficient, respectively, and adds the intercept coefficient to obtain the dynamic wear rate. The physical dimension of the dynamic wear rate is the equivalent wear ratio per unit day.

[0046] Next, a compensation calculation is performed on the remaining service life based on the dynamic wear rate to obtain the corrected remaining life. The compensation calculation process involves comparing the dynamic wear rate with a preset reference wear rate value, which is obtained by referring to the nominal durability data in the flash memory chip's datasheet. The flash memory datasheet states that the chip can withstand 100,000 erase cycles under standard test conditions, defined as 50 erase cycles per day and a read interference ratio of 10:1.

[0047] Under these standard test conditions, the baseline wear rate is 50 cycles / day divided by 100,000 cycles, which equals 0.0005 cycles / day. Dividing the current physical block's dynamic wear rate by the baseline wear rate of 0.0005 yields a rate ratio, which represents the multiple of the current usage intensity relative to the standard test intensity. Dividing the remaining service life by this rate ratio yields the corrected remaining service life, in days. The corrected remaining service life comprehensively reflects the actual usable time window under the current read / write frequency, erase count, and their coupling effect, providing a more accurate reflection of the actual workload faced by the physical block than the original remaining service life.

[0048] Subsequently, the remaining cycle time is compared with the scheduling decision threshold. The scheduling decision threshold is set statistically based on the data migration safety time window of the flash memory chips in actual applications. Time series data of multiple flash memory chips from the same batch under normal operating conditions before failure are selected, and the 10th percentile of the interval in days from triggering a potential failure risk alarm to the actual occurrence of an uncorrectable data error is calculated. This 10th percentile is used as the base scheduling decision threshold, with a base value set to 7 days. For write-intensive load scenarios such as video surveillance storage, this threshold can be adjusted upwards within the range of 1.2 to 1.5 times the base value; for read-intensive load scenarios such as database queries, this threshold can be adjusted downwards within the range of 0.8 to 1.1 times the base value. The threshold adjustment range is set during deployment based on the actual business load characteristics through the configuration registers of the flash memory controller firmware.

[0049] Then, if the remaining correction period is less than the scheduling decision threshold, the pre-acquired attributes of the data blocks to be processed and the receiving area capacity are extracted, and priority evaluation processing is performed to obtain the migration priority. The attributes of the data blocks to be processed include the number of valid data pages in the data block and the number of data pages marked as invalid. These two values ​​are obtained by traversing the metadata flag bits of each physical page within the physical block; the flag bit for valid pages is 1, and the flag bit for invalid pages is 0. The receiving area capacity refers to the number of currently available free physical blocks in the flash memory chip, which can be obtained by scanning the free page mapping table of the flash memory controller. The specific method of priority evaluation processing is to perform min-max normalization on the three values: the number of valid data pages, the number of invalid data pages, and the number of free physical blocks. The lower bound of the normalization is taken as the total number of physical pages in the physical block (0) and the total number of free blocks (0), and the upper bound is taken as the upper limit of the total number of physical pages in the physical block and the total number of physical blocks in the chip. After normalization, a weighted summation is performed on the three values. The weight of the number of valid data pages is set to 0.2 because the more valid data pages there are, the larger the amount of data to migrate, and the priority should be appropriately reduced rather than increased. The weight of invalid data pages is set to 0.5 because a high percentage of invalid pages indicates low space utilization in the physical block, making data migration cost-effective and highly beneficial, thus deserving the highest weight. The weight of idle physical blocks is set to 0.3 because migration operations will not cause congestion when the receiving end has sufficient capacity, allowing for a more appropriate increase in priority. The weighted sum is the migration priority value, ranging from 0 to 1, with a higher value indicating a greater urgency for data migration in that physical block.

[0050] Next, data migration instructions for physical blocks are generated based on migration priorities. All physical blocks within the current flash memory chip with potential failure risks and remaining correction cycles less than the scheduling decision threshold are sorted from highest to lowest migration priority. The top few physical blocks after sorting are selected as source blocks to be migrated. For each source block to be migrated, a free physical block is sequentially extracted from the free page map table as the migration target block. The order of the free page map table is arranged in ascending order of physical block address. The generated data migration instructions include the source physical block address, the target physical block address, and the migration operation command word. The migration operation command word instructs the flash memory controller to perform a page copy operation, i.e., reading valid data page by page from the source physical block and writing it to the corresponding physical page of the target physical block. After the copy is completed, the source physical block is marked as awaiting reclamation, and the logical address mapping table entry pointing to the source physical block is updated to the physical address of the target physical block. After the data migration is completed, the erase count register value of the source physical block is cleared, and the physical block is added to the end of the free page map table to await future allocation.

[0051] It should be noted that if the remaining cycle is not less than the scheduling decision threshold, it indicates that the current wear and degradation rate of the physical block is within a controllable range, and the probability of data loss in the next scheduling cycle is low. In this case, there is no need to trigger a data migration operation, but it is necessary to continuously track the state change trend of the physical block; therefore, a routine monitoring instruction is generated.

[0052] Next, the routine monitoring command includes three fields: monitoring interval duration, monitoring indicator type, and next evaluation timestamp. The monitoring interval duration is set to the difference between the remaining service life and the scheduling decision threshold multiplied by 24 hours. This calculation method allows the monitoring frequency to naturally increase as the remaining service life shortens. To avoid missed detections due to excessively long monitoring intervals or wasted resources due to excessively short intervals, the monitoring interval duration is limited to between 1 hour and 720 hours. If the duration calculated using the above formula exceeds this range, the corresponding boundary value is used. The monitoring indicator type includes three items: erase count, programming time, and charge retention. The next evaluation timestamp is set to the current real-time clock time plus the monitoring interval duration. After receiving the routine monitoring command, the flash memory controller writes the three fields in the command to the metadata extension area of ​​the physical block. The timer is retried when the next evaluation timestamp arrives to re-trigger the wear assessment and remaining service life calculation for the physical block.

[0053] In step S105, target data within the physical block is extracted according to the data migration instruction to obtain data to be reassembled; the target physical block is matched in the single-level cell flash memory according to the data to be reassembled, and the data to be reassembled is written into the target physical block to obtain the array reconstruction result, including: The data migration instructions are parsed to obtain the logical address mapping relationship and physical offset; The read boundary parameters are calculated based on the physical offset and the pre-acquired physical page size; The physical block is subjected to level signal conversion processing based on the read boundary parameters to obtain the original data fragment and redundancy check code; Based on the redundancy check code, perform iterative error correction calculation on the original data segment to obtain a usable data segment; The available data fragments are then joined with the pre-acquired fragmented data in memory to obtain the data to be reconstructed.

[0054] Data migration instructions use 16-byte fixed-length encoding, storing the source physical block address, target physical block address, mapping table starting index, and physical offset sequentially. They can be extracted byte-by-byte offset. The logical address mapping records the logical address number corresponding to each valid data page, and the physical offset records the page offset of the first valid data page relative to the start of the block. The flash memory controller maintains a logical-to-physical mapping table in the reserved management area, with each block corresponding to one mapping page. Each record consists of a 32-bit logical address number and a 32-bit physical page offset.

[0055] The physical page size is obtained by consulting the flash memory chip datasheet, with a typical value of 16KB. Using the physical offset as the starting page address for the read operation, the physical offsets of all valid page records within the physical block are sequentially read from the mapping table. The largest offset value is found, incremented by 1, and multiplied by the physical page size; the product is the maximum number of bytes to be read. Multiplying the physical offset by the physical page size yields the starting byte address, and the maximum number of bytes serves as the end point of the read range. The starting byte address and the maximum number of bytes together constitute the read boundary parameters, both measured in bytes. Based on these parameters, the flash memory controller initiates continuous page read operations to the target physical block, covering the entire physical storage area from the starting byte address to the maximum number of bytes.

[0056] Secondly, level signal conversion processing is performed on the physical block according to the read boundary parameters to obtain the original data segment and redundancy check code. The flash memory controller applies a read reference voltage to each word line of the target physical block through a built-in charge pump boost circuit. The read reference voltage is based on multiple reference voltage settings given in the flash memory datasheet. This setting is determined by a voltage search strategy embedded in the flash memory controller firmware. It is applied sequentially in 25mV steps within the range of 0V to 4.5V, and the bit flip ratio is detected. After the read reference voltage is applied, each memory cell determines its conduction state based on the number of electrons on its floating gate. When conducting, the charge on the bit line is detected by the inductive amplifier and converted into a binary logic level of 0 or 1. The flash memory controller aggregates the level data of all bit lines in the same physical page into an original data segment. The length of the original data segment of each physical page is equal to the physical page size of 16KB. Redundancy check (BCH) codes are check bytes automatically added by the error correction engine during page programming of the flash memory chip. They are stored in a spare area at the end of each page of data, with a capacity of 2208 bytes. The BCH code is used, with a code rate of 512 bytes of data plus 24 bytes of check code. A single page can correct up to 40 bits of errors.

[0057] Subsequently, iterative error correction calculations are performed on the original data segment according to the redundancy check code to obtain a usable data segment. The error correction code engine selects the BCH iterative decoding algorithm. First, it calculates the syndrome polynomial of the original data segment. If the syndrome is all zero, it is determined that there is no error and the original data is directly output. If the syndrome is non-zero, the Berlekamp-Massey iterative algorithm is called to solve the error location polynomial. Then, the Chien search algorithm is used to determine the specific position of the error bit in each sub-code block, and the bit corresponding to the error position is flipped from 0 to 1 for correction. Each iteration processes a 512-byte data sub-code block and its corresponding 24-byte check code. A single page contains a total of 32 sub-code blocks. After the error correction code engine corrects each one, it concatenates the de-checked pure data parts of all sub-code blocks in sequence to obtain a usable data segment of approximately 16KB in length. If the number of error bits in a sub-code block exceeds the error correction capability limit of 40 bits of the BCH code, the sub-code block is marked as uncorrectable. The flash memory controller discards the sub-code segment data and records an uncorrectable error event.

[0058] Then, the available data segments are concatenated with the pre-acquired preceding fragment data in memory to obtain the data to be reassembled. The preceding fragment data consists of available data segments logically contiguous with the data in other physical blocks preceding the current physical block. This preceding fragment data has been read during the pre-migration operation and temporarily stored in the flash controller's internal SRAM buffer, which has a capacity of 256KB. The flash controller appends the available data segments of this physical block to the end of the preceding fragment data in the internal SRAM buffer in ascending memory address order. The two segments form a contiguous data set in the memory address space, which is the data to be reassembled. The starting byte address of the data to be reassembled corresponds to the first byte of the preceding fragment data, and the ending byte address corresponds to the last byte of the current available data segment.

[0059] In one implementation, the step of matching a target physical block in the single-level cell flash memory according to the data to be reassembled, and writing the data to be reassembled into the target physical block to obtain the array reconstruction result includes: Extract the metadata tags corresponding to the data to be reassembled, and traverse the free page mapping table of the single-level cell flash memory according to the metadata tags; Free blocks with fewer erase counts than the limit threshold are selected from the free page mapping table and used as target physical blocks. Obtain the physical characteristic parameters of the target physical block, and generate the initial programming voltage and step voltage based on the physical characteristic parameters; A page programming sequence is generated based on the initial programming voltage and the step voltage. Charge injection is then performed on the target physical block according to the page programming sequence to obtain the array reconstruction result.

[0060] It should be noted that the metadata tag is stored at the header of the buffer containing the data to be reassembled, occupying 32 bytes, and includes three fields: the logical partition number to which the data belongs, the data priority identifier, and the total length of the data. The free page map is a bitmap structure built by the flash controller during the initialization phase through a full disk scan. Each physical block corresponds to one bit; a bit value of 1 indicates that the physical block is currently free, and a bit value of 0 indicates that the physical block is occupied or unavailable due to a bad block marker. When traversing the free page map, it reads sequentially from the starting byte of the bitmap, skipping physical blocks with a bit value of 0, and only retaining candidate free blocks with a bit value of 1.

[0061] Next, free blocks with erase counts below a threshold are selected as target physical blocks based on the free page mapping table. The threshold is set as follows: the median erase count of all physical blocks in the current flash memory chip is calculated. Specifically, the erase count register of each physical block is read, all values ​​are sorted in ascending order, and the middle value is taken. If the total number of physical blocks is even, the arithmetic mean of the two middle values ​​is taken. This median value is multiplied by 1.2 to obtain the threshold. This threshold avoids both the concentrated use of brand-new physical blocks causing thermal wear areas and the use of physical blocks nearing the end of their lifespan for storing migration data. For each candidate free block, its erase count is read from the erase count register and compared with the threshold. Only physical blocks with erase counts below the threshold are selected. If multiple physical blocks are selected, the one with the furthest distance between its physical block address and the source physical block address is chosen first. The physical block address distance is defined as the absolute value of the difference between the two physical block addresses, thus balancing the charge pump load distribution across different areas of the flash memory chip.

[0062] Secondly, the physical characteristic parameters of the target physical block are obtained, and the initial programming voltage and step voltage are generated based on these parameters. The physical characteristic parameters include the number of erases for the target physical block and the average programming time recorded since manufacturing. These two parameters are obtained in the same way as the erase count and historical programming time obtained in the previous steps. The initial programming voltage is determined by a lookup table. A programming voltage reference table is pre-installed in the flash memory controller firmware. This table is calibrated by the flash memory chip manufacturer through wafer-level testing and burned into the chip's read-only memory area. The table contains 256 entries, with the quotient of the erase count divided by 1000 as the index address. Each entry stores the optimal initial programming voltage value corresponding to that erase / write interval. This reference table is a standard configuration in the chip's factory firmware. Those skilled in the art can directly obtain the initial programming voltage value corresponding to each erase interval by reading the flash memory chip's read-only memory area, or set it according to the ISPP start voltage recommended in the chip datasheet. The step voltage is fixed at 200mV, a value derived from the recommended step amplitude for incremental step pulse programming in the flash memory datasheet.

[0063] Subsequently, a page programming sequence is generated based on the initial programming voltage and the step voltage. Charge injection is then performed on the target physical block according to this sequence to obtain the array reconstruction result. The page programming sequence is generated using an incremental step pulse programming method. The first programming pulse applies the initial programming voltage to the word line of the target physical page, with a fixed pulse width of 30 microseconds. Immediately after the pulse ends, a read verification is performed on the page, comparing the read data bit-by-bit with the corresponding portion of the data to be reconstructed. If the comparison matches, the page is marked as successfully programmed. If the comparison does not match, the programming voltage is increased by one step voltage value, and a second pulse is applied, maintaining the same pulse width. This pulse application and verification process is repeated until the read data completely matches the data to be reconstructed or the cumulative number of pulses reaches the maximum programming pulse count limit of 8 specified in the flash memory specification. Charge injection is performed on all data pages of the data to be reconstructed in this manner. After all pages are programmed, the flash memory controller marks the target physical block as occupied and updates the mapping table entries from logical addresses to target physical addresses, thus obtaining the array reconstruction result.

[0064] According to the page programming sequence, charge injection processing is performed on the target physical block to obtain array reconstruction results, including: The page programming sequence is input into the state distribution prediction model to perform distribution extrapolation processing, resulting in the state distribution prediction curve; Extract the peak width value of the state distribution prediction curve and compare the peak width value with a preset safety margin threshold. If the peak width value does not exceed the safety margin threshold, then a programming injection instruction is sent to the target physical block according to the page programming sequence to obtain the array reconstruction result; If the peak width value exceeds the safety margin threshold, a sequence adjustment instruction is generated and the page programming sequence is regenerated.

[0065] It should be noted that the state distribution prediction model adopts a feedforward neural network structure. The input layer receives a 4-dimensional vector, specifically the initial programming voltage value, step voltage value, pulse width value, and erase count value of the target physical block in the page programming sequence. The hidden layer has two layers, each containing 16 neurons, and the activation function is a linear rectified function. The output layer generates four values, corresponding to the peak position and peak width parameters of the Gaussian distribution of the programming state, and the peak position and peak width parameters of the Gaussian distribution of the erase state, respectively. The training dataset for this model was obtained from accelerated aging tests of flash memory chips. Different programming voltage combinations were applied to 10 chips under different erase / write cycles. After each programming cycle, the threshold voltage distribution was measured by reading the reference voltage scan command, and the peak position and peak width of each distribution were obtained by fitting a Gaussian mixture model as labels. Approximately 2000 samples were accumulated, and the training and validation sets were divided in a 7:3 ratio. During training, a mean squared error loss function was used, with an initial learning rate of 0.001, which decayed to 0.8 every 50 rounds. Training stopped when the validation set loss did not decrease for 20 consecutive rounds.

[0066] Next, the 4D input vector corresponding to the page programming sequence is fed into the model for forward propagation. The output of each hidden layer is activated by a linear rectified function and then passed on. The output layer directly outputs the 4D result without using an activation function. The peak width parameter corresponding to the programming state in the output is multiplied by 2.355 to obtain the peak width value. This value represents the broadening of the threshold voltage distribution of the memory cell after programming, and its dimension is V.

[0067] The safety margin threshold is determined based on the data retention reliability boundary defined in the flash memory chip datasheet. The flash memory datasheet specifies that, within the normal operating temperature range, if the peak width of the programming state threshold voltage distribution exceeds 0.3V, it will cause the decision boundaries of adjacent memory states to overlap, causing the bit error rate to exceed the error correction capability of the error correction engine. Therefore, the safety margin threshold is set to 0.3V. If the peak width does not exceed 0.3V, it indicates that the threshold voltage distribution generated by the current page programming sequence meets the reliable storage requirements. Then, a programming injection command is sent to the page buffer of the target physical block according to the voltage step and pulse parameters in the page programming sequence. The flash memory controller applies pulses sequentially, and reads a verification after each pulse is completed until the data is correctly written, obtaining the array reconstruction result.

[0068] Subsequently, if the peak width exceeds 0.3V, a sequence adjustment instruction is generated and the page programming sequence is regenerated. The sequence adjustment instruction reduces the step voltage by 50mV from its original value and extends the pulse width by 10 microseconds, thereby reducing the increment of charge injection each time and reducing the dispersion of injection amount between cells. The page programming sequence is reassembled with the adjusted parameters and input into the state distribution prediction model again for distribution extrapolation. If the peak width still exceeds the threshold after adjustment, the step voltage continues to decrease in 50mV increments until the peak width is below 0.3V or the step voltage drops to the lower limit of 100mV, and then the final programming injection instruction is executed.

[0069] like Figure 3 As shown in the figure, this graph displays the state distribution prediction curve of the threshold voltage distribution of the target physical block after array reconstruction. The probability density distribution clearly shows that after the state distribution prediction model extrapolates the distribution of the page programming sequence, the threshold voltage distribution, which might have overlapped due to wear and degradation, is effectively separated into two independent Gaussian components: the erase state (green fill, peak value approximately 0.8V) and the programming state (red fill, peak value approximately 2.5V). These two components form a clear decision boundary at the decision reference voltage (purple dashed line, approximately 1.5V). However, the peak width of the programming state, marked in the figure, is 0.59V, exceeding the preset safety margin threshold of 0.3V. This indicates that the threshold voltage distribution generated by the current page programming sequence is too broad, and there is a risk of overlapping decision boundaries between adjacent memory states. This result intuitively demonstrates that the proposed scheme uses a feedforward neural network state distribution prediction model to predict the threshold voltage distribution after programming, extract peak width values, and compare them with the safety margin threshold. This hierarchical verification mechanism can predict whether the programming quality meets the reliable storage requirements before charge injection. If the peak width exceeds the standard, a sequence adjustment instruction (reducing the step voltage and extending the pulse width) is triggered to regenerate the page programming sequence, thereby effectively eliminating the hidden danger of threshold voltage distribution degradation caused by improper programming parameters. This provides a solid distribution pattern verification data foundation for maintaining the reliability of the array reconstruction results.

[0070] In summary, this invention discloses a dynamic array reconstruction method for SLC NAND, which enables proactive control of single-cell flash memory wear and improves data reliability and storage system operating efficiency.

[0071] A second embodiment of the present invention provides an SLC NAND dynamic array reconfiguration system, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method described above.

[0072] It should be noted that the SLC NAND dynamic array reconstruction system provided in this embodiment of the invention is used to execute all the process steps of the SLC NAND dynamic array reconstruction method in the above embodiment. The working principle and beneficial effects of the two are one-to-one, so they will not be described again.

[0073] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for reconfiguring an SLC NAND dynamic array, characterized in that, include: Obtain the number of erases and historical programming time for physical blocks in a single-level cell flash memory; Based on the number of erasures and the historical programming time, feature extraction and state classification are performed to obtain the initial wear level of the physical block; The charge retention amount is obtained based on the initial wear level. If the charge retention amount is less than the preset capacity warning threshold, it is determined that the physical block has a potential failure risk. Regression prediction processing is performed based on the initial wear level and the charge retention amount to obtain the remaining service life. If the charge retention amount is not less than the capacity warning threshold, then the physical block is determined to be in normal condition; If the physical block has a potential failure risk, the remaining service life is compared with a preset scheduling decision threshold; if the remaining service life is less than the scheduling decision threshold, a data migration instruction for the physical block is generated; if the remaining service life is not less than the scheduling decision threshold, a regular monitoring instruction is generated. The target data within the physical block is extracted according to the data migration instruction to obtain the data to be reassembled; the target physical block is matched in the single-level cell flash memory according to the data to be reassembled, and the data to be reassembled is written into the target physical block to obtain the array reconstruction result; The step of obtaining the corresponding charge retention amount based on the initial wear level includes: reading the voltage distribution offset characteristics of the physical block based on the initial wear level; performing distribution curve fitting processing based on the voltage distribution offset characteristics to obtain the charge retention amount; performing attenuation trajectory fitting processing based on the charge retention amount and a pre-acquired resting time to obtain the charge loss rate; performing a product operation processing based on the charge loss rate and a pre-acquired voltage drift amount to obtain a risk assessment value; comparing the risk assessment value with a preset risk benchmark threshold; if the risk assessment value is greater than the risk benchmark threshold, triggering an operation to compare the charge retention amount with the capacity warning threshold; if the risk assessment value is not greater than the risk benchmark threshold, determining that the physical block is in normal condition.

2. The SLC NAND dynamic array reconfiguration method according to claim 1, characterized in that, The step of performing feature extraction and state classification processing based on the number of erasures and the historical programming time to obtain the initial wear level of the physical block includes: A state feature vector is constructed based on the number of erasures and the historical programming time. Perform node splitting and purity evaluation processing on the state feature vector to obtain the node splitting gain value; If the node split gain value is greater than the preset gain determination threshold, then multi-dimensional classification and determination processing is performed on the state feature vector to obtain a voting matrix; if the node split gain value is not greater than the gain determination threshold, then the classification and determination processing is terminated. The initial wear level of the physical block is obtained by performing majority voting statistics based on the voting matrix.

3. The SLC NAND dynamic array reconfiguration method according to claim 1, characterized in that, The step of performing regression prediction processing based on the initial wear level and the charge retention amount to obtain the remaining service life includes: Based on the initial wear level and the charge retention amount, distribution feature extraction processing is performed to obtain a distribution morphology feature vector; The distribution feature vector is input into a pre-trained regression prediction model to perform nonlinear mapping processing, thereby obtaining the degradation rate value. A linear extrapolation calculation is performed based on the degradation rate value and the initial wear level to obtain the ultimate erase / write threshold. The remaining service life is determined based on the stated write / erase threshold.

4. The SLC NAND dynamic array reconfiguration method according to claim 1, characterized in that, The remaining service life is compared with a preset scheduling decision threshold; if the remaining service life is less than the scheduling decision threshold, a data migration instruction for the physical block is generated, including: The read / write frequency of the physical block is obtained, and a multivariate linear fitting process is performed based on the read / write frequency and the number of erases to obtain the dynamic wear rate; Based on the dynamic wear rate, a compensation calculation is performed on the remaining service life to obtain the corrected remaining service life; The remaining correction period is compared with a preset scheduling decision threshold; If the remaining correction period is less than the scheduling decision threshold, the attributes of the data block to be processed and the capacity of the receiving area are extracted in advance and priority evaluation is performed to obtain the migration priority. Data migration instructions for the physical block are generated based on the migration priority.

5. The SLC NAND dynamic array reconfiguration method according to claim 1, characterized in that, The step of extracting the target data within the physical block according to the data migration instruction to obtain the data to be reassembled includes: The data migration instructions are parsed to obtain the logical address mapping relationship and physical offset; The read boundary parameters are calculated based on the physical offset and the pre-acquired physical page size; The physical block is subjected to level signal conversion processing based on the read boundary parameters to obtain the original data fragment and redundancy check code; Based on the redundancy check code, perform iterative error correction calculation on the original data segment to obtain a usable data segment; The available data fragments are then joined with the pre-acquired fragmented data in memory to obtain the data to be reconstructed.

6. The SLC NAND dynamic array reconfiguration method according to claim 1, characterized in that, The step of matching the target physical block in the single-level cell flash memory according to the data to be reconstructed, and writing the data to be reconstructed into the target physical block to obtain the array reconstruction result includes: Extract the metadata tags corresponding to the data to be reassembled, and traverse the free page mapping table of the single-level cell flash memory according to the metadata tags; According to the free page mapping table, free blocks with fewer erase / write cycles than the limit threshold are selected as target physical blocks; Obtain the physical characteristic parameters of the target physical block, and generate the initial programming voltage and step voltage based on the physical characteristic parameters; A page programming sequence is generated based on the initial programming voltage and the step voltage. Charge injection is then performed on the target physical block according to the page programming sequence to obtain the array reconstruction result.

7. The SLC NAND dynamic array reconfiguration method according to claim 6, characterized in that, The step of performing charge injection processing on the target physical block according to the page programming sequence to obtain the array reconstruction result includes: The page programming sequence is input into the state distribution prediction model to perform distribution extrapolation processing, resulting in the state distribution prediction curve; Extract the peak width value of the state distribution prediction curve and compare the peak width value with a preset safety margin threshold. If the peak width value does not exceed the safety margin threshold, then a programming injection instruction is sent to the target physical block according to the page programming sequence to obtain the array reconstruction result; If the peak width value exceeds the safety margin threshold, a sequence adjustment instruction is generated and the page programming sequence is regenerated.

8. An SLC NAND dynamic array reconfiguration system, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the SLC NAND dynamic array reconstruction method according to any one of claims 1 to 7.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by the processor, the program implements the SLC NAND dynamic array reconstruction method according to any one of claims 1 to 7.

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