A data read-write method, device and equipment of a solid state disk

Abstract

The application discloses a data read-write method of a solid state disk, comprising the following steps: step one, capacity parameter acquisition; step two, virtual block construction; step three, storage area division management; step four, read-write instruction identification; and step five, data read-write execution. The application also discloses a data read-write method device of a solid state disk, comprising a capacity calculation module, a virtual block allocation module, a division management module, a read-write execution module and a self-adaptive optimization module. The application adopts a virtual block dynamic allocation mode based on the actual capacity of a system table, calculates the ratio of the total capacity of the system table to the capacity of a single entity block, determines the required number of entity blocks, and reasonably integrates a plurality of small-capacity system tables in the same virtual block corresponding entity block, thereby avoiding the space waste caused by the single small-capacity system table occupying a complete entity block.

Description

Technical Field

[0001] This invention relates to the field of solid-state drive (SSD) storage technology, and in particular to a method, apparatus, and device for reading and writing data on a solid-state drive. Background Technology

[0002] Solid-state drives (SSDs), also known as solid-state drives, are hard drives made of solid-state electronic storage chip arrays. Because they do not have the mechanical devices such as drives required by mechanical hard drives, and there are no moving parts inside the entire disk, they are called solid-state drives. SSDs use NAND flash memory as their core storage medium and have advantages such as non-volatility, high speed, and low power consumption. They are widely used in terminals, servers, and data centers.

[0003] Current data read / write methods for solid-state drives (SSDs) use fixed-capacity virtual blocks. Small-capacity system tables result in numerous idle blocks and low space utilization. The core issue with this fixed-capacity virtual block allocation is the failure to dynamically adjust the number and capacity of virtual blocks based on the actual capacity requirements of the system tables. This is particularly problematic for large numbers of small-capacity system tables, leading to severe idle NAND flash memory blocks and a significant reduction in space utilization. Therefore, this application proposes a data read / write method, apparatus, and device for solid-state drives (SSDs). Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a data reading and writing method, apparatus, and device for solid-state drives.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A method, apparatus, and device for reading and writing data on a solid-state drive (SSD) include the following steps:

[0007] Step 1: Capacity Parameter Acquisition and Calculation. Obtain the core capacity parameters required for the operation of the solid-state drive (SSD). First, collect the total capacity of all first system tables and the total capacity of all second system tables in the SSD. At the same time, obtain the fixed capacity of a single physical block in the NAND flash memory module. Then, based on the collected capacity parameters, calculate the number of physical blocks required to store the two types of system tables respectively. The number of physical blocks required to store the first system table is recorded as the first quantity, and the number of physical blocks required to store the second system table is recorded as the second quantity. Ensure that the calculation results can fully support the data of the corresponding system table without capacity overflow.

[0008] Step 2: Virtual Block Construction and Data Block Division. Complete the division of the system table storage area and the user data storage area. Based on the first and second quantities calculated in Step 1, select the corresponding number of physical blocks from all physical blocks of the NAND flash memory module, and construct the first virtual block and the second virtual block respectively. The first virtual block is dedicated to storing all first system tables, and the second virtual block is dedicated to storing all second system tables. At the same time, all other physical blocks except the selected virtual blocks are uniformly divided into data blocks to store user data from the host. The data blocks are initially partitioned to prepare for subsequent hot and cold data distribution.

[0009] Step 3: Storage area divide-and-conquer management, realizing independent scheduling of different types of storage areas. The chip enable CE areas and data planes of the NAND flash memory module are divided and managed. The first virtual block, the second virtual block and the data block are respectively allocated to different CE areas and data planes, realizing independent parallel management of the three types of areas, avoiding resource contention between system table data and user data during storage and read / write, and improving the overall read / write concurrency performance;

[0010] Step 4: Read / write command identification and matching. Complete the parsing of host commands and the invocation of corresponding logic. Receive read / write commands issued by the host through the host interface in real time. The controller parses the core information of the read / write command, including the command type, logical address of the target data, data length and data type. Based on the parsing results, match the corresponding read / write logic and determine the data read or write path.

[0011] Step 5: Data Read / Write Execution and Status Feedback. Complete data interaction and provide feedback on the running status. Based on the read / write logic matched in Step 4, and combined with the pre-operations of data temporary storage, ECC checksum generation, and FTL address mapping, the corresponding CE region and data plane are scheduled through a divide-and-conquer management mechanism to execute data read or write operations. During the data read / write process, cache scheduling, wear leveling, and garbage collection optimization logic are executed synchronously to ensure read / write efficiency and the lifespan of the solid-state drive. After the read / write operation is completed, the system table, logical address, and physical address mapping table are updated in a timely manner, and the read / write success or failure status information is sent back to the host to ensure communication synchronization between the host and the solid-state drive.

[0012] Preferably, the calculation logic for the capacity parameter in step one is to use an up-rounding method to calculate the ratio of the total capacity of all first system tables to the capacity of a single entity block to obtain a first quantity; and to calculate the ratio of the total capacity of all second system tables to the capacity of a single entity block to obtain a second quantity. By using up-rounding, the system table data can be fully stored, avoiding data loss or storage overflow due to insufficient capacity.

[0013] Preferably, the construction logic of the virtual blocks in step two is as follows: according to the priority order of CE region, data plane, and physical blocks, a first number of physical blocks are selected to form a first virtual block, and a second number of physical blocks are selected to form a second virtual block; the partitioning logic of virtual blocks and data blocks is independent of each other and does not occupy each other's storage resources. After the partitioning is completed, the number allocation of each block can be dynamically adjusted according to changes in system table capacity or user data volume.

[0014] Preferably, the specific logical operation process of data writing in step five is as follows: after the controller parses the host write instruction, if it determines that the data type is system table data, it will be diverted to the corresponding virtual block; if it determines that it is user data, it will be divided into hot data and cold data according to its access frequency, and diverted to the hot data area or cold data area of ​​the data block respectively; the data is first temporarily cached, and the corresponding ECC check code is generated. Then, the mapping from logical address to physical address is completed through FTL. The divide-and-conquer scheduling logic is used to realize concurrent writing of multiple CEs and multiple planes. After the writing is completed, the mapping table and the system table are updated, and the writing status is returned to the host.

[0015] Preferably, the divide-and-conquer scheduling logic specifically corresponds to the divide-and-conquer management mechanism in step three, which independently and in parallel manages the CE region and the data plane. For system table data and user data, as well as hot data and cold data, dedicated CE channels and data planes are allocated to avoid different types of data competing for read and write resources, thereby further improving write concurrency efficiency.

[0016] Preferably, the specific logical operation process of data reading in step five is as follows: after the controller parses the logical address and data length in the host read instruction, it first determines whether the target data exists in the cache. If the cache is hit, the data is directly sent back to the host; if it is not hit, the physical address of the target data is obtained through FTL mapping, the corresponding data plane is scheduled to read the target data in parallel, the data is sent into the cache after passing ECC verification, and then sent back to the host. At the same time, high-frequency read data is kept in the cache to optimize the subsequent read efficiency.

[0017] Preferably, the cache scheduling logic in step five specifically involves real-time statistics of the read frequency of all data, prefetching and caching frequently accessed hot data, and temporarily storing low-frequency accessed data in the free area of ​​the cache according to priority. When the cache capacity is insufficient, the cache space occupied by low-frequency data is released first, and the read and write response speed of hot data and system table data is guaranteed first.

[0018] Preferably, the data type identification logic in step four is to clearly distinguish between system table data and user data by parsing the data identifier field in the read / write instructions; wherein the first system table data is metadata with a capacity smaller than a single entity block, and the second system table data is metadata with a capacity not less than a single entity block; user data is further divided into hot data and cold data according to its access frequency, providing a basis for subsequent data diversion and divide-and-conquer scheduling, and realizing data classification read / write management.

[0019] An apparatus for reading and writing data on a solid-state drive includes the following modules:

[0020] Capacity calculation module: used to collect the total capacity and single entity block capacity of the first system table and the second system table, and to calculate the number of entity blocks required to store the two types of system tables;

[0021] Virtual block allocation module: Based on the number of blocks obtained by the capacity calculation module, it constructs the first virtual block and the second virtual block, divides the data blocks, and completes the initial marking of the storage area;

[0022] Divide and conquer management module: Used to perform parallel scheduling management of the CE region and data plane of NAND flash memory module, realize independent scheduling of virtual blocks and data blocks, and avoid resource contention;

[0023] Read / write execution module: used to parse read / write commands issued by the host, schedule cache, execute data read / write operations, and complete data verification and status feedback;

[0024] Adaptive optimization module: Used to perform cache scheduling, wear leveling and garbage collection logic to optimize read and write efficiency and extend the life of solid-state drives.

[0025] A solid-state drive (SSD) data read / write device includes a processor, which executes a computer program stored in a memory to implement the data read / write method of the SSD.

[0026] The present invention has the following beneficial effects:

[0027] 1. By dynamically allocating virtual blocks based on the actual capacity of the system table, the ratio of the total capacity of the system table to the capacity of a single physical block is calculated to determine the required number of physical blocks. Multiple small-capacity system tables are rationally integrated and stored in the physical blocks corresponding to the same virtual block. This avoids the waste of space caused by a single small-capacity system table occupying a complete physical block, effectively revitalizes idle storage space, reduces flash memory resource waste, significantly improves the utilization rate of NAND flash physical blocks, and avoids idle storage space.

[0028] 2. The CE region and data plane of NAND flash memory are managed in a separate manner. The virtual blocks storing the system table and the data blocks storing user data are allocated to different CE channels and data planes. This enables independent parallel reading and writing of system table data and user data, avoiding contention for read and write resources. At the same time, the dynamically allocated virtual blocks can optimize the storage location according to the access frequency of the system table, improve the read and write speed of the system table, thereby reducing the overall read and write latency of the solid-state drive and improving the concurrent read and write bandwidth. This is especially suitable for scenarios with high read and write performance requirements, such as data centers.

[0029] 3. By separating user data into hot and cold blocks and managing virtual blocks and data blocks independently, the system avoids mixing hot and cold data, reduces the generation of invalid data pages, lowers the frequency of garbage collection, and thus reduces write amplification and the number of NAND flash erases. At the same time, it uses wear leveling logic to count the number of erases of each physical block in real time and dynamically adjusts the data write position to achieve wear leveling of all flash blocks, effectively extending the overall lifespan of the solid-state drive and improving the stability and reliability of the device. Attached Figure Description

[0030] Figure 1 This is a flowchart illustrating the read / write logic of a solid-state drive data read / write method proposed in this invention.

[0031] Figure 2 This is a schematic diagram illustrating the management of virtual blocks in this invention;

[0032] Figure 3 This is a schematic diagram of the virtual block allocation device in this invention. Detailed Implementation

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0034] Reference Figure 1 A method for reading and writing data on a solid-state drive, comprising:

[0035] Step 1: Capacity Parameter Acquisition and Calculation

[0036] First, the core capacity parameters are collected through the parameter acquisition unit built into the controller: the total capacity of all first system tables (ECC verification information table 40MB, bad block marking table 20MB, device status variable table 20MB) S1=80MB, the total capacity of all second system tables (L2P mapping table 180MB, free block linked list 60MB, block wear statistics table 40MB) S2=280MB, the fixed capacity of a single physical block in the NAND flash memory module B=128MB, and the standard physical block capacity of TLC NAND can be adjusted according to the actual flash memory model;

[0037] Following the rounding-up calculation logic, calculate the first quantity and the second quantity respectively: The first quantity N1 = ceil(S1 / B) = ceil(80MB / 128MB) = 1 (that is, storing all the first system tables only requires 1 entity block).

[0038] The second quantity N2 = ceil(S2 / B) = ceil(280MB / 128MB) = 3 (that is, 3 entity blocks are needed to store all the second system tables). By rounding up, we can ensure that 280MB of data in the second system table can be completely stored (the total capacity of 3 entity blocks is 384MB), avoiding capacity overflow, and also avoiding the problem that some system table data cannot be stored due to the use of rounding down.

[0039] Step Two: Virtual Block Construction and Data Block Division

[0040] Based on N1=1 and N2=3 calculated in step one, virtual blocks are constructed according to the priority order of "CE region, data plane, entity block". First, CE region number 0 is selected from the 8 CE regions. In the first data plane of this region, one entity block (number 0-0-0) is selected as the first virtual block, which is used to store all first system tables. Then, from the remaining data plane of CE region number 0 and CE region number 1, three entity blocks (numbers 0-1-0, 0-2-0, 1-0-0) are selected as the second virtual blocks, which are used to store all second system tables. Among them, the L2P mapping table is stored in block number 0-1-0, the free block linked list is stored in block number 0-2-0, and the block wear statistics table is stored in block number 1-0-0.

[0041] After the virtual blocks are constructed, the remaining 1024-1-3=1020 physical blocks are uniformly divided into data blocks. Simultaneously, according to dynamic adjustment logic, the data blocks are initially partitioned into a hot data area (200 physical blocks, used to store user data accessed ≥10 times / minute, such as system logs and frequently used application data), a cold data area (720 physical blocks, used to store user data accessed <10 times / minute, such as backup files and infrequently used documents), and a free area (100 physical blocks, used for effective data migration and wear leveling during garbage collection), preparing for subsequent hot and cold data distribution. The virtual blocks and data blocks are independent of each other and do not occupy storage resources. If the capacity of the first system table increases to 150MB, the first number can be dynamically adjusted to 2, selecting one physical block from the free area of ​​the data blocks to supplement the first virtual block, ensuring adaptation to changes in system table capacity.

[0042] Step 3: Storage Area Divide and Conquer Management

[0043] Following the divide-and-conquer management logic, the eight CE regions of the NAND flash memory module and the four data planes of each CE region are managed independently and in parallel. The specific allocation scheme is as follows: the first virtual block (numbered 0-0-0) is allocated to plane 0 of the CE0 region; the three physical blocks of the second virtual block are allocated to planes 1 and 2 of the CE0 region and plane 0 of the CE1 region, respectively; the hot data area of ​​the data block is allocated to all data planes of the CE2-CE3 regions; the cold data area is allocated to all data planes of the CE4-CE6 regions; and the idle area is allocated to all data planes of the CE7 region.

[0044] This divide-and-conquer management approach enables independent scheduling of the first virtual block, the second virtual block, and the data block. System table data and user data occupy different CE channels and data planes, avoiding the problem of different types of data competing for read and write resources in traditional management methods, thus improving overall read and write concurrency performance. When the host issues system table update commands and user data write commands simultaneously, system table data can be written in parallel through planes 0-2 of the CE0 area, and user data can be written in parallel through planes CE2-CE3. The two do not interfere with each other, improving concurrency efficiency by more than 30%.

[0045] Step 4: Read / Write Command Recognition and Matching

[0046] The controller receives read and write commands from the host via the PCIe 4.0 interface in real time. According to the recognition logic, it parses the core information of the command. The read and write command contains a 4-byte data identifier field, where 0x00 represents the first system table data, 0x01 represents the second system table data, 0x02 represents hot user data, and 0x03 represents cold user data. At the same time, it parses the logical address (64-bit), data length (maximum supported 16MB), and command type (0x00 for read command, 0x01 for write command) in the command.

[0047] Based on the parsing results, the corresponding read / write logic is matched. If the instruction type is a write instruction and the data identifier is 0x00, the first virtual block write logic is matched, and the write path is determined to be CE0-plane 0-entity block 0-0-0. If the data identifier is 0x01, the second virtual block write logic is matched, and the write path is determined according to the specific system table type (L2P mapping table writes to CE0-plane 1-entity block 0-1-0). If the data identifier is 0x02, the hot data area write logic is matched, and the write path is determined to be the hot data area entity block in the CE2-CE3 region. If the data identifier is 0x03, the cold data area write logic is matched, and the write path is determined to be the cold data area entity block in the CE4-CE6 region. The matching logic of the read instruction corresponds to that of the write instruction, and the read path is determined according to the data identifier to ensure that the read / write path accurately matches the data type.

[0048] Step 5: Data Read / Write Execution and Status Feedback

[0049] Data write execution: Taking the host issuing a write command "Write L2P mapping table data (data length 64MB, data identifier 0x01)" as an example, after the controller parses the command, it determines that it is the second system table data, and diverts it to the second virtual block number 0-1-0 physical block. The data is first temporarily stored in the system table cache area of ​​8GB DRAM cache (dedicated cache space, capacity 1GB). The ECC verification unit built into the cache generates a 16-bit ECC check code (used for subsequent data verification to avoid data transmission errors). Then, the mapping from logical address (0x00000000-0x003FFFFFF) to physical address (CE0-plane 1-physical block 0-1-0-page 0 to page 127) is completed through FTL (flash translation layer).

[0050] According to the divide-and-conquer scheduling logic, plane 1 of the CE0 region is scheduled, and concurrent programming operation is initiated. The L2P mapping table data and ECC check code are written to the corresponding physical page. After the writing is completed, the version information of the L2P mapping table (marked as V2.0) and the update timestamp in the system table are updated in a timely manner. The "write successful" status information (status code 0x00) is sent back to the host through the PCIe interface. If a physical page write failure is detected during the writing process, the bad block marking logic is immediately triggered to mark the physical page as a bad block. An idle physical page is rescheduled to complete the writing, and the "write retry successful" status information is sent back.

[0051] Taking the host issuing a write command "Write user office document (data length 32MB, access frequency 15 times / minute, data identifier 0x02)" as an example, the controller determines that it is hot user data, diverts it to the hot data area number 2-0-0 entity block, temporarily stores the data in the hot data cache area of ​​DRAM, generates an ECC check code, completes address mapping through FTL, schedules plane 0 of CE2 area for concurrent writing, updates the free block linked list after writing is completed, and returns the writing status.

[0052] Data read execution: Taking the host issuing a read instruction "read bad block marking table (data length 20MB, data identifier 0x00)" as an example, after the controller parses the instruction, it first determines whether the data exists in the system table cache area of ​​the DRAM cache (because the bad block marking table is a frequently accessed system table data, it is already resident in the cache). If the cache is hit, the data is read directly from the cache.

[0053] After ECC verification and finding no errors, the data is sent back to the host via the PCIe interface with a read latency of ≤10μs. If the host issues a read command to "read the backup file in the cold data area (data length 64MB, data identifier 0x03)", the controller determines that the cache has missed. It obtains the physical address (CE4-plane 0-entity block 4-0-0) through FTL mapping, schedules plane 0 in the CE4 area to read the data in parallel, and sends the data to the cache after passing ECC verification (temporarily stored for 10 minutes, and the cache space is released if there is no further access during this period). The data is then sent back to the host, and the access frequency of the data is recorded in the statistics unit. If the subsequent access frequency increases to ≥10 times / minute, the data is automatically migrated to the hot data area.

[0054] Cache scheduling optimization: The controller counts the read frequency of all data in real time and implements hierarchical management through the cache scheduling unit. High-frequency access data (access frequency ≥ 10 times / minute, such as system table data and frequently used user data) is prefetched into the resident cache area of ​​DRAM cache (capacity 2GB) to ensure fast access;

[0055] Low-frequency access data (access frequency 5-10 times / minute) is temporarily stored in the temporary cache area (capacity 3GB) and retained for 1 hour;

[0056] Very low-frequency access data (access frequency < 5 times / minute) is temporarily stored in the cache's temporary cache area and retained for 30 minutes;

[0057] When the cache capacity is insufficient (remaining space < 1GB), the cache space occupied by very low-frequency access data is released first, followed by the space occupied by low-frequency access data. Priority is given to ensuring the read and write response speed of high-frequency data and system table data, so as to avoid the increase in read and write latency caused by cache overflow.

[0058] Wear leveling optimization: The controller uses the wear statistics unit to count the number of erases of all physical blocks (including virtual blocks and data blocks) in real time, and builds a complete wear statistics ledger (updated once per hour). The preset erase count threshold is 3000 times (the standard erase life of TLCNAND).

[0059] When the erase count of a certain physical block (such as cold data block number 4-0-0) reaches 2800 times (exceeding 90% of the threshold), the write logic is automatically adjusted. Subsequent cold data is preferentially written to physical blocks with lower erase counts (such as block number 6-3-0, erase count 1200 times). At the same time, the valid data in block number 4-0-0 is migrated in batches to the free area to reduce its erase frequency. This achieves wear leveling of all flash blocks, ensuring that the difference in erase counts among all physical blocks does not exceed 500 times, and extending the overall lifespan of the solid-state drive to more than 30,000 hours.

[0060] Garbage collection optimization: The controller identifies invalid data pages in each block in real time. The preset threshold for the proportion of invalid data pages is 70%. When the proportion of invalid data pages in the hot data area block number 2-1-0 reaches 75% (exceeding the threshold), the garbage collection process is triggered.

[0061] First, the valid data pages within the block are identified using FTL. The valid data is then moved in batches to the 7-0-0 entity block in the free area. Simultaneously, the physical address information in the L2P mapping table is updated. After the move is complete, the 2-1-0 entity block is completely erased (erasure time ≤ 500ms) to release storage space. This block is then updated to the free block list as a backup block for subsequent hot data writing. The garbage collection process is executed in parallel in the background, without interfering with normal read and write operations, ensuring that the impact of garbage collection on read and write performance is reduced to less than 10%.

[0062] Reference Figure 2 and Figure 3 The data read / write device is integrated into the solid-state drive controller and is used to execute data read / write methods. The specific structure and function of each module are as follows:

[0063] (1) Capacity calculation module: Implemented by hardware logic circuit, integrated into the storage management unit of the controller, and electrically connected to the NAND flash array and system table storage unit. Its main functions include: acquiring the total capacity of the first system table and the second system table through the SPI interface (reading the capacity identifier of the header of the system table in real time); reading the capacity of a single physical block through the NAND controller (reading the configuration register of the flash chip); having a built-in rounding up operation unit to complete the calculation of the first quantity and the second quantity, transmitting the calculation result to the virtual block allocation module, and storing it in the system register for subsequent module calls; when the capacity of the system table changes, it re-acquires and calculates in real time, and outputs the updated quantity information.

[0064] (2) Virtual block allocation module: Implemented using firmware logic, connected to the capacity calculation module and NAND flash array, receiving the first quantity and the second quantity output by the capacity calculation module, and has a built-in block filtering unit and partition marking unit; the block filtering unit selects the corresponding number of physical blocks from the NAND flash array according to the priority of "CE area, data plane, physical block", constructs the first virtual block and the second virtual block, generates a mapping relationship table between virtual blocks and physical blocks, and stores it in DRAM cache; the partition marking unit divides the remaining physical blocks into hot data area, cold data area and free area, marks the type identifier of each block, and supports dynamic adjustment function. When the system table capacity or user data volume changes, the number allocation of each block is adjusted and the mapping relationship table is updated.

[0065] (3) Divide and conquer management module: It is implemented by combining hardware and firmware and is connected to the virtual block allocation module, the CE controller of the NAND flash array and the data plane controller. It has a built-in CE scheduling unit and a data plane scheduling unit. The CE scheduling unit allocates dedicated CE channels for the first virtual block, the second virtual block and the data block to avoid channel conflicts. The data plane scheduling unit allocates dedicated data planes for each block to realize multi-plane parallel read and write. At the same time, it monitors the load of each CE channel and the data plane in real time. When the load of a certain channel is too high (≥80%), it dynamically adjusts the data allocation to balance the load and improve the concurrency efficiency.

[0066] (4) Read / Write Execution Module: Integrated into the read / write channel unit of the controller, it is connected to the host interface, DRAM cache, and divide-and-conquer management module; it has a built-in instruction parsing unit, cache scheduling unit, ECC verification unit, FTL mapping unit, and status feedback unit; the instruction parsing unit parses the read / write instructions issued by the host, extracts the core information, and matches the corresponding read / write logic; the cache scheduling unit works with the DRAM cache to realize the temporary storage, prefetching, and release of data; the ECC verification unit generates ECC verification codes to verify the read / write data and avoid data errors; the FTL mapping unit completes the conversion between logical address and physical address and supports dynamic updating of the mapping table; the status feedback unit sends status information back to the host after the read / write operation is completed to ensure communication synchronization.

[0067] (5) Adaptive optimization module: connected to the read / write execution module, NAND flash array, and DRAM cache, with built-in cache optimization unit, wear leveling unit, and garbage collection unit; the cache optimization unit counts the access frequency of data in real time to realize hierarchical management and dynamic release of the cache; the wear leveling unit counts the number of erases of each block and triggers wear leveling adjustment to extend the life of the device; the garbage collection unit identifies invalid data pages, triggers the garbage collection process, releases storage space, and reduces the impact on read / write performance; the three units work independently and in parallel, while being uniformly scheduled by the controller to ensure that the optimization logic and read / write process run in tandem.

[0068] The specific composition and connection relationships of the solid-state drive device, as well as the specific parameters and functions of each component, are as follows to ensure the integrity and feasibility of the device:

[0069] (1) Host interface: It adopts PCIe4.0x4 interface, supports NVMe2.0 protocol, and has a transmission rate of up to 8GB / s. It is used to establish a high-speed communication link with the host. The interface has a built-in signal isolation unit to reduce interference and ensure the stability of data transmission. Its main functions include: receiving read and write commands and data issued by the host, sending back read and write completion status information and read data to the host, and supporting hot-swapping function to adapt to the usage needs of different scenarios.

[0070] (2) Processor: It adopts the ARM Cortex-A55 architecture with a main frequency of 1.2GHz, integrates the above-mentioned data reading and writing device, and also has a built-in power management unit, clock management unit, and error handling unit; it is electrically connected to each module of the data reading and writing device, and realizes the collaborative work of each module through the internal bus to complete the full process control of data reading and writing; the error handling unit can detect errors in the reading and writing process in real time, trigger the retry mechanism or bad block marking, and ensure the stable operation of the device.

[0071] (3) DRAM cache: 8GB capacity, using DDR4 3200MHz, connected to the read and write execution module of the data read and write device through the DDR bus, divided into system table cache area (1GB), hot data cache area (3GB), cold data cache area (3GB), and free cache area (1GB); main functions include: temporarily storing data to be read and written, ECC check code, and hot data, improving read and write response speed, reducing the number of read and write cycles of NAND flash memory, and extending flash memory life; supports cache power loss protection, powered by supercapacitor, to ensure that the data in the cache is not lost after power failure.

[0072] (4) NAND flash array: It adopts TLC NAND flash chips, with a total of 8 chips, each chip with a capacity of 128GB and a total capacity of 1TB; the single physical block capacity is 128MB, each chip contains 128 physical blocks, divided into 4 data planes, and the 8 chips have a total of 8 CE regions and 32 data planes; it is connected to the virtual block allocation module and divide-and-conquer management module of the data read and write device, providing physical blocks for constructing virtual blocks and data blocks to realize long-term data storage; it supports multi-plane concurrent programming and reading to improve read and write bandwidth.

[0073] In addition, solid-state drive devices also include a power management unit and a clock management unit: the power management unit uses a DC-DC conversion circuit with an input voltage of 5V and output voltages of 3.3V, 1.8V, and 1.2V, providing stable power to the controller, DRAM cache, and NAND flash memory array, while also supporting low-power mode to reduce standby power consumption; the clock management unit uses a crystal oscillator circuit to provide a 100MHz clock signal to ensure the synchronous operation of all components and improve the stability of device operation.

[0074] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for reading and writing data on a solid-state drive, characterized in that, Includes the following steps: Step 1: Capacity Parameter Acquisition and Calculation. Obtain the core capacity parameters required for the operation of the solid-state drive (SSD). First, collect the total capacity of all first system tables and the total capacity of all second system tables in the SSD. At the same time, obtain the fixed capacity of a single physical block in the NAND flash memory module. Then, based on the collected capacity parameters, calculate the number of physical blocks required to store the two types of system tables respectively. The number of physical blocks required to store the first system table is recorded as the first quantity, and the number of physical blocks required to store the second system table is recorded as the second quantity. Ensure that the calculation results can fully support the data of the corresponding system table without capacity overflow. Step 2: Virtual Block Construction and Data Block Division. Complete the division of the system table storage area and the user data storage area. Based on the first and second quantities calculated in Step 1, select the corresponding number of physical blocks from all physical blocks of the NAND flash memory module, and construct the first virtual block and the second virtual block respectively. The first virtual block is dedicated to storing all first system tables, and the second virtual block is dedicated to storing all second system tables. At the same time, all other physical blocks except the selected virtual blocks are uniformly divided into data blocks to store user data from the host. The data blocks are initially partitioned to prepare for subsequent hot and cold data distribution. Step 3: Storage area divide-and-conquer management, realizing independent scheduling of different types of storage areas. The chip enable CE areas and data planes of the NAND flash memory module are divided and managed. The first virtual block, the second virtual block and the data block are respectively allocated to different CE areas and data planes, realizing independent parallel management of the three types of areas, avoiding resource contention between system table data and user data during storage and read / write, and improving the overall read / write concurrency performance; Step 4: Read and write command identification and matching. Complete the parsing of host commands and the invocation of corresponding logic. Receive read and write commands issued by the host through the host interface in real time. The controller parses the core information of the read and write command, including command type, logical address of target data, data length and data type. Based on the parsing results, match the corresponding read and write logic to determine the data read or write path. Step 5: Data Read / Write Execution and Status Feedback. Complete data interaction and provide feedback on the running status. Based on the read / write logic matched in Step 4, and combined with the pre-operations of data temporary storage, ECC checksum generation, and FTL address mapping, the corresponding CE region and data plane are scheduled through a divide-and-conquer management mechanism to execute data read or write operations. During the data read / write process, cache scheduling, wear leveling, and garbage collection optimization logic are executed synchronously to ensure read / write efficiency and the lifespan of the solid-state drive. After the read / write operation is completed, the system table, logical address, and physical address mapping table are updated in a timely manner, and the read / write success or failure status information is sent back to the host to ensure communication synchronization between the host and the solid-state drive.

2. The data read / write method for a solid-state drive according to claim 1, characterized in that, The calculation logic for the capacity parameter in step one is to use the rounding up method to calculate the ratio of the total capacity of all first system tables to the capacity of a single entity block to obtain the first quantity; and to calculate the ratio of the total capacity of all second system tables to the capacity of a single entity block to obtain the second quantity. By rounding up, it is ensured that the system table data can be completely stored, avoiding data loss or storage overflow due to insufficient capacity.

3. The data read / write method for a solid-state drive according to claim 1, characterized in that, In step two, the construction logic of the virtual blocks is as follows: according to the priority order of CE area, data plane, and physical blocks, a first number of physical blocks are selected to form the first virtual block, and a second number of physical blocks are selected to form the second virtual block. The partitioning logic of virtual blocks and data blocks is independent of each other and does not occupy each other's storage resources. After the partitioning is completed, the number allocation of each block can be dynamically adjusted according to changes in system table capacity or user data volume.

4. The data read / write method for a solid-state drive according to claim 1, characterized in that, The specific logic of data writing in step five is as follows: after the controller parses the host write command, if it determines that the data type is system table data, it will be diverted to the corresponding virtual block; if it determines that it is user data, it will be divided into hot data and cold data according to its access frequency, and diverted to the hot data area or cold data area of ​​the data block respectively; the data is first temporarily cached, and the corresponding ECC check code is generated. Then, the mapping from logical address to physical address is completed through FTL. The divide-and-conquer scheduling logic is used to realize concurrent writing of multiple CEs and multiple planes. After the writing is completed, the mapping table and system table are updated, and the writing status is returned to the host.

5. A data read / write method for a solid-state drive according to claim 4, characterized in that, The divide-and-conquer scheduling logic specifically corresponds to the divide-and-conquer management mechanism in step three, which manages the CE region and data plane independently and in parallel. For system table data and user data, as well as hot data and cold data, dedicated CE channels and data planes are allocated to avoid different types of data competing for read and write resources, thereby further improving write concurrency efficiency.

6. A data read / write method for a solid-state drive according to claim 1, characterized in that, The specific logic of data reading in step five is as follows: after the controller parses the logical address and data length in the host read instruction, it first determines whether the target data exists in the cache. If the cache is hit, the data is directly sent back to the host; if it is not hit, the physical address of the target data is obtained through FTL mapping, the corresponding data plane is scheduled to read the target data in parallel, the data is sent into the cache after passing ECC verification, and then sent back to the host. At the same time, high-frequency read data is kept in the cache to optimize the subsequent read efficiency.

7. A data read / write method for a solid-state drive according to claim 1, characterized in that, The cache scheduling logic in step five specifically involves real-time statistics of the read frequency of all data, prefetching frequently accessed hot data and keeping it permanently in the cache, and temporarily storing in the free area of ​​the cache according to priority for infrequently accessed data; when the cache capacity is insufficient, the cache space occupied by infrequent data is released first, and the read and write response speed of hot data and system table data is guaranteed first.

8. A data read / write method for a solid-state drive according to claim 1, characterized in that, The data type identification logic in step four is to clearly distinguish between system table data and user data by parsing the data identifier field in the read and write instructions; the first system table data is metadata with a capacity smaller than a single entity block, and the second system table data is metadata with a capacity not less than a single entity block; user data is further divided into hot data and cold data according to its access frequency, providing a basis for subsequent data diversion and divide-and-conquer scheduling, and realizing data classification read and write management.

9. An apparatus for performing a data read / write method for a solid-state drive as described in any one of claims 1-8, characterized in that, Includes the following modules: Capacity calculation module: used to collect the total capacity and single entity block capacity of the first system table and the second system table, and to calculate the number of entity blocks required to store the two types of system tables; Virtual block allocation module: Based on the number of blocks obtained by the capacity calculation module, it constructs the first virtual block and the second virtual block, divides the data blocks, and completes the initial marking of the storage area; Divide and conquer management module: Used to perform parallel scheduling management of the CE region and data plane of NAND flash memory module, realize independent scheduling of virtual blocks and data blocks, and avoid resource contention; Read / write execution module: used to parse read / write commands issued by the host, schedule cache, execute data read / write operations, and complete data verification and status feedback; Adaptive optimization module: Used to perform cache scheduling, wear leveling and garbage collection logic to optimize read and write efficiency and extend the life of solid-state drives.

10. A solid-state drive (SSD) data read / write device, characterized in that, The device includes a processor that executes a computer program stored in a memory to implement the steps of the data read / write method of the solid-state drive as described in any one of claims 1 to 8.

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