A ternary processor hardware implementation method based on FPGA

Abstract

This invention discloses a hardware implementation method for a ternary processor based on FPGA, belonging to the interdisciplinary field of digital integrated circuits and computer architecture. The method includes: (a) defining two-line encoding: mapping ternary logic values ​​{-1, 0, +1} to four level combinations of two binary signal lines (00→0, 01→-1, 10→+1, 11→invalid); (b) designing a 24-bit fixed-length instruction format, encoding 50 ternary instructions, covering ten functions: data transfer, tri-state logic, arithmetic addition, subtraction, multiplication, and division, conditional jumps, comparison tests, hardware stack, subroutine calls, shifting and rotating, and system control; (c) describing the ternary processor in synthesizable Verilog HDL as six modules: instruction ROM, decoder, tri-state ALU (including trit carry chain), register file (R0 hard-connected to zero), data RAM, and serial pipelined state machine (FETCH→DECODE→EXEC→WRITEBACK); (d) using domestic FPGA synthesis tools to synthesize, place, and route the Verilog code, generating a bitstream and burning it to the FPGA; (e) verifying the correctness of all 50 instructions through serial communication. This invention breaks through the industry mindset that "ternary calculations must rely on tri-state transistors." It implements a complete ternary CPU on a standard FPGA containing only binary logic units, and all Verilog code is synthesizable, which can be directly used as front-end design input for ASIC fabrication.

Description

Technical fields: This invention belongs to the interdisciplinary field of digital integrated circuits and computer architecture, specifically relating to a method for implementing a complete ternary central processing unit (CPU) on a standard field-programmable gate array (FPGA) containing only binary logic units (lookup tables (LUTs) and flip-flops (FFs)) using a synthesizable hardware description language. This invention does not rely on tri-state transistors or other special semiconductor devices. Background Technology

[0001] Ternary, based on the balanced three-value system {-1, 0, +1}, has theoretical advantages in information density and computational efficiency. Mathematically, it has been proven that balanced ternary is the integer number system with the data representation efficiency closest to the theoretical optimal value (e≈2.718, corresponding to a radix efficiency of 1.057). However, the hardware implementation of ternary computers has stagnated for a long time, mainly due to three reasons: 1. The "Missing Tri-State Transistor" Dilemma. The semiconductor industry has never been able to mass-produce transistors that natively represent three logic levels on a single device. Academia and industry generally believe that without tri-state transistors, ternary processors are impossible. This "device-driven logic" mindset has led to a stagnation in ternary computing research for over half a century.

[0002] 2. The only historical attempt: the Setun computer (1958, Soviet Union). The Setun computer used a ferrite core to achieve three-state storage and operation, and was the world's only mass-produced ternary computer. However, because it operated based on special magnetic materials, it could not be integrated with semiconductors, and its industrial production and maintenance costs were extremely high, preventing its large-scale deployment.

[0003] 3. Recent academic research: limited to module-level experiments. Some researchers have attempted to implement ternary logic gates or simple adders on FPGAs, but these are limited to single-module simulations and have not resulted in a complete processor that includes instruction fetch, decoding, execution, write-back, memory access, and interrupts.

[0004] The core concept of this invention is that the ternary logic layer and the binary physical layer can be separated. On an FPGA composed of binary transistors, one ternary bit (trit) is mapped to two binary signal lines through "double-line encoding," and the truth table for ternary operations is directly implemented using combinational logic in the FPGA lookup table (LUT). This fundamentally bypasses the deadlock of "equal-state transistors"—ternary calculations do not depend on ternary semiconductor devices, but are directly constructed on existing binary devices through mapping of the logic layer. Summary of the Invention

[0005] The technical problem to be solved by this invention is: (1) How to implement a complete CPU that can directly perform ternary operations on gate-level hardware, rather than a software simulator, on an FPGA containing only binary logic elements (LUT+FF) using a synthesizable hardware description language? (2) How to define the hardware encoding format of the ternary instruction set so that it can be adapted to the 24-bit instruction memory of the FPGA and cover the complete CPU functions such as data transfer, arithmetic logic, conditional jump, subroutine call, stack operation, I / O? (3) How to design a ternary arithmetic logic unit (ALU) so that it can perform operations directly in the ternary value range {-1, 0, +1}, instead of downgrading the ternary operands to binary integers before each operation? (4) How to design a pipelined control state machine and register file to coordinate the operation of each stage of fetch-decode-execute-write-back on the FPGA? (5) How to ensure that all Verilog code passes the comprehensive verification of the domestic FPGA synthesis tool (Ziguang Tongchuang PDS) and that the bitstream can be burned to the physical FPGA to run and output the correct results? Technical solution

[0006] This invention provides a hardware implementation method for a ternary processor based on FPGA, comprising the following core steps and modules: (a) Two-wire encoding definition: Ternary logic values ​​{-1, 0, +1} are mapped to a combination of levels on two binary signal lines. 0 is mapped to (0,0), -1 to (0,1), and +1 to (1,0). The (1,1) state is reserved as an invalid code for error detection. Each trit carries a 2-bit binary signal, and N trits constitute a 2N-bit data path.

[0007] (b) Design of a 50-instruction ternary instruction set: Employing a 24-bit fixed-length instruction format, it includes a 6-bit opcode (corresponding to 50 instructions), a 3-bit destination register address, a 3-bit source register 1 address, a 3-bit source register 2 address, a 1-bit reserved field, and an 8-bit immediate numeric field. Instructions are categorized into ten classes based on function: data transfer (Class A, 7 instructions), tri-state logic (Class B, 4 instructions), basic arithmetic (Class C, 3 instructions), advanced arithmetic (Class D, 3 instructions), conditional jumps (Class E, 7 instructions), comparison tests (Class F, 2 instructions), stack operations (Class G, 2 instructions), subroutines (Class H, 2 instructions), shift and rotate (Class I, 4 instructions), system control (Class J, 5 instructions), and 11 additional extended / enhanced instructions.

[0008] (c) Synthesizable Verilog modular design: The ternary processor is decomposed into instruction memory (IMEM, 16 address × 24 bits), instruction decoder, tri-state ALU, register file (6 4-trit registers, R0 hard-connected to zero), data memory (DMEM, 16 address × 8 bits) and serial pipelined control state machine (FETCH→DECODE→EXEC→WRITEBACK), all modules are written in synthesizable Verilog HDL.

[0009] (d) FPGA Synthesis and Verification: The Verilog code was synthesized, placed and routed using the domestic FPGA synthesis tool (Ziguang Tongchuang Pango Design Suite), and a bitstream file was generated and burned to the PG2L100H FPGA. The test instruction sequence was written to the instruction ROM through the UART serial port, and the register values ​​and data memory contents were read back after running. All 50 instructions were verified one by one. Beneficial effects

[0010] No tri-state transistor required: This invention implements a complete ternary processor on a standard binary FPGA (containing only LUT and FF), breaking the industry mindset that "ternary calculations must rely on tri-state transistors".

[0011] All instructions have been verified on the FPGA: 100% pass rate for 50 instructions (106 behavioral simulations + 0 errors in PDS synthesis + actual bitstream programming and running), not purely theoretical derivation.

[0012] Directly convertible to ASIC tape-out: All Verilog code is synthesizable (no initial blocks, no non-synthesizable system functions, and meets all syntax constraints of the PDS ADS synthesizer), and the verified logic can be directly used as input for ASIC front-end design.

[0013] Fully compatible with domestic toolchains: It uses the Ziguang Tongchuang PG2L100H FPGA and Pango Design Suite synthesis tools, without relying on imported EDA tools, and has independent and controllable engineering feasibility.

[0014] The engineering methodology is complete: a complete engineering implementation chain has been established, which includes "dual-line coding definition → instruction set design → Verilog modular description → FPGA synthesis → bitstream programming → real machine verification". Attached Figure Description

[0015] This invention has a total of 8 accompanying drawings.

[0016] Figure 1This is an overview block diagram of the FPGA ternary processor system architecture. The diagram shows the six main functional modules inside the PG2L100H FPGA chip (instruction ROM, decoder, tri-state ALU, register file, data RAM, and pipeline control state machine) and the data paths and control signal connections between them. The upper left label "FETCH→DECODE→EXEC→WRITEBACK" indicates the pipeline execution sequence.

[0017] Figure 2 This is a mapping diagram of two-line encoded ternary values ​​and binary signals. The diagram lists four encoding states in tabular form—(00→0), (01→-1), (10→+1), and (11→invalid / reserved)—and labels the corresponding level state for each signal line. The Verilog mapping is labeled at the bottom.

[0018] Figure 3 This is a diagram of a 24-bit ternary instruction format. The diagram divides the 24-bit instruction word into the following bit segments: [23:18] 6-bit opcode, [17:15] 3-bit destination register, [14:12] 3-bit source register 1 address, [11:9] 3-bit source register 2 address, [8] 1 reserved bit, and [7:0] 8-bit immediate value. An example instruction is given at the bottom: "ADD R3,R1,R2 → 24'h10_3_1_2_00".

[0019] Figure 4 This is a pipeline control state machine transition diagram. The diagram uses six circular nodes to represent six states—IDLE, FETCH, DECODE, EXEC, WRITEBACK, and HALTED—and arrows to indicate state transition relationships. The main loop is IDLE→FETCH→DECODE→EXEC→WRITEBACK→FETCH, with branches triggered by the HALT instruction to enter the HALTED state.

[0020] Figure 5 This is a diagram of the internal structure of a tri-state ALU module. The left side of the diagram shows three input ports (6-bit opcode, operand A, operand B), the middle section shows four types of arithmetic cores (truth table direct calculation NOT / AND / OR / XOR, carry chain ADD / SUB, trit-by-trit independent MUL, full arithmetic conversion DIV / MOD), and the right side shows five outputs (operation result, zero flag flag_z, sign flag flag_s, overflow flag flag_o, carry output carry_out).

[0021] Figure 6This is a schematic diagram of the carry-through chain. Taking the 4-trit addition "ADD R3,R1,R2" as an example, it shows the process of the carry signal propagating step by step from the lowest trit (trit0) to the higher bits. The lowest bit Cin=0, and the highest bit Cout is output as carry_out, which can be used for overflow detection.

[0022] Figure 7 This is a schematic diagram of register file R0 hard-wired to zero. The diagram shows the organization of six registers (R0~R5). R0 is a special register; write operations are ignored by the circuit, and read operations always return all zeros, used to provide a zero constant and as a reference for calculations. R1~R5 are general-purpose read / write registers. The right side is labeled with dual read ports (rs1→, rs2→) and single write ports (←rd wen).

[0023] Figure 8 This is a statistical chart showing the FPGA practical verification results of 50 instructions. The bar chart displays the pass rate for 11 groups across ten instruction categories and extended categories. The horizontal axis represents the instruction category label, and the vertical axis represents the number of passed instructions. Each group is labeled with the "Number of Passed Instructions / Total Number of Instructions" ratio. The top indicates the conclusion "50 / 50 All Passed (100%)". The bottom indicates the verification platform information. Detailed Implementation

[0024] The core innovation of this invention lies in its dual-line encoding scheme. On an FPGA containing only binary logic units, it is impossible to directly represent three logic states on a single physical signal line. This invention defines the encoding mapping relationship: Taking a 4-trit (4 ternary bits) data path as an example, the data bus width is 4 × 2 = 8 bits. In Verilog code, unified encoding is achieved through macro definitions: `define TRIT_0 2'b00 `define TRIT_N1 2'b01 `define TRIT_P1 2'b10 All logical operations within the ALU are based on these codes. For example, the ternary NOT operation is implemented in Verilog as follows: when TRIT_P1 is encountered, TRIT_N1 is output; when TRIT_N1 is encountered, TRIT_P1 is output; and when TRIT_0 is encountered, TRIT_0 is output.

[0025] Taking the 4-trit addition "ADD R3, R1, R2" as an example, the carry propagation process is described in detail.

[0026] Let R1 store the ternary values ​​{a3, a2, a1, a0} (each ai is a 2-bit code), and R2 store the values ​​{b3, b2, b1, b0}. The ALU starts its operations from the least significant bit trit0: Step 1 (trit0): Input A0=R1[1:0], B0=R2[1:0], and carry Cin0=0 (TRIT_0). Call the ternary full adder function FA3 to calculate A0+B0+Cin0 (the ternary addition truth table covers the seven possible sums from -3 to +3), and output the current trit, sum0[1:0], and carry1[1:0].

[0027] Step 2 (trit1): Input A1=R1[3:2], B1=R2[3:2], and carry Cin1=carry1. Similarly, call FA3 to output sum1[1:0] and carry2[1:0].

[0028] Step 3 (trit2): Input A2=R1[5:4], B2=R2[5:4], carry Cin2=carry2. Output sum2[1:0] and carry3[1:0].

[0029] Step 4 (trit3): Input A3=R1[7:6], B3=R2[7:6], carry Cin3=carry3. Output sum3[1:0] and final carry_out[1:0].

[0030] The final result is result = {sum3, sum2, sum1, sum0} (8 digits in total).

[0031] The subtraction "SUB R3, R1, R2" is implemented as follows: First, the B operands are negativeed one by one (TRIT_P1→TRIT_N1, TRIT_N1→TRIT_P1) to obtain B_neg, and then the addition process of A+B_neg is executed.

[0032] Overflow detection: If carry_out is not equal to TRIT_0 (non-zero), it means that the result exceeds the range that 4-trit can represent [-40, +40], and the flag_o is set to 1.

[0033] This invention implements a complete hardware stack subroutine calling mechanism, using the CALL and RET instructions: CALL instruction (encoded 0x32): During the EXEC phase, the hardware automatically completes two steps: SP register ← SP - 1 (stack pointer decrement) stack[SP-1]←PC+1 (push the return address, i.e., PC+1, onto the top of the stack). Then, in the WRITEBACK phase, update the PC to the target address (the absolute address provided by the immediate numeric field).

[0034] RET instruction (encoded 0x33): During the EXEC phase, the hardware completes this automatically. The return address is read from the top of the stack into ret_addr_latched. Then, during the WRITEBACK phase, the PC is updated to the return address, and SP is incremented by 1.

[0035] Taking a level 2 nested call as an example: Address 0: LDI R1, +1 (Initialization) Address 1: CALL addr=4 (Push PC=2 onto stack, jump to address 4) Address 2: HALT (Return and halt) ... Address 4: LDI R2, +4 (Subroutine A) Address 5: CALL addr=8 (Push PC=6 onto stack, jump to address 8) Address 6: RET (Pop PC=6, jump to address 6... i.e., itself) Address 7: HALT ... Address 8: LDIR3, +8 (Subroutine B) Address 9: RET (Pop PC=2, return to address 2) Call chain: 0→CALL→4→CALL→8→RET→2(HALT). The stack mechanism implements hierarchical storage and restoration of addresses.

[0036] The MUL instruction (encoded 0x12) performs ternary logical multiplication. Unlike the full arithmetic transformation of DIV / MOD, MUL performs ternary logical multiplication independently for each corresponding trit position of the two operands, referring to the ternary multiplication truth table: For 4-trit operands, trit0 to trit0, trit1 to trit1, trit2 to trit2, and trit3 to trit3 are each independently looked up in the table, and the operation results are combined into a 4-trit output.

[0037] The MAC (multiply-accumulate) instruction, based on the MUL result, further performs a ternary addition with the old value in the destination register to achieve a compound operation of "product + accumulated value → result".

[0038] Target platform: Unisoc Logos2 series PG2L100H-6 FBG676 packaged FPGA, mounted on an ALINX development board.

[0039] Toolchain: Unisplendour Pango Design Suite 2025.1-ads (Fabric Compiler build193266).

[0040] Key syntax constraints (for PDS ADS synthesizer): The use of initial blocks for logic initialization is prohibited (its behavior during synthesis is unpredictable). The use of non-synthesizable system functions such as $display and $readmemh is prohibited. Using variables as dynamic indices for bit selection (such as reg_array[variable]) is prohibited. The generate block follows PDS-specific syntax specifications. Overall process: RTL Analysis → Syntax Check, Module Hierarchy Analysis: Passed (8.8 seconds) RTL Refinement → Expression Simplification, Constant Propagation: in 0.5 seconds Inference → DFF / FSM / RAM structure identification: Passed (5.4 seconds) Compilation → Logic optimization, resource mapping: Passed (27 seconds, peak memory 180MB) Synthesis → Gate-level netlist generation: Passed (zero errors) The comprehensive tool identified a total of 4 RAM structures (16×24-bit instruction ROM, 16×8-bit stack, 8×8-bit dual-port register file, and 16×8-bit data RAM) and 6 state machines (CPU main state machine, UART transceiver state machine, SPI / I2C state machine, etc.).

[0041] Real-world verification method: The Python test script sends a sequence of instructions to the FPGA via UART (115200 baud rate) → the FPGA executes the instructions → the register values ​​and memory contents are read back → the Python script compares each item with the expected value → outputs PASS / FAIL.

[0042] Verification coverage: Data transfer (A): 7 / 7 PASS Logical Operations (B): 4 / 4 PASS Basic Arithmetic (C): 3 / 3 PASS Advanced Arithmetic (D): 3 / 3 PASS Jump to (E): 7 / 7 PASS Comparison Test (F): 2 / 2 PASS Stack operation (G): 2 / 2 PASS Subroutine (H): 2 / 2 PASS Shift rotation (I): 4 / 4 PASS System Control (J): 5 / 5 PASS Extended instruction: 11 / 11 PASS

[0043] Each instruction covers at least three verification dimensions: basic function verification, boundary value verification (-40 and +40), and zero value verification.

[0044] Industrial Applicability: The FPGA ternary processor implemented in this invention has clear industrial applicability: Logic verification platform: can be used to verify the correctness of ternary instruction set design and provide a hardware runtime environment for ternary compiler development.

[0045] Embedded coprocessor: It can be integrated into a binary SoC system as a coprocessor, leveraging the fact that ternary is more sensitive to anomalies than binary in scenarios such as anomaly detection and pattern matching.

[0046] ASIC front-end design: After the verified Verilog code is mapped to the standard cell library, it can be directly entered into the ASIC back-end design process (synthesis → placement and routing → DRC / LVS → tape-out). The FPGA implementation stage of this invention has completed the most critical logic verification stage of ASIC tape-out.

[0047] Domestic full-chain compatibility: The target device (PG2L100H) and synthesis tool (PDS) are both domestic solutions, which do not rely on imported EDA tools and have independent and controllable engineering feasibility.

[0048] Education and Research: Providing a tangible hardware experimental platform for teaching and research in ternary computation theory.

[0049] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A hardware implementation method for a ternary processor based on FPGA, characterized in that, Includes the following steps: (a) Two-line encoding definition steps: Map the set of ternary logic values ​​{-1, 0, +1} to the level combination of two binary signal lines. Define the encoding rules as follows: logic value 0 corresponds to line A low level and line B low level (2'b00), logic value -1 corresponds to line A low level and line B high level (2'b01), logic value +1 corresponds to line A high level and line B low level (2'b10), and the (2'b11) state is reserved as invalid encoding for error detection; each ternary bit (trit) is carried by 2 bits of binary signal, and N trits constitute a 2N-bit data path width; this encoding enables FPGA chips containing only binary logic elements (LUT lookup table and FF flip-flop) to carry ternary data paths without the need for tri-state transistors; (b) Design steps for a 50-instruction set in ternary form: Define a 24-bit fixed-length instruction format, arranged bit by bit as follows: [23:18] is a 6-bit opcode field, [17:15] is a 3-bit destination register field, [14:12] is a 3-bit source register 1 field, [11:9] is a 3-bit source register 2 field, [8] is a 1-bit reserved / function extension field, and [7:0] is an 8-bit immediate number field that can carry 4-trit ternary immediate numbers; the 50 instructions cover eleven categories of functions, including data transfer, tri-state logic operations, basic and advanced arithmetic operations, conditional jumps, comparison tests, stack operations, subroutine calls and returns, shifting and rotation, system control, and extension enhancements. All instructions have a unique opcode encoding and are executed directly in the ternary value range {-1,0,+1}; (c) Synthesizable Verilog modular description steps: The ternary processor is described in synthesizable Verilog HDL as six major hardware modules: instruction memory (IMEM, 16 address × 24 bits), instruction decoder, tri-state arithmetic logic unit (ALU), register file (6 4-trit registers, R0 hard-connected to zero), data memory (DMEM, 16 address × 8 bits), and serial pipelined control state machine (FETCH→DECODE→EXEC→WRITEBACK→FETCH loop, or enter HALTED halt state via HALT instruction); all Verilog code does not contain initial logic initialization blocks, does not contain non-synthesizable system function calls such as $display / $readmemh, and does not contain variable dynamic bit selection indexes; (d) FPGA synthesis and programming steps: Use the FPGA vendor's synthesis toolchain to perform RTL analysis, synthesis, placement and routing on the Verilog code, generate a bitstream configuration file, and download it to the FPGA chip; all synthesis reports 0 errors; (e) Full instruction verification steps based on UART serial port: The pre-compiled test instruction sequence is transmitted and written into the instruction memory one by one through the serial communication interface (UART), the CPU is started to execute, and after execution is completed, the contents of the register file and data memory are read back through UART and compared with the expected values ​​one by one to realize the closed-loop verification of the correctness of all 50 instructions.

2. The method according to claim 1, characterized in that, The three-state ALU module has been verified in a closed-loop manner for four sets of computational functions: Logical operations: NOT (tri-state NOT), AND (tri-state AND), OR (tri-state OR), XOR (tri-state XOR), all are executed directly based on the truth table of the ternary {-1,0,+1} fields, without being downgraded to binary integer operations; Arithmetic operations: ADD (addition) and SUB (subtraction) employ a trit-by-trit carry-forward mechanism—starting from the least significant bit trit0, the A and B of the current trit and the carry from the previous level are input into a ternary full adder. The full adder covers the input sum (seven possibilities from -3 to +3), outputs the sum of the current trit and the carry to the next level, propagating from trit0 to the most significant bit trit (N-1); NEG (negation of trit-by-trit); Advanced Arithmetic Group: MUL (trit-wise logical multiplication) – Simultaneously and independently performs ternary multiplication truth table (-1×-1=+1, -1×+1=-1, +1×+1=+1, multiplying by 0 results in 0) on each corresponding trit position of two operands, with no carry propagation between trits; DIV (integer division) and MOD (integer modulo) – Convert multi-trit operands to signed integers through weighted summation, perform integer division or modulo, and then map the integer result back to multi-trit ternary encoding through greedy bitwise conversion; Flag determination: flag_z = 1 if and only if all trits in the result are 0; flag_s = 1 if and only if the first non-zero trit encountered from the most significant trit to the lowest is -1; flag_o = 1 if the final carry of addition / subtraction is non-zero or the absolute value of multiplication result exceeds the range of N-trit; carry_out (2 bits) outputs the final carry value of ADD / SUB; All four sets of operations were verified through trit-level truth table comparison and behavioral-level simulation (106 test cases), forming a closed loop of operation functions.

3. The method according to claim 1, characterized in that, The 50 ternary instruction sets are divided into eleven categories according to function, and all have completed closed-loop verification on a real machine: Data transfer classes (Series A, 7 categories): NOP (No Operation), MOV (Register Transfer), LDI (Immediate Load), LDM (Direct Memory Read), STM (Direct Memory Write), LDR (Register Indirect Read), STR (Register Indirect Write); covering four addressing modes: immediate, direct register, direct memory, and indirect register addressing; Three-state logic operations (Series B, 4): NOT, AND, OR, XOR, executed based on the three-value truth table {-1, 0, +1}; Basic Arithmetic Classes (C Series, 3): ADD (including trit carry chains), SUB, NEG; Advanced Arithmetic Classes (D Series, 3): MUL (trit-wise independent logical multiplication), DIV (full arithmetic division), MOD (full arithmetic modulo); Conditional jump types (E series, 7): JMP (unconditional), JZ (zero jump), JNZ (non-zero jump), JP (positive jump), JN (negative jump), JO (overflow jump), JNO (no overflow jump); seven jump conditions cover all flag combinations, and the jump address is specified by the instruction immediate field; Comparison test classes (F series, 2): CMP (bit-by-bit comparison from the most significant trit to the least significant trit), TEST (transformation of A sign based on B sign); Stack operations (G series, 2): PUSH (decrement SP and push onto the stack), POP (pop from the stack and increment SP); Subroutine classes (H series, 2): CALL (jump after pushing return address PC+1), RET (return by popping stack); supports 2 levels and above of nested calls; Shift and rotation types (I series, 4 types): SHL, SHR, ROL, ROR, the shift value is the absolute value of the B operand; System control categories (J series, 5 items): IN (input), OUT (output), HALT (stop), SWI (soft interrupt reserved), RTI (interrupt return reserved); Extended and enhanced instructions (11): ABS (absolute value), SGN (sign), MAC (multiply-accumulate), MIN / MIN (minimum / maximum), CLZ (count leading zeros), CNZ (non-zero detection), SEL (tri-state selection), MUX (multiplexing), SYNC (synchronization barrier reservation), BARR (barrier reservation); The fifty instructions cover the AJ10 series (39 instructions) plus extensions (11 instructions). All instructions were programmed and run on the FPGA and verified by comparing each instruction with the UART (50 / 50=100%).

4. The method according to claim 1, characterized in that, The closed-loop state transition of the serial pipelined control state machine is defined as follows: Status codes: IDLE=3'd0, FETCH=3'd1, DECODE=3'd2, EXEC=3'd3, WRITEBACK=3'd4, HALTED=3'd7; Startup path: cpu_run signal is valid (rising edge) in IDLE state → FETCH; Main loop (FETCH→DECODE→EXEC→WRITEBACK→FETCH): FETCH reads the instruction ROM at the PC address and outputs the 24-bit instruction word → DECODE parses the opcode / register address / immediate value / control signal → EXEC performs ALU operations or memory access or stack operations or I / O → WRITEBACK writes back the result and updates the PC (PC+1 or jump address or return address); Stop path: DECODE is decoded to HALT instruction → HALTED (3'd7) stop state; Since the state machine is executed serially (not in parallel pipeline), after the jump instruction updates the PC in the WRITEBACK state, the next FETCH state automatically fetches the new address instruction, eliminating the need for pipeline flushing logic. The state machine has been verified by FPGA operation to ensure that all 6 state transition paths are executed correctly, forming a control flow closed loop.

5. The method according to claim 1, characterized in that, The register file module contains the following closed-loop verified structure: Six 4-trit wide registers R0~R5, each register is 8 bits (4 trit × 2 bits / trit); The hardwired R0 is all zero (8'b00000000), so write operations to R0 are invalid and read operations always return all zero. This zero-constant characteristic has been verified by a special closed-loop test: after performing write operations on different registers multiple times and reading back, R0 is always zero, while R1~R5 are maintained independently. Dual-port reading: Two independent read address ports (rs1_addr and rs2_addr) can read the values ​​of any two registers simultaneously. Data consistency was verified by two sets of tests: reading the same register simultaneously and reading different registers simultaneously. Single-port write: One write address port (rd_addr), one write data port (wdata), and one write enable signal (wen). The write enable signal is only set when the instruction type is writable in the WRITEBACK state; non-writable instructions such as jump / compare / stack / HALT are prohibited from writing.

6. The method according to claim 1, characterized in that, The instruction memory is initialized without relying on the initial block or the $readmemh system function using the following method: During power-on reset (rst_n=0), IMEM is filled with HALT instruction code (24'h3A_0_0000) address by address; After the reset is released, 24-bit instruction data is received through the UART serial port. With the write enable (imem_wen) and write address (imem_waddr) signals, the test instructions are written to the specified address one by one. This method fully complies with the synthesizability constraints of the Ziguang Tongchuang PDS ADS synthesizer, and has been verified with zero errors in PDS synthesis, forming an IMEM initialization closed loop.

7. The method according to claim 1, characterized in that, The complete operation flow of the subroutine call (CALL) and return (RET) instructions in the EXEC and WRITEBACK phases is as follows: CALL: In the EXEC phase, the return address (the PC value latched in the pipeline DECODE phase plus 1) is pushed onto the stack (stack[SP-1]←pipe_pc_d+1), and the stack pointer is decremented (SP←SP-1); in the WRITEBACK phase, the PC is updated to the absolute address specified by the immediate value; RET: During the EXEC phase, the return address is read from the stack (ret_addr_latched ← stack[SP]), and the stack pointer is incremented (SP ← SP+1); During the WRITEBACK phase, the PC is updated to ret_addr_latched; The stack pointer SP is an independent hardware resource outside of the register file and data memory. The stack storage space stack[0:15] has a depth of 16. The CALL / RET function was verified through three closed-loop tests: simple round trip (returning to the original position after the call), SP recovery (SP returning to its original position after multiple calls), and 2-level nested call (1→2→4→8 value passing chain), all of which executed correctly.

8. The method according to claim 1, characterized in that, The UART closed-loop verification method in step (e) specifically includes: The host computer sends instruction loading protocol frames through the UART serial port (115200bps), the FPGA parses the protocol frames and writes the instruction data to the specified address of IMEM, completing the remote loading of all 50 test instructions; The host computer sends a CPU start command, the cpu_run signal on the FPGA is set, and the state machine changes from IDLE to FETCH to start execution. The host computer sends a read-back command, and the FPGA transmits the values ​​of the register file (R0~R5) and the contents of the data memory (DMEM[0~15]) byte by byte back via UART; The host computer compares the read-back values ​​with the theoretical values ​​pre-calculated by the Python software model item by item. The results of all 50 instructions are consistent with the expected values, forming a complete verification loop of "instruction injection → FPGA execution → result read-back → software comparison".

9. A single-chip FPGA ternary processing system, characterized in that, An FPGA chip integrates: A ternary CPU core includes an instruction ROM (16 addresses × 24 bits), an instruction decoder (6-bit opcode decoder), a tri-state arithmetic logic unit (four sets of operations), a register file (R0 hard-wired zero, 6 × 8 bits), a data RAM (16 addresses × 8 bits, supporting direct and indirect addressing), and a serial pipelined control state machine (6 states). UART serial communication module: 115200bps, used to receive instruction data and send calculation results; All the above modules are interconnected internally within the FPGA chip via wires, without relying on an embedded CPU soft core (such as MicroBlaze) or hard core processor (such as ARM Cortex) on the FPGA chip. All programmable logic resources of the FPGA (LUT lookup table, FF flip-flops, BRAM block RAM) are used only to construct the ternary processor circuit. All Verilog source code of the ternary CPU core is synthesizable. It is synthesized using a domestic FPGA synthesis tool (Ziguang Tongchuang Pango Design Suite) to generate gate-level netlists and bitstream files. The synthesis report has 0 errors and 0 warnings, and supports direct migration from FPGA verification to ASIC standard cell design.

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