An instruction pipeline, program execution method and processor

Abstract

The embodiment of the application discloses an instruction pipeline, a program running method and a processor, relates to the technical field of computers, and can effectively improve the utilization rate of the processor.The instruction pipeline comprises: a running module, which is used for running a first thread corresponding to a first context in the case that a program running context is the first context, the first thread comprising at least one instruction, the at least one instruction comprising a target instruction; the first context being stored in a first register group of the running module; a detection module, which is electrically connected with the running module and is used for detecting whether the target instruction exists in the running module; and a switching module, which is respectively electrically connected with the detection module and the running module and is used for switching the program running context in the running module from the first context to a second context pre-stored in a second register group of the running module in the case that the detection module detects the target instruction.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to an instruction pipeline, a program execution method, and a processor. Background Technology

[0002] High-concurrency scenarios place high demands on the processor's multi-threaded scheduling capabilities. For example, when a thread experiences a cache miss, it typically takes a considerable amount of time to request data from memory, causing the instruction pipeline to become blocked. To prevent the processor from idling and waiting, the execution of that thread can be paused and another thread can be executed instead, thereby improving processor utilization.

[0003] However, in some more complex applications, although many instructions are time-consuming, they are often highly correlated with the software application and do not have clear hardware characteristics like cache misses. Therefore, the processor usually does not detect the instruction pipeline blockage caused by these instructions and can only idle and wait, which greatly reduces the processor utilization. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an instruction pipeline, a program execution method, and a processor, which can effectively improve the utilization rate of the processor.

[0005] In a first aspect, embodiments of the present invention provide an instruction pipeline, comprising: a running module, configured to run a first thread corresponding to the first context when the program running context is a first context, the first thread including at least one instruction, the at least one instruction including a target instruction; the first context being stored in a first register group of the running module; a detection module, electrically connected to the running module, configured to detect whether the target instruction exists in the running module; a switching module, electrically connected to both the detection module and the running module, configured to switch the program running context in the running module from the first context to a second context pre-stored in a second register group of the running module when the detection module detects the target instruction; the running module is further configured to run a second thread corresponding to the second context after the switching module switches the program running context from the first context to the second context.

[0006] In one embodiment, the runtime module includes at least one pipeline stage; wherein each pipeline stage includes a corresponding first register group and a corresponding second register group; the program runtime context has a corresponding program runtime context component in each pipeline stage; the first context has a corresponding first context component in each pipeline stage, and the first context component is stored in the first register group corresponding to the pipeline stage; the second context has a corresponding second context component in each pipeline stage, and the second context component is stored in the second register group corresponding to the pipeline stage.

[0007] In one embodiment, the detection module includes at least one detection submodule, each detection submodule being electrically connected to a corresponding pipeline stage; each detection submodule is specifically used to detect whether the target instruction exists in the corresponding pipeline stage; the switching module includes at least one switching submodule, each switching submodule being electrically connected to a corresponding pipeline stage and the corresponding detection submodule, specifically used to switch the program execution context component corresponding to the pipeline stage from the first context component to the second context component when the detection submodule detects the target instruction; the running module is specifically used to run a second thread corresponding to the second context component in the pipeline stage after the switching submodule switches the program execution context component corresponding to the pipeline stage from the first context component to the second context component.

[0008] In one embodiment, the instruction pipeline further includes: a selection module, electrically connected to the switching module, configured to select a thread in a "ready" state as a third thread from the ready thread queue after the switching module switches the program execution context from the first context to the second context; and a storage module, electrically connected to both the selection module and the execution module, configured to replace the first context with the third context corresponding to the third thread selected by the selection module and store it in the first register group of the execution module.

[0009] In one implementation, the storage module is specifically used to: retrieve the third context corresponding to the third thread from the memory; and store the third context in place of the first context into the first register group.

[0010] In one implementation, the second thread includes at least one instruction, the at least one instruction including the target instruction; the detection module is further configured to detect whether the target instruction exists in the running module after the running module runs the second thread corresponding to the second context; the switching module is further configured to switch the program running context from the second context to the third context in response to the detection module detecting the target instruction; the running module is further configured to continue running the first thread corresponding to the first context with the third context as the new first context and the third thread as the new first thread.

[0011] In one implementation, the target instruction is located after an instruction of a preset category, wherein the instruction of the preset category is an instruction whose execution time is greater than a preset time threshold.

[0012] In one implementation, the target instruction occupies at least one byte, or the lower four bits of a byte.

[0013] In one implementation, the target instructions are contained in the source code of the first thread, and / or the target instructions are inserted by the compiler when compiling the source code of the first thread.

[0014] Secondly, embodiments of the present invention also provide a program execution method, comprising: when the program execution context is a first context, executing a first thread corresponding to the first context, the first thread including at least one instruction, the at least one instruction including a target instruction; the first context being stored in a first register group; in response to detecting the target instruction in the instruction pipeline of the program execution, switching the program execution context from the first context to a second context pre-stored in a second register group; and executing a second thread corresponding to the second context.

[0015] In one embodiment, the instruction pipeline includes at least one pipeline stage; wherein each pipeline stage includes a corresponding first register set and a corresponding second register set; the program execution context has a corresponding program execution context component in each pipeline stage; the first context has a corresponding first context component in each pipeline stage, and the first context component is stored in the first register set corresponding to the pipeline stage; the second context has a corresponding second context component in each pipeline stage, and the second context component is stored in the second register set corresponding to the pipeline stage.

[0016] In one implementation, switching the program execution context from the first context to the second context in response to detecting the target instruction in the instruction pipeline of the program execution includes: switching the program execution context component corresponding to the pipeline stage from the first context component to the second context component in response to detecting the target instruction in any of the pipeline stages; running the second thread corresponding to the second context includes: running the second thread corresponding to the second context in the pipeline stage.

[0017] In one implementation, after switching the program running context from the first context to the second context, the method further includes: selecting a thread as a third thread from at least one thread in a "ready" state; and replacing the first context with the third context corresponding to the third thread and storing it in the first register group.

[0018] In one implementation, replacing the first context with the third context corresponding to the third thread and storing it in the first register group includes: retrieving the third context corresponding to the third thread from memory; and storing the third context in place of the first context in the first register group.

[0019] In one implementation, the second thread includes at least one instruction, the at least one instruction including the target instruction; after running the second thread corresponding to the second context, the method further includes: in response to detecting the target instruction in the instruction pipeline of the program execution, switching the program execution context from the second context to the third context; using the third context as the new first context, using the third thread as the new first thread, jumping to the step of running the first thread corresponding to the first context when the program execution context is the first context, and continuing to execute iteratively.

[0020] In one implementation, the target instruction is located after an instruction of a preset category, wherein the instruction of the preset category is an instruction whose execution time is greater than a preset time threshold.

[0021] In one implementation, the target instruction occupies at least one byte, or the lower four bits of a byte.

[0022] In one implementation, the target instructions are contained in the source code of the first thread, and / or the target instructions are inserted by the compiler when compiling the source code of the first thread.

[0023] Thirdly, embodiments of the present invention also provide a processor including any of the instruction pipelines provided in embodiments of the present invention.

[0024] The embodiments of the present invention provide an instruction pipeline, a program execution method, and a processor. The instruction pipeline includes a execution module, a detection module, and a switching module. The execution module can run a first thread corresponding to a first context when the program execution context is a first context. The detection module can detect the presence of a target instruction in the execution module. The switching module, upon detecting the target instruction, can switch the program execution context from the first context to a second context pre-stored in a second register set. Based on this, the execution module can run a second thread corresponding to the second context. In other words, the instruction pipeline provided by the embodiments of the present invention can use a target instruction in the first thread as an indication for thread switching, and based on this indication, switch the program execution context from the first context to the second context. Since the second context is pre-stored in the second register set, the program execution context can be switched conveniently and quickly through register operations. This allows the instruction pipeline to quickly prepare for and switch to the execution of the second thread. Thus, when the execution of the first thread causes excessive processor idling, the above operation can be used to pause the first thread and run the second thread, thereby avoiding excessive processor waiting time and effectively improving processor utilization. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 A schematic diagram of an instruction pipeline provided for an embodiment of the present invention; Figure 2 Another schematic diagram of the instruction pipeline provided for an embodiment of the present invention; Figure 3 This is a schematic diagram of instruction flow and program execution context switching in the instruction pipeline in an embodiment of the present invention. Figure 4 Another schematic diagram of an instruction pipeline structure provided for an embodiment of the present invention; Figure 5 A flowchart of a program execution method provided for an embodiment of the present invention; Figure 6 A schematic diagram of a processor provided for an embodiment of the present invention. Detailed Implementation

[0027] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0028] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0029] In a first aspect, embodiments of the present invention provide an instruction pipeline that can effectively improve processor utilization.

[0030] like Figure 1 As shown, an embodiment of the present invention provides an instruction pipeline 3, comprising: like Figure 1 As shown, an embodiment of the present invention provides an instruction pipeline 3, comprising: The execution module 11 is configured to run a first thread corresponding to the first context when the program execution context is a first context. The first thread includes at least one instruction, and the at least one instruction includes a target instruction. The first context is stored in a first register group. The detection module 12 is electrically connected to the operation module 11 and is used to detect whether the target instruction exists in the operation module 11; The switching module 13 is electrically connected to the detection module 12 and the running module 11 respectively, and is used to switch the program running context in the running module 11 from the first context to the second context pre-stored in the second register group when the detection module 12 detects the target instruction. The running module 11 is also used to run a second thread corresponding to the second context after the switching module 13 switches the program running context from the first context to the second context.

[0031] The instruction pipeline 3 provided in the embodiments of the present invention may include a running module 11, a detection module 12, and a switching module 13. The running module 11 can run a first thread corresponding to the first context when the program running context is a first context. The detection module 12 can detect whether a target instruction exists in the running module 11. The switching module 13 can switch the program running context from the first context to a second context pre-stored in a second register set when the detection module 12 detects the target instruction. Based on this, the running module 11 can run a second thread corresponding to the second context. That is, the instruction pipeline provided in the embodiments of the present invention can use the target instruction in the first thread as an indication for thread switching, and switch the program running context from the first context to the second context based on this indication. Since the second context is pre-stored in the second register set, the program running context can be switched through convenient and quick register operations. This allows the instruction pipeline to quickly prepare for and switch to the second thread. Thus, when the execution of the first thread causes excessive processor idling, the first thread can be paused and the second thread executed through the above operation, thereby avoiding excessive processor waiting time and effectively improving processor utilization.

[0032] In embodiments of the present invention, instruction pipeline refers to a method of dividing the operation of an instruction into multiple small steps to improve the efficiency of processor instruction execution, with each step being completed by a dedicated circuit. In one example, instruction pipeline may include steps such as instruction fetch, decoding, operand address calculation, operand fetch, instruction execution, and operand write, where each step can be implemented by a corresponding circuit, and the circuit corresponding to each step can be called a pipeline stage.

[0033] In embodiments of the present invention, a program may include one or more instructions. The program runs in a processor, which is the process of the instructions in the program being processed in the instruction pipeline. The program execution context refers to the values ​​stored in some registers in the instruction pipeline when the instructions in the program are processed. When the program includes multiple threads, each thread has its own corresponding context when processed in the instruction pipeline; for example, the first thread has a corresponding first context, the second thread has a corresponding second context, and so on. In one example, the first context may be pre-stored in a first register set, and the second context may be pre-stored in a second register set. Both the first and second register sets may include one or more registers. When the first thread runs, the program execution context is the first context; when the second thread runs, the program execution context is the second context.

[0034] The execution module 11 can run a first thread corresponding to the first context when the program execution context is the first context. The first thread can include at least one instruction, and each instruction can flow into the instruction pipeline sequentially and be processed by the instruction pipeline. The detection module 12 can detect each instruction flowing through the execution module 11 to detect whether the target instruction exists in the execution module 11.

[0035] The switching module 13 can be used to switch the program execution context from the first context to the second context, which is pre-stored in the second register group, when the detection module 12 detects the target instruction. Since both the first and second contexts are pre-stored in their respective registers, the program context can be switched quickly and conveniently through register operations. For example, in one implementation, the program context can be switched by modifying the values ​​of preset flag bits in both the first and second register groups. For instance, when the preset flag bit in the first register group is "1", it indicates that the program execution context is the first context; when the preset flag bit in the first register group is "0", it indicates that the program execution context is not the first context, and so on. After the switching module 13 switches the program execution context from the first context to the second context, the execution module 11 can run the second thread corresponding to the second context. That is, after the program execution context is switched, the program running in the instruction pipeline can also be switched accordingly.

[0036] It should be noted that, in the embodiments of the present invention, the target instruction can refer to any instruction whose meaning does not conflict with other instructions of the processor. The target instruction can be defined as needed, as long as it can be distinguished from other instructions of the processor. The embodiments of the present invention do not limit this.

[0037] In one implementation, the target instruction may occupy one or more bytes. In another implementation, the target instruction may occupy the lower four bits of a byte. In this way, during instruction decoding, the fourth byte can be decoded directly without the need for shifting as required for the higher four bits, thus enabling faster identification of the target instruction and faster context switching.

[0038] The target instruction can be located after an instruction of a preset category, wherein the preset category of instructions can be instructions whose execution time exceeds a preset duration threshold. Specifically, the preset duration threshold can be set and adjusted as needed. In this way, when an instruction of the preset category is about to cause pipeline blockage, the instruction pipeline has already identified the target instruction following that instruction through decoding, and thus, based on the target instruction, initiates related operations such as context switching and thread switching.

[0039] Target instructions can be set in the first thread in various ways. For example, in one implementation, the target instructions can be included in the source code of the first thread. In another implementation, the target instructions can also be inserted by the compiler when compiling the source code of the first thread. In yet another implementation, some target instructions can be included in the source code of the first thread, and other target instructions can be inserted by the compiler; embodiments of the present invention do not limit this.

[0040] Specifically, such as Figure 2 As shown, in one embodiment of the present invention, the execution module 11 may include at least one pipeline stage 110; wherein each pipeline stage 110 may include a corresponding first register group 111 and a corresponding second register group 112; the program execution context may have a corresponding program execution context component in each pipeline stage 110, and the program execution context components together constitute a complete program execution context. Similarly, the first context has a corresponding first context component in each pipeline stage 110, and the first context components together constitute a complete first context, and each first context component is stored in the first register group 111 corresponding to the pipeline stage 110. The second context has a corresponding second context component in each pipeline stage 110, and the second context components together constitute a complete second context, and each second context component is stored in the second register group 112 corresponding to the pipeline stage 110.

[0041] In one embodiment, the detection module 12 may include at least one detection submodule 120, each detection submodule 120 being electrically connected to a corresponding pipeline stage 110; each detection submodule 120 may specifically be used to detect whether a target instruction exists in the corresponding pipeline stage 110; based on this, the switching module 13 may include at least one switching submodule 130, each switching submodule 130 being electrically connected to a corresponding pipeline stage 110 and the corresponding detection submodule 120 respectively, and may specifically be used to switch the program execution context component corresponding to the pipeline stage 110 from a first context component to a second context component when the detection submodule 120 detects a target instruction; correspondingly, the running module 11 may also run a second thread corresponding to the second context in the pipeline stage 110 after the switching submodule 130 switches the program execution context component corresponding to the pipeline stage 110 from the first context component to the second context component.

[0042] In other words, in the embodiments of the present invention, when switching threads in the program executed in the instruction pipeline, this can be achieved by switching threads at each pipeline stage. Specifically, each pipeline stage 110 can be checked for the presence of a target instruction. If a target instruction exists, the program execution context component corresponding to that pipeline stage 110 is switched, and after the program context component is switched, the running thread is switched. In this way, as the target instruction is passed through each pipeline stage, the entire instruction pipeline can gradually complete the switching of program execution and thread switching.

[0043] For example, a schematic diagram of instruction flow and program execution context switching in an instruction pipeline can be shown as follows: Figure 3 As shown in the diagram, in the first clock cycle, the first, second, and third pipeline stages of the instruction pipeline are all executing thread A. The program execution context of each pipeline stage is the context of thread A, which is stored in the first register set of each pipeline stage. The context of thread B is stored in the second register set of each pipeline stage. In the second clock cycle, the target instruction from thread A flows into the first pipeline stage, indicating a need for a context switch. In response, in the third clock cycle, the first pipeline stage replaces the program execution context from thread A's context with thread B's context. Simultaneously, in the third clock cycle, the target instruction flows from the first pipeline stage to the second pipeline stage, indicating a need for a context switch. In response, in the fourth clock cycle, the second pipeline stage replaces the program execution context from thread A's context with thread B's context, and so on.

[0044] Furthermore, such as Figure 4 As shown, in one embodiment of the present invention, the instruction pipeline 3 may further include a selection module 14 and a storage module 15. Specifically, the selection module 14 may be electrically connected to the switching module 13, and is used to select a thread in a "ready" state from the ready thread queue Q1 as the third thread after the switching module 13 switches the program execution context from the first context to the second context. The storage module 15 may be electrically connected to the selection module 14 and the execution module 11 respectively, and is used to replace the first context with the third context corresponding to the third thread selected by the selection module 14, and store it in the first register group of the execution module 11.

[0045] In this embodiment, after the switching module 13 switches the program execution context from the first context to the second context, since the second thread will subsequently run, the first context stored in the first register group is no longer of practical use. Therefore, the ready thread queue Q1 can be checked to see which threads are included. According to a preset rule, a thread in the "ready" state is selected from the ready thread queue Q1 as the third thread, and the third thread's corresponding third context replaces the original first context and is stored in the first register group, thus preparing for the next context switch. Here, the ready thread queue Q1 is a thread queue in which all threads are in the "ready" state. The preset rule may include, for example, a first-in-first-out (FIFO) rule.

[0046] In a specific implementation, the storage module 15 can be used to: retrieve the third context corresponding to the third thread from the memory; and store the third context in place of the first context in the first register group. That is to say, in this embodiment, the third context corresponding to the third thread can be stored in memory (for example, it can be stored in random access memory (RAM)). When needed, the third context is retrieved from the memory and stored in the first register group, thereby achieving both improved processor performance and reduced register hardware costs.

[0047] Of course, in another embodiment of the present invention, if the program only includes two threads, the first thread and the second thread, it is not necessary to look up the third context. Instead, the first context can be kept in the first register group so that when the second thread is blocked, it can be switched back to the first thread.

[0048] In an embodiment of the present invention, after the switching module 13 switches the program execution context from the first context to the second context, the execution module 11 can run the second thread corresponding to the second context. Similar to the first thread, in one embodiment of the present invention, the second thread may also include at least one instruction, which may include a target instruction. Based on this, the detection module 12 can also detect whether a target instruction exists in the execution module 11 after the execution module 11 runs the second thread corresponding to the second context; the switching module 13 can also switch the program execution context from the second context to the third context in response to the detection module 12 detecting the target instruction. Based on this, in one embodiment, the execution module 11 can also be used to continue running the first thread corresponding to the first context with the third context as the new first context and the third thread as the new first thread. In this way, the first register group and the second register group can be used alternately to store the program execution context and to store the spare context (that is, the context of the thread to be executed), thereby making the switching of the program execution context faster and more flexible, and facilitating further improvement of processor utilization.

[0049] Accordingly, in a second aspect, embodiments of the present invention also provide a program execution method that can effectively improve processor utilization.

[0050] like Figure 5 As shown, the program execution method provided in the embodiments of the present invention may include: S21, when the program execution context is a first context, a first thread corresponding to the first context is executed, the first thread includes at least one instruction, the at least one instruction includes a target instruction; the first context is stored in a first register group; S22, in response to detecting the target instruction in the instruction pipeline of the program execution, the program execution context is switched from the first context to the second context pre-stored in the second register group; S23, run the second thread corresponding to the second context.

[0051] The program execution method provided by the embodiments of the present invention, when the program execution context is a first context, executes a first thread corresponding to the first context. The first thread includes at least one instruction, and the at least one instruction includes a target instruction. The first context is stored in a first register set. In response to detecting the target instruction in the instruction pipeline of the program execution, the program execution context is switched from the first context to a second context pre-stored in a second register set, and a second thread corresponding to the second context is executed. That is, the program execution method provided by the embodiments of the present invention can use the target instruction in the first thread as an indication for thread switching, and switch the program execution context from the first context to the second context based on this indication. Since the second context is pre-stored in the second register set, the program execution context can be switched through convenient and quick register operations, so that the instruction pipeline can quickly prepare for the execution of the second thread and switch to the execution of the second thread. In this way, when the execution of the first thread causes the processor to idle and wait too much, the first thread can be paused through the above operation, and the second thread can be executed, thereby avoiding the processor waiting for too long and effectively improving the processor utilization.

[0052] In embodiments of the present invention, instruction pipeline refers to a method of dividing the operation of an instruction into multiple small steps to improve the efficiency of processor instruction execution, with each step being completed by a dedicated circuit. In one example, instruction pipeline may include steps such as instruction fetch, decoding, operand address calculation, operand fetch, instruction execution, and operand write, where each step can be implemented by a corresponding circuit, and the circuit corresponding to each step can be called a pipeline stage.

[0053] In embodiments of the present invention, a program may include one or more instructions. The program runs in a processor, which is the process of the instructions in the program being processed in the instruction pipeline. The program execution context refers to the values ​​stored in some registers in the instruction pipeline when the instructions in the program are processed. When the program includes multiple threads, each thread has its own corresponding context when processed in the instruction pipeline; for example, the first thread has a corresponding first context, the second thread has a corresponding second context, and so on. In one example, the first context may be pre-stored in a first register set, and the second context may be pre-stored in a second register set. Both the first and second register sets may include one or more registers. When the first thread runs, the program execution context is the first context; when the second thread runs, the program execution context is the second context.

[0054] In step S21, when the program execution context is the first context, a first thread corresponding to the first context can be run. The first thread may include at least one instruction, which can sequentially flow into the instruction pipeline and be processed by the instruction pipeline. In step S22, in response to the detection of a target instruction in the instruction pipeline of the program execution, the program execution context can be switched from the first context to a second context pre-stored in the second register group. Since both the first and second contexts are pre-stored in their respective registers, the program context can be switched quickly and conveniently through register operations. For example, in one embodiment, the program context can be switched by modifying the values ​​of preset flag bits in the first register group and the second register group. For example, when the preset flag bit in the first register group is "1", it indicates that the program execution context is the first context; when the preset flag bit in the first register group is "0", it indicates that the program execution context is not the first context, etc. After switching the program execution context from the first context to the second context, the second thread corresponding to the second context can be run in step S23. In other words, after a program execution context switch, the program running in the instruction pipeline can also switch accordingly.

[0055] It should be noted that, in the embodiments of the present invention, the target instruction can refer to any instruction whose meaning does not conflict with other instructions of the processor. The target instruction can be defined as needed, as long as it can be distinguished from other instructions of the processor. The embodiments of the present invention do not limit this.

[0056] In one implementation, the target instruction may occupy one or more bytes. In another implementation, the target instruction may occupy the lower four bits of a byte. In this way, during instruction decoding, the fourth byte can be decoded directly without the need for shifting as required for the higher four bits, thus enabling faster identification of the target instruction and faster context switching.

[0057] In one implementation, the target instruction may be located after an instruction of a preset category, wherein the preset category of instructions may be instructions whose execution time exceeds a preset duration threshold. Specifically, the preset duration threshold can be set and adjusted as needed. Thus, when an instruction of the preset category is about to cause pipeline congestion, the instruction pipeline has already decoded and identified the target instruction following that instruction, thereby initiating context switching and thread switching operations based on the target instruction.

[0058] Target instructions can be set in the first thread in various ways. For example, in one implementation, the target instructions can be included in the source code of the first thread. In another implementation, the target instructions can also be inserted by the compiler when compiling the source code of the first thread. In yet another implementation, some target instructions can be included in the source code of the first thread, and other target instructions can be inserted by the compiler; embodiments of the present invention do not limit this.

[0059] Specifically, in one embodiment of the present invention, the instruction pipeline may include at least one pipeline stage; wherein each pipeline stage may include a corresponding first register set and a corresponding second register set; the program execution context has a corresponding program execution context component in each pipeline stage, and the program execution context components together constitute a complete program execution context. Similarly, the first context has a corresponding first context component in each pipeline stage, and the first context components together constitute a complete first context, and the first context component is stored in the first register set corresponding to the pipeline stage. The second context has a corresponding second context component in each pipeline stage, and the second context components together constitute a complete second context, and the second context component is stored in the second register set corresponding to the pipeline stage.

[0060] Based on this, step S22, in response to detecting the target instruction in the instruction pipeline of the program execution, switching the program execution context from the first context to the second context, specifically may include: in response to detecting the target instruction at any pipeline stage, switching the program execution context component corresponding to that pipeline stage from the first context component to the second context component. Correspondingly, step S23, in running the second thread corresponding to the second context, specifically may include: running the second thread corresponding to the second context in that pipeline stage.

[0061] In other words, in the embodiments of the present invention, when switching threads in the program executed in the instruction pipeline, this can be achieved by switching threads at each pipeline stage. Specifically, each pipeline stage can be checked for the presence of a target instruction. If a target instruction exists, the program execution context component corresponding to that pipeline stage is switched, and after the program context component has been switched, the running thread is switched. In this way, as the target instruction is passed through each pipeline stage, the entire instruction pipeline can gradually complete the switching of program execution and thread switching.

[0062] Furthermore, in one embodiment of the present invention, after step S23 switches the program running context from the first context to the second context, the program running method provided by the embodiment of the present invention may further include: selecting a thread as a third thread from at least one thread in a "ready" state; replacing the first context with the third context corresponding to the third thread and storing it in the first register group.

[0063] In this embodiment, after switching the program execution context from the first context to the second context, since the second thread will subsequently run, the first context stored in the first register group is no longer of practical use. Therefore, the ready thread queue Q1 can be checked to see which threads are included. According to a preset rule, a thread in the "ready" state is selected from the ready thread queue Q1 as the third thread, and the third thread's corresponding third context replaces the original first context and is stored in the first register group, thus preparing for the next context switch. Here, the ready thread queue Q1 is a thread queue in which all threads are in the "ready" state. The preset rule may include, for example, a first-in, first-out (FIFO) rule.

[0064] In one implementation, replacing the first context with the third context corresponding to the third thread and storing it in the first register group may specifically include: retrieving the third context corresponding to the third thread from memory; and storing the third context in place of the first context in the first register group. That is, in this embodiment, the third context corresponding to the third thread can be stored in memory (e.g., RAM), and when needed, the third context is retrieved from memory and stored in the first register group, thereby achieving both improved processor performance and reduced register hardware costs.

[0065] Of course, in another embodiment of the present invention, if the program only includes two threads, the first thread and the second thread, it is not necessary to look up the third context. Instead, the first context is kept in the first register group so that when the second thread is blocked, the program can switch back to the first thread.

[0066] In embodiments of the present invention, after switching the program execution context from a first context to a second context, a second thread corresponding to the second context can be run in step S23. Similar to the first thread, in one embodiment of the present invention, the second thread may also include at least one instruction, which may include a target instruction. Based on this, after running the second thread corresponding to the second context in step S23, the program execution method provided by the embodiments of the present invention may further include: in response to detecting a target instruction in the instruction pipeline of the program execution, switching the program execution context from the second context to a third context; using the third context as the new first context and the third thread as the new first thread, jumping to the step of running the first thread corresponding to the first context when the program execution context is the first context, and continuing to execute iteratively. In this way, the first register group and the second register group are used alternately to store the program execution context and to store the spare context (that is, the context of the thread to be executed), so that the switching of the program execution context is faster and more flexible, which facilitates further improvement of processor utilization.

[0067] Accordingly, the third aspect, such as Figure 6 As shown, embodiments of the present invention also provide a processor 4, which may include any of the instruction pipelines 3 provided in the foregoing embodiments, and thus can also achieve the corresponding beneficial technical effects. The foregoing has already provided the corresponding description, and will not be repeated here.

[0068] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0069] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0070] In particular, the device embodiment is basically similar to the method embodiment, so the description is relatively simple. For relevant details, please refer to the description of the method embodiment.

[0071] For ease of description, the above apparatus is described by dividing it into various functional units / modules. Of course, in implementing this invention, the functions of each unit / module can be implemented in one or more software and / or hardware.

[0072] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0073] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An instruction pipeline, characterized in that, include: The execution module is configured to run a first thread corresponding to the first context when the program execution context is a first context. The first thread includes at least one instruction, and the at least one instruction includes a target instruction. The first context is stored in the first register group of the execution module. A detection module, electrically connected to the operating module, is used to detect whether the target instruction exists in the operating module; A switching module, electrically connected to the detection module and the running module respectively, is used to switch the program running context in the running module from the first context to a second context pre-stored in the second register group of the running module when the detection module detects the target instruction; The running module is further configured to run a second thread corresponding to the second context after the switching module switches the program running context from the first context to the second context.

2. The instruction pipeline according to claim 1, characterized in that, The running module includes at least one pipeline stage; wherein each pipeline stage includes a corresponding first register group and a corresponding second register group; The program execution context has a corresponding program execution context component in each pipeline stage; The first context has a corresponding first context component in each pipeline stage, and the first context component is stored in the first register group corresponding to the pipeline stage; The second context has a corresponding second context component in each pipeline stage, and the second context component is stored in the second register group corresponding to that pipeline stage.

3. The instruction pipeline according to claim 2, characterized in that, The detection module includes at least one detection submodule, and each detection submodule is electrically connected to a corresponding flow stage. Each of the detection submodules is specifically used to detect whether the target instruction exists in the corresponding pipeline stage; The switching module includes at least one switching submodule. Each switching submodule is electrically connected to a corresponding pipeline level and a corresponding detection submodule. Specifically, when the detection submodule detects the target instruction, it switches the program execution context component corresponding to the pipeline level from the first context component to the second context component. The running module is specifically used to run a second thread corresponding to the second context in the pipeline after the switching submodule switches the program running context component corresponding to the pipeline from the first context component to the second context component.

4. The instruction pipeline according to any one of claims 1 to 3, characterized in that, Also includes: The selection module, electrically connected to the switching module, is used to select a thread in the "ready" state from the ready thread queue as the third thread after the switching module switches the program running context from the first context to the second context. The storage module is electrically connected to both the selection module and the running module, and is used to replace the first context with the third context corresponding to the third thread selected by the selection module, and store it in the first register group of the running module.

5. The instruction pipeline according to claim 4, characterized in that, The storage module is specifically used for: Retrieve the third context corresponding to the third thread from memory; The third context is used to replace the first context and stored in the first register group.

6. The instruction pipeline according to claim 4, characterized in that, The second thread includes at least one instruction, the at least one instruction including the target instruction; The detection module is further configured to detect whether the target instruction exists in the running module after the running module runs the second thread corresponding to the second context; The switching module is further configured to switch the program running context from the second context to the third context in response to the detection module detecting the target instruction; The running module is further configured to use the third context as the new first context and the third thread as the new first thread to continue running the first thread corresponding to the first context.

7. The instruction pipeline according to any one of claims 1 to 3, characterized in that, The target instruction is located after an instruction of a preset category, wherein the instruction of the preset category is an instruction whose execution time is greater than a preset time threshold.

8. The instruction pipeline according to any one of claims 1 to 3, characterized in that, The target instruction occupies at least one byte, or the lower four bits of a byte.

9. The instruction pipeline according to any one of claims 1 to 3, characterized in that, The target instructions are contained in the source code of the first thread, and / or the target instructions are inserted by the compiler when compiling the source code of the first thread.

10. A method for running a program, characterized in that, include: When the program execution context is a first context, a first thread corresponding to the first context is executed. The first thread includes at least one instruction, and the at least one instruction includes a target instruction. The first context is stored in a first register group. In response to detecting the target instruction in the instruction pipeline of the program execution, the program execution context is switched from the first context to a second context pre-stored in the second register set; Run the second thread corresponding to the second context.

11. The method according to claim 10, characterized in that, The instruction pipeline includes at least one pipeline stage; wherein each pipeline stage includes a corresponding first register set and a corresponding second register set; The program execution context has a corresponding program execution context component in each pipeline stage; The first context has a corresponding first context component in each pipeline stage, and the first context component is stored in the first register group corresponding to the pipeline stage; The second context has a corresponding second context component in each pipeline stage, and the second context component is stored in the second register group corresponding to that pipeline stage.

12. The method according to claim 11, characterized in that, The step of switching the program execution context from the first context to the second context in response to detecting the target instruction in the instruction pipeline of the program execution includes: In response to detecting the target instruction in any of the pipeline stages, the program execution context component corresponding to that pipeline stage is switched from the first context component to the second context component; The second thread running in the second context includes: The second thread corresponding to the second context runs in this pipeline stage.

13. The method according to any one of claims 10 to 12, characterized in that, After switching the program execution context from the first context to the second context, the method further includes: Select one thread as the third thread from at least one thread that is in the "ready" state; The first context is replaced by the third context corresponding to the third thread and stored in the first register group.

14. The method according to claim 13, characterized in that, The step of replacing the first context with the third context corresponding to the third thread and storing it in the first register group includes: Retrieve the third context corresponding to the third thread from memory; The third context is stored in the first register group instead of the first context.

15. The method according to claim 13, characterized in that, The second thread includes at least one instruction, the at least one instruction including the target instruction; After running the second thread corresponding to the second context, the method further includes: In response to detecting the target instruction in the instruction pipeline of the program execution, the program execution context is switched from the second context to the third context; Using the third context as the new first context and the third thread as the new first thread, jump to the step of running the first thread corresponding to the first context when the program running context is the first context, and continue to execute iteratively.

16. The method according to any one of claims 10 to 12, characterized in that, The target instruction is located after an instruction of a preset category, wherein the instruction of the preset category is an instruction whose execution time is greater than a preset time threshold.

17. The method according to any one of claims 10 to 12, characterized in that, The target instruction occupies at least one byte, or the lower four bits of a byte.

18. The method according to any one of claims 10 to 12, characterized in that, The target instructions are contained in the source code of the first thread, and / or the target instructions are inserted by the compiler when compiling the source code of the first thread.

19. A processor, characterized in that, The instruction pipeline includes any one of claims 1-9.

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