FPGA multitask dynamic scheduling system

Abstract

The application provides an FPGA multitask dynamic scheduling system and relates to the technical field of multitask scheduling, and comprises a collection module, a monitoring module and a construction module.The collection module is used for collecting task description information of each meteorological task in real time, and the task description information comprises a current calculation amount, a resource demand type and quantity, a task priority and a task state.The monitoring module is used for dynamically monitoring a current occupancy rate and a remaining available resource amount of each type of resource on each FPGA according to the task description information, and collecting real-time state data of a plurality of physical monitoring points distributed on each FPGA chip.The construction module is used for constructing a resource performance distribution hypersurface of each FPGA chip based on the real-time state data, and performing elliptic curve fitting on the resource performance distribution hypersurface to obtain a plurality of elliptic equivalent performance lines.The application guarantees real-time processing of high-priority meteorological tasks and improves overall resource utilization efficiency of the FPGA chip.

Description

Technical Field

[0001] This invention relates to the field of Internet of Things (IoT) smart terminal technology, and in particular to an FPGA multi-task dynamic scheduling system. Background Technology

[0002] In the field of meteorological scientific computing, high-performance computing servers based on FPGAs have been widely used for real-time processing of various meteorological monitoring data. The traditional FPGA multi-task scheduling system used by a provincial meteorological center has obvious scheduling strategy defects when processing meteorological computing tasks with dynamically changing priorities, such as short-term heavy precipitation and typhoon path simulation. The system relies on the initial computational load and fixed priority of the task to carry out static resource allocation. It does not combine the real-time status data such as temperature and voltage at different physical locations of the FPGA chip to build a resource efficiency distribution model, does not make differentiated corrections for resource efficiency in different regions, and lacks a reasonable resource preemption mechanism. When a high-priority meteorological task arrives, it waits for a low-priority task to finish before allocating resources.

[0003] Technical issues in traditional scheduling systems cause processing delays in high-priority meteorological early warning tasks, and the overall resource utilization efficiency of FPGA chips is at a low level, making it difficult for the system to meet the core requirements of meteorological disaster early warning work for real-time data processing and efficient hardware resource utilization. Summary of the Invention

[0004] This invention provides an FPGA multi-task dynamic scheduling system to ensure the real-time processing of high-priority meteorological tasks and improve the overall resource utilization efficiency of FPGA chips.

[0005] To solve the above-mentioned technical problems, the technical solution of the present invention is as follows: The first aspect is an FPGA multi-task dynamic scheduling system, including: The data acquisition module is used to collect task description information for each meteorological task in real time. The task description information includes the current computational load, resource requirement type and quantity, task priority, and task status. The monitoring module is used to dynamically monitor the current occupancy rate and remaining available resources of each type of resource on each FPGA based on the task description information, and to collect real-time status data of multiple physical monitoring points distributed on each FPGA chip. The module is used to construct the resource efficiency distribution hypersurface of each FPGA chip based on real-time status data, and to perform elliptic curve fitting on the resource efficiency distribution hypersurface to obtain multiple elliptic isoelectric lines; according to the distribution of the elliptic isoelectric lines, the resource efficiency distribution hypersurface is divided into regions to obtain multiple sub-regions and the efficiency correction coefficients corresponding to each sub-region. The sorting module is used to calculate the resource quota for each task in the task queue waiting to be scheduled based on the resource availability data of each FPGA and the performance correction coefficient of each sub-region, so as to obtain the corrected resource quota; and sort the task queue according to the current priority of each task to obtain the sorting result. The scheduling module allocates FPGA resources to tasks in descending order of priority based on the sorting results and resource quotas. If the available resources are insufficient, it preempts low-priority tasks that have already occupied resources and allocates the resources occupied by the preempted low-priority tasks to high-priority tasks. During task execution, it reclaims and reallocates resources in real time based on the dynamic changes in task computation and priority to achieve adaptive scheduling of FPGA multi-tasks.

[0006] Furthermore, based on the task description information, the current occupancy rate and remaining available resources of each type of resource on each FPGA are dynamically monitored, and real-time status data from multiple physical monitoring points distributed across each FPGA chip are collected, including: The raw transaction data streams from meteorological satellites, ground observation stations, and radar monitoring networks are captured in real time to obtain raw transaction data streams containing gridded meteorological data, radar reflectivity factor data, and automatic station observation data; The original transaction data stream is parsed and fields are extracted to obtain the updated task description information for each meteorological task, as well as the monitoring trigger signal that triggers the collection of physical monitoring point status. Update the data based on the task description information, update the current computational load and resource requirement type and quantity of each meteorological task, and dynamically calculate the current occupancy rate and remaining available resources of the logic units, DSP operation modules and on-chip storage units on each FPGA based on the updated task description information; and start real-time status data acquisition of temperature monitoring points, voltage monitoring points and current monitoring points distributed on each FPGA chip according to the monitoring trigger signal.

[0007] Furthermore, based on real-time status data, a resource efficiency distribution hypersurface is constructed for each FPGA chip, and elliptic curve fitting is performed on the resource efficiency distribution hypersurface to obtain multiple elliptic isoelectric lines, including: Extract the real-time status data and corresponding resource usage data of each physical monitoring point on each FPGA chip. The physical monitoring points include temperature monitoring points, voltage monitoring points and current monitoring points. Using the physical location coordinates of each FPGA chip as the plane basis, the real-time status data and resource occupancy data at each physical monitoring point are weighted and fused to obtain the comprehensive resource efficiency index at each physical monitoring point. The comprehensive index is then used as the vertical axis to construct the resource efficiency distribution hypersurface of each FPGA chip. Multiple equivalent energy value sections are selected on the resource efficiency distribution hypersurface, and elliptic curve fitting is performed on the data points on each equivalent energy value section to obtain multiple elliptic equivalent energy lines corresponding to different efficiency values.

[0008] Furthermore, based on the distribution of elliptical equipotential lines, the resource efficiency distribution hypersurface is divided into regions, resulting in multiple sub-regions and corresponding efficiency correction coefficients for each sub-region, including: Based on the distribution density and curvature variation of multiple elliptical equipotential lines on the resource efficiency distribution hypersurface, the efficiency gradient between adjacent equipotential lines is calculated to obtain the efficiency gradient data at each location on each FPGA chip. Based on the efficiency gradient data, the resource efficiency distribution hypersurface is divided into multiple sub-regions with continuous efficiency gradients, and the efficiency gradient change rate in each sub-region is less than a preset threshold. Calculate the ratio of the comprehensive resource efficiency index at the center point of each sub-region to the comprehensive resource efficiency index of the global average of each FPGA chip, and use the ratio of the comprehensive index as the efficiency correction coefficient of the sub-region.

[0009] Furthermore, based on the resource availability data of each FPGA and the performance correction coefficient of each sub-region, resource quotas are calculated for each task in the task queue waiting to be scheduled, resulting in corrected resource quotas, including: The current remaining available resources of logic units, DSP computing modules and on-chip memory units on each FPGA are obtained, and the performance correction coefficients of each sub-region of the FPGA are obtained. For each task in the queue of tasks waiting to be scheduled, based on the type and quantity of resource requirements, traverse each sub-region of each FPGA and calculate the equivalent resource usage required to deploy the task in different sub-regions. The sub-region with the smallest equivalent resource consumption is selected as the candidate deployment region for the tasks waiting to be scheduled, and the smallest equivalent resource consumption is used as the modified resource quota for the tasks waiting to be scheduled. Based on the revised resource quotas for each task and the selected candidate deployment regions, a resource quota allocation scheme for each task is obtained.

[0010] Furthermore, the task queue is sorted according to the current priority of each task, resulting in the following sorting results: Extract the task identifier and candidate deployment area of ​​each task from the resource quota allocation scheme of each task, and determine the ring number corresponding to each candidate deployment area according to the inside-out order of the divided sub-regions in the elliptical equipotential energy line distribution. Based on the current priority of each task, the dynamic rate of change of computational load, the task waiting time, and the ring zone number of the candidate deployment area, the dynamic scheduling priority value of each task is obtained through weighted calculation. The tasks in the waiting task queue are sorted in descending order of dynamic scheduling priority to obtain the sorted task queue, which is the sorting result.

[0011] Furthermore, based on the sorting results and resource quotas, FPGA resources are allocated to tasks in descending order of priority. If the currently available resources are insufficient, low-priority tasks that have already occupied resources are preempted, and the resources occupied by the preempted low-priority tasks are allocated to high-priority tasks, including: Extract the currently assigned tasks sequentially from the sorted task queue, and obtain the modified resource quota and corresponding candidate deployment area from the resource quota allocation scheme of each task; query the remaining available resources of each type of resource in the candidate deployment area on each FPGA to determine whether the modified resource quota requirements of each task are met. If the conditions are met, the task is deployed to the candidate deployment area, and the occupancy rate and remaining available resources of the logic units, DSP computing modules and on-chip storage units in the area are updated. If the conditions are not met, all tasks currently being executed on each FPGA are traversed, and preemptible tasks with lower priority than the current task to be assigned are selected. The execution of preemptible tasks is paused in order of priority from low to high, and the resources occupied by the preemptible tasks are reclaimed until the sum of the reclaimed resources and the remaining available resources in the candidate deployment area meets the modified resource quota requirements of the task to be assigned. The recovered resources are merged with the remaining available resources in the candidate deployment area, allocated to the tasks to be assigned, and deployed to the candidate deployment area. The suspended preemptible tasks are then added back to the queue of tasks waiting to be scheduled.

[0012] Furthermore, during task execution, resources are dynamically reclaimed and reallocated in real time based on changes in task computational load and priority to achieve adaptive scheduling of FPGA multi-tasks, including: During task execution, the updated task description information of each task, the updated occupancy rate and remaining available resources of each type of resource on each FPGA, and the performance correction coefficient of each task deployment area are obtained in real time. Based on the task description information, it is determined whether the resource reallocation triggering conditions are met. The triggering conditions include the arrival of a new high-priority task, the priority of the currently executing task being increased, the computational load of the currently executing task being lower than its current resource quota, and the completion of task execution. When any trigger condition is detected, identify the low-priority task with a lower priority than the high-priority task to be scheduled or the low-priority task with low resource utilization efficiency among the currently executing tasks, suspend the execution of the low-priority task, reclaim the occupied resources, and add the suspended task back to the queue of tasks waiting to be scheduled. Based on the updated resource availability data and the performance correction coefficients of each sub-region, the resource quotas of all tasks in the waiting scheduling task queue are recalculated, sorted and allocated to obtain a resource allocation scheme. According to the new resource allocation scheme, the tasks to be executed are deployed to the designated sub-regions of the corresponding FPGA and resumed execution, and the resource occupancy status of each FPGA is updated to complete adaptive scheduling.

[0013] In a second aspect, a computing device includes: One or more processors; A storage device for storing one or more programs that, when executed by one or more processors, cause the one or more processors to execute the system.

[0014] Thirdly, a computer-readable storage medium storing a program that, when executed by a processor, performs the system.

[0015] The above-described solution of the present invention has at least the following beneficial effects: By employing real-time acquisition of meteorological task description information and FPGA chip physical monitoring data, constructing a resource efficiency distribution hypersurface and dividing the region to calculate efficiency correction coefficients, and combining these coefficients to correct resource quotas, and obtaining dynamic scheduling priority values ​​for tasks through multi-dimensional weighting, while implementing priority-oriented preemptive resource allocation and adaptive resource reallocation during task execution, this technology effectively overcomes the technical problems of traditional FPGA multi-task scheduling systems that use static resource allocation, fail to combine FPGA physical state for differentiated resource efficiency configuration, and lack a high-priority task resource preemption mechanism, leading to delays in high-priority meteorological task processing and low FPGA chip resource utilization. This achieves precise matching between meteorological computing tasks and the actual resource efficiency of FPGA chips, ensuring real-time processing of high-priority meteorological early warning tasks, and dynamically adapting to changes in the computational load and priority of meteorological tasks, thereby improving the overall resource utilization efficiency of FPGA chips and meeting the core requirements of meteorological disaster early warning for real-time data processing and efficient hardware resource utilization. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of an FPGA multi-task dynamic scheduling system provided in an embodiment of the present invention.

[0017] Figure 2 The FPGA multi-task dynamic scheduling system provided in the embodiments of the present invention divides the resource efficiency distribution hypersurface into regions based on the distribution of elliptical equipotential lines, and obtains multiple sub-regions and the efficiency correction coefficients corresponding to each sub-region. Detailed Implementation

[0018] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0019] like Figure 1 As shown, an embodiment of the present invention proposes an intelligent diagnostic and processing system for abnormal states of urban electronic police monitoring support poles, comprising: The data acquisition module is used to collect task description information for each meteorological task in real time. The task description information includes the current computational load, resource requirement type and quantity, task priority, and task status. The monitoring module is used to dynamically monitor the current occupancy rate and remaining available resources of each type of resource on each FPGA based on the task description information, and to collect real-time status data of multiple physical monitoring points distributed on each FPGA chip. The module is used to construct the resource efficiency distribution hypersurface of each FPGA chip based on real-time status data, and to perform elliptic curve fitting on the resource efficiency distribution hypersurface to obtain multiple elliptic isoelectric lines; according to the distribution of the elliptic isoelectric lines, the resource efficiency distribution hypersurface is divided into regions to obtain multiple sub-regions and the efficiency correction coefficients corresponding to each sub-region. The sorting module is used to calculate the resource quota for each task in the task queue waiting to be scheduled based on the resource availability data of each FPGA and the performance correction coefficient of each sub-region, so as to obtain the corrected resource quota; and sort the task queue according to the current priority of each task to obtain the sorting result. The scheduling module allocates FPGA resources to tasks in descending order of priority based on the sorting results and resource quotas. If the available resources are insufficient, it preempts low-priority tasks that have already occupied resources and allocates the resources occupied by the preempted low-priority tasks to high-priority tasks. During task execution, it reclaims and reallocates resources in real time based on the dynamic changes in task computation and priority to achieve adaptive scheduling of FPGA multi-tasks.

[0020] In this embodiment of the invention, the system employs real-time acquisition of descriptive information such as computational load and resource requirements of meteorological tasks, dynamic monitoring of FPGA resource occupancy and chip physical monitoring point status, construction of a resource efficiency distribution hypersurface and fitting of elliptical iso-efficiency lines, division of regional computational efficiency correction coefficients, and adjustment of task resource quotas based on these coefficients. Tasks are then prioritized and prioritized, implementing priority-oriented preemptive FPGA resource allocation. Furthermore, during task execution, resources are dynamically reclaimed and reallocated based on changes in computational load and priority. This overcomes the technical problems of traditional FPGA multi-task scheduling systems, such as static resource allocation, failure to consider resource efficiency in conjunction with the actual chip status, lack of a high-priority task resource preemption mechanism, and difficulty in adapting to dynamic task changes. Ultimately, this achieves precise adaptation between meteorological tasks and FPGA resources, ensures real-time processing of high-priority meteorological tasks, enables adaptive scheduling of FPGA multi-tasks, and improves the overall resource utilization efficiency of the FPGA chip.

[0021] In a preferred embodiment of the present invention, task description information for each meteorological task is collected in real time. This task description information includes the current computational load, resource requirement type and quantity, task priority, and task status. Specifically, this includes: establishing a real-time meteorological task information collection terminal, which simultaneously connects to both the meteorological task application end and the FPGA task execution end, enabling the collection of full task information for newly applied meteorological tasks and currently executing meteorological tasks. The collection process is dynamically refreshed at a rate of seconds to ensure the real-time nature of the information. The collection terminal obtains basic application information for newly applied meteorological tasks from the application end and extracts execution node information and processed data information for currently executing meteorological tasks from the execution end, forming a basic information database for all meteorological tasks. A unique task is assigned to each meteorological task in the basic information database. The system identifies and manages task information separately. Based on a basic information database, it calculates the current computational load for each meteorological task sequentially. First, it extracts the initial computational load from the task application. Combining the real-time increment of meteorological data with the unit data processing computational load coefficient for the corresponding meteorological task type, it calculates the real-time newly added computational load: Real-time newly added computational load = Real-time increment of meteorological data × Unit data processing computational load coefficient. The unit data processing computational load coefficient is pre-calibrated according to different meteorological task types such as short-term heavy precipitation simulation, typhoon path simulation, and routine meteorological monitoring. Then, it extracts the completed computational load of the currently executing task. For newly applied tasks, the completed computational load is 0. Finally, it obtains the current computational load for each meteorological task: Current computational load = Initial computational load + Real-time newly added computational load - Completed computational load.

[0022] After completing the current computational workload calculation, the resource requirements and quantities for each meteorological task are determined. The resource requirements are uniformly categorized into three types: FPGA logic units, FPGA DSP computing modules, and FPGA on-chip storage units. Then, based on the unit processing power of each resource type, the required quantity for each type is calculated: Resource Requirement Quantity = Current Computational Workload ÷ Unit Processing Power of the Corresponding Resource Type. The unit processing power of an FPGA logic unit is the number of meteorological computation instructions that can be processed per unit per second; the unit processing power of an FPGA DSP computing module is the number of meteorological data floating-point operations that can be completed per module per second; and the unit processing power of an FPGA on-chip storage unit is the amount of raw meteorological data and intermediate processed data that can be stably stored per unit. If the calculation result contains a decimal, it is rounded up to obtain the final resource requirement. The number of source requests is determined, and the task priority of each meteorological task is verified. A weighted calculation method is used to determine the priority value. The priority value = business type weight × basic business priority + data urgency weight × urgency coefficient + initial application priority weight, and the sum of the weights of business type weight, data urgency weight, and initial application priority weight is 1. Among them, the basic business priority of meteorological disaster early warning tasks is the highest value, the basic business priority of routine meteorological data statistics tasks is the basic value, the data urgency is divided into three levels of high, medium and low according to the effective update time of meteorological data and corresponding to different urgency coefficients, and the initial application priority is the basic priority value submitted by the task application end. According to the priority value from high to low, the meteorological tasks are divided into priority levels to form the final task priority of each task.

[0023] The task status of each meteorological task is determined based on the actual progress information of the task's application node, scheduling node, execution node, and completion node. Newly applied meteorological tasks that have not yet entered the scheduling queue are determined to be in a pending application state; meteorological tasks that have entered the scheduling queue but have not been allocated FPGA resources are determined to be in a waiting scheduling state; meteorological tasks that have been allocated FPGA resources and are performing calculations are determined to be in an executing state; meteorological tasks that have been suspended due to resource preemption are determined to be in a suspended state; and meteorological tasks that have completed all current calculations and output calculation results are determined to be in a completed state. After completing the verification and determination of all information on the current calculation volume, resource requirement type and quantity, task priority, and task status of a single meteorological task, the information of each dimension is associated and bound with the task identifier and entered into the meteorological task description information database. The acquisition terminal repeats the above process at a frequency of seconds to update and synchronize the information in the database in real time, thus completing the real-time acquisition of the description information of each meteorological task.

[0024] In this embodiment of the invention, by building a real-time acquisition terminal with full-terminal connectivity and combining standardized calculation and verification rules, accurate, real-time, and comprehensive acquisition of meteorological task description information from all dimensions is achieved. This solves the technical problems of lagging task information acquisition, large deviations in current calculation volume estimation, inaccurate resource demand verification, fixed task priorities without dynamic adjustment, and ambiguous task status determination in traditional scheduling systems. It forms a complete, accurate, and real-time updated meteorological task description information database, providing reliable and unified data source support for FPGA resource dynamic monitoring, resource efficiency modeling, resource quota calculation, and task sorting and scheduling, ensuring the orderly implementation of the FPGA multi-task dynamic scheduling process from the data source.

[0025] In a preferred embodiment of the present invention, based on task description information, the current occupancy rate and remaining available resources of each type of resource on each FPGA are dynamically monitored, and real-time status data of multiple physical monitoring points distributed on each FPGA chip are collected, including: Real-time capture of raw transactional data streams from meteorological satellites, ground observation stations, and radar monitoring networks yields raw transactional data streams containing gridded meteorological data, radar reflectivity factor data, and automatic weather station observation data. Specifically, this involves: establishing a high-speed multi-source meteorological raw data capture architecture. This architecture establishes dedicated high-speed data transmission links with the meteorological satellite data receiver, the ground observation station data transmission end, and the radar monitoring network data aggregation end. These links employ a high-bandwidth, low-latency transmission mode to ensure the real-time transmission of massive amounts of meteorological data. The capture architecture synchronously captures the output data from each data source at millisecond-level frequencies, including data transmitted from meteorological satellites. The system receives all global gridded meteorological data, automatic station observation data such as temperature, precipitation, and wind speed transmitted from various ground observation stations, and radar reflectivity factor data obtained from radar monitoring network scanning. During the reception process, data integrity is verified for each type of data, and invalid data such as lost frames and out-of-order frames generated during transmission are removed. The verified valid gridded meteorological data, radar reflectivity factor data, and automatic station observation data are then packaged in a unified format to form a structured raw transaction data stream. After packaging, a data acquisition timestamp and data source identifier are added to the data stream to complete the real-time acquisition of the raw transaction data stream.

[0026] The system performs protocol parsing and field extraction on the raw transaction data stream to obtain updated task description information for each meteorological task, as well as monitoring trigger signals for physical monitoring point status acquisition. Specifically, this includes: parsing and extracting the encapsulated raw transaction data stream; accurately identifying the transmission protocol of the raw transaction data stream; matching the dedicated transmission protocols of corresponding data sources such as meteorological satellite-to-ground transmission protocols, ground observation station serial port transmission protocols, and radar monitoring network transmission protocols; parsing the frame structure of the raw transaction data stream according to the standard parsing rules of each protocol; removing redundant data fields such as protocol headers, check bits, and frame trailers; and extracting core valid data fields containing meteorological data increments, task execution association identifiers, and data validity periods. From these core valid data fields, the system matches the corresponding meteorological task based on the task execution association identifier, extracts information such as real-time meteorological data increments and resource requirement adjustments for that task, and integrates these to form updated task description information for each meteorological task. Simultaneously, a monitoring trigger threshold is set. When the extracted meteorological data increment reaches the preset threshold or task resource requirements are adjusted, the system automatically receives a monitoring trigger signal for physical monitoring point status acquisition. This signal carries the corresponding FPGA chip identifier and acquisition start command.

[0027] Based on the updated task description information, the current computational load and resource requirement types and quantities for each meteorological task are updated. The current occupancy rate and remaining available resources of the logic units, DSP processing modules, and on-chip storage units on each FPGA are dynamically calculated based on the updated task description information. Real-time status data acquisition of temperature, voltage, and current monitoring points distributed on each FPGA chip is initiated based on monitoring trigger signals. Specifically, this includes: receiving updated task description information, accurately matching the task identifier with the corresponding meteorological task, synchronously updating the meteorological data increments and resource requirement adjustment information in the updated data to the task description information database of each meteorological task, achieving real-time updates of the current computational load and resource requirement types and quantities for each meteorological task; dynamically calculating the resource status of each FPGA based on the updated task description information; calculating the total capacity of the logic units, DSP processing modules, and on-chip storage units for each FPGA; calculating the quantity of each type of resource currently occupied by all meteorological tasks currently allocated to that FPGA; and calculating the current occupancy rate and remaining available resources for each type of resource. The current occupancy rate is calculated as follows: (Current occupancy of a certain type of resource / Quantity of that type of resource). The remaining available resources are calculated as follows: (Total resource capacity) × 100%, and the total available resources of a certain type of resource is calculated as: Total resource capacity of a certain type of resource - Current occupancy of that type of resource. After performing the above calculations for the three types of resources in sequence, the current occupancy rate and remaining available resources of each type of resource on each FPGA are associated with the FPGA chip identifier to form a real-time ledger of FPGA resource status. This ledger is updated synchronously according to the data update frequency. While completing the FPGA resource status calculation, a monitoring trigger signal is received. Based on the FPGA chip identifier in the signal, the status acquisition process of the distributed physical monitoring points on each FPGA chip is initiated. For temperature monitoring points, voltage monitoring points, and current monitoring points in different physical areas of the FPGA chip, real-time data is acquired at a millisecond frequency using dedicated hardware. During the acquisition process, the original acquired values ​​are filtered to remove abnormal extreme values ​​caused by hardware fluctuations and retain valid monitoring values. The filtered real-time temperature of each temperature monitoring point, real-time voltage of each voltage monitoring point, and real-time current of each current monitoring point are bound with the corresponding FPGA chip identifier and physical location information of the monitoring point to form a real-time dataset of FPGA chip physical status. This dataset is synchronously stored in the hardware status database of the scheduling system to complete the real-time status data acquisition of all physical monitoring points.

[0028] In this embodiment of the invention, by building a high-speed acquisition and precise analysis architecture for multi-source meteorological data, real-time reception and effective information extraction of massive amounts of raw meteorological data are achieved. This solves the problems of lagging meteorological data acquisition and inaccurate analysis in traditional scheduling systems, ensuring the timeliness and accuracy of task description information updates. Simultaneously, based on the updated data, dynamic calculation of meteorological task information and FPGA resource status is completed. Through a clear calculation process, the accurate calculation of the occupancy rate and remaining available resources of various FPGA resources is achieved, solving the numerical deviation problem caused by static statistical resource status in traditional systems. Furthermore, a triggered acquisition method is used to complete the status acquisition of physical monitoring points on the FPGA chip, ensuring the real-time nature of physical status data, avoiding meaningless continuous acquisition, improving acquisition efficiency, and providing real and accurate hardware physical status data for constructing an FPGA resource performance distribution model. Overall, real-time synchronous updates of meteorological task information, FPGA resource status, and FPGA physical status are achieved, providing comprehensive, accurate, and real-time basic data support for dynamic scheduling of FPGA multi-tasks, ensuring a high degree of matching between scheduling decisions and actual task requirements and hardware status.

[0029] In a preferred embodiment of the present invention, a resource efficiency distribution hypersurface for each FPGA chip is constructed based on real-time status data, and elliptic curve fitting is performed on the resource efficiency distribution hypersurface to obtain multiple elliptic isodynamic lines, including: Real-time status data and corresponding resource usage data of each physical monitoring point on each FPGA chip are extracted. These physical monitoring points include temperature, voltage, and current monitoring points. Specifically, this involves: establishing an FPGA chip data association and extraction architecture; creating a bidirectional data synchronization link with the FPGA resource status real-time ledger and hardware status database; extracting full physical monitoring point data for each FPGA chip from the hardware status database at millisecond intervals; strictly associating the extraction with FPGA chip identification and monitoring point physical location information; accurately obtaining the real-time temperature value of each temperature monitoring point, the real-time voltage value of each voltage monitoring point, and the real-time current value of each current monitoring point; and simultaneously removing abnormal data caused by hardware interference, retaining only the most accurate data. Effective monitoring data is collected and timestamped. Resource occupancy data corresponding to the physical location of each physical monitoring point is extracted from the real-time log of FPGA resource status. For the FPGA chip area where each monitoring point is located, the real-time occupancy rate of logic units, DSP computing modules, and on-chip storage units in that area is extracted to ensure that the status data of the physical monitoring point and the resource occupancy data of the corresponding area are completely matched in terms of collection time and physical location. The real-time status data of the physical monitoring points of each FPGA chip and the resource occupancy data of the corresponding area are integrated into a structured dataset. The dataset contains core fields such as chip identifier, monitoring point location, temperature / voltage / current value, and area resource occupancy rate, completing the accurate extraction and integration of data.

[0030] Using the physical location coordinates of each FPGA chip as a planar basis, the real-time status data and resource occupancy data at each physical monitoring point are weighted and fused to obtain a comprehensive resource efficiency index for each physical monitoring point. Using this comprehensive index as the ordinate, a resource efficiency distribution hypersurface for each FPGA chip is constructed. Specifically, this involves: establishing a correlation system between physical location and resource efficiency for each FPGA chip; standardizing and weighting the status data and corresponding regional resource occupancy data of the physical monitoring points; quantitatively calculating the comprehensive resource efficiency index for each monitoring point; and finally constructing a resource efficiency distribution hypersurface that accurately reflects the differences in resource efficiency at different physical locations of the FPGA chip. The implementation process is as follows: A two-dimensional coordinate basis for the physical location of an FPGA chip is constructed using a single FPGA chip as an independent modeling unit. First, the geometric center of the chip is determined as the origin of the two-dimensional coordinate system. The horizontal physical extension direction of the chip is set as the X-axis, and the vertical physical extension direction is set as the Y-axis. According to the actual physical size of the FPGA chip, a continuous coordinate grid is divided using a proportional scaling principle. The accuracy of the grid matches the deployment density of the physical monitoring points, ensuring that each distributed physical monitoring point can be matched with a unique (X, Y) coordinate value in the two-dimensional coordinate system. This coordinate value corresponds precisely to the actual physical location of the monitoring point, forming a planar basis with the physical location as the core, laying the foundation for locating the resource efficiency value of each location.

[0031] Multi-dimensional data normalization processing is necessary because the temperature, voltage, and current of physical monitoring points are hardware operating status parameters, while the regional resource occupancy rate is a resource utilization parameter. These two types of data have significantly different dimensions and value ranges, making direct fusion calculation difficult. Therefore, it is necessary to normalize each of the four types of data separately, mapping all data to the 0-1 interval to eliminate dimensional differences and provide calculable standardized data for subsequent weighted fusion. If the normalized calculation result of any data exceeds the 0-1 interval, it is uniformly corrected to 0. The specific calculation formula and the meaning of the letters are as follows: Temperature normalized value: ,in, This is the normalized temperature value. For the real-time temperature value of the monitoring point, This is the minimum temperature for the FPGA chip to operate normally. The highest normal operating temperature of the FPGA chip; normalized voltage value: ,in, This is the normalized voltage value. For the real-time voltage value of the monitoring point, This is the lower limit of the rated voltage of the FPGA chip. The upper limit of the rated voltage of the FPGA chip; normalized current value: ,in, This is the normalized value of the current. To monitor the real-time current value at the monitoring point, This is the lower limit of the rated current of the FPGA chip. The maximum rated current of the FPGA chip; normalized value of regional resource occupancy: ,in, This is the normalized value of regional resource utilization rate. This represents the actual resource occupancy rate of the FPGA area where the monitoring point is located.

[0032] The weighted fusion computing resource efficiency comprehensive index combines the actual impact of different physical states and resource utilization states of FPGA chips on resource efficiency in meteorological scientific computing scenarios, and assigns differentiated weights to four types of normalized data, including temperature weight. 0.3, Voltage Weighting =0.2, current weight =0.2, Regional resource occupancy rate weight =0.3. Through a weighted fusion formula, the four types of standardized data are integrated into a quantitative indicator that can comprehensively characterize the resource efficiency of the area where the monitoring point is located, namely the comprehensive resource efficiency index. The calculation formula and design logic are as follows: ,in This is a comprehensive resource efficiency index, ranging from 0 to 1. A value closer to 1 indicates higher resource efficiency in that area. Design logic: Higher temperatures in the FPGA chip area lead to poorer hardware stability and lower resource efficiency; therefore, the temperature value is [not specified]. This achieves an inverse correlation between temperature and performance; the closer the normalized values ​​of voltage and current are to 1, the more stable the working state of that area of ​​the chip is; the closer the normalized value of resource utilization is to 1, the more fully the resources are utilized in that area. All three are positively correlated with resource performance, so they can be directly substituted into the formula for calculation.

[0033] According to the above formula, the comprehensive resource efficiency index E of all physical monitoring points on each FPGA chip is calculated one by one, and this index is bound to the (X, Y) coordinate values ​​of the monitoring points to form a correspondence between physical location and efficiency index. A hypersurface for FPGA chip resource efficiency distribution is constructed. Using the two-dimensional coordinates (X, Y) of the FPGA chip physical location built in step 1 as the plane basis, and the calculated comprehensive resource efficiency index E as the Z-axis, a three-dimensional coordinate system is constructed. All three-dimensional coordinate data (X, Y, E) of all physical monitoring points are imported into a dedicated algorithm for surface construction. Because the physical monitoring points are distributed, there are blank areas on the chip where no monitoring points are deployed. Therefore, cubic spline interpolation is used to accurately calculate the comprehensive resource efficiency index value of the blank areas based on the efficiency indices of the surrounding existing monitoring points, filling the gaps in the three-dimensional coordinate data. Based on the completed full three-dimensional coordinate data, a continuous and smooth hypersurface for resource efficiency distribution is obtained. This hypersurface can completely and intuitively depict the differences and trends in resource efficiency distribution at different physical locations on a single FPGA chip, realizing the visualization and quantitative modeling of FPGA chip resource efficiency.

[0034] Multiple equivalent efficiency value sections are selected on the resource efficiency distribution hypersurface. Elliptic curve fitting is performed on the data points on each equivalent efficiency value section to obtain multiple elliptical equivalent efficiency lines corresponding to different efficiency values. Specifically, this includes: determining the resource efficiency value intervals: using the minimum and maximum values ​​of the comprehensive resource efficiency index as boundaries, multiple different efficiency value thresholds are selected according to the principle of equal intervals. Each threshold corresponds to an equivalent efficiency value section. For each equivalent efficiency value section, all data points on that section are extracted: on the resource efficiency distribution hypersurface, all (X, Y) coordinate points whose Z-axis value equals the corresponding efficiency value threshold are selected to form the dataset for that equivalent efficiency value section. Elliptic curve fitting is performed on each dataset using the least squares method: the general equation of the elliptic curve is set as follows. Ax2+Bxy+Cy2+Dx+Ey+F=0 The (X, Y) coordinates in the dataset are substituted into the equation; the coefficients of the equation are solved by the least squares method to minimize the sum of the squared distances from all data points to the fitted curve, thus obtaining the elliptic curve equation corresponding to the equivalent performance value section; the fitting effect is verified, and if the goodness of fit is lower than the preset threshold, the performance value threshold is adjusted, data points are extracted again, and the fitting is repeated until the requirements are met. The above process is repeated to complete the elliptic curve fitting for all equivalent performance value sections, and finally multiple elliptic equivalent performance lines corresponding to different performance values ​​are obtained. Each equivalent performance line accurately corresponds to the physical region on the FPGA chip with the same resource performance level.

[0035] In this embodiment of the invention, by accurately extracting and matching the status data of the physical monitoring points of the FPGA chip with the corresponding regional resource occupancy data, the problem of traditional scheduling systems not correlating hardware physical status with resource occupancy is solved. By normalizing and weighted fusion to calculate the comprehensive resource efficiency index, a resource efficiency distribution hypersurface is constructed, realizing a quantitative characterization of the resource efficiency of different physical locations of the FPGA chip, breaking through the limitation of traditional systems that only evaluate the FPGA resource status from an overall level. By fitting multiple elliptical iso-efficiency lines through elliptic curves, regions with different efficiency levels on the FPGA chip are accurately divided, providing an intuitive and quantitative basic model for resource efficiency region division and efficiency correction coefficient calculation. This allows subsequent resource quota correction and task deployment to accurately match the actual efficiency distribution of the FPGA chip, improving the accuracy and rationality of resource allocation.

[0036] like Figure 2 As shown, in another preferred embodiment of the present invention, the resource efficiency distribution hypersurface is divided into regions based on the distribution of elliptical equivalence lines to obtain multiple sub-regions and efficiency correction coefficients corresponding to each sub-region, including: Based on the distribution density and curvature variation of multiple elliptical equivalence lines on the resource efficiency distribution hypersurface, the efficiency gradient between adjacent equivalence lines is calculated to obtain efficiency gradient data at each location on each FPGA chip. Specifically, this includes: sorting out all elliptical equivalence lines on the resource efficiency distribution hypersurface of each FPGA chip, extracting the comprehensive resource efficiency index value corresponding to each equivalence line, the core geometric parameters on the FPGA two-dimensional coordinate basis (X, Y), and the distribution density of the equivalence lines, and integrating the information into a structured elliptical... The circular equivalence line basic information database provides a complete and unified data source for gradient calculation. Based on this database, the efficiency gradient between adjacent equivalence lines is calculated according to a unified logic. The efficiency gradient is a core indicator characterizing the change in the comprehensive resource efficiency index within a unit physical distance between adjacent equivalence lines, directly reflecting the rate of efficiency change at different locations of the FPGA chip. First, the efficiency difference is calculated: select any two adjacent elliptical equivalence lines, and subtract the efficiency value corresponding to the lower-value equivalence line from the efficiency value corresponding to the higher-value equivalence line to obtain the efficiency difference Δ. E , that is, Δ E =High-value equivalent performance line performance value -Low-value equivalent performance line performance value; then calculate the average physical distance: For these two adjacent equivalent performance lines, select multiple sets of feature points on the FPGA two-dimensional coordinate base, such as the endpoints of the major and minor axes of the equivalent performance lines, and the four quadrant points. Calculate the Euclidean distance between each set of feature points, and take the average of all Euclidean distances as the average physical distance Δ between the two adjacent equivalent performance lines. D .

[0037] Calculate the basic performance gradient value using the formula G=ΔE / ΔD The basic performance gradient value G is calculated as the performance gradient value. The larger the value, the more drastic the performance change per unit physical distance in the region. Curvature correction is performed: the curvature value of each segment of each isoperformance line is extracted. If the curvature of a certain segment of the isoperformance line exceeds the preset curvature threshold calibrated based on the meteorological calculation scenario, it indicates that the performance distribution change in the region is more complex. The gradient value corresponding to this segment needs to be multiplied by a correction factor of 1.1 to ensure that the gradient data can accurately reflect the performance change differences caused by curvature. Full-position gradient data is obtained: the corrected gradient values ​​of each segment are accurately mapped to the corresponding physical positions on the FPGA two-dimensional coordinate base. Then, the gradient values ​​of the areas not covered by the isoperformance lines are supplemented by linear interpolation. Finally, the performance gradient data of all positions on each FPGA chip is obtained, realizing full matching of physical position and performance gradient value.

[0038] Based on the performance gradient data, the resource performance distribution hypersurface is divided into multiple sub-regions with continuous performance gradients. The rate of change of the performance gradient within each sub-region is less than a preset threshold. Specifically, after obtaining the full-chip performance gradient data, and considering the core requirements of meteorological computing tasks for the stability of FPGA resource performance, a threshold for the rate of change of performance gradient is preset. This threshold explicitly requires that the change in performance gradient value between any two points within a sub-region does not exceed 5% per millimeter. This ensures that the performance change within the sub-region is continuous and gradual, avoiding a decrease in meteorological task execution efficiency due to sudden performance changes. Based on this preset threshold, the FPGA chip sub-region division is completed in an orderly manner according to the following process: Determine the starting point for division: using the FPGA chip's two-dimensional coordinates... The geometric center of the base is used as the starting point for partitioning. The efficiency gradient data at each location is traversed in a fixed order from the center to the periphery and from the high-efficiency zone to the low-efficiency zone. The region is expanded outward from the starting point by coordinate grid points. For each grid point expanded, the gradient change rate between that point and all existing points in the region is immediately calculated. The gradient change rate is calculated as follows: Gradient change rate = |Current expanded point gradient value - Average gradient value of existing points in the region| / Average gradient value of existing points in the region × 100%. If the gradient change rate of all locations in the expanded region is less than a preset threshold, the expansion continues in that direction. If the gradient change rate of a certain expanded point exceeds the threshold, the expansion in that direction is stopped, thus determining the physical boundary of the sub-region.

[0039] Repeat the above expansion-calculation-determination process until the entire two-dimensional coordinate base of the FPGA chip is completely divided, resulting in multiple sub-regions with continuous performance gradients. Each sub-region has clear boundary coordinates, and the rate of change of performance gradient at all locations within the region meets the requirement of being less than a preset threshold. Assign a unique identifier to each sub-region, record its boundary coordinates and gradient data at all locations within the region, forming a sub-region division ledger for the FPGA chip, providing basic support for the calculation of performance correction coefficients.

[0040] The ratio of the comprehensive resource efficiency index at the center point of each sub-region to the comprehensive resource efficiency index of the global average resource efficiency index of each FPGA chip is calculated. This ratio is used as the efficiency correction coefficient for the sub-region. Specifically, this involves: calculating the efficiency correction coefficient of each sub-region according to a standardized process based on the divided sub-regions, thereby quantifying the degree of difference between each sub-region and the global average efficiency of the chip; calculating the (X, Y) coordinates of the geometric center point of each sub-region based on its boundary coordinates, with this center point serving as a representative position characterizing the overall efficiency of the sub-region; accurately extracting the comprehensive resource efficiency index corresponding to this center point from the 3D data of the FPGA chip resource efficiency distribution hypersurface; iterating through the comprehensive resource efficiency indices of all physical monitoring points on the hypersurface, first summing the total efficiency indices of all monitoring points, then dividing by the total number of physical monitoring points to obtain the global average comprehensive resource efficiency index of each FPGA chip. The calculation formula is as follows: E avg =Sum of comprehensive resource efficiency indicators of all physical monitoring points / Total number of physical monitoring points.

[0041] Calculate the performance correction factor: The performance correction factor is calculated using the formula: Performance Correction Factor = E center / E avg ,in E center For the comprehensive resource efficiency index value corresponding to the geometric center point of a certain sub-region of the FPGA chip, calculate the efficiency correction coefficient for each sub-region. This coefficient directly reflects the difference between the sub-region and the global average efficiency of the chip. A coefficient greater than 1 indicates that the efficiency of the sub-region is higher than the global average level, a coefficient less than 1 indicates that it is lower than the global average level, and a coefficient equal to 1 indicates that it is consistent with the global average level. If the calculated efficiency correction coefficient exceeds the reasonable range of 0.5-2.0 calibrated based on the meteorological calculation scenario, the entire process of extracting the sub-region center point and calculating the global average efficiency needs to be rechecked to correct data errors. After confirming that all coefficients are calculated correctly, bind the efficiency correction coefficient with the unique identifier of the corresponding sub-region to complete the calculation of the efficiency correction coefficients for all sub-regions.

[0042] In this embodiment of the invention, by quantifying the performance gradient between elliptical iso-performance lines, the limitations of traditional scheduling systems in evaluating FPGA resource performance holistically and identifying local performance differences are overcome, thus accurately characterizing the performance variation features at different locations of the FPGA chip. Sub-regions are divided according to the continuity of the performance gradient, ensuring that performance changes within each sub-region are gradual and stable, avoiding the problem of decreased resource utilization efficiency after meteorological mission deployment due to sudden performance changes. By calculating the ratio of the performance at the center point of a sub-region to the global average performance, a performance correction coefficient is obtained, quantifying the performance differences between sub-regions. This provides a core quantitative basis for the accurate correction of meteorological mission resource quotas, enabling resource allocation to accurately match the actual performance levels of different regions of the FPGA chip, thereby improving the rationality and accuracy of meteorological mission resource allocation.

[0043] In a preferred embodiment of the present invention, based on the resource availability data of each FPGA and combined with the performance correction coefficient of each sub-region, a resource quota is calculated for each task in the task queue waiting to be scheduled, resulting in a corrected resource quota, including: The process involves obtaining the current remaining available resources for logic units, DSP processing modules, and on-chip memory units on each FPGA, and acquiring the performance correction coefficients for each sub-region of the FPGA. Specifically, this includes: synchronously updating the real-time FPGA resource status ledger and the FPGA sub-region performance correction coefficient ledger at millisecond levels to ensure the data in the ledgers is up-to-date. The resource status ledger is updated to reflect the latest total capacity and occupied amount of each type of resource for each FPGA, while the performance correction coefficient ledger retains the unique identifier, boundary coordinates, and precise performance correction coefficient values ​​for all sub-regions of each FPGA. The process also involves retrieving FPGA resource availability data: for each individual FPGA chip, the chip-level remaining available resources for logic units, DSP processing modules, and on-chip memory units are retrieved one by one. Then, based on the sub-region division results of the chip, the chip-level remaining available resources are broken down into the remaining available resources for each type of resource at the sub-region level, according to the physical proportion of the sub-region and the actual resource deployment. For example, if an FPGA chip has a total of 1000 logic units remaining... The physical ratio of the two sub-regions is 6:4. After the initial split, the remaining logical units in the two sub-regions are 600 and 400 respectively. After fine-tuning based on the existing resource occupancy in the sub-regions, the precise remaining amount of the three types of resources in each sub-region is finally determined. This results in a four-dimensional resource list consisting of FPGA chip identifier, sub-region identifier, resource type, and sub-region-level remaining available resources. From the performance correction coefficient ledger, the corresponding sub-region is matched according to the FPGA chip identifier, and the performance correction coefficient for each sub-region is extracted. This coefficient is the final verified precise value without correction error. This results in a three-dimensional coefficient list consisting of FPGA chip identifier, sub-region identifier, and performance correction coefficient. The four-dimensional resource list and the three-dimensional coefficient list are cross-matched according to FPGA chip identifier and sub-region identifier. Entries with failed matches, missing data, or abnormal values ​​are removed to ensure that each sub-region with remaining resources has a corresponding performance correction coefficient. This is ultimately integrated into an accurate database of FPGA resources and performance, providing a unique and effective data source for subsequent calculations of equivalent resource occupancy.

[0044] For each task in the waiting task queue, based on the type and quantity of resource requirements, traverse each sub-region of each FPGA to calculate the equivalent resource occupancy required when deploying the task in different sub-regions. Specifically, this includes: taking a single meteorological task in the waiting task queue as an independent calculation unit, strictly relying on the approved basic resource requirements of the task, and combining the FPGA resource and performance precision database, calculating the equivalent resource occupancy after task deployment chip by chip and sub-region by sub-region, ensuring that the calculation results are highly compatible with the sub-region performance. Specific operations include: extracting the basic resource requirements of the current task to be calculated from the meteorological task description information database, clarifying the basic requirements of the task for three types of resources: FPGA logic units, DSP computing modules, and on-chip storage units. This quantity is a precise value calculated by formula and rounded up, with no room for adjustment; proceeding chip by chip, then within each chip... The algorithm iterates through all sub-regions with available resources in the FPGA resource and performance database, ensuring no deployable scenario is overlooked. It calculates the equivalent resource occupancy of each sub-region based on its resource type: for a given FPGA sub-region, its performance correction coefficient is extracted. Combined with the task's basic resource requirements, the equivalent resource occupancy for each of the three resource types is calculated. The core calculation logic is: Equivalent resource occupancy for a single resource type = Basic requirement quantity of that resource / Corresponding sub-region performance correction coefficient. Two decimal places are retained during the calculation to ensure accuracy. For example, if a task requires 150 logic units and 80 DSP modules, and the performance correction coefficient for a sub-region is 1.2, then the equivalent occupancy of logic units in that sub-region is 150 / 1.2 = 125.00, and the equivalent occupancy of DSP modules is 80 / 1.2 ≈ 66.67.

[0045] Calculate the total equivalent resource occupancy of a sub-region: Summate the equivalent resource occupancy of each of the three resource types in the sub-region to obtain the total equivalent resource occupancy of the task deployed to the current sub-region. For example, in the example above, if the equivalent occupancy of on-chip storage units is 50.00, then the total equivalent resource occupancy = 125.00 + 66.67 + 50.00 = 241.67. After each sub-region calculation is completed, immediately record the complete information of task identifier - FPGA chip identifier - sub-region identifier - equivalent occupancy of each resource type - total equivalent resource occupancy to form a detailed table of sub-region equivalent resource occupancy calculation for the task. After traversing all deployable sub-regions, the detailed table will contain the calculation data of all deployable scenarios for the task.

[0046] The sub-region with the lowest equivalent resource consumption is selected as the candidate deployment region for the task awaiting scheduling, and the lowest equivalent resource consumption is used as the adjusted resource quota for the task. Specifically, this involves: calculating a detailed table of equivalent resource consumption for sub-regions based on a single task; determining effective deployment regions through multi-dimensional filtering; selecting the optimal region as the candidate deployment region; and verifying the final resource quota for the task after performance adjustment to ensure that the quota is suitable for the sub-region's performance and meets the actual execution requirements of the task. Specifically, resource matching verification is performed on all sub-regions in the calculation details table, checking the remaining available resources of logic units, DSP processing modules, and on-chip storage units within each sub-region to ensure they are greater than or equal to the equivalent resource consumption of the corresponding resource type for the task in that sub-region. If all three resource types are satisfied, the sub-region is considered an effective deployment region; if any one type is not satisfied, it is eliminated, ensuring no risk of insufficient resources after task deployment. From all effective deployment sub-regions, the sub-region with the lowest total equivalent resource consumption is selected as the candidate deployment region for the task. If multiple sub-regions have the same total equivalent resource occupancy, a second screening is conducted based on the sub-region efficiency correction coefficient from high to low and the overall FPGA chip resource remaining rate from high to low to ensure that the selected candidate regions are the regions with the best efficiency and the most economical resource utilization. The equivalent resource occupancy of each resource type corresponding to the candidate deployment regions is extracted, and the equivalent value of each type of resource is rounded up. The rounded value is the corrected quota of that type of resource. The quota of the three types of resources is integrated to obtain the corrected total resource quota of the task. The purpose of rounding up is to avoid resource gaps caused by decimal parts and ensure sufficient resources during task execution. For example, if the equivalent occupancy of a logic unit in a sub-region is 66.67, it is rounded up to 67, which is the corrected quota of the logic unit. The task identifier, candidate deployment regions, corrected quota of each resource type, and corrected total resource quota are uniquely associated and bound to form the resource quota and deployment candidate information sheet for the task, thus completing the quota calculation and region determination for a single task.

[0047] Based on the revised resource quotas for each task and the selected candidate deployment regions, a resource quota allocation scheme for each task is obtained. Specifically, this includes: integrating the resource quotas and deployment candidate information sheets of all tasks in the waiting task queue; through multiple rounds of resource conflict verification and adjustment, a structured and directly executable resource quota allocation scheme is finally obtained, ensuring that the resource allocation of all tasks within the scheme is conflict-free and the deployment regions are reasonable. The specific operations are as follows: integrating the resource quotas and deployment candidate information sheets of all tasks to form a preliminary resource quota allocation scheme, which is categorized by FPGA chip and sub-region, recording the task list to be deployed in each region and the resource quota amount of each task; and, for each sub-region, calculating the sum of the revised resource quota amounts of all tasks to be deployed within that region, and determining whether the sum is less than or equal to the total resource quota amount for that sub-region. The remaining available resources for a given region are determined. If the total of all resource types meets the requirements, then there is no resource conflict in that sub-region. If the total of a certain type of resource exceeds the remaining available resources, then there is a resource conflict in that sub-region. For sub-regions with resource conflicts, resources are adjusted according to task priority from high to low, prioritizing the deployment needs of high-priority tasks and reallocating low-priority tasks: low-priority tasks are removed from the conflicting sub-regions, and other valid deployment sub-regions are re-traversed within the FPGA chip to recalculate the equivalent resource occupancy, determine new candidate regions, and adjust the quota. If there are no other valid deployment sub-regions within the same chip, valid sub-regions are traversed across FPGA chips to recalculate the quota and determine candidate regions. This verification and adjustment process is repeated until there are no resource conflicts in any sub-region.

[0048] After conflict resolution, a formal FPGA multi-task resource quota allocation scheme is formulated. The scheme includes three core parts: First, based on FPGA chip identifiers and sub-region identifiers, the task identifiers and priorities deployed in each region are clearly defined. Second, the corrected quota amounts for logic units, DSP computing modules, and on-chip storage units for each task within the deployment region are clearly defined, as well as the remaining available resources for each type of resource after allocation in each region. Third, the resource allocation order and deployment start time window for each task are clearly defined to ensure orderly scheduling and execution. The formal scheme undergoes a comprehensive review to confirm the absence of resource conflicts, data errors, and task deployment and performance compatibility. After the review is passed, the scheme is synchronized to the resource allocation and execution module of the FPGA multi-task scheduling system to provide a basis for subsequent task scheduling and execution.

[0049] In this embodiment of the invention, by dividing the remaining FPGA chip-level resources into sub-regions, the limitations of traditional scheduling systems that allocate resources only based on the chip as a whole are overcome, achieving refined and regionalized resource allocation. By combining the sub-region efficiency correction coefficient to calculate the equivalent resource occupancy, the task resource requirements are highly matched with the actual efficiency of the sub-regions, solving the technical problems of resource waste in high-efficiency areas and insufficient resources in low-efficiency areas caused by the one-size-fits-all resource allocation of traditional systems. By screening effective deployment areas from multiple dimensions and selecting the optimal candidate areas, the task execution requirements are met with minimal resource consumption, improving the overall resource utilization efficiency of the FPGA chip. Through sub-region-level resource conflict verification and hierarchical adjustment strategies, the resource requirements of high-priority meteorological tasks are prioritized, avoiding task execution delays caused by resource conflicts, and meeting the real-time requirements of meteorological disaster early warning. The final structured resource quota allocation scheme clarifies the deployment details, quota details, and execution guidelines, making FPGA resource allocation execution systematic and ensuring the orderliness and feasibility of the scheduling process. From the perspective of resource quota verification, it provides core support for the high efficiency of the entire FPGA multi-task dynamic scheduling.

[0050] In a preferred embodiment of the present invention, the task queue is sorted according to the current priority of each task to obtain a sorting result, including: The process involves extracting the task identifier and candidate deployment region for each task from the resource quota allocation scheme, and determining the ring zone number corresponding to each candidate deployment region based on the inside-out order of the divided sub-regions in the elliptical equivalence line distribution. Specifically, this includes extracting key task information from the obtained formal resource quota allocation scheme, and then, combined with the distribution characteristics of the FPGA chip's elliptical equivalence lines, assigning a unique ring zone number to each task's candidate deployment region. This achieves a precise association between the task deployment region and the FPGA performance ring zone. The specific operation involves accurately extracting the task identifier and complete candidate deployment region information from the FPGA resource quota allocation scheme for each task in the waiting task queue. The information includes the FPGA chip identifier and the unique identifier of the sub-region. At the same time, it retrieves the original data of the elliptical equivalent line distribution of the FPGA chip and the sub-region division ledger to ensure that the three types of data are accurately matched according to the chip identifier, without data misalignment or missing data. Based on the distribution characteristics of the elliptical equivalent lines of the FPGA chip from the inside to the outside, a unified ring numbering rule is formulated. Taking the geometric center of the FPGA chip as the core origin of the ring, and according to the spatial distribution order of the elliptical equivalent lines from the inside to the outside, a continuous ring number is assigned to each complete elliptical equivalent line. The number starts from 1 and increases sequentially. The smaller the ring number, the higher the resource efficiency of the FPGA region corresponding to the ring. The larger the ring number, the lower the resource efficiency of the region.

[0051] For each candidate deployment region of a task, the geometric center point of the sub-region is used as the core reference. Combined with the physical boundary coordinates of the sub-region, it is determined which elliptical equivalent energy line of the FPGA chip the main spatial range of the sub-region falls within. The sequence number of this ellipse is the sequence number of the corresponding ellipse of the candidate deployment region. If the spatial range of the sub-region spans multiple ellipses, only the sequence number of the ellipse in which the main body is located is taken as the final ellipse sequence number, and the cross-ellipse distribution of the sub-region is recorded simultaneously. The task identifier, candidate deployment region, and ellipse sequence number of each task are uniquely associated and bound to form a standardized task-deployment region-ellipse sequence number correspondence list. There are no duplicate or invalid entries in the list, providing basic indicator data for the calculation of dynamic scheduling priority.

[0052] Based on the current priority of each task, the dynamic rate of change of computational load, the task waiting time, and the ring zone number of the candidate deployment area, a weighted calculation is performed to obtain the dynamic scheduling priority value of each task. Specifically, this involves selecting four core indicators: current task priority, dynamic rate of change of computational load, task waiting time, and ring zone number of the candidate deployment area. First, the raw data of each indicator is normalized to eliminate dimensional differences. Then, the weights of each indicator are set according to the scheduling requirements of the meteorological computing scenario. Finally, the dynamic scheduling priority value of each task is obtained through weighted summation. A higher value indicates a higher scheduling priority. The specific operation involves extracting and calculating the raw data of the four core indicators for each task from the meteorological task description information database and the task-deployment area-ring zone number correspondence list. All data uses the latest collected values, and the calculation method remains consistent with the previous steps: the determined task priority level is converted into a quantitative value, and then... Meteorological tasks are assigned importance values ​​from highest to lowest. For example, the highest priority for meteorological disaster early warning is assigned 5, the next highest is assigned 4, and the lowest is assigned 1. The higher the quantified value, the higher the actual priority of the task. The dynamic change rate of the task's computational workload is reflected by the formula: Dynamic Change Rate of Computational Workload = (Current Computational Workload - Computational Workload at the Previous Data Collection Time) / Computational Workload at the Previous Data Collection Time × 100%. A positive result indicates an increase in computational workload, while a negative result indicates a decrease. The absolute value of the result is used for processing. The larger the absolute value of the change rate, the more drastic the fluctuation in computational workload, and the higher the priority for scheduling. The cumulative waiting time, in seconds, is calculated from the moment the task officially enters the waiting queue until the current moment. The longer the waiting time, the longer the task has been waiting for scheduling, and the higher the priority should be. Finally, the determined ring zone number is a natural number; the smaller the number, the higher the efficiency of the candidate area.

[0053] Normalization of the four-dimensional indicator data: Due to the differences in the dimensions and value ranges of the four indicators, they cannot be directly used in the weighted calculation. Therefore, all raw indicator data are uniformly mapped to the 0-1 range to complete the normalization process. If the normalization result exceeds the 0-1 range, it is uniformly corrected to 0 or 1. The specific normalization method is as follows: Normalized value of current task priority = quantized value of current task priority / maximum value of quantized priority values ​​of all tasks to be scheduled; Normalized value of dynamic change rate of computational workload = absolute value of dynamic change rate of task computational workload / maximum value of absolute value of dynamic change rate of computational workload of all tasks to be scheduled; Normalized value of task waiting time = actual waiting time of task / maximum value of waiting time of all tasks to be scheduled; Normalized value of ring zone number = 1 / ring zone number of candidate deployment area. Since the smaller the ring zone number, the higher the efficiency, the reciprocal form is used to realize the positive correlation between the indicator value and the regional efficiency. The larger the normalized value, the higher the efficiency of the candidate area.

[0054] In accordance with the core requirements of meteorological scientific computing for real-time performance and hardware efficiency, differentiated weightings are assigned to four normalized indicators. The sum of all indicator weights is 1 to ensure the rationality of the calculation results. In this embodiment, the weights are set as follows: current task priority weight 0.4, dynamic change rate of computational workload weight 0.2, task waiting time weight 0.2, and normalized value of ring zone number weight 0.2. This weighting prioritizes high-priority meteorological tasks while taking into account fluctuations in task computational workload, waiting time, and FPGA hardware efficiency. The dynamic scheduling priority is calculated by weighted summation: the four normalized indicator values ​​for each task are calculated according to a unified formula. Weighted calculations yield dynamic scheduling priority values, calculated using the formula: Dynamic scheduling priority value = (normalized value of current task priority × 0.4) + (normalized value of dynamic change rate of computational load × 0.2) + (normalized value of task waiting time × 0.2) + (normalized value of ring sequence number × 0.2). The calculation result is rounded to three decimal places to ensure numerical precision. A priority value association list is established: each task's task identifier is uniquely bound to the calculated dynamic scheduling priority value, and simultaneously associated with the task's four original indicator values ​​and normalized values, forming a task-dynamic scheduling priority value-indicator detail correspondence list, providing a core basis for task queue sorting.

[0055] The tasks in the waiting task queue are sorted according to their dynamic scheduling priority from highest to lowest to obtain a sorted task queue, which serves as the sorting result. Specifically, this involves: using dynamic scheduling priority as the core sorting criterion, formulating a core + secondary sorting rule, and sorting the waiting task queue in an orderly manner to obtain a standardized task queue sorting result that can directly guide execution. The specific operation is as follows: based on the task-dynamic scheduling priority-indicator detail correspondence list, all waiting tasks are sorted according to their dynamic scheduling priority from highest to lowest. The higher the dynamic scheduling priority value, the higher the position in the scheduling queue, and the more likely the task is to obtain FPGA resource allocation qualification.

[0056] To address situations where multiple tasks have identical dynamic scheduling priority values, a hierarchical secondary sorting rule is established to determine the task order sequentially, ensuring the uniqueness and rigor of the sorting results. The secondary sorting rule is as follows: first, tasks are sorted from highest to lowest based on their current priority quantification value; if this metric is still the same, they are then sorted from longest to shortest waiting time; if still the same, they are finally sorted from highest to lowest based on the absolute value of the dynamic change rate of computational load. Following the core + secondary sorting rule, all tasks to be scheduled are sorted one by one, and each sorted task is assigned a unique consecutive scheduling sequence number. Smaller scheduling sequence numbers indicate higher scheduling priority. The higher the priority, the better. Based on the sorting results, a standardized task queue sorting result list is obtained. The list contains core information such as scheduling sequence number, task identifier, dynamic scheduling priority value, candidate deployment area, ring sequence number, current task priority, dynamic change rate of computational load, and task waiting time. The task queue sorting result list is synchronized to the resource allocation execution module of the FPGA multi-task scheduling system. At the same time, the list is fully reviewed to confirm that there are no sorting misalignments, missing data, duplicate sequence numbers, or other issues. After the review is passed, the list becomes the final task queue sorting result, which serves as the direct execution basis for subsequent sequential allocation of FPGA resources.

[0057] In this embodiment of the invention, the traditional FPGA multi-task scheduling system, which only sorts tasks by fixed priority, combines the real-time characteristics of meteorological tasks with the resource efficiency distribution characteristics of FPGA chips. It introduces multi-dimensional indicators to construct a dynamic scheduling priority weight calculation system, making the task sorting results more in line with the actual scheduling needs of meteorological scientific computing. This solves the technical problem that the traditional sorting method ignores changes in task computation, waiting time, and hardware status. By defining ring numbers for candidate deployment areas and incorporating them into the sorting indicators, the linkage between task sorting and FPGA hardware performance status is realized, allowing tasks adapted to high-performance areas to be reasonably prioritized and scheduling, thereby improving the utilization efficiency of FPGA chip resources from the sorting level.

[0058] Normalization of each indicator eliminates the dimensional differences between different indicators. Differentiated weights are set based on meteorological scenarios to ensure the objectivity and rationality of dynamic scheduling priority calculation. The core + secondary sorting rule solves the sorting problem of tasks with the same priority weight, making the sorting process more rigorous and the result more unique. The final standardized sorting result list clarifies the scheduling order of tasks and all core information, providing a clear and effective basis for priority-based preemptive resource allocation. This ensures that high-priority meteorological disaster early warning tasks with drastic fluctuations in computational load and long waiting times are prioritized for scheduling, meeting the core requirement of real-time data processing for meteorological disaster early warning and improving the scientific and rational scheduling of the entire FPGA multi-task scheduling system.

[0059] In a preferred embodiment of the present invention, FPGA resources are allocated to tasks in descending order of priority based on the sorting results and resource quotas. If the currently available resources are insufficient, low-priority tasks that have already occupied resources are preempted, and the resources occupied by the preempted low-priority tasks are allocated to high-priority tasks. This includes: The system extracts currently assigned tasks sequentially from the sorted task queue and obtains the revised resource quota and corresponding candidate deployment area from the resource quota allocation scheme of each task. It then queries the remaining available resources of each type of resource within the candidate deployment area on each FPGA to determine if the revised resource quota requirements for each task are met. Specifically, this includes: extracting the currently assigned task at the top of the sorted task queue; accurately obtaining two key pieces of information from the resource quota allocation scheme of this task: the revised resource quota and the candidate deployment area; and querying the real-time remaining available resources of the three types of resources within the aforementioned candidate deployment area using the FPGA resource status monitoring system: remaining available resources for logic units, DSP computing modules, and on-chip storage units. The remaining available resources = total capacity of this type of resource - currently occupied quantity, ensuring that the query results are consistent with the actual hardware status.

[0060] Availability is assessed for the three types of resources, with the following rules: If the remaining available quantity of a certain type of resource in the candidate area is greater than or equal to the modified resource quota for the corresponding type for the task, then the resources are considered sufficient. If the remaining available quantity of any type of resource is less than the corresponding quota, the resources are considered insufficient, and a preemption process must be initiated. The task to be assigned requires 100 logic units, 50 DSP modules, and 80 on-chip storage units. If the candidate area has 80 remaining logic units, 50 remaining DSP modules, and 90 remaining on-chip storage units, then the resources are considered insufficient because the remaining quantity of logic units is less than the required quota. If the candidate area has 100 remaining logic units, 50 remaining DSP modules, and 80 remaining on-chip storage units, and all three types are satisfied, then the resources are considered sufficient.

[0061] If the conditions are met, the task is deployed to the candidate deployment area, and the occupancy rate and remaining available resources of the logic units, DSP computing modules, and on-chip storage units within the area are updated. If the conditions are not met, all tasks currently executing on each FPGA are iterated through, and preemptible tasks with lower priority than the current task to be assigned are selected. The execution of preemptible tasks is then paused sequentially according to their priority from low to high, and the resources occupied by the preemptible tasks are reclaimed until the sum of the reclaimed resources and the remaining available resources in the candidate deployment area meets the modified resource quota requirements of the task to be assigned. Specifically, if sufficient resources are determined, a task deployment instruction is issued to the FPGA scheduling and execution module to load the task to be assigned into the hardware execution unit corresponding to the candidate deployment area, start task execution, and calculate and update the occupancy rates of the three types of resources. The updated occupied amount = the original occupied amount + the corresponding type of resource quota for the task after modification; calculate and update the remaining available amount of the three types of resources: the updated remaining available amount = the original remaining available amount - the corresponding type of resource quota for the task after modification; calculate and update the occupancy rate of the three types of resources: occupancy rate = (updated occupied amount / total capacity of the resource type) × 100%; all calculation results are synchronized to the FPGA resource status ledger in real time to ensure that the ledger data is consistent with the actual hardware status. The total capacity of the candidate area logic units is 200, the original occupied amount is 80, and the remaining available amount is 120; the quota of logic units to be allocated is 50, then the updated occupied amount = 80 + 50 = 130, the remaining available amount = 120 - 50 = 70, and the occupancy rate = (130 / 200) × 100% = 65%.

[0062] If resource shortage is detected, the following process is used to preempt low-priority task resources: Screening the list of preemptible tasks: Iterate through all tasks currently executing on the FPGA chip in the candidate deployment area, filtering out two types of preemptible tasks that meet the following criteria: tasks with a priority lower than the currently assigned task, and whose resource type matches the required type of the assigned task; Sort the selected preemptible tasks from low to high priority to form a preemptible task list, and sequentially pause tasks, reclaim resources, and verify: Starting from the first item in the preemptible task list, repeatedly perform the operations of pausing tasks, reclaiming resources, and verifying the total resources until the remaining available amount of the three types of resources plus the amount of reclaimed resources all meet the quota requirements of the assigned task; Issue a pause command to the FPGA execution module to pause the currently selected preemptible task, automatically save the task execution progress, and ensure that it can continue running when restarted; Count the actual number of logic units, DSP processing modules, and on-chip storage units occupied by the preemptible task, and allocate all resources accordingly. The available resources are reclaimed to the candidate deployment area. The accumulation rule for the reclaimed resources is: Current reclaimed resources = Cumulative reclaimed resources + Reclaimed resources of the corresponding type from the paused task. The sum of the remaining available resources in the candidate area and the reclaimed resources is calculated, with the rule: Total resources = Original remaining available resources in the candidate area + Cumulative reclaimed resources. It is determined whether the sum is greater than or equal to the resource quota of the corresponding type of the task to be assigned. If the sum of the three types of resources meets the requirements, the preemption stops. If not, the next low-priority task in the list is selected and the above operation is repeated. The task to be assigned requires 100 logical units, and the original remaining logical units in the candidate area are 80, so at least 20 need to be reclaimed. The preemptible task 1 occupies 15 logical units, and the total resources after reclamation are 80 + 15 = 95. The preemptible task 2 occupies 10 logical units, and the total resources after reclamation are 80 + 25 = 105. The total resources of the DSP computing module and on-chip storage unit meet the requirements, so the preemption stops.

[0063] The recovered resources are merged with the remaining available resources in the candidate deployment area and allocated to the tasks to be assigned. These tasks are then deployed to the candidate deployment area, and any suspended preemptible tasks are re-added to the queue of tasks awaiting scheduling. Specifically, this involves: merging all recovered resources with the original remaining available resources in the candidate deployment area to form a total available resource pool. The merging rule is: the total available resource pool for a certain type of resource = the original remaining available resources in the candidate area + the cumulative recovered resources of that type; allocating corresponding resources from the total available resource pool according to the revised quota of the tasks to be assigned; updating the remaining amount in the total available resource pool after allocation: remaining amount after allocation = total available resource pool amount - quota of the corresponding type for the task to be assigned; and then scheduling the task to the FPGA. The execution module issues instructions to load the tasks to be assigned into the hardware execution units corresponding to the candidate deployment areas, and starts task execution based on the allocated resources; at the same time, it updates the FPGA resource status ledger: occupied amount = original occupied amount + quota amount corresponding to the type of task to be assigned; remaining available amount = remaining amount after allocation; occupancy rate = (updated occupied amount / total capacity of this type of resource) × 100%, collects all suspended preemptible tasks, organizes and saves key information such as execution progress, occupied resource amount, and original priority of each task when it was suspended; marks the task with a re-enqueue flag after preemption, and adds it back to the queue of tasks waiting to be scheduled, ensuring that its priority can be recalculated and participate in resource allocation in subsequent scheduling stages.

[0064] In this embodiment of the invention, the real-time execution of high-priority tasks is guaranteed: through a preemptive resource allocation mechanism, even if FPGA resources are insufficient, high-priority tasks can acquire resources first, solving the problem of high-priority tasks waiting due to insufficient resources in traditional scheduling. This aligns with the core real-time requirements of scenarios such as meteorology and emergency response. Resources are categorized, verified, reclaimed, and allocated according to logic units, DSP computing modules, and on-chip storage units, avoiding waste caused by overall resource reclamation. This ensures that each type of resource can accurately match task requirements, improving the overall utilization efficiency of FPGA resources. When preempting resources, they are executed in order of priority from low to high, and the preempted task saves its execution progress and is re-enqueued, maximizing the guarantee of high-priority task requirements and preventing low-priority tasks from being permanently shelved. This balances scheduling efficiency and the fairness of task execution, ensuring traceability of resource status and stable system operation: every resource allocation, reclamation, and deployment operation updates the resource status ledger in real time. All resource changes have a clear calculation process and data record, facilitating later traceability and investigation, and improving the stability and maintainability of the FPGA multi-task scheduling system.

[0065] In a preferred embodiment of the present invention, during task execution, resources are dynamically reclaimed and reallocated based on changes in task computational load and priority to achieve adaptive scheduling of FPGA multi-tasks, including: During task execution, the updated task description information of each task, the updated occupancy rate and remaining available resources of each type of resource on each FPGA, and the performance correction coefficient of each task deployment area are acquired in real time. Based on the task description information, it is determined whether the resource reallocation trigger conditions are met. The trigger conditions include the arrival of a new high-priority task, the priority of an currently executing task being increased, the computational load of an currently executing task being lower than its current resource quota, and the completion of task execution. Specifically, with a collection period of 100ms, three types of core data are collected synchronously: updated information of all currently executing / newly arriving tasks; updated occupancy rate and remaining available resources of the three types of resources on each FPGA and each sub-region; and real-time performance correction coefficients of each task deployment sub-region. The trigger conditions and judgment logic are defined: four types of trigger conditions are preset, and the condition is marked when any one of them is met. Resource reallocation needs to be initiated if: a new high-priority task arrives with a priority higher than all currently executing tasks, and there is insufficient resource in the candidate area; the priority of an executing task is increased by ≥1 level compared to the previous collection cycle, and the increased priority is higher than some low-priority tasks in the same area; the task's computational load is lower than the current quota; and the resource utilization efficiency is calculated as follows: resource utilization efficiency = (current actual computational load / theoretical maximum computational load corresponding to the allocated quota) × 100%. If the efficiency is <60% (meteorological scenario calibration value), it is considered inefficient resource utilization. The theoretical maximum computational load is calculated based on the deployment area efficiency correction coefficient to match the actual hardware capabilities; and when the task execution progress reaches 100% and the output result is normal, all resources need to be reclaimed. For scenarios that meet the trigger conditions, a reallocation trigger identifier should be marked, and all monitoring data at the trigger time should be archived.

[0066] When any trigger condition is detected, identify low-priority tasks with lower priority than high-priority tasks awaiting scheduling or with low resource utilization efficiency among currently executing tasks. Suspend the execution of low-priority tasks, reclaim the occupied resources, and add the suspended tasks back to the queue of tasks awaiting scheduling. Specifically, if the trigger condition is a newly arrived high-priority task or an upgrade of the priority of an executing task: lock the FPGA chip to which the candidate deployment area of ​​the high-priority task belongs, traverse all currently executing tasks on that chip, and filter out executing tasks with priority quantization values ​​lower than the high-priority task; sort them from low to high priority quantization values, and if priorities are the same, sort them from high to low resource utilization to form a list of tasks to be suspended. If the trigger condition is that the computational load of an executing task is lower than the current quota: filter all executing tasks with resource utilization efficiency <60%, further filter out low-priority tasks with priority quantization values ​​≤3, sort them from low to high resource utilization to form a list of tasks to be suspended. If the trigger condition is that the task has been completed: directly add the completed task with a normal result to the resource reclamation list, without pausing, and directly reclaim resources.

[0067] After meticulously identifying the target tasks, the system performs differentiated resource reclamation operations for tasks in different lists to ensure hardware security and prevent data loss: A safe pause command is issued to the FPGA execution module, which automatically backs up the task's critical execution state to the FPGA's on-chip cache and external storage to prevent data loss; the actual number of logic units, DSP processing modules, and on-chip storage units occupied by the task is read, and resources are transferred from the occupied pool to the available resource pool. The calculation rule is: the remaining available amount of a certain type of resource after reclamation = the remaining available amount before reclamation + the amount of the corresponding type of resource occupied by the task; the remaining available amount of resources after reclamation is updated in real time. The resource occupancy rate is synchronized to the distributed resource ledger, and the resource status is marked as available. For completed tasks in the resource reclamation list: all resources occupied by the task are directly reclaimed, and the task is removed from the list of tasks in execution, marked as completed, and the task execution log is archived. After the suspended tasks are re-enqueued in a standardized manner, in order to ensure the scheduling fairness of low-priority tasks, the system immediately performs a re-enqueuing operation on the suspended tasks: each suspended task is given an adaptive re-enqueuing identifier, the task's suspension status data is packaged, and the packaged task information is pushed to the end of the queue of tasks waiting to be scheduled, so as to ensure that the subsequent resource reallocation process can identify and recalculate its quota and priority.

[0068] Based on the updated resource availability data and the performance correction coefficients for each sub-region, resource quotas for all tasks in the waiting scheduling task queue are recalculated, sorted, and allocated to obtain a resource allocation scheme. Specifically, this includes: writing all reclaimed resources into the FPGA resource ledger; updating the remaining available, occupied, and occupancy rates of logic units, DSP processing modules, and on-chip storage units for each FPGA and sub-region to ensure the ledger data is completely consistent with the actual hardware status; and reading the latest FPGA sub-region temperature and load data to recalculate the real-time performance correction coefficients for each sub-region. Replace the old coefficient values ​​in the ledger; add a redistribution version number and update timestamp to the updated ledger data to avoid data confusion; recalculate the resource quotas for all tasks awaiting scheduling. After the data source update is complete, calculate the resource quotas for each task in the queue of tasks awaiting scheduling, ensuring that the quotas are adapted to the current resource and performance status: retrieve the updated resource ledger data, obtain the remaining available amount of the three types of resources and the total capacity of each sub-region of each FPGA; traverse different sub-regions to calculate the equivalent resource occupancy of tasks; prioritize selecting the sub-region with the lowest equivalent occupancy + remaining available amount ≥ equivalent occupancy as the optimal one. Candidate regions; The basic resource requirements of the task are adjusted based on the performance correction coefficient of the optimal candidate region to obtain the adjusted resource quota. The calculation rule is: Adjusted quota = Basic resource requirement of the task × (Base performance / Real-time performance correction coefficient of the sub-region). Example: If the basic resource requirement of the task is 100 logical units, the base performance is 100 GFLOPS, and the real-time performance correction coefficient of the candidate region is 85.5 GFLOPS, then the adjusted quota = 100 × (100 / 85.5) ≈ 117 logical units. After recalculating the task dynamic scheduling priority and sorting all tasks, the quota recalculation is completed. The system recalculates and sorts the dynamic scheduling priorities based on the latest task attributes: current task priority, rate of change of computational workload, waiting time, and candidate region ring number; rate of change of computational workload = (current computational workload - computational workload of the previous cycle) / computational workload of the previous cycle × 100%, normalized value of candidate region ring number = 1 / ring number; final priority score calculation: final priority score = (priority quantification value / highest priority value) × 40% + (rate of change of computational workload / maximum rate of change) × 20% + (waiting time / longest waiting time) × 20% + normalized value of ring number × 20%.

[0069] The tasks are sorted from highest to lowest priority score. If scores are the same, they are sorted again by priority quantification value, waiting time, and rate of change of computational load, resulting in a new task sorting queue. A new allocation scheme without resource conflicts is obtained. Based on the new task sorting queue, the system checks the resource suitability of each task: the optimal candidate region is allocated to each task in order of sorting. The verification rule is that the total quota of all allocated tasks in the same sub-region is less than or equal to the total resource capacity of the corresponding sub-region. If the candidate region of a task is insufficient, a second-best candidate region is selected for the task and the verification is repeated until there are no conflicts. Finally, a complete allocation scheme is obtained.

[0070] According to the new resource allocation scheme, tasks to be executed are deployed to designated sub-regions of the corresponding FPGAs and their execution resumes. The resource occupancy status of each FPGA is updated to achieve adaptive scheduling. Specifically, this includes: After receiving the allocation scheme, the scheduling and execution module deploys tasks according to their type: it issues resource allocation and task start instructions, and the hardware execution module loads the task into an idle execution unit in the designated sub-region, allocates the corresponding number of logic units, DSP processing modules, and on-chip storage units, and starts task execution; for tasks that have been paused and re-entered into the queue: it issues resource allocation and task resumption instructions, the hardware execution module loads the task into the designated sub-region, allocates new resource quotas, and resumes execution from the paused computing node; if the candidate region resources for a task are still insufficient, it is kept in the waiting task queue for further scheduling. Each monitoring cycle involves rescheduling and real-time updates to the resource status ledger. Upon completion of each task's deployment / recovery, the resource status of the corresponding FPGA sub-region is updated. The calculation rules are consistent with the initial allocation process, ensuring accurate ledger data: Updated occupied amount = Pre-update occupied amount + Corrected resource quota for the corresponding type of task; Updated remaining available amount = Pre-update remaining available amount - Corrected resource quota for the corresponding type of task; Updated occupancy rate = Updated occupied amount / Total capacity of this type of resource × 100%; The total capacity of candidate region logic units is 200, with 80 occupied and 120 remaining available before the update; The re-entry task has a corrected quota of 30, so the updated occupied amount = 80 + 30 = 110, the remaining available amount = 120 - 30 = 90, and the occupancy rate = 110 / 200 × 100% = 55%. After all update operations are completed, the consistency between the ledger data and the hardware register data is automatically verified. The error must be ≤0.1%. If the error exceeds the limit, data calibration is triggered. After the adaptive scheduling task deployment and ledger update are completed, the latest task execution status and resource status are collected to carry out closed-loop verification: whether high-priority tasks are executing normally, whether the resource utilization efficiency of all executing tasks is ≥60%, and whether there are resource conflicts in each FPGA sub-region. If all verification items are met, the current round of adaptive scheduling is marked as complete, and the process returns to the 100-millisecond high-frequency monitoring cycle. If any verification item is not met, the process is immediately repeated to re-identify and reclaim resources, reconstruct the allocation scheme and deployment verification process until the verification items meet the standards.

[0071] In this embodiment of the invention, a delay-free transition is achieved through real-time data synchronization and instruction seamless integration. Compared to traditional segmented scheduling, this improves overall response efficiency and better adapts to the high real-time requirements of scenarios such as meteorological services. The resource reclamation method is precise and reasonable, maximizing resource utilization. This invention filters tasks for resource reclamation based on different triggering conditions and scenarios, reclamating resources only for low-priority tasks or tasks with low resource utilization efficiency. While fully releasing redundant resources, it does not affect the normal execution of core high-priority tasks, effectively improving the overall resource utilization efficiency of the FPGA. The resource quota calculation and task sorting have strong dynamic adaptability, and the scheduling logic is more scientific and reasonable. When recalculating resource quotas, a real-time performance correction coefficient is combined, and when reordering tasks, multi-dimensional task attributes are taken into account. The resulting resource allocation scheme can accurately match the FPGA. The system monitors the real-time operating status of the hardware to avoid resource mismatch issues, while balancing task continuation capability and scheduling fairness to ensure the continuity of business operations. Suspended tasks can retain their complete execution status and be re-added to the scheduling queue, ensuring the real-time execution needs of high-priority tasks while preventing low-priority tasks from being shelved for a long time. This effectively guarantees the continuity of various meteorological tasks. A closed-loop verification mechanism provides stability assurance for system operation. After task deployment, the scheduling effect is fully verified. If the expected results are not achieved, the scheduling process is automatically re-executed. Combined with the real-time calibration mechanism of the resource status ledger, the entire process of resource changes is traceable and verifiable, which greatly improves the overall operational stability of the FPGA multi-task scheduling system.

[0072] Embodiments of the present invention also provide a computing device, including: a processor and a memory storing a computer program, wherein the computer program, when executed by the processor, performs the method described above. All implementations in the above method embodiments are applicable to this embodiment and can achieve the same technical effects.

[0073] Embodiments of the present invention also provide a computer-readable storage medium storing instructions that, when executed on a computer, cause the computer to perform the method described above. All implementations in the above method embodiments are applicable to this embodiment and can achieve the same technical effects.

[0074] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and such improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. An FPGA multi-task dynamic scheduling system, characterized in that, include: The data acquisition module is used to collect task description information for each meteorological task in real time. The task description information includes the current computational load, resource requirement type and quantity, task priority, and task status. The monitoring module is used to dynamically monitor the current occupancy rate and remaining available resources of each type of resource on each FPGA based on the task description information, and to collect real-time status data of multiple physical monitoring points distributed on each FPGA chip. The module is used to construct the resource efficiency distribution hypersurface of each FPGA chip based on real-time status data, and to perform elliptic curve fitting on the resource efficiency distribution hypersurface to obtain multiple elliptic isoelectric lines; according to the distribution of the elliptic isoelectric lines, the resource efficiency distribution hypersurface is divided into regions to obtain multiple sub-regions and the efficiency correction coefficients corresponding to each sub-region. The sorting module is used to calculate the resource quota for each task in the task queue waiting to be scheduled based on the resource availability data of each FPGA and the performance correction coefficient of each sub-region, so as to obtain the corrected resource quota; and sort the task queue according to the current priority of each task to obtain the sorting result. The scheduling module is used to allocate FPGA resources to tasks in order of priority from high to low according to the sorting results and resource quotas. If the available resources are insufficient, it will preempt the low-priority tasks that have already occupied resources and allocate the resources occupied by the preempted low-priority tasks to the high-priority tasks. During task execution, resources are reclaimed and reallocated in real time based on the dynamic changes in task computation and priority to achieve adaptive scheduling of FPGA multi-tasks.

2. The FPGA multi-task dynamic scheduling system according to claim 1, characterized in that, Real-time capture of raw transaction data streams; dynamic monitoring of the current occupancy rate and remaining available resources of each type of resource on each FPGA based on task description information; and collection of real-time status data from multiple physical monitoring points distributed across each FPGA chip, including: The raw transaction data streams from meteorological satellites, ground observation stations, and radar monitoring networks are captured in real time to obtain raw transaction data streams containing gridded meteorological data, radar reflectivity factor data, and automatic station observation data; The original transaction data stream is parsed and fields are extracted to obtain the updated task description information for each meteorological task, as well as the monitoring trigger signal that triggers the collection of physical monitoring point status. Update the data based on the task description information, update the current computational load and resource requirement type and quantity of each meteorological task, and dynamically calculate the current occupancy rate and remaining available resources of the logic units, DSP operation modules and on-chip storage units on each FPGA based on the updated task description information; and start real-time status data acquisition of temperature monitoring points, voltage monitoring points and current monitoring points distributed on each FPGA chip according to the monitoring trigger signal.

3. The FPGA multi-task dynamic scheduling system according to claim 2, characterized in that, Based on real-time status data, a resource efficiency distribution hypersurface is constructed for each FPGA chip, and elliptic curve fitting is performed on the hypersurface to obtain multiple elliptic iso-efficiency lines, including: Extract the real-time status data and corresponding resource usage data of each physical monitoring point on each FPGA chip. The physical monitoring points include temperature monitoring points, voltage monitoring points and current monitoring points. Using the physical location coordinates of each FPGA chip as the plane basis, the real-time status data and resource occupancy data at each physical monitoring point are weighted and fused to obtain the comprehensive resource efficiency index at each physical monitoring point. The comprehensive index is then used as the vertical axis to construct the resource efficiency distribution hypersurface of each FPGA chip. Multiple equivalent energy value sections are selected on the resource efficiency distribution hypersurface, and elliptic curve fitting is performed on the data points on each equivalent energy value section to obtain multiple elliptic equivalent energy lines corresponding to different efficiency values.

4. The FPGA multi-task dynamic scheduling system according to claim 3, characterized in that, Based on the distribution of elliptical isodynamic lines, the hypersurface of resource efficiency distribution is divided into regions, resulting in multiple sub-regions and corresponding efficiency correction coefficients for each sub-region, including: Based on the distribution density and curvature variation of multiple elliptical equipotential lines on the resource efficiency distribution hypersurface, the efficiency gradient between adjacent equipotential lines is calculated to obtain the efficiency gradient data at each location on each FPGA chip. Based on the efficiency gradient data, the resource efficiency distribution hypersurface is divided into multiple sub-regions with continuous efficiency gradients, and the efficiency gradient change rate in each sub-region is less than a preset threshold. Calculate the ratio of the comprehensive resource efficiency index at the center point of each sub-region to the comprehensive resource efficiency index of the global average of each FPGA chip, and use the ratio of the comprehensive index as the efficiency correction coefficient of the sub-region.

5. The FPGA multi-task dynamic scheduling system according to claim 4, characterized in that, Based on the resource availability data of each FPGA and the performance correction coefficients for each sub-region, resource quotas are calculated for each task in the waiting task queue to obtain the corrected resource quotas, including: The current remaining available resources of logic units, DSP computing modules and on-chip memory units on each FPGA are obtained, and the performance correction coefficients of each sub-region of the FPGA are obtained. For each task in the waiting queue, based on the type and quantity of resource requirements, traverse each sub-region of each FPGA and calculate the equivalent resource usage required to deploy the task in different sub-regions. The sub-region with the smallest equivalent resource consumption is selected as the candidate deployment region for the tasks waiting to be scheduled, and the smallest equivalent resource consumption is used as the modified resource quota for the tasks waiting to be scheduled. Based on the revised resource quotas for each task and the selected candidate deployment regions, a resource quota allocation scheme for each task is obtained.

6. The FPGA multi-task dynamic scheduling system according to claim 5, characterized in that, The task queue is then sorted according to the current priority of each task, resulting in the following sorting order: Extract the task identifier and candidate deployment area of ​​each task from the resource quota allocation scheme of each task, and determine the ring number corresponding to each candidate deployment area according to the inside-out order of the divided sub-regions in the elliptical equipotential energy line distribution. Based on the current priority of each task, the dynamic rate of change of computational load, the task waiting time, and the ring number of the candidate deployment area, the dynamic scheduling priority value of each task is obtained through weighted calculation. The tasks in the waiting task queue are sorted in descending order of dynamic scheduling priority to obtain the sorted task queue, which is the sorting result.

7. The FPGA multi-task dynamic scheduling system according to claim 6, characterized in that, Based on the sorting results and resource quotas, FPGA resources are allocated to tasks in descending order of priority. If the currently available resources are insufficient, low-priority tasks that are already using resources are preempted, and the resources used by the preempted low-priority tasks are allocated to high-priority tasks, including: Extract the currently assigned tasks sequentially from the sorted task queue, and obtain the modified resource quota and corresponding candidate deployment area from the resource quota allocation scheme of each task; query the remaining available resources of each type of resource in the candidate deployment area on each FPGA to determine whether the modified resource quota requirements of each task are met. If the conditions are met, the task is deployed to the candidate deployment area, and the occupancy rate and remaining available resources of the logic units, DSP computing modules and on-chip storage units in the area are updated. If the conditions are not met, all tasks currently being executed on each FPGA are traversed, and preemptible tasks with lower priority than the current task to be assigned are selected. The execution of preemptible tasks is paused in order of priority from low to high, and the resources occupied by the preemptible tasks are reclaimed until the sum of the reclaimed resources and the remaining available resources in the candidate deployment area meets the modified resource quota requirements of the task to be assigned. The recovered resources are merged with the remaining available resources in the candidate deployment area, allocated to the tasks to be assigned, and deployed to the candidate deployment area. The suspended preemptible tasks are then added back to the queue of tasks waiting to be scheduled.

8. The FPGA multi-task dynamic scheduling system according to claim 7, characterized in that, During task execution, resources are dynamically reclaimed and reallocated in real time based on changes in task computational load and priority to achieve adaptive scheduling of FPGA multi-tasks, including: During task execution, the updated task description information of each task, the updated occupancy rate and remaining available resources of each type of resource on each FPGA, and the performance correction coefficient of each task deployment area are obtained in real time. Based on the task description information, it is determined whether the resource reallocation triggering conditions are met. The triggering conditions include the arrival of a new high-priority task, the priority of the currently executing task being increased, the computational load of the currently executing task being lower than its current resource quota, and the completion of task execution. When any trigger condition is detected, identify the low-priority task with a lower priority than the high-priority task to be scheduled or the low-priority task with low resource utilization efficiency among the currently executing tasks, suspend the execution of the low-priority task, reclaim the occupied resources, and add the suspended task back to the queue of tasks waiting to be scheduled. Based on the updated resource availability data and the performance correction coefficients of each sub-region, the resource quotas of all tasks in the waiting scheduling task queue are recalculated, sorted and allocated to obtain a resource allocation scheme. According to the new resource allocation scheme, the tasks to be executed are deployed to the designated sub-regions of the corresponding FPGA and resumed execution, and the resource occupancy status of each FPGA is updated to complete adaptive scheduling.

9. A computing device, characterized in that, include: One or more processors; A storage device for storing one or more programs, which, when executed by the one or more processors, cause the one or more processors to perform the system as described in any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a program that, when executed by a processor, performs the system as described in any one of claims 1 to 8.

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