A data read-write method and a data read-write system

Abstract

The application discloses a data read-write method and a data read-write system, and belongs to the technical field of memories. The method is applied to a master control chip in a solid state disk based on a phase change memory, and comprises the following steps: in response to a read-write request, a target physical address corresponding to a storage unit to be accessed is acquired; the target physical address comprises a low-bit physical positioning field; an ONFI channel number is calculated according to the target physical address and a preset mapping function; the ONFI channel number is written into a high-bit scheduling field, and the high-bit scheduling field and the low-bit physical positioning field are spliced according to a preset address structure to obtain a physical medium positioning address; the physical medium positioning address is subjected to format conversion to obtain a hardware physical address, and the hardware physical address is sent to a bridge chip, so that the bridge chip extracts the ONFI channel number and forwards the ONFI channel number to an operation controller; and the operation controller is used for executing data read-write; wherein the high-bit scheduling field has the same bit offset in the physical medium positioning address and the hardware physical address.

Description

Technical Field

[0001] This application belongs to the field of memory technology, specifically relating to a data read / write method and a data read / write system. Background Technology

[0002] In the enterprise-grade solid-state drive (SSD) field, a three-layer controller architecture is commonly used: the SSD controller chip is responsible for managing the flash translation layer (FTL), the operation controller (OP) is used to execute the underlying physical media operations, and the bridge chip completes signal protocol conversion and command forwarding between the SSD controller chip and the OP controller. Phase-change memory (PCM), as a new generation of non-volatile storage media, has advantages such as direct writing per word line, no block erase limitations, and low latency.

[0003] However, existing NAND flash-based solutions suffer from poor hardware compatibility when applied to PCM. Summary of the Invention

[0004] The purpose of this application is to provide a data read / write method and system that can solve the problem of poor hardware compatibility when NAND Flash is applied to PCM.

[0005] The technical solution adopted by this application to solve its technical problem is: In a first aspect, embodiments of this application provide a data read / write method applied to a main controller chip in a solid-state drive based on phase-change memory (PCM), the method comprising: In response to a read / write request, the target physical address corresponding to the storage unit to be accessed is obtained; the target physical address includes a low-order physical location field. Calculate the ONFI channel number of the Open NAND flash interface based on the target physical address and the preset mapping function; Write the ONFI channel number into the high-order scheduling field, and concatenate the high-order scheduling field and the low-order physical location field according to the preset address structure to obtain the physical medium location address; The physical medium location address is format-converted to obtain a hardware physical address, and the hardware physical address is sent to the bridging chip so that the bridging chip can extract the ONFI channel number and forward it to the operation controller; the operation controller is used to perform data read and write operations. The high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address.

[0006] Secondly, embodiments of this application provide a data read / write method applied to a bridge chip in a PCM-based solid-state drive, the method comprising: Receive the hardware physical address sent by the main control chip; Extract the ONFI channel number and forward it to the operation controller so that the operation controller can perform data read and write operations; The hardware physical address is generated by the main control chip in the following way: In response to a read / write request, the target physical address corresponding to the storage unit to be accessed is obtained; based on the target physical address and a preset mapping function, the ONFI channel number is calculated, the ONFI channel number is written into the high-order scheduling field, and the high-order scheduling field and the low-order physical location field are concatenated according to the preset address structure to obtain the physical media location address; the physical media location address is then converted to obtain the hardware physical address; the target physical address includes the low-order physical location field, and the high-order scheduling field has the same bit offset in both the physical media location address and the hardware physical address.

[0007] Thirdly, embodiments of this application provide a data read / write system applied to a PCM-based solid-state drive, the system comprising a main control chip, a bridge chip, and an operation controller; the main control chip includes: A flash translation layer is used to obtain the target physical address corresponding to the storage unit to be accessed in response to a read / write request; the target physical address includes a low-order physical location field; The backend management module is used to calculate the ONFI channel number based on the target physical address and a preset mapping function; write the ONFI channel number into the high-order scheduling field, and concatenate the high-order scheduling field and the low-order physical location field according to the preset address structure to obtain the physical media location address; perform format conversion on the physical media location address to obtain the hardware physical address, and send the hardware physical address to the bridging chip; The bridging chip is used to extract the ONFI channel number and forward it to the operation controller; The operation controller is used to perform data reading and writing; The high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address.

[0008] The beneficial effects of this application are: In this embodiment, firstly, the ONFI channel number is dynamically calculated using a preset mapping function, transforming the channel allocation logic from explicit encoding by the main controller to implicit derivation of the address field. This simplifies the process of allocating physical addresses and significantly improves channel bandwidth utilization. Secondly, since the ONFI channel number is dynamically generated by the mapping function, different PCM modules with different structures can be seamlessly adapted by switching different mapping functions, eliminating the need to redesign the bridge chip and operation controller, thus greatly reducing hardware upgrade and maintenance costs. Finally, by setting a high-order scheduling field and ensuring that the high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address, the bridge chip can directly extract the ONFI channel number at a fixed position to complete forwarding without parsing address semantics. This eliminates the translation delay of the bridge chip, thereby reducing chip area and power consumption. Attached Figure Description

[0009] Figure 1 This is a flowchart of a data read / write method provided in an embodiment of this application.

[0010] Figure 2 This is a bit field structure diagram of a physical medium location address provided in an embodiment of this application.

[0011] Figure 3 This is a bit field structure diagram of a hardware physical address provided in an embodiment of this application.

[0012] Figure 4 This is a schematic diagram of the dynamic mapping effect of an ONFI channel provided in an embodiment of this application.

[0013] Figure 5 This is a format conversion diagram from physical media location address to hardware physical address provided in an embodiment of this application.

[0014] Figure 6 This is a flowchart of another data read / write method provided in the embodiments of this application.

[0015] Figure 7 This is a block diagram of a data read / write system provided in an embodiment of this application.

[0016] Figure 8 This is a flowchart of an addressing method provided in an embodiment of this application.

[0017] Figure 9 This is a block diagram of a data read / write device provided in an embodiment of this application.

[0018] Figure 10 This is a block diagram of another data read / write device provided in the embodiments of this application.

[0019] Figure 11This is a block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0020] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0021] The following will clearly and completely describe the concept, specific structure, and resulting technical effects of this application in conjunction with embodiments and accompanying drawings, so as to fully understand the purpose, features, and effects of this application. Obviously, the described embodiments are only a part of the embodiments of this application, not all of them. Other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application. Furthermore, all connections / linkages involved in the patent do not simply refer to direct contact between components, but rather to the ability to form a better connection structure by adding or reducing connecting accessories according to specific implementation conditions. The various technical features in this application can be combined interactively without contradicting each other.

[0022] Phase Change Memory (PCM) is a resistive non-volatile memory and is widely recognized as the next-generation mainstream memory alternative. It relies on the reversible phase transition of crystalline and amorphous chalcogenide materials and the difference in resistance to store binary data.

[0023] Solid-state drives (SSDs) are hard drives that use flash memory chips for storage and have no mechanical rotating parts. They are used to replace older mechanical hard drives (HDDs) and are used in computers, laptops, and servers.

[0024] In the enterprise-grade solid-state drive (SSD) field, a three-layer controller architecture is commonly used: the SSD controller chip is responsible for managing the flash translation layer (FTL), the operation controller (OP) is used to execute the underlying physical media operations, and the bridge chip completes signal protocol conversion and command forwarding between the SSD controller chip and the OP controller. Phase-change memory (PCM), as a new generation of non-volatile storage media, has advantages such as direct writing per word line, no block erase limitations, and low latency.

[0025] The existing physical addressing scheme based on NAND Flash (a four-level structure of Die / Plane / Block / Page) has the following technical problems when applied to PCM.

[0026] 1. Address space redundancy. PCM uses a fixed-size page as the smallest addressable unit and does not have Block and LUN levels. However, existing schemes still allocate address widths for these levels (a Block usually occupies 14 to 16 bits), resulting in wasted address space and redundant FTL mapping logic.

[0027] 2. The bridging chip becomes a bottleneck. In existing solutions, the logical address generated by the SSD controller needs to be translated into a physical address format recognizable by the OP controller by the bridging chip. This translation process introduces additional latency and increases hardware complexity.

[0028] 3. Insufficient utilization of channel parallelism. In the existing solution, the ONFI (Open NAND Flash Interface) channel number is statically encoded as a fixed field in the address, which cannot automatically optimize the distribution of data among channels according to the physical topology (number of channels, number of ranks) of PCM, thus limiting the utilization of parallel bandwidth.

[0029] 4. Poor hardware adaptability. The address structure is bound to specific hardware specifications. When the number of channels or the number of ranks in the PCM module changes, the address resolution logic needs to be redesigned.

[0030] To address the aforementioned problems, this application provides a data reading and writing method and a data reading and writing system. The data reading and writing method provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0031] Figure 1 This is a flowchart of a data read / write method provided in an embodiment of this application. See also... Figure 1 This method is applied to the controller chip in a PCM-based solid-state drive, and includes the following steps.

[0032] Step 101: In response to the read / write request, obtain the target physical address corresponding to the storage unit to be accessed.

[0033] In this embodiment of the application, the target physical address includes a low-order physical location field.

[0034] In some embodiments, the target physical address can be a 64-bit physical address allocated by the master control chip FTL, which includes the PCM particle number, Rank, word line and page address, and is used to uniquely identify the physical storage location in the phase change memory for this write operation.

[0035] In some embodiments, the low-order physical location field occupies 28 bits, and the low-order physical location field from low to high is as follows: a 12-bit page address field, a 13-bit word line address field, a 2-bit Rank identifier field, and a 1-bit PCM parallel channel identifier field; the 28-bit encoding space corresponds one-to-one with the physical storage units of the phase-change memory, and there is no invalid address encoding without a corresponding physical unit.

[0036] In some embodiments, step 101 may include: the main control chip receiving a read / write request sent by the host, obtaining the logical block address (LBA) carried in the read / write request, and performing address mapping through FTL to obtain the target physical address of the memory cell to be accessed.

[0037] For example, the host sends a read / write command, which includes the starting logical block address (LBA Start) and length. It then queries the free physical page management table (FTL) to obtain the physical coordinates of the memory cell to be accessed, including the PCM parallel channel identifier field (pcm_ch), the rank identifier field (rank), the word line address field (row), and the page address field (page). This target physical address uniquely identifies the physical storage location within the phase-change memory and serves as an input parameter for subsequent calculation of the ONFI channel number.

[0038] Step 102: Calculate the ONFI channel number of the Open NAND gate flash interface based on the target physical address and the preset mapping function.

[0039] In this embodiment, the ONFI channel is the physical channel between the solid-state drive controller chip and the PCM storage chip. The ONFI channel number is used to identify which specific ONFI channel among multiple ONFI channels, and the value of the ONFI channel number ranges from 0 to N. 1, N is the total number of ONFI channels.

[0040] For example, an enterprise-grade SSD controller chip includes 8 ONFI channels. Each channel is connected to one or more storage chips through an independent physical connection. The ONFI channels are numbered ONFIChannel0 to Channel7.

[0041] In some embodiments, the ONFI channel number is dynamically calculated based on the physical address field using a mapping function, and is extracted by the bridging chip for channel routing of commands and data.

[0042] For example, the ONFI channel number is represented by onfi_ch, and the preset mapping function is a configurable mapping function F. The ONFI channel number can be dynamically calculated using the formula: onfi_ch=F(pcm_ch,rank,page).

[0043] In some embodiments, the main control chip includes a back-end management module, and the mapping function is stored in the configurable register of the back-end management module. Different mapping functions are switched in response to changes in the number of channels or the number of ranks of the PCM module.

[0044] For example, the mapping function supports configuration switching of 1 to 16 PCM parallel channels and 1 to 4 Ranks. When switching, only the mapping function needs to be updated, without modifying the hardware logic of the bridge chip and the operation controller.

[0045] It should be noted that when the mapping function supports more than two PCM parallel channels, the bit width of the PCM parallel channel identifier field needs to be expanded accordingly. In this embodiment, for ease of description, the scenario with two PCM parallel channels, that is, a 1-bit PCM parallel channel identifier field, is used for illustration.

[0046] Step 103: Write the ONFI channel number into the high-order scheduling field, and concatenate the high-order scheduling field and the low-order physical location field according to the preset address structure to obtain the physical media location address.

[0047] In this embodiment, the high-order scheduling field is a fixed bit field located in the high-order region of the physical medium location address. It is used to carry scheduling control information for data transmission and is not used to identify the physical location of the PCM storage unit.

[0048] In this embodiment, the low-order physical location field is a fixed bit field located in the low-order region of the physical medium location address, used to uniquely identify the physical storage unit in the phase-change memory.

[0049] In some embodiments, the physical media location address adopts a 64-bit flat structure, including a low-order physical location field and a high-order scheduling field. The high-order scheduling field is located in the high-order region of the address and includes the ONFI channel number and reservation interval field. The low-order physical location region consists of the PCM parallel channel identifier field, the Rank identifier field, the word line address field, and the page address field.

[0050] For example, the preset address structure includes the following fields from least significant bit to most significant bit: page field (page offset), row field (word line address), rank field (rank identifier), and pcm_ch field (PCM parallel channel identifier). These four fields constitute the complete physical media location address, occupying 12 bits, 13 bits, 2 bits, and 1 bit respectively, for a total of 28 bits.

[0051] In some embodiments, after calculating the ONFI channel number according to a preset mapping function, the value is written to a fixed offset position in the high-order scheduling field.

[0052] Step 104: Convert the physical medium location address to obtain the hardware physical address, and send the hardware physical address to the bridging chip so that the bridging chip can extract the ONFI channel number and forward it to the operation controller; the operation controller is used to perform data read and write.

[0053] The high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address.

[0054] In some embodiments, the high-order scheduling field is located above the low-order physical location field. In order to ensure that the bridging chip can complete the routing without parsing the address semantics, the high-order scheduling field is isolated by inserting a reserved interval field to ensure that the bit offset position of onfi_ch 66 remains fixed during the process of converting the physical medium location address to the hardware physical address.

[0055] In some embodiments, the bridging chip directly extracts the fixed position of the high-order scheduling field through combinational logic to obtain the ONFI channel number, thereby forwarding the address information and data to the operation controller. This design decouples storage addressing (low-order bits) from transmission scheduling (high-order bits), allowing the same address structure to be adapted to PCM modules with different numbers of channels through a switching mapping function.

[0056] The above technical solution dynamically calculates the ONFI channel number using a preset mapping function, transforming the channel allocation logic from explicit encoding by the main controller to implicit derivation from the address field. This simplifies the process of allocating physical addresses and significantly improves channel bandwidth utilization. Secondly, since the ONFI channel number is dynamically generated by the mapping function, different PCM modules with different structures can be seamlessly adapted by switching different mapping functions, eliminating the need to redesign the bridge chip and operation controller, thus greatly reducing hardware upgrade and maintenance costs. Finally, by setting a high-order scheduling field and ensuring that the high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address, the bridge chip can directly extract the ONFI channel number at a fixed position to complete forwarding without parsing address semantics. This eliminates the translation delay of the bridge chip, thereby reducing chip area and power consumption.

[0057] In some embodiments, prior to step 101, the above data read / write method may further include: defining the address structure of the physical medium location address and the hardware physical address.

[0058] The low-order physical location field includes at least the PCM parallel channel identifier field, the Rank identifier field, the page address field, and the word line address field; the high-order scheduling field has a reserved interval field to separate the low-order physical location field from the bit field where the ONFI channel number is located.

[0059] In this embodiment, the PCM parallel channel identifier field can be the PCM parallel channel identifier field corresponding to the PCM particle, used to identify the PCM storage particle or physical channel group to which the storage unit to be accessed belongs. In a system with multiple PCM particles, the pcm_ch field serves as a physical isolation boundary, used to isolate access paths between different particles.

[0060] In this embodiment, the Rank identifier field (rank) is used to identify different Ranks (logical memory blocks) under the same PCM particle, supporting multi-Rank interleaved access.

[0061] In this embodiment, the row field is used to locate the word line of the PCM, and the page field is used to locate the specific page offset within the word line.

[0062] In one possible implementation, the physical media location address is in 64-bit logical address format, and the low-order physical location field does not include the Block and LUN fields.

[0063] In one possible implementation, the low-order physical location field occupies 28 bits. The low-order physical location field, from the least significant bit to the most significant bit, consists of: a 12-bit page address field, a 13-bit word line address field, a 2-bit Rank identifier field, and a 1-bit PCM parallel channel identifier field. The 28-bit encoding space corresponds one-to-one with the physical storage units of the phase-change memory, and there is no invalid address encoding without a corresponding physical unit.

[0064] For example, see Figure 2 The low-order physical location field is represented by a white area, while the high-order scheduling field is represented by a gray area. The low-order physical location field includes: page61 (12 bits) representing the page offset; row62 (13 bits) representing the word line address; rank63 (2 bits) representing the rank identifier; and pcm_ch64 (1 bit) representing the PCM parallel channel identifier. The low-order physical location field is used to uniquely identify a specific physical storage unit on the PCM medium.

[0065] It's important to note that in traditional NAND SSDs, NAND Flash-based solid-state drives typically employ a four-level physical address structure: Die / Plane / Block / Page. The physical address includes a Block field (14-16 bits) and a LUN field. Due to manufacturing defects, redundant block retention, and erasure limitations of NAND media, the Block number space often contains numerous discontinuous "holes" (invalid codes). When managing physical addresses, the FTL (Functional Layer Transport) must maintain a complex valid address mapping table or skip table to avoid these invalid codes, increasing address resolution latency and management algorithm complexity. In contrast, Phase-Change Memory (PCM) features direct page-by-page writing and no block erase limitations, eliminating the need for Block and LUN levels. All 2^28 codes in the physical location field (page4096 × row8192 × rank4 × pcm_ch2 = 268,435,456 4K pages) correspond one-to-one with physical storage units, with no invalid codes to skip. However, directly applying the traditional NAND address structure to PCM would not only waste valuable address bandwidth but also inherit unnecessary address holes, hindering PCM performance. Therefore, by defining a 28-bit flat physical address field containing only the page, row, rank, and pcm_ch fields, a continuous, hole-free physical address space was achieved.

[0066] In some embodiments, the high-level scheduling field includes a reservation interval field for separating the ONFI channel number from the low-level physical location field.

[0067] In one possible implementation, the high-order scheduling field occupies 36 bits. From low to high, the high-order scheduling field consists of: a 16-bit reserved interval field, a 4-bit fixed offset field, and a 16-bit reserved extension field. The fixed offset field is used to write the ONFI channel number, and the reserved extension field is a reserved high-order field used to ensure that the physical address structure is a fixed 64-bit width and to reserve space for future expansion.

[0068] In one possible implementation, the reserved extension field is always zero and does not participate in address resolution or format conversion. For example, the reserved extension field is a high-order reserved field reserved for future expansion, register alignment, or address bus matching. Its value is always 0, does not affect address semantics, and is used to ensure that the total address width is fixed at 64 bits and is compatible with subsequent capacity or function expansion.

[0069] For example, see Figure 2The high-order scheduling fields include: rsvd065 is 16 bits, indicating a reserved interval field used to separate the low-order physical location field and the high-order scheduling field by padding with 0; onfi_ch66 is 4 bits, indicating the ONFI channel number; and rsvd167 is 16 bits, indicating a reserved extension field.

[0070] In this way, by flattening the physical address of PCM into a continuous encoding space without hierarchy or gaps, the complex address validity judgment is transformed into a simple linear arithmetic operation. This achieves a performance leap from table lookup to direct calculation in core algorithms such as full scan, wear leveling partitioning, and garbage collection target selection, and significantly reduces the algorithm complexity.

[0071] In some embodiments, the hardware physical address includes two parts: a physical location segment and a scheduling segment. The physical location segment is used to copy the original value of the low-order physical location field and fill it with zero-aligned bits, while the scheduling segment is used to carry the ONFI channel number and the copy information of the low-order physical location field.

[0072] In one possible implementation, the physical location segment, from least significant bit to most significant bit, consists of: page field, row field, alignment reserve bit rsvd0, rank field, pcm_ch field, and compatibility reserve bit (rsvd1), where the page, row, rank, and pcm_ch fields are directly mapped from the least significant physical location field.

[0073] In one possible implementation, the scheduling segment, from least significant bit to most significant bit, consists of: a reserved field (rsvd2), rank, a redundant copy of the pcm_ch field, and an onfi_ch field located at a fixed bit offset. The onfi_ch field occupies the same bit offset in the higher-order scheduling field and the scheduling segment, allowing the bridging chip to extract and select the target ONFI channel through combinational logic.

[0074] In one possible implementation, the physical location segment is the lower 32 bits of the hardware physical address, and the scheduling segment is the higher 16 bits of the hardware physical address.

[0075] For example, see Figure 3 ADDR0 (physical location segment) is the lower 32-bit field, including the page, row, rank, and pcm_ch fields; therefore, ADDR0 includes... Figure 2All low-order physical location fields in ADDR0. A portion of the reserved interval field (rsvd0) is also filled into the compatibility reserved bit (rsvd1) in ADDR0 to ensure the alignment of physical location information in the hardware bus. ADDR1 (scheduling segment) is a high 16-bit field, including the onfi_ch field (ONFI channel number) and redundant copies of the page, row, rank, and pcm_ch fields; ADDR1 forces onfi_ch to fall on global bits [44:47] through prep bits (rsvd2). It can be seen that the ONFI channel number is located at bits 44 to 47 in both the physical media location address and the hardware physical address. The onfi_ch field in the physical media location address (pba_pcm_t) is consistent with the onfi_ch field in the hardware physical address (pcm_addr_t) in terms of bit offset, thereby achieving bit alignment between the physical media location address and the hardware physical address.

[0076] In some embodiments, before step 101, the method further includes: setting the block address width in the storage command engine register of the operation controller to zero and setting the logic unit address width to zero; setting the register width configuration field to the total width of the physical location segment in the hardware physical address.

[0077] In this embodiment, the register bit width configuration field (page_addr_width) is used to specify the total bit width occupied by the physical location segment in the hardware physical address, so that O The P controller identifies the physical location segment in the hardware physical address.

[0078] In one possible implementation, during the SSD controller chip initialization phase, the data is sent to the O... The Flash Command Engine (FCE) register of the P controller is written with configuration values, setting block_addr_width and lun_addr_width to 0, and configuring page_addr_width to cover the bit width of all physical address segments in the hardware physical address space, thus making 0 When resolving physical addresses, the P controller ignores the Block and LUN fields and locates PCM storage units only based on the low-order physical location fields (page / row / rank / pcm_ch).

[0079] In some embodiments, the operation controller is used to resolve the physical storage location based on the physical location segment in the hardware physical address.

[0080] In this way, by setting the block address width and logic cell address width to zero, the NAND Flash-specific Block and LUN levels are eliminated, enabling O The P controller can directly parse PCM storage cells based on flattened physical location fields, thereby reducing hardware complexity, improving address efficiency, and enhancing media adaptability.

[0081] In some embodiments, the target physical address includes a PCM parallel channel identifier field, and step 102 includes steps 1021 and 1022.

[0082] Step 1021: Divide the ONFI channels according to the PCM parallel channel identifier field to obtain multiple channel groups; Step 1022: Interleave and allocate the channel numbers within each channel group according to the low-order bits of the page address to obtain the ONFI channel numbers.

[0083] In this embodiment, the channel groups corresponding to different PCM parallel channel identifier fields do not overlap.

[0084] In this embodiment, the PCM parallel channel identifier field (pcm_ch) is a bit field in the target physical address used to identify the ownership of the phase-change memory chip. In a system with multiple PCM memory chips, the PCM parallel channel identifier field is used to divide different ONFI channel groups, enabling the mapping function to limit access requests to a specific physical channel range based on the PCM parallel channel identifier field, thereby avoiding access conflicts between different PCM chips and achieving granular-level physical isolation.

[0085] For example, pcm_ch=0 corresponds to channels 0~3, and pcm_ch=1 corresponds to channels 4~7. The ONFI channels are allocated using the following formula.

[0086]

[0087] Where pcm_ch represents the PCM parallel channel identifier field, page represents the page address, N represents the total number of ONFI channels, and pcm_count represents the number of PCM parallel channels in each channel group.

[0088] In some embodiments, step 1022 includes: automatically interleaving and allocating consecutive page commands between different ONFI channels by taking the low-order bits of the page address (page) field as the ONFI channel number within each PCM channel group.

[0089] For example, if page is 0, 4, 8, ..., then the least significant bit is 00; if page is 1, 5, 9, ..., then the least significant bit is 01; if page is 2, 6, 10, ..., then the least significant bit is 10; if page is 3, 7, 11, ..., then the least significant bit is 11. In this way, when the master controller initiates multiple requests at the same time, the addresses are scattered across different channels, avoiding congestion of the ONFI channel caused by continuous page writing. The hardware can perform read and write operations in true parallel, improving data throughput.

[0090] In some other embodiments, step 102 includes step 1023.

[0091] Step 1023: Perform a modulo operation on consecutive page addresses according to the total number of ONFI channels to obtain the ONFI channel number, so that multiple consecutive page addresses are automatically interleaved and allocated to the same number of ONFI channels.

[0092] In one possible implementation, by performing a modulo operation on consecutive page addresses (pages) based on the total number of ONFI channels N, the lower log2(N) bits of the page are directly used as the ONFI channel number, thereby enabling the automatic cyclic interleaving and allocation of multiple consecutive page addresses among N channels.

[0093] In one possible implementation, step 1023 may include: calculating the ONFI channel number by performing a predefined low-order modulo allocation formula on consecutive page addresses. The predefined low-order modulo allocation formula includes: onfi_ch = page & (N 1).

[0094] For example, see Figure 4 Taking a typical configuration of single PCM channel + single Rank + 8 ONFI channels as an example, the implementation process of page interleaving allocation is as follows.

[0095] Mapping formula: onfi_ch = page & 7 (take the lower 3 bits of the page field) Working principle: The FTL layer allocates pba_pcm_t addresses sequentially for host write requests, with the page field incrementing from 0. The backend management module performs a page&7 operation on each address to obtain the channel number from 0 to 7. Since the page is a continuously incrementing integer, the lower 3 bits naturally form a cyclic sequence of 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, 2,... thus enabling eight consecutive page commands to be automatically distributed across eight different ONFI channels for parallel execution.

[0096] Taking 8 channels as an example, the channel allocation of consecutive pages within the same PU is as follows: Page address | Page & 7 | Assigned to ONFI channel ---------|----------|------------- 0 | 0 | Channel 0 1 | 1 | Channel 1 2 | 2 | Channel 2 3 | 3 | Channel 3 4 | 4 | Channel 4 5 | 5 | Channel 5 6 | 6 | Channel 6 7 | 7 | Channel 7 8 | 0 | Channel 0 (New round of interlacing) 9 | 1 | Channel 1 ... | ... | ... Using the above method, the FTL layer only needs to allocate page addresses sequentially and incrementally, without maintaining a channel state table or performing load balancing scheduling. The interleaving effect is automatically guaranteed by the mathematical properties of bit operations. For 4096 pages (12-bit page field) within the same row, each ONFI channel evenly distributes the operations of 4096 / 8=512 pages, achieving ideal channel bandwidth balance.

[0097] In one possible implementation, under a dual PCM channel configuration, the interleaving granularity becomes 4 (page & 3), with each PCM physical channel occupying 4 ONFI channels exclusively. Groups are isolated through the pcm_ch field to avoid interference between commands from different PCM granules.

[0098] In this way, when the master controller initiates multiple requests at the same time, the addresses are scattered across different channels, avoiding congestion of the ONFI channel caused by continuous page writing. The hardware can perform read and write operations in true parallel, improving data throughput.

[0099] In some embodiments, step 103 includes: Step 1031: Write the ONFI channel number into the fixed offset field in the high-order scheduling field; Step 1032: Concatenate the high-order scheduling field and the low-order physical location field according to the address structure to obtain the physical medium location address; The low-level physical location field includes at least the PCM parallel channel identifier field, Rank identifier field, page address field, and word line address field corresponding to the PCM particle; the high-level scheduling field includes a reservation interval field, which is used to separate the ONFI channel number from the low-level physical location field.

[0100] In the embodiments of this application, the fixed offset field can be a bit range whose position in the address structure remains unchanged.

[0101] For example, see Figure 2 The fixed offset field can be bit[44:47].

[0102] In some embodiments, step 104 includes: Step 1041: During the process of converting the physical medium location address to the hardware physical address, the low-order physical location field is rearranged in terms of bit position without numerical calculation transformation. Step 1042: Send the hardware physical address to the bridging chip so that the bridging chip can extract the ONFI channel number through combinational logic circuits and forward the hardware physical address to the operation controller according to the preset packet sub-rules based on the ONFI channel number.

[0103] In one possible implementation, forwarding the hardware physical address to the operation controller according to the ONFI channel number and a preset packet sub-rule may include: forwarding the physical location segment and the scheduling segment to the operation controller in sequence according to the ONFI channel number.

[0104] In one possible implementation, read / write commands and hardware physical addresses are forwarded to the operation controller according to a preset packet splitting rule based on the ONFI channel number. For example, the preset packet splitting order could be to first send ADDR0 along with the read / write command, and then send ADDR1.

[0105] In one possible implementation, step 1041 may include: during the process of converting the physical medium location address to the hardware physical address, only the bit positions of the field values ​​of the low-order physical location field in the hardware physical address are rearranged, and no arithmetic operations, logical operations, or lookup table conversions are performed on the values ​​of the low-order physical location field.

[0106] For example, the low-order physical location field is rearranged in bit position without numerical calculation transformation as shown below.

[0107] 1. Clear the target address pcm_addr_t=0; 2. Copy the physical location field to ADDR0 (lower 32 bits): pcm_addr_t.page = pba_pcm_t.page (12-bit, value unchanged, target bit[0:11]); pcm_addr_t.row = pba_pcm_t.row (13 bits, value unchanged, target bits[12:24]); pcm_addr_t.rank=pba_pcm_t.rank(2 bits, value remains unchanged, target bits[26:27]); pcm_addr_t.pcm_ch=pba_pcm_t.pcm_ch(1 bit, value unchanged, target bit

[28] ); pcm_addr_t.rsvd0=0 (1-bit alignment padding, bit

[25] ); pcm_addr_t.rsvd1=0 (3-bit plane compatibility reserved, bit[29:31]) 3. Fill in the replica field and channel number of ADDR1 (high 16 bits): pcm_addr_t.rsvd2=0 (8-bit padding, bit[32:39]); pcm_addr_t.rank_high = pba_pcm_t.rank(2-bit copy, bit[40:41]); pcm_addr_t.pcm_ch_high=pba_pcm_t.pcm_ch (2-bit copy, bit[42:43]); pcm_addr_t.onfi_ch=F(pcm_ch,rank,page) (4 bits, dynamically calculated value, bit[44:47]).

[0108] Among them, rank_high and pcm_ch_high are redundant copies of the physical location field, used to simplify O in specific operating modes. The P controller's resolution of physical addresses does not affect address semantics.

[0109] For example, see Figure 5 "Direct mapping" refers to rearranging the bit positions of the low-order physical location field without performing numerical calculations or transformations. While directly mapping to ADDR0, pcm_ch and rank also serve as input parameters to the mapping function F. The calculation result of mapping function F is written to the onfi_ch field at a specific location in the hardware physical address. The bridge chip only needs to read the onfi_ch field according to a fixed physical address format to obtain the channel number, thus achieving separation between software logic and hardware implementation.

[0110] In this way, by rearranging the bit positions of the low-order physical location field without performing numerical calculations, not only is a deterministic conversion from FTL address to hardware address achieved, but also the separation of software logic and hardware implementation is realized.

[0111] Figure 6 This is a flowchart of a data read / write method provided in an embodiment of this application. See also... Figure 6 This method is applied to a bridge chip in a PCM-based solid-state drive, and includes the following steps.

[0112] Step 201: Receive the hardware physical address sent by the main control chip.

[0113] The hardware physical address is generated by the main control chip in the following way: In response to a read / write request, the target physical address corresponding to the storage unit to be accessed is obtained; based on the target physical address and a preset mapping function, the ONFI channel number is calculated, the ONFI channel number is written into the high-order scheduling field, and the high-order scheduling field and the low-order physical location field are concatenated according to the preset address structure to obtain the physical media location address; the physical media location address is then converted to obtain the hardware physical address; the target physical address includes the low-order physical location field, and the high-order scheduling field has the same bit offset in both the physical media location address and the hardware physical address.

[0114] Step 202: Extract the ONFI channel number and forward it to the operation controller so that the operation controller can perform data read and write operations.

[0115] In some embodiments, step 202 includes steps 2021 to 2022.

[0116] Step 2021: Extract the ONFI channel number using combinational logic circuits.

[0117] Step 2022: Based on the ONFI channel number, forward the hardware physical address to the operation controller according to the preset packet sub-rules, so that the operation controller routes the read / write command to the corresponding ONFI channel according to the ONFI channel number, parses the low-order physical location field to locate the PCM physical unit, and generates the timing signal to drive the PCM medium.

[0118] In one possible implementation, step 2021 may include: directly outputting the 4-bit field located at a fixed bit offset in the scheduling segment (ADDR1) of the hardware physical address as the ONFI channel number through combinational logic, without involving clock control, table lookup, or calculation, thereby achieving zero-latency channel selection.

[0119] In one possible implementation, step 2022 may include: sequentially issuing read / write commands, ADDR0, and ADDR1; and extracting the ONFI channel number from the field at a fixed bit offset in ADDR1 to select the target channel, without performing a translation operation on the address format. The translation operation may include conversion or table lookup.

[0120] In one possible implementation, the FCE engine of the operation controller routes read / write commands to the target ONFI channel based on the ONFI channel number; and parses the page, row, rank, and pcm_ch fields of the hardware physical address based on the preset bit width of all physical location fields (page_addr_width) to generate precise timing signals adapted to the phase-change memory medium to complete the data read or write operation.

[0121] In this way, since the ONFI channel number maintains the same bit offset in the physical medium location address and the hardware physical address, the bridging chip can directly obtain the channel number through pure combinational logic without performing address resolution or table lookup operations, thereby reducing the bridging chip area and access latency.

[0122] In summary, in this embodiment, the ONFI channel number is dynamically calculated using a preset mapping function, transforming the channel allocation logic from explicit encoding by the main controller to implicit derivation of the address field. This simplifies the physical address allocation process and significantly improves channel bandwidth utilization. Secondly, since the ONFI channel number is dynamically generated by the mapping function, different PCM modules with different structures can be seamlessly adapted by switching different mapping functions, eliminating the need to redesign the bridge chip and operation controller, thus greatly reducing hardware upgrade and maintenance costs. Finally, by setting a high-order scheduling field and ensuring that the high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address, the bridge chip can directly extract the ONFI channel number at a fixed position to complete forwarding without parsing address semantics, eliminating the translation delay of the bridge chip and thus reducing chip area and power consumption.

[0123] Figure 7 This is a block diagram of a data read / write system provided in an embodiment of this application. See also... Figure 7 This system is applied to PCM-based solid-state drives and includes a main controller chip 10, a bridge chip 20, and an operation controller; the main controller chip 10 includes: Flash translation layer 11 is used to obtain the target physical address corresponding to the storage unit to be accessed in response to read / write requests; the target physical address includes a low-order physical location field; The backend management module 12 is used to calculate the ONFI channel number based on the target physical address and the preset mapping function; write the ONFI channel number into the high-order scheduling field, and concatenate the high-order scheduling field and the low-order physical location field according to the preset address structure to obtain the physical media location address; convert the format of the physical media location address to obtain the hardware physical address, and send the hardware physical address to the bridge chip 20. Bridge chip 20 is used to extract the ONFI channel number and forward it to operation controller 30; The operation controller 30 is used to perform data reading and writing; Among them, the high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address.

[0124] In some embodiments, the SSD controller chip and the bridge chip are physically connected via an on-chip interconnect bus or a high-speed serial interface, which is used to send the hardware physical address and access command to the bridge chip after the controller chip completes the address construction.

[0125] In some embodiments, the SSD controller chip is coupled to the bridge chip through an interconnect interface, which splits the hardware physical address into the lower 32 bits ADDR0 and the higher 16 bits ADDR1 and sends it to the bridge chip. The bridge chip extracts the ONFI channel number based on the fixed bit offset and completes the routing forwarding.

[0126] In some embodiments, the SSD controller chip and the bridge chip are connected via a chip-level interconnect interface. The controller chip, after constructing and formatting the physical address internally, sends the hardware physical address and access commands to the bridge chip, which then forwards them to the O (Operation Controller) chip in a bit-aligned, transparent manner. P controller.

[0127] In some embodiments, the back-end management module is not an independent physical chip, but a logical function module integrated inside the SSD controller chip 10. It is used to perform dynamic mapping of the ONFI channel and address format conversion inside the controller, thereby reducing the implementation complexity of the bridge chip.

[0128] In some embodiments, the bridging chip includes combinational logic circuitry configured to extract an ONFI channel number field located at a fixed bit offset from the ADDR1 field of the hardware physical address format, and to directly use the channel number to select a target ONFI channel, wherein the combinational logic circuitry does not contain an address mapping table, an arithmetic logic unit, or a timing state machine.

[0129] In some embodiments, the FCE engine of the operation controller 30 routes read / write commands to the target ONFI channel based on the ONFI channel number; and parses the page, row, rank, and pcm_ch fields of the hardware physical address based on the preset bit width of all physical location fields (page_addr_width) to generate precise timing signals adapted to the phase-change memory medium to complete the data read or write operation.

[0130] In summary, in this embodiment, the ONFI channel number is dynamically calculated using a preset mapping function, transforming the channel allocation logic from explicit encoding by the main controller to implicit derivation of the address field. This simplifies the physical address allocation process and significantly improves channel bandwidth utilization. Secondly, since the ONFI channel number is dynamically generated by the mapping function, different PCM modules with different structures can be seamlessly adapted by switching different mapping functions, eliminating the need to redesign the bridge chip and operation controller, thus greatly reducing hardware upgrade and maintenance costs. Finally, by setting a high-order scheduling field and ensuring that the high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address, the bridge chip can directly extract the ONFI channel number at a fixed position to complete forwarding without parsing address semantics, eliminating the translation delay of the bridge chip and thus reducing chip area and power consumption.

[0131] Figure 8 This is a flowchart of an addressing method provided in an embodiment of this application. See also... Figure 8 This method is applied to Figure 7 The data read / write system shown includes the following steps.

[0132] Step 301: Define the address structure of the physical medium location address and the hardware physical address.

[0133] Step 302: Set the block address width in the storage command engine register of the operation controller to zero, and set the logic unit address width to zero.

[0134] Step 303: In response to the read / write request, the flash translation layer obtains the target physical address corresponding to the storage unit to be accessed.

[0135] Step 304: The backend management module calculates the ONFI channel number based on the target physical address and the preset mapping function.

[0136] Step 305: The backend management module writes the ONFI channel number into the fixed offset field in the high-order scheduling field.

[0137] Step 306: The backend management module concatenates the high-order scheduling field and the low-order physical location field according to the address structure to obtain the physical media location address.

[0138] Step 307: During the process of converting the physical medium location address to the hardware physical address, the backend management module rearranges the bit positions of the low-order physical location field without performing numerical calculations or transformations.

[0139] Step 308: The backend management module sends the hardware physical address to the bridging chip.

[0140] Step 309: The bridging chip extracts the ONFI channel number through combinational logic circuits and forwards the hardware physical address to the operation controller according to the packet sub-scheme rules based on the ONFI channel number.

[0141] Step 310: The operation controller routes the read / write command to the corresponding ONFI channel according to the ONFI channel number.

[0142] Step 311: The operation controller parses the low-order physical positioning field to locate the PCM physical unit and generates a timing signal to drive the PCM medium.

[0143] In summary, in this embodiment, firstly, the ONFI channel number occupies the same fixed position in both address formats. The bridging chip only needs to extract the corresponding field for routing and packet forwarding, simplifying the hardware logic from table lookup translation to combinational logic extraction, significantly reducing translation latency. Secondly, the ONFI channel number is dynamically calculated from the address field by the mapping function. The FTL layer of the SSD controller chip does not need to be aware of the channel topology to achieve hardware-level load balancing, significantly improving bandwidth utilization compared to the fixed encoding scheme. Thirdly, the defined physical location field directly addresses all PCM storage units, and configuring block_addr_width to 0 eliminates Block / LUN holes. FTL mapping table entries can be directly used as physical offsets. Finally, the same address structure can be adapted to PCM modules with different channel / rank numbers by switching the mapping function, without requiring modification to the bridging chip and OP controller.

[0144] Figure 9 This is a block diagram of a data read / write device provided in an embodiment of this application, such as... Figure 9 As shown, the data read / write device 400 is used in the main control chip of a solid-state drive based on phase-change memory (PCM), and includes the following modules.

[0145] Address acquisition module 401 is used to obtain the target physical address corresponding to the storage unit to be accessed in response to a read / write request; the target physical address includes a low-order physical location field; The channel mapping module 402 is used to calculate the ONFI channel number of the open NAND flash interface based on the target physical address and the preset mapping function. The field writing module 403 is used to write the ONFI channel number into the high-order scheduling field and to concatenate the high-order scheduling field and the low-order physical location field according to the preset address structure to obtain the physical media location address. Address sending module 404 is used to convert the physical medium location address into a format to obtain a hardware physical address, and send the hardware physical address to the bridging chip so that the bridging chip can extract the ONFI channel number and forward it to the operation controller; the operation controller is used to perform data read and write. Among them, the high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address.

[0146] Optionally, the target physical address includes a PCM parallel channel identifier field, and the channel mapping module 402 is specifically used for: The ONFI channels are divided according to the PCM parallel channel identifier field to obtain multiple channel groups; the channel groups corresponding to different PCM parallel channel identifier fields do not overlap. Within each channel group, the channel numbers are interleaved and allocated according to the low-order bits of the page address to obtain the ONFI channel number.

[0147] Optionally, the channel mapping module 402 is specifically used for: The consecutive page addresses are moduloed according to the total number of ONFI channels to obtain the ONFI channel number, so that multiple consecutive page addresses are automatically interleaved and allocated to the same number of ONFI channels.

[0148] Optionally, the field writing module 403 is specifically used for: Write the ONFI channel number into the fixed offset field of the high-order scheduling field; By concatenating the high-order scheduling field and the low-order physical location field according to the address structure, the physical medium location address is obtained.

[0149] Optionally, the address sending module 404 is specifically used for: During the process of converting the physical medium location address to the hardware physical address, the low-order physical location field is rearranged in bit position without numerical calculation transformation. The hardware physical address is sent to the bridging chip, so that the bridging chip can extract the ONFI channel number through combinational logic circuits and forward the hardware physical address to the operation controller according to the preset packet sub-rules based on the ONFI channel number.

[0150] Optionally, the data read / write device 400 further includes a configuration module for: Set the block address width in the storage command engine register of the operation controller to zero, and set the logic unit address width to zero; Set the register bit width configuration field to the total bit width of the physical location segment in the hardware physical address.

[0151] Optionally, the low-order physical location field includes at least the PCM parallel channel identifier field, the Rank identifier field, the page address field, and the word line address field; the high-order scheduling field includes a reservation interval field, used to separate the ONFI channel number from the low-order physical location field.

[0152] Optionally, the low-order physical location field occupies 28 bits, and the low-order physical location field from low to high is as follows: a 12-bit page address field, a 13-bit word line address field, a 2-bit Rank identifier field, and a 1-bit PCM parallel channel identifier field; the 28-bit encoding space corresponds one-to-one with the physical storage units of the phase-change memory, and there is no invalid address encoding without a corresponding physical unit.

[0153] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0154] Figure 10 This is a block diagram of another data read / write device provided in the embodiments of this application, such as... Figure 10As shown, the data read / write device 500 is used in a bridge chip in a PCM-based solid-state drive and includes the following modules.

[0155] Address receiving module 501 is used to receive the hardware physical address sent by the main control chip; The data forwarding module 502 is used to extract the ONFI channel number and forward it to the operation controller so that the operation controller can perform data read and write operations. The hardware physical address is generated by the main control chip in the following way: In response to a read / write request, the target physical address corresponding to the storage unit to be accessed is obtained; based on the target physical address and a preset mapping function, the ONFI channel number is calculated, the ONFI channel number is written into the high-order scheduling field, and the high-order scheduling field and the low-order physical location field are concatenated according to the preset address structure to obtain the physical media location address; the physical media location address is then converted to obtain the hardware physical address; the target physical address includes the low-order physical location field, and the high-order scheduling field has the same bit offset in both the physical media location address and the hardware physical address.

[0156] As the device embodiment is basically similar to the method embodiment, the description is relatively simple, and relevant parts can be found in the description of the method embodiment.

[0157] Figure 11 This is a structural block diagram of an electronic device according to an exemplary embodiment. For example... Figure 11 As shown, the electronic device includes: a processor, a memory, a communication interface, and a communication bus. The processor, the memory, and the communication interface communicate with each other through the communication bus. The memory is used to store at least one executable instruction, which causes the processor to perform the steps of the data read / write method of the aforementioned embodiment.

[0158] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory including instructions that can be executed by a processor of an electronic device to perform the above-described method. For example, the non-transitory computer-readable storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0159] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above-described data read / write method embodiments and achieve the same technical effect. To avoid repetition, these will not be described again here.

[0160] This application also provides a computer program product, including a computer program and a data read / write method implemented when the computer program is executed by a processor.

[0161] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar parts between the various embodiments can be referred to each other.

[0162] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus, or computer program products. Therefore, embodiments of this application can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of this application can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0163] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks of the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0164] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a predictive manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0165] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0166] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0167] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0168] The above is a detailed description of the preferred embodiments of this application. However, the invention of this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A data read / write method, characterized in that, A controller chip used in a solid-state drive based on phase-change memory (PCM), the method comprising: In response to a read / write request, the target physical address corresponding to the storage unit to be accessed is obtained; the target physical address includes a low-order physical location field. Calculate the ONFI channel number of the Open NAND flash interface based on the target physical address and the preset mapping function; Write the ONFI channel number into the high-order scheduling field, and concatenate the high-order scheduling field and the low-order physical location field according to the preset address structure to obtain the physical medium location address; The physical medium location address is format-converted to obtain a hardware physical address, and the hardware physical address is sent to the bridging chip so that the bridging chip can extract the ONFI channel number and forward it to the operation controller; the operation controller is used to perform data read and write operations. The high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address.

2. The method according to claim 1, characterized in that, The target physical address includes a PCM parallel channel identifier field. The calculation of the Open NAND flash interface (ONFI) channel number based on the target physical address and a preset mapping function includes: The ONFI channels are divided according to the PCM parallel channel identifier field to obtain multiple channel groups; the channel groups corresponding to different PCM parallel channel identifier fields do not overlap. Within each channel group, the channel numbers are interleaved and allocated according to the low-order bits of the page address to obtain the ONFI channel numbers.

3. The method according to claim 1, characterized in that, The step of calculating the ONFI channel number of the Open NAND flash interface based on the target physical address and a preset mapping function includes: The consecutive page addresses are moduloed according to the total number of ONFI channels to obtain the ONFI channel number, so that multiple consecutive page addresses are automatically interleaved and allocated to the same number of ONFI channels.

4. The method according to claim 1, characterized in that, The step of writing the ONFI channel number into the high-order scheduling field and concatenating the high-order scheduling field and the low-order physical location field according to a preset address structure to obtain the physical media location address includes: Write the ONFI channel number into the fixed offset field of the high-order scheduling field; By concatenating the high-order scheduling field and the low-order physical location field according to the address structure, the physical medium location address is obtained.

5. The method according to claim 1, characterized in that, The step of converting the physical medium location address to obtain a hardware physical address and sending the hardware physical address to the bridging chip, so that the bridging chip can extract the ONFI channel number and forward it to the operation controller, includes: During the process of converting the physical medium location address to the hardware physical address, the low-order physical location field is rearranged in bit position without numerical calculation transformation. The hardware physical address is sent to the bridging chip, so that the bridging chip can extract the ONFI channel number through combinational logic circuits and forward the hardware physical address to the operation controller according to the preset packet sub-rules based on the ONFI channel number.

6. The method according to claim 1, characterized in that, Before obtaining the target physical address corresponding to the storage unit to be accessed in response to a read / write request, the method further includes: Set the block address width in the storage command engine register of the operation controller to zero, and set the logic unit address width to zero; Set the register bit width configuration field to the total bit width of the physical location segment in the hardware physical address.

7. The method according to claim 1, characterized in that, The low-order physical location field includes at least a PCM parallel channel identifier field, a Rank identifier field, a page address field, and a word line address field; the high-order scheduling field includes a reservation interval field, used to separate the ONFI channel number from the low-order physical location field.

8. The method according to any one of claims 1 to 7, characterized in that, The low-order physical location field occupies 28 bits, and the low-order physical location field consists of the following bits from low to high: a 12-bit page address field, a 13-bit word line address field, a 2-bit Rank identifier field, and a 1-bit PCM parallel channel identifier field. The 28-bit encoding space corresponds one-to-one with the physical storage units of the phase-change memory, and there are no invalid address codes without corresponding physical units.

9. A data read / write method, characterized in that, A bridge chip applied in a PCM-based solid-state drive, the method comprising: Receive the hardware physical address sent by the main control chip; Extract the ONFI channel number and forward it to the operation controller so that the operation controller can perform data read and write operations; The hardware physical address is generated by the main control chip in the following way: In response to a read / write request, the target physical address corresponding to the storage unit to be accessed is obtained; based on the target physical address and a preset mapping function, the ONFI channel number is calculated, the ONFI channel number is written into the high-order scheduling field, and the high-order scheduling field and the low-order physical location field are concatenated according to the preset address structure to obtain the physical media location address; the physical media location address is then converted to obtain the hardware physical address; the target physical address includes the low-order physical location field, and the high-order scheduling field has the same bit offset in both the physical media location address and the hardware physical address.

10. A data read / write system, characterized in that, For use in PCM-based solid-state drives, the system includes a main control chip, a bridge chip, and an operation controller; the main control chip includes: A flash translation layer is used to obtain the target physical address corresponding to the storage unit to be accessed in response to a read / write request; the target physical address includes a low-order physical location field; The backend management module is used to calculate the ONFI channel number based on the target physical address and a preset mapping function; write the ONFI channel number into the high-order scheduling field, and concatenate the high-order scheduling field and the low-order physical location field according to the preset address structure to obtain the physical media location address; perform format conversion on the physical media location address to obtain the hardware physical address, and send the hardware physical address to the bridging chip; The bridging chip is used to extract the ONFI channel number and forward it to the operation controller; The operation controller is used to perform data reading and writing; The high-order scheduling field has the same bit offset in the physical medium location address and the hardware physical address.

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