Multiplexed dual rank memory device and method of storing control and testing thereof

Abstract

The application provides a multiplexing double-row memory device and a storage control and test method thereof, and belongs to the technical field of memory testing. The memory device comprises: a host in communication connection with an MRCD and an MDB, which sends control commands to the MRCD through a CA bus and sends test data and receives data to the MDB; the MRCD receives and analyzes the control commands to generate test mode control signals, which are transmitted to the MDB and control / address commands are transmitted to the DRAM to control the read / write operation of the corresponding physical row; a write configuration unit in the test mode receives the test mode control signals, copies and simultaneously writes the same test data into two physical rows; a read comparison unit receives two read-back data returned by the two physical rows, performs consistency comparison and generates a comparison result. The application independently completes the data path test and consistency comparison to reduce the CPU load.

Description

Technical Field

[0001] This invention relates to the technical field of memory testing, and in particular to a multiplexed dual-row memory device and its storage control and testing method. Background Technology

[0002] Multiplexed Rank Dual Inline Memory Modules (MRDIMMs) enable the host to simultaneously access two physical rows of dynamic random access memory (DRAMs) by setting up multiplexed register clock drivers (register control drivers) and multiplexed data buffers on the module, thereby doubling memory bandwidth. Currently, MRDIMMs have become an important memory solution for bandwidth-sensitive applications such as high-performance computing and artificial intelligence.

[0003] In existing storage systems, the Central Processing Unit (CPU) undertakes most of the storage control and testing tasks, including data path management, training operations, and test mode control. During storage testing, the CPU needs to write test data to memory via the data bus and, after reading it back, perform a software-level comparison of the data returned from different physical rows or different data paths to determine whether data transmission and storage access are normal. This process has the following drawbacks:

[0004] First, the CPU needs to perform a large number of computational operations such as writing, reading, storing, and comparing bit by bit of test data, which leads to excessive CPU load and squeezes out the CPU's computing resources for processing regular business.

[0005] Second, test data needs to be frequently used for data bus transmission. In particular, the complete readback data from both physical rows needs to be transmitted to the CPU, which causes the data bus to be occupied by test data for a long time, resulting in a decrease in system response speed.

[0006] Third, the bit-by-bit comparison process is time-consuming and difficult to complete the judgment synchronously during the data readback process, resulting in low testing efficiency.

[0007] Fourth, in a multiplexed dual-row memory module system, if the CPU uniformly schedules and manages the test tasks of all memory modules, the memory modules cannot execute tests in parallel, and the system scalability is severely limited.

[0008] In view of this, a novel multiplexed dual-row memory device and its storage control and testing method are proposed to solve all or part of the above problems. Summary of the Invention

[0009] To address at least one of the aforementioned problems and deficiencies in the prior art, embodiments of the present invention provide a multiplexed dual-row memory device and its storage control and testing method. By integrating a test mode module within the data buffer, the data buffer can autonomously complete data path control and data consistency comparison between the two physical rows, offloading the storage testing function from the CPU to be executed locally on the multiplexed dual-row memory device, significantly reducing CPU load, lowering data bus occupancy, and improving system response speed. A forced mapping mechanism with different directions is constructed through a first test mode and a second test mode to achieve bidirectional verification of the data path between the two physical rows, improving test coverage and fault location capabilities. A hardware parallel comparison structure is adopted, enabling synchronous comparison during data return, resulting in fast comparison speed and low latency. The technical solution is as follows:

[0010] According to one aspect of the present invention, a multiplexed dual-row memory device is provided, the multiplexed dual-row memory device comprising:

[0011] The host computer communicates with the register control driver and the data buffer, respectively.

[0012] The host sends control commands to the register control driver via the command / address bus, and sends test data to and receives data from the data buffer via the data bus.

[0013] The register control driver receives and parses control commands, generates test mode control signals based on the control commands and passes them to the data buffer, and passes control / address commands to the dynamic random access memory to control the corresponding physical row to perform read and write operations;

[0014] The data buffer is communicatively connected to the first physical row and the second physical row respectively. The data buffer integrates a test mode module, which includes a write configuration unit and a read comparison unit.

[0015] In test mode, the write configuration unit receives the test mode control signal, controls the data write path according to the working mode indicated by the test mode control signal, copies the same test data and writes it to the first physical row and the second physical row at the same time.

[0016] The read comparison unit receives two readback data corresponding to the same test data, returned by the first physical row and the second physical row, performs a consistency comparison on the two readback data, and generates a comparison result;

[0017] The data buffer sends the comparison results back to the host via the data bus.

[0018] According to another aspect of the present invention, a storage control and testing method for a multiplexed dual-row memory device is provided, applicable to the multiplexed dual-row memory device described above. The storage control and testing method includes:

[0019] The host configures test mode parameters to the data buffer through the register control driver. After the test mode parameters are parsed by the register control driver, they are converted into test mode control signals. The data buffer switches to the corresponding working mode according to the test mode control signals.

[0020] The data buffer controls the data write path according to the test mode control signal. In test mode, the same test data is copied and written to the first physical row and the second physical row at the same time.

[0021] The host issues a read request, and the register control driver controls the return data of the first physical row and / or the second physical row according to the read request;

[0022] The data buffer receives the first data returned by the first physical row and the second data returned by the second physical row, performs a consistency comparison on the first data and the second data, and generates a comparison result.

[0023] The data buffer sends the comparison results back to the host via the data bus.

[0024] The multiplexed dual-row memory device and its storage control and testing method provided by the embodiments of the present invention have at least one or a portion of the following advantages:

[0025] (1) By integrating the test mode module inside the data buffer (MDB), the MDB can autonomously complete the data path control of write operations and the data consistency comparison of read operations. This migrates some control and test functions that were originally executed by the host (e.g., CPU) to be executed locally on the multiplexed dual-row memory device (MRDIMM). The CPU does not need to participate in the data comparison process, thereby reducing the CPU load, reducing the data bus occupation, and improving the system response speed. At the same time, in a multi-MRDIMM system, multiple MRDIMMs can be supported to execute tests in parallel, reducing the CPU test management overhead and improving the system scalability.

[0026] (2) By setting three working modes, namely normal mode, first test mode and second test mode, MRDIMM can be flexibly switched between normal access state and test state; in normal mode, MDB maintains transparent transmission and does not affect the correctness and performance of the system's regular business data access.

[0027] (3) In the first test mode, the same first data is written to the first physical row and the second physical row at the same time and the first returned data and the second returned data returned by the two physical rows are compared to see if they are consistent; in the second test mode, the same second data is written to the first physical row and the second physical row at the same time and the third returned data and the fourth returned data returned by the two physical rows are compared to see if they are consistent; through two different directions of forced mapping mechanism, bidirectional verification of the data path between the two physical rows is realized, effectively detecting data inconsistency problems caused by abnormalities of physical rows, data channels or memory itself, and improving test coverage and fault location capability;

[0028] (4) The read comparison unit adopts multiple parallel comparison sub-units, each sub-unit corresponds to a set of data channel inputs, and parallel bit-by-bit comparison is realized through XOR logic gates; the hardware parallel comparison method has no serial path, and the increase in bit width only affects the parallel scale without significantly increasing the critical path delay. Therefore, the comparison can be completed synchronously during the data return process, without the CPU performing additional reading, storage and software operation on the returned data, resulting in high comparison speed and low latency.

[0029] (5) The test mode control signal participates in the logic control as a real-time control signal inside the MDB without address mapping registration, ensuring the immediacy of mode switching and avoiding additional delay caused by register configuration.

[0030] (6) The comparison result is automatically transmitted back to the host via the data bus after the comparison unit completes the comparison. The host does not need to actively poll to know the test completion status, which further reduces CPU overhead.

[0031] (7) The test mode control signal is generated in real time by MRCD according to the test mode start command sent by the host and transmitted to MDB, realizing a three-level collaborative test mode configuration mechanism of host-MRCD-MDB, with a clear configuration process and rapid response;

[0032] (8) In the first test mode, the first comparison operation is performed to generate the first comparison pass result or the first comparison failure result. In the second test mode, the second comparison operation is performed to generate the second comparison pass result or the second comparison failure result. The comparison result clearly indicates whether the test passes or fails, which makes it easy for the host to make a quick judgment.

[0033] (9) The host can send a normal mode configuration command to the MDB through the MRCD to make the MDB exit the test mode and restore the normal working state, ensuring that the system can seamlessly return to normal business operation after the test is completed;

[0034] (10) A complete test process is formed by five core steps: configuration, writing, reading request, comparison, and return. Each step works together to achieve full automation from test mode configuration to comparison result return, without the need for CPU intervention at each stage. Attached Figure Description

[0035] These and / or other aspects and advantages of the present invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:

[0036] Figure 1 This is a system architecture diagram illustrating the storage control and testing method for a multiplexed dual-row memory device according to an embodiment of the present invention.

[0037] Figure 2 This is a schematic diagram of the data path of an MDB under different working modes according to an embodiment of the present invention;

[0038] Figure 3 In order to be in Figure 1 The flowchart shown illustrates the execution steps of a host initiating a complete first test mode under the system architecture shown.

[0039] Figure 4 To combine Figure 1 and Figure 3 A schematic diagram illustrating a specific example of the execution of a multiplexed dual-row memory device in the first test mode. Detailed Implementation

[0040] The technical solution of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention and should not be construed as a limitation thereof.

[0041] The core concept of this invention is to migrate some of the control and testing functions originally executed by the Central Processing Unit (CPU) to a Multiplexed Rank Dual Inline Memory Module (MRDIMM), allowing the MRDIMM to autonomously complete data path selection and testing, realize local writing, local comparison, and result feedback, thereby reducing CPU load, improving system response speed, and facilitating system expansion.

[0042] In test mode, the same test data is forcibly copied by the data buffer (MDB) and written to two physical rows (Rank 0 and Rank 1) at the same time. Then, the two read-back data returned by the two physical rows, which should be exactly the same, are compared at the hardware level to form a forced mapping and a double-write and double-compare mechanism.

[0043] Specifically, in the first test mode, the same first data (R0 data) is written to the first physical row (Rank 0) and the second physical row (Rank 1) at the same time, and the R0 data returned by the two physical rows are compared to see if they are consistent; in the second test mode, the same second data (R1 data) is written to the first physical row and the second physical row at the same time, and the R1 data returned by the two physical rows are compared to see if they are consistent.

[0044] In other words, this invention does not employ the internal memory refresh control or timing optimization structures used in existing technologies. Instead, it uses an external CPU to control a multiplexed data buffer (MDB) via a multiplexed register control driver (MRDIMM Register Control Driver, MRCD) to perform data consistency comparison tests. By decentralizing the test logic to the MDB, this invention enables the MRDIMM to independently complete data path testing, reducing CPU involvement. In multi-MRDIMM systems, this invention can support multiple MRDIMMs executing tests in parallel, thereby reducing CPU test management overhead and improving system scalability.

[0045] See Figure 1 The diagram illustrates the system architecture of the storage control and testing method for a multiplexed dual-row memory device according to an embodiment of the present invention.

[0046] like Figure 1 As shown, the multiplexed dual-row memory device (hereinafter referred to as MRDIMM) of the present invention includes a host (CPU), a multiplexing register control driver (hereinafter referred to as MRCD), and a multiplexing data buffer (hereinafter referred to as MDB). The two physical rows of the Dynamic Random Access Memory (DRAM) are denoted as the first physical row (Rank 0) and the second physical row (Rank 1), respectively.

[0047] The host communicates with both the MRCD and MDB, acting as the initiator of the system architecture and the receiver of test results. The host sends control commands (including test configuration commands) to the MRCD via the Command / Address (CA) bus and interacts with the MDB via the Data (DQ) bus (including sending and receiving test data from the MDB). The host is used to issue control / address signals, send and receive data via the data bus, and also to issue test mode start commands and configure test mode parameters. Test mode parameters instruct the MDB to switch from normal operating state to the corresponding test operating state and determine the mapping direction and comparison method used by the MDB in the test operating state.

[0048] The MRCD, acting as the control path, is responsible for receiving and parsing control commands sent by the host, generating test mode control signals based on these commands and transmitting them to the MDB, as well as transmitting control / address commands to the DRAM to control the corresponding physical bus to perform read and write operations. The MRCD receives and parses control / address commands from the host, coordinating the internal operations of the MDB; it also transmits control / address commands to the DRAM to control the corresponding physical bus to perform read and write operations. The MRCD transmits the host's test mode configuration intent to the MDB and controls the DRAM's physical bus to perform read and write operations. The host configures high-level test mode parameters, which, after being parsed by the MRCD, are converted into lower-level test mode control signals that the MDB can directly use for logic control.

[0049] The MDB, serving as the data path, is the core execution unit of this invention. The MDB is communicatively connected to both the first and second physical queues. Internally, the MDB integrates a test mode module, which includes a write configuration (WR: Test ModeControl) unit and a read comparison (RD: Compare) unit. The MDB receives DQ data from the host and, in test mode, performs forced mapping, data comparison, and comparison result feedback.

[0050] The write configuration unit receives the test mode control signal and controls the data write path according to the working mode indicated by the test mode control signal. The write configuration unit is used to write test mode parameters, start or disable the test mode, control the test mode behavior according to the configuration, and determine which data to output (controlling the MDB data path according to the test mode parameters).

[0051] The read comparison unit is the core component for performing consistency comparisons. In test mode, it does not receive two different sets of test data from different sources, but rather two sets of read-back data after the same test data has been written to the first physical stack and the second physical stack, respectively. The read comparison unit performs parallel consistency comparisons of these two sets of read-back data at the hardware level, without CPU intervention, and generates a signal reflecting the comparison result.

[0052] The DRAM is divided into two physically independent physical rows: Rank 0 and Rank 1. Each row contains a DRAM array and input / output (I / O) logic, and is connected to the MDB via a data channel (e.g., a BL[15:0] bit-width data channel). The signal flow is as follows:

[0053] During a write operation, the host's DQ data enters the MDB's write configuration unit, and the configuration (including normal mode, first test mode and second test mode) determines whether to write separately or force copy to Rank 0 and Rank 1.

[0054] During a read operation, the data returned by Rank 0 and Rank 1 enters the read comparison unit of the MDB for hardware comparison, and the comparison result is then directly transmitted back to the host through the DQ path.

[0055] The first data (hereinafter referred to as R0 data) represents data transmitted via the path corresponding to Rank 0 or configured to be sent to the path corresponding to Rank 0. The second data (hereinafter referred to as R1 data) represents data transmitted via the path corresponding to Rank 1 or configured to be sent to the path corresponding to Rank 1.

[0056] In this invention, R0 data and R1 data are identifiers used to distinguish the source or original ownership of data. In test mode, test data refers to the selected data used for copying and simultaneously writing to two physical rows. For example, in the first test mode, R0 data is the test data; in the second test mode, R1 data is the test data. Therefore, test data and R0 / R1 data are the same data represented in different test scenarios, and they are essentially the same.

[0057] See Figure 2 The diagram illustrates the data path of an MDB in different operating modes according to an embodiment.

[0058] Figure 2 Yes Figure 1 The detailed explanation of the data flow direction of the internal write configuration unit of the MDB under different working modes intuitively expresses the "forced mapping" mechanism of the present invention.

[0059] MDB's operating modes include normal mode, first test mode, and second test mode:

[0060] Normal Mode: In this mode, the MDB is in a transparent transmission state, without changing the original data access relationship. The path is as follows: when the control signal accesses Rank 0, R0 data is directly written to Rank 0; when the control signal accesses Rank 1, R1 data is directly written to Rank 1. At this time, the MDB does not change the original access relationship, and the system accesses data in the normal way, thus not affecting normal business data read and write. This mode ensures that the present invention does not affect the read and write performance and correctness of the system's normal business in non-test states.

[0061] First test mode: The core feature is forced mapping using R0 data as the test source data. In this mode, MDB executes the first forced mapping logic. The path is: while R0 data is being normally written to Rank 0, Figure 2 The red forced mapping path copies the same R0 data and writes it to Rank 1. At this time, the write configuration unit copies the R0 data and writes it to both Rank 0 and Rank 1 simultaneously, while the R1 data is not involved in this test write (i.e., it is not sent or participates in this test write, for example, it is blocked or bypassed). This mode is used to verify whether the read data is consistent when two physical rows simultaneously store R0 data.

[0062] The second test mode: The core feature is forced mapping using R1 data as the test source data. In this mode, MDB executes the second forced mapping logic. The path is: while R1 data is being normally written to Rank 1, Figure 2 The red forced mapping path copies the same R1 data and writes it to Rank 0. At this time, the write configuration unit copies the R1 data and writes it to both Rank 0 and Rank 1 simultaneously, while the R0 data is not involved in this test write (i.e., it is not sent or participates in this test write, for example, it is blocked or bypassed). This mode is used to verify whether the read-back data is consistent when two physical rows simultaneously store R1 data.

[0063] The essential difference between the first and second test modes lies in the source data that is copied and forcibly mapped: the first test mode uses R0 data as the test source data, while the second test mode uses R1 data as the test source data. They do not compare the R0 and R1 data themselves, but rather compare whether the two returned data sets generated from the same source data in two different physical rows are consistent.

[0064] The write configuration unit controls the internal data path selection logic by reading test mode parameters. Specifically, the data path switching control can be achieved through a multiplexer (MUX), selection logic, or other equivalent hardware structures. This invention does not limit the specific circuit implementation method.

[0065] During a read operation, in the first test mode, the read comparison unit receives the first returned data from Rank 0 and the second returned data from Rank 1, and compares whether the first returned data and the second returned data are consistent. Both the first and second returned data are read-back data from Rank 0. In the second test mode, the read comparison unit receives the third returned data from Rank 0 and the fourth returned data from Rank 1, and compares whether the third returned data and the fourth returned data are consistent. Both the third and fourth returned data are read-back data from Rank 1.

[0066] In one example, the read comparison unit comprises multiple parallel comparison subunits (e.g., 16 parallel comparison subunits), each corresponding to a set of data channel inputs (e.g., a set of BL channel inputs). The input data for Rank 0 and Rank 1 enters the corresponding parallel comparison subunit through each set of data channels.

[0067] Each parallel comparison subunit performs parallel comparisons of two input data sets and outputs the comparison result. The parallel comparison subunit uses XOR logic gates to implement bit-wise comparisons. Bit-wise comparisons implemented with XOR logic gates have no serial path; increasing the bit width only affects the parallelism scale and does not significantly increase critical path latency. The hardware overhead is mainly the increase in the number of XOR gates with increasing bit width; the latency is only a small gate-level latency and does not increase linearly with bit width, thus resulting in a faster overall comparison speed. The comparison process is completed internally within the MDB; the CPU does not need to receive and store two complete sets of data, nor does it need to perform software bit-wise comparisons, thereby reducing CPU load and data bus usage. The comparison result is not stored but directly sent back to the CPU.

[0068] In the read comparison unit, after the MDB completes the comparison, it automatically sends the comparison result back to the CPU. The CPU can know the test completion status through the received comparison result without having to actively poll.

[0069] In the first test mode, the read comparison unit performs the first comparison operation: it receives the first returned data from Rank 0 and the second returned data from Rank 1, compares whether the first returned data and the second returned data are consistent, and generates a first comparison pass result if they are consistent, and generates a first comparison failure result if they are inconsistent.

[0070] In the second test mode, the read comparison unit performs the second comparison operation: it receives the third returned data from Rank 0 and the fourth returned data from Rank 1, compares whether the third returned data and the fourth returned data are consistent, and generates a second comparison pass result if they are consistent, and generates a second comparison failure result if they are inconsistent.

[0071] Taking R0 data as an example, the read comparison unit performs a consistency check on the two R0 return data in the first test mode and the second test mode. If the two R0 return data are consistent, a comparison pass result is generated; if the two R0 return data are inconsistent, a comparison failure result is generated.

[0072] Furthermore, if the comparison result of the two R0 returned data is the first comparison result, and the comparison result of the two R1 returned data is the second comparison result, the MDB generates the final comparison result based on the first comparison result and the second comparison result; when both the first comparison result and the second comparison result are passed, the final comparison result is passed, otherwise the final comparison result is failed.

[0073] After the comparison is completed by the read comparison unit, the comparison result is sent back to the host via the DQ path. The host determines whether the test passes based on the received comparison result. When a comparison discrepancy occurs, the corresponding discrepancy information will be reflected in the comparison result and automatically sent back to the CPU, which will then determine the subsequent processing strategy based on the comparison result.

[0074] In one example, the test mode control signal participates in logic control as a real-time control signal within the MDB, without being registered or address-mapped. This control parameter is not registered or address-mapped within the MDB, but participates in logic control as a real-time control signal (e.g., switching the MUX selector), causing the MDB to switch from normal mode to either the first or second test mode state. This feature ensures the immediacy of mode switching, avoiding delays caused by register configuration.

[0075] The test mode control signal is generated in real time by the MRCD based on the test mode start command sent by the host and transmitted to the MDB. After receiving the CA command sent by the host, the MRCD parses the test mode start command and test mode parameters, and controls the MDB to write the test mode parameters. The MRCD directly generates the test mode control signal based on the received mode control command and transmits it to the MDB to control the test-related functional modules.

[0076] See Figure 3 This illustrates the invention. Figure 1 The flowchart illustrates the execution steps of a host initiating a complete first test mode under the system architecture.

[0077] like Figure 3 As shown, the test process includes a configuration phase, a read request phase, a data return and comparison phase, and a data output phase.

[0078] Step 1: Configuration phase.

[0079] The host sends a write command to the MRCD via the CA bus to set the first test mode parameters and configure the comparison parameters.

[0080] After the MRCD parses the command, it generates a test mode control signal and passes it to the MDB. It is important to note that this parameter is not address-mapped and stored within the MDB. Instead, it is used as a real-time control signal in logic control (e.g., switching the MUX selector) to switch the MDB from normal mode to the first test mode state.

[0081] Step 2: Read request phase.

[0082] The host sends a read request (including address / command, forwarded via MRCD).

[0083] After a read request is issued, MRCD controls DRAM Rank 0 and Rank 1 to respond simultaneously. In the first test mode, MDB will force the reading of R0 return data from Rank 0 and R0 return data from Rank 1.

[0084] Step 3: Data return and comparison stage.

[0085] Rank 0 and Rank 1 return data to the MDB simultaneously. The comparator in the MDB performs a consistency comparison between the two data streams and generates a comparison result.

[0086] The comparison logic employs a hardware parallel XOR structure to perform bit-by-bit comparisons, eliminating the need for a serial path. Increasing the bit width only affects the parallelism scale and does not significantly increase critical path latency. Therefore, the MDB can complete the comparison synchronously during data return, without requiring the CPU to pause for reading, storage, or software computation.

[0087] Step 4: Data output stage.

[0088] According to the rules of the first test mode, MDB outputs the Rank 0 data to the host, and also outputs the comparison results.

[0089] The comparison result is sent back to the host via the DQ path. The host only needs to read the result to determine whether the memory access test passed. In particular, this solution does not require repeated testing. Whether to perform multiple tests is determined by the upper-layer testing process, and the result is automatically sent back after the MDB comparison is completed, without the need for the CPU to actively poll.

[0090] Based on the above system architecture, data path, and execution flow, the storage control and testing method of the present invention specifically includes the following steps:

[0091] Step S100, Configuration Steps: The host initiates the test mode and configures the test mode parameters.

[0092] The host sends a test mode start command to the MRCD and configures the test mode parameters. The test mode parameters include at least a working mode identifier, a test source data identifier, and a comparison method. The working mode identifier indicates whether the MDB is operating in normal mode, the first test mode, or the second test mode; the test source data identifier indicates whether R0 or R1 data is used as the source data for this test; and the comparison method instructs the MDB to perform an overall consistency comparison.

[0093] After receiving the CA command sent by the host, the MRCD parses the test mode start command and test mode parameters, and controls the MDB to write the test mode parameters.

[0094] When the working mode is identified as normal mode, the MDB maintains normal mapping, with R0 data written to Rank 0 and R1 data written to Rank 1.

[0095] When the working mode is identified as the first test mode, MDB starts the test mode module and uses R0 data as the test source data.

[0096] When the working mode is identified as the second test mode, MDB starts the test mode module and uses R1 data as the test source data.

[0097] Step S200, Writing Step: MDB controls the writing path according to the test mode parameters.

[0098] In normal mode, MDB does not change the original data paths of Rank 0 and Rank 1, but only performs regular data buffering and forwarding. At this time, R0 data is written to Rank 0, and R1 data is written to Rank 1.

[0099] In the first test mode, MDB writes R0 data to Rank 0, and simultaneously forces the same R0 data to be mapped and written to Rank 1.

[0100] In the second test mode, MDB writes R1 data to Rank 1, while simultaneously forcibly mapping the same R1 data and writing it to Rank 0.

[0101] Step S300, Read Request Step: The host initiates a read request, and Rank 0 and Rank 1 return the data to be compared.

[0102] After the host issues a read request, the MRCD controls Rank 0 and Rank 1 to return data based on the read request. After the read request is issued, the MRCD controls DRAM Rank 0 and Rank 1 to respond simultaneously.

[0103] In the first test mode, Rank 0 returns the data returned by R0, and Rank 1 returns the data returned by R0 (that is, both physical ranks return the readback data of the first data).

[0104] In the second test mode, Rank 1 returns the data returned by R1, and Rank 0 returns the data returned by R1 (that is, both physical ranks return the readback data of the second data).

[0105] The returned data enters the read comparison unit of the MDB for processing.

[0106] Step S400, Comparison Step: MDB performs a consistency comparison on the two returned data generated from the same source data in two physical rows.

[0107] MDB performs consistency comparisons based on the test mode parameters. In the first test mode, MDB compares whether the R0 returned data in Rank 0 is consistent with the R0 returned data in Rank 1; in the second test mode, MDB compares whether the R1 returned data in Rank 1 is consistent with the R1 returned data in Rank 0.

[0108] MDB receives the first data returned by Rank 0 and the second data returned by Rank 1, performs a consistency comparison on the first and second data, and generates a comparison result. The comparison logic uses a hardware parallel XOR structure to implement bit-by-bit comparison. MDB can complete the comparison synchronously during the data return process, without requiring the CPU to pause for reading, storage, or software computation.

[0109] Step S500, Return Step: MDB returns the comparison result to the host.

[0110] After the comparison is complete, the MDB will send the comparison result generated by the read comparison unit back to the host via the DQ path. The host will then determine whether the test passed based on the received comparison result.

[0111] Step S600, Mode Recovery Step: The host sends a normal mode configuration command to the MDB via the MRCD, causing the MDB to exit test mode and return to normal data access state. After the CPU receives the comparison result, it can also send a normal mode configuration command via the MRCD, causing the MDB to exit test mode and return to normal operation. The MDB is only responsible for performing the comparison and outputting the comparison result; it does not perform fault location. Both test mode and normal mode are controlled by the MRCD.

[0112] See Figure 4 This illustrates a specific example of the execution of a multiplexed dual-row memory device in the first test mode.

[0113] In a preferred embodiment, to achieve both the actual read-back data and the hardware comparison result being sent back to the host (CPU), the MDB's read comparison unit performs alternating multiplexing (or overlapping multiplexing) of the data at the output end. Specifically, the MDB places the read-back data of the first physical row (Rank 0) in the first position (e.g., an odd-numbered position) of the output data stream, and places the corresponding hardware bit-by-bit comparison result in the second position (e.g., an even-numbered position). The multiplexed data stream is automatically sent back to the host via the data bus (DQ). Through this multiplexing mechanism, the host only needs to receive the data stream once to simultaneously obtain the actual read-back data (used to verify the data quantity) and the hardware consistency comparison result (used to determine whether the dual-row storage is consistent), without the need for active polling, receiving two complete read-back data sets, or performing software-level bit-by-bit comparisons, further reducing the data bus usage and the host's computational load.

[0114] In a more specific example, taking the first test mode as an example, assume the write configuration unit has copied the same data (e.g., data sequence 0, 2, 4, 6) and written it simultaneously to the first and second physical rows. When the host initiates a read request, both physical rows return the same data; that is, Rank 0 returns 0, 2, 4, 6, and Rank 1 also returns 0, 2, 4, 6. These two read-back data sets enter the MDB's read comparison unit. The read comparison unit uses a parallel XOR logic circuit to perform a consistency comparison on the corresponding data in the two physical rows. Since the two data sets are completely consistent, the read comparison unit generates a comparison result of "comparison passed" for all data sets (e.g., ...). Figure 4 (All zeros in the table represent data consistency). Subsequently, the MDB's read comparison unit performs alternating multiplexing of the data at the output: the read data from Rank 0 (0, 2, 4, 6) is placed in odd-numbered positions of the output data stream, and the corresponding comparison result (0, 0, 0, 0) is placed in even-numbered positions. The multiplexed output data stream becomes 0, 0, 2, 0, 4, 0, 6, 0. This multiplexed data stream is automatically transmitted back to the host via the data bus path. After receiving this data stream, the host can extract the actual read data (0, 2, 4, 6) from the odd-numbered positions and the consistency comparison result (0, 0, 0, 0) from the even-numbered positions, thus simultaneously obtaining the data content and the test result.

[0115] Based on this, the CPU can also jointly determine the anomaly type by considering the amount of data sent, the amount of data received, and the results of the dual-rank comparison, thereby achieving more accurate fault location. For example:

[0116] Scenario 1: If the data is complete and both Rank values ​​are consistent, the test is considered passed.

[0117] Scenario 2: If the data quantity is complete but the two ranks are inconsistent, the anomaly is more likely to occur in the DRAM memory cell or the Rank branch data path (i.e., the data channel between the MDB and the physical row).

[0118] Scenario 3: If both Ranks are consistent but received data is missing (e.g., the CPU sends 100 test data points, but only receives 99), the anomaly is more likely to occur in the common data channel between the MDB and the CPU, or in the multiplexing, parallel-to-serial conversion, and output stages within the MDB.

[0119] Through the aforementioned joint judgment mechanism, the host can initially locate the area where the anomaly occurred based on the amount of data returned by MDB and the comparison results without relying on additional diagnostic hardware or complex software analysis, further improving testing efficiency and fault diagnosis capabilities.

[0120] This invention can test all storage addresses, not just a few representative addresses, to achieve complete coverage of the storage space.

[0121] When R0 data and R1 data correspond to data groups with different attributes, MDB can verify the write and read consistency of data groups with different attributes in two physical rows through the first test mode and the second test mode, thereby improving the ability to locate data path anomalies.

[0122] The number of parallel comparison subunits in the read comparison unit corresponds to the number of data channel groups. For example, there can be 16 parallel comparison subunits, with each subunit corresponding to a set of BL channel inputs. However, the present invention is not limited to this, and the number of comparison subunits can be adjusted according to the actual data channel width.

[0123] The test mode parameters are not address-mapped and registered within the MDB, but instead participate in logic control as real-time control signals. Of course, those skilled in the art will understand that register configuration can also be used to implement this, depending on design requirements; these are all equivalent alternatives to the present invention.

[0124] After the test mode is configured, MDB controls the data write path according to the test mode parameters. In the data return and comparison phase, bit-by-bit comparison is implemented using parallel XOR, with no serial path. Increasing the bit width only affects the parallel scale and does not significantly increase the critical path latency, thus achieving high comparison speed.

[0125] The comparison unit uses an XOR structure to perform bit-wise comparisons of the input data. The hardware overhead is mainly the number of XOR gates that increases with the bit width, while the delay is only a small amount of gate-level delay and does not increase linearly with the bit width. Therefore, the overall comparison speed is relatively fast.

[0126] The multiplexed dual-row memory device and its storage control and testing method provided by the embodiments of the present invention have at least one or a portion of the following advantages:

[0127] (1) By integrating the test mode module inside the data buffer (MDB), the MDB autonomously completes the data path control of write operations and the data consistency comparison of read operations. This migrates some control and test functions that were originally executed by the host (e.g., CPU) to be executed locally on the multiplexed dual-row memory device (MRDIMM). The CPU does not need to participate in the data comparison process, thereby reducing the CPU load, reducing the data bus occupation, and improving the system response speed. At the same time, in a multi-MRDIMM system, multiple MRDIMMs can be supported to execute tests in parallel, reducing the CPU test management overhead and improving the system scalability.

[0128] (2) By setting three working modes, namely normal mode, first test mode and second test mode, MRDIMM can be flexibly switched between normal access state and test state; in normal mode, MDB maintains transparent transmission and does not affect the correctness and performance of the system's regular business data access.

[0129] (3) In the first test mode, the same first data is written to the first physical row and the second physical row at the same time and the first returned data and the second returned data returned by the two physical rows are compared to see if they are consistent; in the second test mode, the same second data is written to the first physical row and the second physical row at the same time and the third returned data and the fourth returned data returned by the two physical rows are compared to see if they are consistent; through two different directions of forced mapping mechanism, bidirectional verification of the data path between the two physical rows is realized, effectively detecting data inconsistency problems caused by abnormalities of physical rows, data channels or memory itself, and improving test coverage and fault location capability;

[0130] (4) The read comparison unit adopts multiple parallel comparison sub-units, each sub-unit corresponds to a set of data channel inputs, and parallel bit-by-bit comparison is realized through XOR logic gates; the hardware parallel comparison method has no serial path, and the increase in bit width only affects the parallel scale without significantly increasing the critical path delay. Therefore, the comparison can be completed synchronously during the data return process, without the CPU performing additional reading, storage and software operation on the returned data, resulting in high comparison speed and low latency.

[0131] (5) The test mode control signal participates in the logic control as a real-time control signal inside the MDB without address mapping registration, ensuring the immediacy of mode switching and avoiding additional delay caused by register configuration.

[0132] (6) The comparison result is automatically transmitted back to the host via the data bus after the comparison unit completes the comparison. The host does not need to actively poll to know the test completion status, which further reduces CPU overhead.

[0133] (7) The test mode control signal is generated in real time by MRCD according to the test mode start command sent by the host and transmitted to MDB, realizing a three-level collaborative test mode configuration mechanism of host-MRCD-MDB, with a clear configuration process and rapid response;

[0134] (8) In the first test mode, the first comparison operation is performed to generate the first comparison pass result or the first comparison failure result. In the second test mode, the second comparison operation is performed to generate the second comparison pass result or the second comparison failure result. The comparison result clearly indicates whether the test passes or fails, which makes it easy for the host to make a quick judgment.

[0135] (9) The host can send a normal mode configuration command to the MDB through the MRCD to make the MDB exit the test mode and restore the normal working state, ensuring that the system can seamlessly return to normal business operation after the test is completed;

[0136] (10) A complete test process is formed by five core steps: configuration, writing, reading request, comparison, and return. Each step works together to achieve full automation from test mode configuration to comparison result return, without the need for CPU intervention at each stage.

[0137] While some embodiments of the present general inventive concept have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined by the claims and their equivalents.

Claims

1. A multiplexed dual-row memory device, characterized in that, The multiplexed dual-row memory device includes: The host is communicatively connected to both the register control driver and the data buffer. The host sends control commands to the register control driver via the command / address bus, and sends test data to and receives data from the data buffer via the data bus. The register control driver receives and parses the control command, generates a test mode control signal based on the control command and transmits it to the data buffer, and transmits control / address commands to the dynamic random access memory to control the corresponding physical row to perform read and write operations; The data buffer is communicatively connected to the first physical row and the second physical row respectively. The data buffer integrates a test mode module, which includes a write configuration unit and a read comparison unit. In test mode, the write configuration unit receives the test mode control signal, controls the data write path according to the working mode indicated by the test mode control signal, and copies the same test data and writes it to the first physical row and the second physical row at the same time. The read comparison unit receives two readback data corresponding to the same test data, one returned by the first physical row and the other by the second physical row, performs a consistency comparison on the two readback data, and generates a comparison result. The data buffer transmits the comparison result back to the host via the data bus.

2. The multiplexed dual-row memory device according to claim 1, characterized in that, The working modes include normal mode, first test mode, and second test mode; In the normal mode, the write configuration unit controls the first data to be written to the first physical row and controls the second data to be written to the second physical row; In the first test mode, the write configuration unit copies the first data and writes it to both the first physical row and the second physical row simultaneously, while the second data does not participate in the writing process. In the second test mode, the write configuration unit copies the second data and writes it to both the first physical row and the second physical row simultaneously, while the first data is not written.

3. The multiplexed dual-row memory device according to claim 2, characterized in that, In the first test mode, the read comparison unit receives the first return data returned by the first physical row and the second return data returned by the second physical row, and compares whether the first return data and the second return data are consistent, wherein the first return data and the second return data are both read-back data of the first data; In the second test mode, the read comparison unit receives the third return data returned by the first physical row and the fourth return data returned by the second physical row, and compares whether the third return data and the fourth return data are consistent, wherein the third return data and the fourth return data are both read-back data of the second data.

4. The multiplexed dual-row memory device according to claim 1, characterized in that, The read comparison unit includes multiple parallel comparison subunits. Each of the parallel comparison subunits corresponds to a set of data channel inputs. The input data of the first physical row and the second physical row are compared bit by bit in parallel through each set of data channels, and the comparison result is output. The parallel comparison subunit uses XOR logic gates to implement the bit-by-bit comparison.

5. The multiplexed dual-row memory device according to claim 1, characterized in that, The test mode control signal is used as a real-time control signal within the data buffer for logical control, without being registered via address mapping.

6. The multiplexed dual-row memory device according to claim 1, characterized in that, The comparison result is transmitted back to the host via the data bus after the comparison is completed by the read comparison unit, and the host does not perform active polling.

7. The multiplexed dual-row memory device according to claim 2, characterized in that, The test mode control signal is generated in real time by the register control driver based on the test mode start command sent by the host and transmitted to the data buffer.

8. The multiplexed dual-row memory device according to claim 2, characterized in that, In the first test mode, the read comparison unit performs a first comparison operation: comparing whether the first returned data read back from the first physical row is consistent with the second returned data read back from the second physical row. If they are consistent, a first comparison pass result is generated; if they are inconsistent, a first comparison failure result is generated. In the second test mode, the read comparison unit performs a second comparison operation: comparing whether the third returned data read back from the first physical row is consistent with the fourth returned data read back from the second physical row. If they are consistent, a second comparison pass result is generated; if they are inconsistent, a second comparison failure result is generated.

9. The multiplexed dual-row memory device according to any one of claims 1-8, characterized in that, The host sends a normal mode configuration command to the data buffer through the register control driver, causing the data buffer to exit the test mode and return to normal working state.

10. A storage control and testing method for a multiplexed dual-row memory device, applied to the multiplexed dual-row memory device according to any one of claims 1-9, characterized in that, The storage control and testing methods include: The host configures test mode parameters to the data buffer through the register control driver. The test mode parameters are parsed by the register control driver and converted into test mode control signals. The data buffer switches to the corresponding working mode according to the test mode control signals. The data buffer controls the data writing path according to the test mode control signal, wherein in the test mode, the same test data is copied and written to the first physical row and the second physical row at the same time; The host issues a read request, and the register control driver controls the return data of the first physical row and / or the second physical row according to the read request; The data buffer receives the first data returned by the first physical row and the second data returned by the second physical row, performs a consistency comparison on the first data and the second data, and generates a comparison result; The data buffer transmits the comparison result back to the host via the data bus.

11. The storage control and testing method according to claim 10, characterized in that, The working modes include a first test mode and a second test mode; In the first test mode, the writing step includes: copying the first data and writing it simultaneously to the first physical row and the second physical row; In the second test mode, the writing step includes: copying the second data and writing it simultaneously to the first physical row and the second physical row.

12. The storage control and testing method according to claim 11, characterized in that, In the first test mode, the comparison step includes: comparing whether the first returned data read back from the first physical row is consistent with the second returned data read back from the second physical row, wherein the first returned data and the second returned data are both read-back data of the first data; In the second test mode, the comparison step includes: comparing whether the third returned data read back from the first physical row is consistent with the fourth returned data read back from the second physical row, wherein the third returned data and the fourth returned data are both read-back data of the second data.

13. The storage control and testing method according to claim 12, characterized in that, In the comparison step, the data buffer uses multiple parallel comparison sub-units to perform parallel bit-by-bit comparisons of the input data of the first physical row and the second physical row, with each parallel comparison sub-unit corresponding to a set of data channel inputs.

14. The storage control and testing method according to any one of claims 10-13, characterized in that, The storage control and testing method also includes a recovery step: the host sends a normal mode configuration instruction to the data buffer through the register control driver, so that the data buffer exits the test mode and returns to the normal data access state.

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