CXL switch-based intra-server near-memory computing task affinity scheduling and access path selection method
Patent Information
- Application Number
- CN202610985010.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-03
- Publication Date
- 2026-09-22
AI Technical Summary
[0004]本发明提供一种基于CXL Switch的服务器内近存计算任务亲和性调度与访问路径选择方法用来克服现有技术中任务调度与数据驻留位置脱节、访问路径静态且缺乏事务级访问模式感知的缺陷
[0022]本申请提供了一种计算机可读存储介质，其上存储有计算机程序，所述程序被处理器执行时实现基于CXL Switch的服务器内近存计算任务亲和性调度与访问路径选择方法。
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Abstract
Description
Technical Field
[0001] This invention relates to a method for affinity scheduling and access path selection of near-memory computing tasks within a server based on CXL Switch, and particularly to the field of near-memory computing technology within a server. Background Technology
[0002] CXL (Compute Express Link) is a high-speed cache-coherent interconnect protocol built on the PCIe physical layer, allowing hosts to directly access remote memory with load / store semantics. The CXL Switch, as the core switching chip in the CXL Fabric, connects multiple CPU sockets to multiple CXL devices within the server.
[0003] In near-data computing architectures, computational tasks are scheduled to execute on processors or accelerators close to the data's residing location to reduce data transfer overhead. However, existing technologies still have significant shortcomings in affinity scheduling and access path selection for near-data computing tasks within servers. First, existing task schedulers primarily make scheduling decisions based on the availability of computing resources, without considering the physical distribution of the data required by the task within the CXL memory pool. This leads to a disconnect between scheduling and data residing location, preventing true near-data computing. Second, the access path of the CXL switch is statically determined during system initialization. When multiple tasks compete for the same port bandwidth, it cannot be dynamically adjusted to alleviate congestion or adapt to the differentiated access requirements of different tasks. Furthermore, existing CXL switches lack real-time awareness of CXL.mem transaction-level access patterns, causing the scheduler to be unable to know the specific access patterns and port congestion status of each task, resulting in "blind scheduling." Summary of the Invention
[0004] This invention provides a server-side near-memory computing task affinity scheduling and access path selection method based on CXL Switch to overcome the shortcomings of existing technologies, such as the disconnect between task scheduling and data residence location, static access paths, and lack of transaction-level access mode awareness.
[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:
[0006] This invention discloses a method for affinity scheduling and access path selection of near-memory computing tasks within a server based on a CXL Switch, comprising: receiving a data address issued by the operating system scheduler and associated with a computing task; tracking CXL.mem transactions initiated by the computing task based on the data address, and determining the access mode type of the computing task by extracting and statistically analyzing its multi-dimensional features; obtaining the real-time congestion status of each port of the CXL Switch; and dynamically selecting the optimal access path for the computing task based on the access mode type, the real-time congestion status, and a preset set of access paths from the input port of the CXL Switch to the CXL memory corresponding to the data address.
[0007] Further, determining the access mode type of the computing task includes: attaching task tags to CXL.mem transactions passing through the CXL Switch based on the source identifier and task-source mapping table of CXL.mem transactions; extracting multi-dimensional access mode features based on statistical data of CXL.mem transactions with the task tags; and classifying the access mode of the computing task according to the multi-dimensional access mode features. Further, the access mode type includes at least one of the following: large-block streaming access mode, random point-and-click access mode, hotspot-focused access mode, and mixed access mode.
[0008] Furthermore, the extraction of multi-dimensional access pattern features also includes: monitoring the rate of change of the CXL.mem transaction count of the computing task within a continuous time window; when the rate of change exceeds a first preset threshold, initiating high-frequency feature sampling of the computing task; when the rate of change is lower than a second preset threshold, switching to low-frequency feature sampling of the computing task.
[0009] Furthermore, the rate of change From the formula Calculation, where Count the transactions for the current window. This is the window length.
[0010] Furthermore, obtaining the real-time congestion status of each port of the CXL Switch includes collecting at least one of the following indicators: port queue depth, average queuing delay, and bandwidth utilization.
[0011] Further, the step of dynamically selecting the optimal access path for the computation task includes: when it is detected that the score of the current access path is lower than the score of the candidate path and the switching condition is met, a delay confirmation process is initiated, and during the delay period, the real-time scores of the original path and the candidate path are continuously collected periodically; at the end of the delay confirmation process, if the difference between the average score of the candidate path and the average score of the original path during the delay period is consistently higher than a preset anti-shake threshold, then path switching is performed; otherwise, the switching is canceled. Further, the anti-shake threshold... The value range is from 0.05 to 0.2.
[0012] This application provides a method for scheduling near-memory computing tasks executed in an operating system, comprising: obtaining a computing task to be scheduled and the data address of the CXL memory to be accessed by the computing task; determining the residence location of the CXL memory data under a CXL Switch connected to the server where the operating system is located based on the data address; receiving the access mode type of the computing task from the CXL Switch; calculating the affinity score between the computing task and each of the candidate computing units based on the access mode type, the data residence location, and the correspondence between candidate computing units and the input port of the CXL Switch; scheduling the computing task to a target computing unit according to the affinity score, and sending the input port information corresponding to the target computing unit to the CXL Switch to collaboratively initiate optimal access path selection.
[0013] Furthermore, the step of calculating the affinity score between the computing task and each of the candidate computing units based on the access mode type, the data residence location, and the correspondence between the candidate computing units and the CXL Switch input port includes: determining a weighting coefficient based on the access mode type; calculating the proximity based on the topological distance between the candidate computing unit and the CXL Switch port corresponding to the data residence location; and calculating the affinity score using a weighted summation formula, combined with the access frequency of the data region corresponding to the data address.
[0014] Furthermore, the weighted summation formula is as follows: ,in, Weighting coefficients based on task access mode type. To determine the proximity of the execution location to the data residing port, This refers to the data access frequency.
[0015] Furthermore, the server-based near-memory computing task affinity scheduling and access path selection method based on CXL Switch also includes: periodically evaluating the effect of the current scheduling strategy on tasks of various access modes based on the deviation ratio between the actual CXL access latency and the expected latency of historically scheduled computing tasks; and dynamically adjusting the weight coefficients assigned to different access mode types when calculating the affinity score based on the variance of the deviation ratio within the sliding window.
[0016] Furthermore, the adjustment amount of the weighting coefficient From the formula Calculate, where, To learn step length, For variance, The normalization constant is This represents the average deviation ratio.
[0017] This application provides a CXL Switch chip, comprising: a transaction processing unit configured to receive CXL.mem transactions; a transaction tracking and classification module configured to track CXL.mem transactions initiated by computing tasks and determine the access mode type of the computing tasks by extracting and statistically analyzing their multi-dimensional features; a congestion monitoring module configured to obtain the real-time congestion status of each port of the CXLSwitch chip; and a dynamic path selection module configured to dynamically select the optimal access path for the computing tasks based on the access mode type, the real-time congestion status, and a preset set of access paths.
[0018] Furthermore, a pressure compensation unit based on a thermal deformation material is provided between the package of the CXL Switch chip and the heat sink. The working state of the pressure compensation unit changes dynamically with the temperature of the CXL Switch chip to compensate for the fluctuation of heat dissipation contact pressure caused by temperature changes.
[0019] This application provides a near-memory computing scheduling device, comprising: a task and address acquisition module configured to acquire a computing task to be scheduled and the data address of the CXL memory to be accessed by the computing task; a residence location determination module configured to determine the residence location of the CXL memory data under the CXL Switch based on the data address; an access mode receiving module configured to receive the access mode type of the computing task from the CXL Switch; an affinity score calculation module configured to calculate the affinity score between the computing task and each of the candidate computing units based on the access mode type, the data residence location, and the correspondence between candidate computing units and CXL Switch input ports; and a scheduling and coordination module configured to schedule the computing task to a target computing unit according to the affinity score and send the input port information corresponding to the target computing unit to the CXL Switch to coordinate the initiation of optimal access path selection.
[0020] This application provides a near-memory computing scheduling system, including the CXL Switch chip as described above, and the near-memory computing scheduling device as described above.
[0021] This application provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the program, it implements a method for affinity scheduling and access path selection of near-memory computing tasks within a server based on CXL Switch.
[0022] This application provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a method for affinity scheduling and access path selection of near-memory computing tasks within a server based on a CXL Switch.
[0023] The beneficial effects achieved by this invention are as follows: By tracking CXL.mem transactions initiated by computing tasks and extracting their multi-dimensional access pattern features, accurate classification of task access patterns is realized, providing a data foundation for subsequent affinity scheduling and path selection. Based on this, on the one hand, at the operating system level, an affinity score is calculated based on access pattern type, data residence location, and the topological relationship of candidate computing units. Tasks are scheduled to the nearest computing unit according to this score, solving the problem of task scheduling being disconnected from data residence location, making computing tasks closer to their required data, thereby significantly reducing data access latency. On the other hand, at the CXL Switch level, the optimal access path is dynamically selected for tasks by combining the task's access pattern type and the real-time congestion status of each port, avoiding congestion and resource waste caused by static paths, and realizing differentiated path services for different types of tasks. Furthermore, by employing a variable-frequency sampling mechanism based on the transaction count change rate, system overhead is reduced during task quiet periods, while feature capture accuracy is guaranteed during burst periods. A dynamic weight update method based on delay feedback and variance enables affinity scoring to adapt to environmental changes. A path switching mechanism based on delayed acknowledgment and anti-jitter threshold effectively suppresses invalid switching caused by instantaneous noise, ensuring path stability. Therefore, this application achieves closed-loop collaborative optimization of perception, scheduling, and execution without violating standard protocols, improving the data access efficiency and resource utilization of the entire CXL memory pooling system. Attached Figure Description
[0024] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:
[0025] Figure 1 This is a flowchart of the present invention. Detailed Implementation
[0026] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.
[0027] Example 1
[0028] Terminology Explanation:
[0029] CXL Switch: Refers to a switching chip that operates based on the Compute Express Link protocol. It is deployed inside a server and is used to route CXL protocol data packets between multiple upstream ports (connecting to the CPU and accelerators) and multiple downstream ports (connecting to CXL memory devices).
[0030] CXL.mem transaction: refers to a read or write operation unit that is initiated through the CXL.mem protocol and accesses remote CXL memory with load / store semantics.
[0031] Access pattern type: refers to the abstract classification of data access behavior patterns after analyzing the statistical characteristics (such as access frequency, read / write ratio, access granularity, etc.) of CXL.mem transactions initiated by computing tasks.
[0032] Data residency location: refers to the current physical location of CXL memory data (e.g., in pages or regions), which can be specifically represented by the downlink port identifier of the CXL Switch connected to the CXL memory device.
[0033] Affinity score: refers to a numerical value used to quantify the proximity between a computing task and a candidate computing unit. This value is calculated based on factors such as the task's data residence location and access mode type. The higher the score, the greater the potential improvement in data access efficiency that may result from executing the task on that computing unit.
[0034] Real-time congestion status: refers to the instantaneous load status of each port of the CXL Switch, which can be characterized by one or more of the following indicators: port output queue depth, average transaction queuing latency, and bandwidth utilization.
[0035] Optimal access path: refers to the optimal forwarding path (which may pass through one or more intermediate switching hops) between the input port (source port) of the CXL Switch where the computing unit that initiated the CXL.mem access is located and the downlink port (destination port) of the CXL memory device where the data is located, based on a comprehensive evaluation of the real-time congestion status and the task access mode type.
[0036] Computing unit: refers to a processing entity capable of performing computing tasks, including but not limited to CPU sockets, GPUs, FPGAs, etc.
[0037] like Figure 1 As shown, a method for affinity scheduling and access path selection of near-memory computing tasks within a server based on CXL Switch includes:
[0038] Step S101: Receive the data address issued by the operating system scheduler and associated with the computing task;
[0039] Step S102: Track the CXL.mem transactions initiated by the computing task based on the data address, and determine the access mode type of the computing task by extracting and statistically analyzing its multi-dimensional features;
[0040] Step S103: Obtain the real-time congestion status of each port of the CXL Switch;
[0041] Step S104: Based on the access mode type, the real-time congestion status, and the preset set of access paths from the CXLSwitch input port to the CXL memory corresponding to the data address, dynamically select the optimal access path for the computing task.
[0042] In this embodiment, the above steps work together. Step S101 enables the CXL Switch to know in advance the range of data addresses that the scheduled task needs to access. Step S102 accurately identifies and analyzes the access behavior characteristics of each computing task based on all CXL.mem transactions arriving at the CXL Switch, thereby classifying the access patterns of the tasks, which provides a basis for subsequent differentiated services. Simultaneously, step S103 continuously monitors the health status within the CXL Fabric, capturing congestion on each link. Finally, step S104 integrates the results of the preceding steps, "tailor-making" a data access path for each task. This allows bandwidth-sensitive access such as large streaming tasks to avoid congested links, while latency-sensitive access such as random queries can choose low-latency paths. This achieves a shift from "static, indiscriminate routing" to "dynamic, task-aware routing," collectively solving the problem of rigid path selection in existing CXL Switches, reducing overall data access latency and improving the bandwidth utilization of the CXL Fabric.
[0043] Taking a specific application scenario as an example, in an AI model training server, the operating system scheduler prepares to schedule a large matrix multiplication calculation task (task A). The scheduler first notifies the CXL Switch of the range of CXL memory addresses that task A will access (step S101). At the same time, another running database index query task (task B) frequently initiates small-granularity CXL.mem read transactions. The transaction tracking unit of the CXL Switch (step S102) observes the behavioral characteristics of task B (high frequency, small granularity, random address) and classifies its access pattern as "random point lookup". Meanwhile, the congestion monitoring unit of the CXL Switch (step S103) discovers that the queue depth of port X connected to a certain CXL memory pool is rising rapidly. When task B initiates the next data access, the dynamic path selection logic (step S104) combines its "random check" access mode type (sensitive to latency) and the high congestion state of port X, and selects a backup path Y with a lower current queue depth and fewer hops from the preset multiple reachable paths to forward the transaction, thereby avoiding queuing on the congested port X and ensuring the low-latency access requirements of task B.
[0044] In one embodiment, step S102 (determining the access mode type of the computing task) specifically includes: attaching task tags to CXL.mem transactions passing through the CXLSwitch based on the source identifier and task-source mapping table of CXL.mem transactions; extracting multi-dimensional access mode features based on the statistical data of CXL.mem transactions with the task tags; and classifying the access modes of the computing tasks according to the multi-dimensional access mode features. Furthermore, combining the above principles, this method can achieve the beneficial effect of providing a refined profile of the access behavior of each computing task, providing the most basic, task-level data input for subsequent affinity scheduling and differentiated path services. As a specific implementation, a Transaction Tagging Unit (TTU) can be set at each input port of the CXL Switch chip. This TTU parses the source port ID of the CXL.mem transaction and queries the task-source mapping table (TSMT) issued by the operating system, thereby tagging each transaction with an internal task tag. All tagged transactions will be aggregated and analyzed. Their multidimensional characteristics (such as the number of transactions per unit time, the ratio of read to write transactions, the distribution of transaction size, the span of target addresses, etc.) will be extracted and statistically analyzed. Finally, the classification results (such as large-block streaming, random point lookup, etc.) will be written into the Task Access Pattern Table (TAPT) maintained inside the chip.
[0045] In some embodiments, the access mode type includes at least one of bulk streaming access mode, random point-and-click access mode, hotspot-concentrated access mode, and hybrid access mode. As a specific classification implementation, "bulk streaming access mode" is typically characterized by high-frequency, large-granularity (e.g., greater than 512B), sequential or fixed-step address access, suitable for scenarios such as full table scans, and prefers high bandwidth and localization during scheduling and path selection; "random point-and-click access mode" is characterized by medium-frequency, small-granularity (e.g., less than 128B), random address jumps, suitable for index lookups, and prefers low latency; "hotspot-concentrated access mode" is characterized by high-frequency, medium-to-small-granularity access addresses highly concentrated in a few pages, suitable for loop iteration, and prefers cache / memory affinity; "hybrid access mode" includes a combination of the above characteristics.
[0046] In one embodiment, the process of extracting multi-dimensional access pattern features in step S102 mentioned above further includes: monitoring the rate of change of the CXL.mem transaction count of the computing task within a continuous time window; initiating high-frequency feature sampling of the computing task when the rate of change exceeds a first preset threshold; and switching to low-frequency feature sampling of the computing task when the rate of change is lower than a second preset threshold. Furthermore, based on the above principles, this approach can significantly reduce the sampling and computational overhead of the system during task quiescent or low-activity periods, while simultaneously achieving a rapid response and capture of peak features during sudden task access, thus achieving a balance between power consumption and accuracy. As a specific implementation, a differential rate of change monitor can be introduced to continuously calculate the rate of change of each task within adjacent sampling windows. (For example to Transaction count change rate within ) .when Exceeding the high trigger threshold When the sampling mode of the task is 5000 txn / sec, switch it to High-Sampling (e.g., 1μs periodic sampling); when Below the low inertia threshold When the frequency of feature calculation is 200 txn / sec, switch to Low-Sampling (e.g., 100μs periodic sampling) to dynamically adjust the frequency of feature calculation.
[0047] In some embodiments, the rate of change From the formula Calculation, where Count the transactions for the current window. This is the window length.
[0048] In one embodiment, step S103 (obtaining the real-time congestion status of each port of the CXL Switch) specifically includes: collecting at least one of the following metrics: port queue depth, average queuing latency, and bandwidth utilization. Furthermore, based on the above principles, this approach can provide a comprehensive and real-time reflection of port load and health status from different dimensions. Queue depth reflects the instantaneous backlog of transactions; average queuing latency directly reflects the waiting time experienced by transactions at the port and is strongly correlated with user experience latency; bandwidth utilization demonstrates the port's capacity usage. By collecting these metrics, the path selection logic can more accurately assess the throughput of each path.
[0049] This application provides a method for scheduling near-memory computing tasks executed in an operating system, the method comprising:
[0050] Step S201: Obtain the computing task to be scheduled and the data address of the CXL memory to be accessed by the computing task;
[0051] Step S202: Based on the data address, determine the location where the CXL memory data resides under the CXL Switch connected to the server where the operating system is located;
[0052] Step S203: Receive the access mode type of the computing task from the CXL Switch;
[0053] Step S204: Based on the access mode type, the data residence location, and the correspondence between the candidate computing units and the CXL Switch input port, calculate the affinity score between the computing task and each of the candidate computing units;
[0054] Step S205: Schedule the computing task to the target computing unit according to the affinity score, and send the input port information corresponding to the target computing unit to the CXL Switch to collaboratively initiate the optimal access path selection.
[0055] In this embodiment, steps S201 to S205 form a complete affinity-aware scheduling process. Steps S201 and S202 clarify "which data the task needs to access" and "where this data is physically located." Step S203 introduces a precise task behavior profile from the CXL Switch. Step S204 uses this information to quantitatively evaluate the potential data access efficiency of the task executed at different locations (such as CPU Socket 0 or GPU 1), i.e., an affinity score. Step S205 finally makes a scheduling decision based on the score and synchronizes the execution location information of the decision to the CXL Switch, enabling it to optimize the access path for the task starting from the correct source port. This method collectively solves the core problem of the disconnect between task scheduling and the physical location of data, scheduling computation tasks to the location closest to the data they need, achieving true near-memory computation, thereby reducing data access latency at its source.
[0056] Continuing with the AI model training scenario as an example, the operating system scheduler obtains the address of the matrix multiplication task A to be scheduled and the large parameter matrix it needs to access in CXL memory (step S201). By querying the data residency location mapping table maintained by the kernel, it is determined that the parameter matrix is currently mainly distributed on the memory devices connected to ports P1 and P2 of the CXL Switch (step S202). At the same time, the scheduler receives from the TAPT table of the CXL Switch that the access mode of task A is classified as "bulk streaming" (step S203). Assume that the current server has two candidate computing units: CPU Socket 0 (connected to Switch input port In0) and GPU 1 (connected to Switch input port In1). The scheduler calculates the affinity score (step S204): since it is a "bulk streaming" task, the bandwidth weight is high; the topological distance (proximity) between ports P1 / P2 and input ports In0 / In1 is calculated; and the historical access frequency of the parameter matrix is combined. Finally, it is calculated that task A has a higher affinity score when executed on CPU Socket 0. Therefore, the scheduler schedules task A to CPU Socket 0 (step S205) and notifies the CXL Switch: subsequent CXL.mem transactions initiated from input port In0 that access a specific address range belong to task A, please perform dynamic path optimization for it.
[0057] In one embodiment, step S204 specifically includes: determining a weighting coefficient based on the access mode type; calculating proximity based on the topological distance between the candidate computing unit and the CXL Switch port corresponding to the data residence location; and calculating the affinity score using a weighted summation formula, combined with the access frequency of the data region corresponding to the data address. Furthermore, based on the above principles, this approach can transform the abstract concept of "affinity" into a calculable and comparable quantitative value, enabling scheduling decisions to shift from experience-based heuristic rules to model-based precise evaluation. As a specific implementation, the operating system kernel can maintain a Data Residence Location Map (DRLMT) to record the Switch downlink port ID where each CXL memory block is currently located, using pages (e.g., 4KB) or regions as the granularity. The affinity scoring algorithm iterates through each candidate computation unit. For each major data region that the task needs to access, it assigns a weight coefficient (Weight(task_type)) based on its access mode type (e.g., a weight of 0.6 for large-scale streaming and 0.8 for random point lookup). This weight coefficient is then multiplied by the reciprocal of the topological distance from the computation unit to the port where the data is located (as the proximity), and then multiplied by the normalized access frequency (Access_Frequency) of the data region. Finally, the scores of all data regions are summed to obtain the total score of the computation unit.
[0058] In some embodiments, the weighted summation formula is: ,in, Weighting coefficients based on task access mode type. To determine the proximity of the execution location to the data residing port, This refers to the data access frequency.
[0059] In one embodiment, the affinity score calculation method mentioned above further includes: periodically evaluating the effect of the current scheduling strategy on tasks of various access modes based on the deviation ratio between the actual CXL access latency and the expected latency of historically scheduled computation tasks; and dynamically adjusting the weight coefficients assigned to different access mode types when calculating the affinity score based on the variance of the deviation ratio within a sliding window. Furthermore, combining the above principles, this approach can bring the beneficial effect of enabling the scheduling system to have online learning and adaptive capabilities. When workload characteristics or data distribution undergo slow-changing drift, the system can automatically micro-schedule the strategy (weights) to maintain optimal scheduling performance without manual intervention from the administrator. As a specific implementation, the system can perform a backtracking evaluation after processing a certain number (e.g., 1000) of scheduling requests. It collects the actual average CXL access latency of each access mode type task (k) within a recent period (sliding window, e.g., W=200 schedulings). Calculate its near-memory delay compared to the ideal near-memory delay. deviation ratio Then calculate the value within that window. mean and variance A small variance indicates that the recent scheduling effect is stable and can be based on... The weights should be adjusted significantly; a large variance indicates an unstable environment or that the original weights are not applicable, and the adjustment should be reduced.
[0060] In some embodiments, the adjustment amount of the weighting coefficient From the formula Calculate, where, To learn step length, For variance, The normalization constant is This represents the average deviation ratio. As a specific parameter example, the learning step size... A value of 0.01 can be used to prevent over-adjustment; this is the normalization constant. A value of 0.1 can be used to map the variance range. The calculated... It can be positive or negative, and is used to update the weight coefficients of the corresponding task type k. After the update, all weights need to be normalized so that their sum is 1.
[0061] In one embodiment, regarding the aforementioned step S104 (dynamically selecting the optimal access path for the computing task) and the path selection in the aforementioned collaborative process, step S104 specifically includes: when it is detected that the score of the current access path is lower than the score of the candidate path and the switching conditions are met, a delayed confirmation process is initiated, and during the delay period, the real-time scores of the original path and the candidate path are periodically collected; at the end of the delayed confirmation process, if the difference between the average score of the candidate path and the average score of the original path during the delay period is continuously higher than a preset anti-jitter threshold, then path switching is performed; otherwise, the switching is canceled. Furthermore, based on the above principles, this approach can effectively suppress frequent path oscillations (ping-pong switching) caused by instantaneous congestion spikes or measurement noise, improving the stability of the CXL Fabric topology and the orderliness of transactions, and avoiding additional overhead caused by invalid switching (such as cache invalidation and transaction reordering). As a specific implementation, when the path selection engine inside the CXL Switch evaluates a path, if it finds that the candidate path score is better than the current path, it does not switch immediately, but instead starts a delayed confirmation timer (e.g., ...). Within this timer window, the engine continues at short cycles (e.g., Two paths are sampled to obtain N (e.g., N=10) discrete path score sampling points. After the timer expires, the average score of the original path and the candidate path is calculated from these N sampling points. and Only when Only then will the actual path switch be performed.
[0062] In some embodiments, the image stabilization threshold The value ranges from 0.05 to 0.2. This range has been validated to strike a good balance between effectively filtering transient jitter and ensuring a timely response to persistent congestion. The default value can be set to 0.1.
[0063] A CXL Switch chip, the CXL Switch chip comprising:
[0064] The transaction processing unit is configured to receive CXL.mem transactions;
[0065] The transaction tracking and classification module is configured to track CXL.mem transactions initiated by computing tasks and determine the access mode type of the computing tasks by extracting and statistically analyzing their multidimensional features.
[0066] The congestion monitoring module is configured to acquire the real-time congestion status of each port of the CXL Switch chip;
[0067] The dynamic path selection module is configured to dynamically select the optimal access path for the computing task based on the access mode type, the real-time congestion status, and a preset set of access paths.
[0068] In one embodiment, a pressure compensation unit based on a thermally deformable material is disposed between the CXL Switch chip package and the heat sink. The operating state of the pressure compensation unit dynamically changes with the temperature of the CXL Switch chip to compensate for fluctuations in heat dissipation contact pressure caused by temperature changes. Furthermore, based on the above principle, this structure can passively and adaptively maintain the optimal contact pressure between the chip and the heat sink interface without external sensors or control circuits, solving the problem of increased thermal resistance due to softening of the thermal interface material at high temperatures. This ensures that the CXL Switch chip maintains a stable operating frequency and performance during high-load near-memory computing scheduling tasks. As a specific implementation, the pressure compensation unit can employ a bimetallic strip structure, composed of two metal alloys with different coefficients of thermal expansion (such as brass and Invar alloy), placed between the chip package and the heat sink base. In the cold state, the bimetallic strip is flat, providing basic preload. When the chip temperature rises, the bimetallic strip bends to one side due to uneven expansion on both sides, increasing the arc height and pushing the heat sink upwards, increasing the compression of the spring screw, thereby increasing the clamping force on the chip and compensating for the softening effect of the thermal interface material.
[0069] This application provides a near-memory computing scheduling device, which includes:
[0070] The task and address acquisition module is configured to acquire the computing task to be scheduled and the data address of the CXL memory to be accessed by the computing task;
[0071] The residence location determination module is configured to determine the residence location of the CXL memory data under the CXLSwitch based on the data address;
[0072] The access mode receiving module is configured to receive the access mode type of the computing task from the CXL Switch;
[0073] The affinity score calculation module is configured to calculate the affinity score between the computing task and each of the candidate computing units based on the access mode type, the data residence location, and the correspondence between the candidate computing units and the CXL Switch input port.
[0074] The scheduling and coordination module is configured to schedule the computing task to the target computing unit according to the affinity score, and send the input port information corresponding to the target computing unit to the CXL Switch to coordinate the initiation of the optimal access path selection.
[0075] This application provides a near-memory computing scheduling system, including the CXL Switch chip as described above, and the near-memory computing scheduling device as described above.
[0076] This application also provides an electronic device, including a memory and a processor. The memory stores a computer program, and when the processor executes the program, it implements a server-based near-memory computing task affinity scheduling and access path selection method based on CXL Switch.
[0077] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements a server-based near-memory computing task affinity scheduling and access path selection method based on CXL Switch.
[0078] It should be noted that, in some optional implementations, in addition to the methods, apparatus, and systems described above, this application may also incorporate the following refined strategies or optimization mechanisms to further improve system performance: 1. Joint decision-making for task-data migration: When the affinity score is too low, the system can evaluate the net benefits of the two options, "migrating task" and "migrating data". Task migration overhead This includes context saving, cache flushing, etc. (approximately) Data migration overhead With data volume and idle bandwidth and protocol overhead coefficient (As in 1.5) Related. Through comparison and In addition to setting a revenue threshold, a migration lock-up period is introduced. This enables joint optimization migration decisions to prevent oscillations. 2. Virtual Link Health Awareness: The completion timestamps of CXL.mem transactions can be used to calculate the latency variance and mean of K consecutive transactions, constructing a link health index. .when If the value is below a threshold (e.g., 0.4), even if the queue depth does not significantly deteriorate, the port can be marked as "sub-healthy" in advance, triggering CAD-PSSE to downgrade the path score of that port or start physical layer retraining, thus achieving proactive fault prevention. 3. Dynamic weight self-adjustment algorithm: Topological weights in path scoring Congestion weight Task adaptation weights Based on the expected delay deviation of the task and port congestion trend Make dynamic adjustments. For example, if the actual latency is higher than the target, reduce the dependence on topological proximity (reduce...). ), increase congestion avoidance (increase) 4. Port Buffer Optimization: Each CXL port output queue can be divided into sub-channels of different depths, such as streaming channels (deep, serving large-scale streaming tasks), point-to-point channels (shallow, serving random point-to-point tasks), and elastic channels (adjustable depth, serving mixed tasks). The TTE-APEC classification results are used to guide transactions into the corresponding channels, achieving differentiated services and mitigating head-end congestion. 5. In-Band Congestion Warning: The reserved bits in the CXL.mem transaction header can carry a 3-bit congestion precursor warning token generated by the PCMU. After downstream devices parse this token, they can reduce the transaction injection rate in advance and notify CAD-PSSE to plan alternative paths in advance, achieving near-zero-overhead congestion precursor detection. 6. Multi-Level Path Caching: The CXL Switch can use a two-level path selection cache. The first level is a mode-specific fully associative cache (grouped by task access mode), providing ultra-low latency hits; the second level is a globally shared hash cache. When the first-level cache miss rate is high, high-frequency paths can be prefetched from the second-level cache to adapt to the lookup requirements of tasks with different access modes. 7. Hot / Cold Page Hierarchical Mapping: Based on the operating system's Data Resident Location Map (DRLMT), a hot page location cache (HPL-Cache) can be maintained for each task, storing only the location information of the top 0.1% of pages with the highest access frequency. Most affinity scoring queries can hit this cache, significantly reducing query latency, while cold page queries fall back to the complete DRLMT. 8. Mechanical Structure Optimization: - CXL connectors can adopt a self-locking anti-loosening structure with spiral guide grooves and elastic locking (including steel balls). The spiral motion during insertion and removal can generate a self-locking force and perform micro-wiping on the terminal surface, improving contact reliability. - CXL memory module slots can use an anti-vibration fixing mechanism combining wedge sliders and disc springs. The wedge slider converts the vertical force of the spring into a horizontal clamping force and has self-locking properties, while the disc spring provides constant force compensation, effectively resisting poor contact caused by vibration.
[0079] It should be noted that in some alternative embodiments, technical terms not explicitly stated in the claims but potentially ambiguous are clarified here: The "candidate computing unit" includes all logical or physical processing cores capable of being assigned computing tasks by the operating system scheduler. This includes not only independent CPU sockets but also processing units in accelerator devices such as GPUs and FPGAs, and even different NUMA nodes within the CPU, the specific scope depending on the configuration of the operating system's scheduling domain. The "preset access path set" refers to the set of all reachable routes from any input port to any destination CXL device established by the CXL Fabric Manager or similar management entity during system initialization or topology discovery phases. This set information is stored in the routing table of the CXL Switch.
[0080] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.
Claims
1. A method for affinity scheduling and access path selection of near-memory computing tasks within a server based on CXL Switch, characterized in that, include: Receive the data address issued by the operating system scheduler and associated with the computing task; Track the CXL.mem transactions initiated by the computing task based on the data address, and determine the access mode type of the computing task by extracting and statistically analyzing its multi-dimensional features; obtain the real-time congestion status of each port of the CXL Switch; Based on the access mode type, the real-time congestion status, and the preset set of access paths from the CXL Switch input port to the CXL memory corresponding to the data address, the optimal access path is dynamically selected for the computing task.
2. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch in a server according to claim 1, characterized in that, include: Obtain the computing task to be scheduled and the data address of the CXL memory to be accessed by the computing task; Based on the data address, determine the location where the CXL memory data resides under the CXLSwitch connected to the server where the operating system is located; Receive the access mode type of the computing task from the CXL Switch; Based on the access mode type, the data residence location, and the correspondence between the candidate computing units and the CXL Switch input port, the affinity score between the computing task and each of the candidate computing units is calculated; The computing task is scheduled to the target computing unit based on the affinity score, and the input port information corresponding to the target computing unit is sent to the CXL Switch to collaboratively initiate the optimal access path selection.
3. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch in a server according to claim 1 or 2, characterized in that, Determining the access mode type of the computing task includes: Based on the source identifier and task-source mapping table of CXL.mem transactions, task tags are added to CXL.mem transactions that pass through the CXL Switch; Based on the statistical data of CXL.mem transactions with the aforementioned task tags, extract multidimensional access pattern features; Based on the multidimensional access pattern characteristics, the access patterns of the computing tasks are classified.
4. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch in a server according to claim 3, characterized in that, The access mode types include at least one of the following: block streaming access mode, random point-to-point access mode, hotspot-focused access mode, and hybrid access mode.
5. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch in a server according to claim 2, characterized in that, The process of calculating the affinity score between the computing task and each of the candidate computing units based on the access mode type, the data residence location, and the correspondence between the candidate computing units and the CXL Switch input port includes: The weighting coefficient is determined based on the access mode type; The proximity is calculated based on the topological distance between the candidate computing unit and the CXL Switch port corresponding to the data residence location; The affinity score is calculated using a weighted summation formula, taking into account the access frequency of the data region corresponding to the data address.
6. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch in a server according to claim 5, characterized in that, The weighted summation formula is: ,in, Weighting coefficients based on task access mode type. To determine the proximity of the execution location to the data residing port, This refers to the data access frequency.
7. The method for affinity scheduling and access path selection of near-memory computing tasks within a server based on CXL Switch according to claim 1, characterized in that, The process of obtaining the real-time congestion status of each port of the CXL Switch includes collecting at least one of the following indicators: port queue depth, average queuing delay, and bandwidth utilization.
8. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch in a server according to claim 3, characterized in that, The extraction of multidimensional access pattern features also includes: Monitor the rate of change of the CXL.mem transaction count of the computing task within a continuous time window; when the rate of change exceeds a first preset threshold, initiate high-frequency feature sampling of the computing task; when the rate of change is lower than a second preset threshold, switch to low-frequency feature sampling of the computing task.
9. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch in a server according to claim 8, characterized in that, The rate of change From the formula Calculation, where Count the transactions for the current window. This is the window length.
10. The method for affinity scheduling and access path selection of near-memory computing tasks based on CXL Switch according to claim 5 or 6, characterized in that, The method further includes: periodically evaluating the effectiveness of the current scheduling strategy for tasks of various access modes based on the ratio of the deviation between the actual CXL access latency and the expected latency of historically scheduled computation tasks; and dynamically adjusting the weight coefficients assigned to different access mode types when calculating the affinity score based on the variance of the deviation ratio within a sliding window. The adjustment amount of the weighting coefficient From the formula Calculate, where, To learn step length, For variance, The normalization constant is This represents the average deviation ratio.