An order-preserving processing device and master-slave communication system

Abstract

The application relates to an order-preserving processing device and a master-slave communication system, which comprises a command cache module and an order-preserving management module; the command cache module receives a command and a command identifier issued by a master device, allocates a storage address for the command, and sends the storage address and the command identifier to the order-preserving management module; the order-preserving management module stores the command identifier, generates order-preserving information containing a write address, a command identifier and a sequence number according to the number of current command identifiers in the sub-module, receives response information and a release address returned by a slave device, matches the order-preserving information according to the release address, determines whether to send the response information and the corresponding command identifier to the master device, and realizes the sequence return of the response information with the same command identifier output by the slave device to the master device.

Description

Technical Field

[0001] This application relates to the field of computer network communication technology, specifically to a sequence-preserving processing device and a master-slave communication system. Background Technology

[0002] Master-slave communication systems are a common communication architecture in digital circuits, consisting of a master device and a slave device. The master device initiates commands, while the slave device receives and executes the commands and returns response information to the master device. Master-slave communication systems are widely used in scenarios such as internal bus interconnection of chips and peripheral device control.

[0003] To improve communication efficiency, bus protocols typically support the master device to send multiple commands continuously. At the same time, bus protocols allow slave devices to return response information out of order, but stipulate that response information with different command identifiers can be returned out of order, while response information with the same command identifier must be returned in the order it was sent.

[0004] When the master device sends each command, it needs to cache the command and its corresponding command identifier. After the response information for that command is returned, the corresponding cache space is released for use by subsequent commands. When multiple commands with the same command identifier are en route simultaneously, the response information returned by the slave device only carries the command identifier. However, at this time, the command identifier corresponds to multiple cached commands, and the system cannot determine which command the response information should correspond to. Summary of the Invention

[0005] This application provides a sequence-preserving processing device and a master-slave communication system to enable the sequential return of response information with the same command identifier from the slave device to the master device.

[0006] According to the first aspect, embodiments of this application provide an order-preserving processing device, including a command caching module and an order-preserving management module;

[0007] The command caching module includes a first control submodule and a command storage submodule; The first control submodule is used to receive the current command and current command identifier issued by the master device, obtain the current write address, write the current command into the command storage submodule according to the current write address, and send the current write address and the current command identifier to the order preservation management module; it is also used to obtain the current read address and send the current read address to the slave device; The command storage submodule is used to store the current command and to send the current command to the slave device in response to a read request from the slave device; The sequence management module includes a second control submodule, an identifier storage submodule, and a sequence information storage submodule; The second control submodule is used to write the current command identifier into the identifier storage submodule according to the current write address, generate the order preservation information of the current command according to the number of current command identifiers in the identifier storage submodule, and store the order preservation information of the current command into the order preservation information storage submodule; wherein the order preservation information of the current command includes the current write address, the current command identifier, and the sequence number; The second control submodule is also used to receive response information and release address returned by the device, match the release address with the write address in each sequence information in the sequence information storage submodule, and if there is a matching sequence information, determine whether to send the response information and the corresponding command identifier to the master device according to the sequence number in the matching sequence information.

[0008] In one specific implementation, the second control submodule is specifically used for: If the number of current command identifiers in the identifier storage submodule is greater than or equal to 2, then the sequence number is determined according to the number of current command identifiers, and the order preservation information of the current command is generated according to the sequence number, the current write address, and the current command identifier; otherwise, the order preservation information of the current command is not generated.

[0009] In one specific implementation, the second control submodule is specifically used for: If the number of current command identifiers in the identifier storage submodule is equal to 2, then a first write address is obtained based on the storage address of a previously stored current command identifier in the identifier storage submodule. The order preservation information of the previously stored command is generated based on the first write address and the current command identifier, and the order preservation information of the previously stored command is stored in the order preservation information storage submodule. The order preservation information of the previously stored command includes the first write address, the current command identifier, and the sequence number.

[0010] In one specific implementation, the order management module further includes a response information caching submodule; The second control submodule is specifically used for: Compare the release address with the write address in each sequence-preserving information in the sequence-preserving information storage submodule; If the release address does not match the write address in any of the order preservation information, the response information and the corresponding command identifier are sent to the master device. If the release address matches the write address in any of the sequence information in the sequence information storage submodule, then the response information is cached in the response information caching submodule. The sequence number in any of the sequence information is obtained. If the sequence number in any of the sequence information is the minimum value among all sequence information with the same command identifier, then the response information and the corresponding command identifier are sent to the master device. Otherwise, the response information and the corresponding command identifier are sent to the master device only after all response information with the same command identifier and a smaller sequence number have been sent to the master device.

[0011] In one specific implementation, the order management module further includes a return status storage submodule, which is used to store the return status value of the response information of each command; The return status includes at least a first status value, a second status value, and a third status value; the first status value indicates that the response information of the corresponding command has not yet been returned from the slave device; the second status value indicates that the response information of the corresponding command has been returned from the slave device, but is not yet allowed to be sent to the master device; the third status value indicates that the response information of the corresponding command has been returned from the slave device and is allowed to be sent to the master device.

[0012] In one specific implementation, the second control submodule is specifically used for: After caching the response information in the response information caching submodule, the return status value corresponding to the response information is set to the second status value; If the release address matches the write address in any of the sequence information in the sequence information storage submodule, and the sequence number in any of the sequence information is the minimum value among all sequence information with the same command identifier, then the return status value corresponding to the response information is updated to the third status value, and the response information and the corresponding command identifier are sent to the master device according to the updated return status value.

[0013] In one specific implementation, the second control submodule is specifically used for: After sending each response message to the master device, the command identifier in the sequence information corresponding to the sent response message is obtained. All sequence information with the command identifier that has not yet been sent is traversed, and the sequence information with the smallest sequence number is obtained. The return status value of the response message corresponding to the sequence information is read. If the return status value is the second status value, the return status value is updated to the third status value, and the corresponding response message and command identifier are sent to the master device according to the updated return status value.

[0014] In one specific implementation, the return status further includes a fourth status value, which indicates that the response information for the corresponding command can be sent but has not yet been returned. The second control submodule is specifically used for: If the release address matches the write address in any of the order-preserving information in the order-preserving information storage submodule, then before caching the response information in the response information caching submodule, if the return status value corresponding to the response information is the fourth status value, then the return status value is updated to the third status value, and the response information and the corresponding command identifier are sent to the master device according to the updated return status value; otherwise, the response information is cached in the response information caching submodule, and the return status value corresponding to the response information is set to the second status value.

[0015] In one specific implementation, the second control submodule is specifically used for: After each response message is sent to the master device, the sequence information and return status value corresponding to the sent response message are marked as invalid, and the corresponding storage resources in the identifier storage submodule are released according to the release address corresponding to the sent response message, and the release address is sent to the command cache module. The first control submodule is used to release the corresponding storage resource in the command storage submodule according to the release address.

[0016] In one specific implementation, the response information caching submodule includes M caching units, each caching unit being used to store the response information and transmission status of a command, wherein the transmission status is used to indicate whether the corresponding response information has been successfully returned to the master device; The return status storage submodule includes M status units, each status unit is used to store the return status value of the response information of a command; The order preservation management module further includes a response vector bitmap, which includes M first flag bits; wherein, the M cache units, the M state units, and the M first flag bits correspond one-to-one, and M is a preset value; The second control submodule is also used for: When the return status value of the response information of any command is updated to the third status value, the first flag bit corresponding to the return status value of the response information of any command is set to the first preset value. When any first flag bit of the response vector bitmap is a first preset value, the response information and command identifier corresponding to the first flag bit are sent to the master device, and the release address is sent to the command cache module. After the response information, command identifier and release address are sent, the first flag bit is updated to a second preset value. Wherein, the first preset value indicates that the corresponding response information triggers a return to the main device, and the second preset value indicates that the corresponding response information does not trigger a return to the main device.

[0017] In one specific implementation, the order-preserving information storage submodule includes an order-preserving tag table and an order counting table; The order preservation tag table includes M tag units, each tag unit is used to store the write address and command identifier of an order preservation information; The sequential counting table includes M counting units, each of which stores a sequential number that preserves order information. Among them, the M cache units, the M state units, the M first flag bits, the M tag units, and the M calculation units correspond one-to-one.

[0018] In one specific implementation, the second control submodule is further configured to send the release address to the command cache module when sending the response information and the corresponding command identifier to the master device; The first control submodule is used to release the corresponding storage resource in the command storage submodule according to the release address.

[0019] In one specific implementation, the command storage submodule includes N command units, each of which is used to store one command; The identifier storage submodule includes N identifier units, each identifier unit is used to store a command identifier; The N command units and the N identification units correspond one-to-one; N is a preset value.

[0020] In one specific implementation, the first control submodule includes a comparison logic submodule, a write address translation unit, a read address translation unit, and a release address translation unit; The comparison logic submodule is used to maintain an idle vector bitmap and a valid vector bitmap, obtain the current write vector based on the idle vector bitmap, and obtain the current read vector based on the valid vector bitmap. The idle vector bitmap includes N second flag bits, each corresponding to one of the N command units. When a second flag bit is at a first preset value, it indicates that the corresponding command unit is idle; when a second flag bit is at a second preset value, it indicates that the corresponding command unit is occupied. The valid vector bitmap includes N third flag bits, each corresponding to one of the N command units. When a third flag bit is at a first preset value, it indicates that there is a command to be read in the corresponding command unit; when a third flag bit is at a second preset value, it indicates that there is no command to be read in the corresponding command unit.

[0021] The write address conversion unit is used to convert the current write vector from one-hot code to binary format to generate the current write address; The read address conversion unit is used to convert the current read vector from one-hot code to binary format to generate the current read address; The release address conversion unit is used to convert the release address from binary format to one-hot code to generate a release vector; The comparison logic submodule is further configured to update the free vector bitmap based on the release vector and the current write vector, and update the valid vector bitmap based on the current write vector and the current read vector.

[0022] According to a second aspect, embodiments of this application provide a master-slave communication system, including a master device, a slave device, and a sequence-preserving processing device as described in the first aspect, wherein the sequence-preserving processing device is coupled between the master device and the slave device; The master device is used to send the current command and the current command identifier to the sequence preservation processing device, and to receive the response information and the corresponding command identifier returned by the sequence preservation processing device. The slave device is used to receive the current read address output by the sequence-preserving processing device, send a read request to the sequence-preserving processing device according to the current read address to read the target command from the sequence-preserving processing device, execute the target command, and return the corresponding response information and release address to the sequence-preserving processing device; the release address is the current read address.

[0023] In one specific implementation, the first control submodule is used to output a full signal to the main device when all command units in the command storage submodule are occupied. The master device is also used to pause issuing commands and command identifiers to the sequence-keeping processing device based on the full signal.

[0024] In one specific implementation, the first control submodule is used to output an empty signal to the slave device when there are no commands to be read in all command units of the command storage submodule; The slave device is also used to suspend sending read requests to the sequence-preserving processing device based on the empty signal.

[0025] The sequence-preserving processing device and master-slave communication system according to the embodiments of this application have the following beneficial effects: The second control submodule writes the current command identifier to the identifier storage submodule based on the current write address, and generates the order preservation information of the current command based on the number of current command identifiers in the identifier storage submodule. The order preservation information of the current command is then stored in the order preservation information storage submodule. The order preservation information of the current command includes the current write address, the current command identifier, and a sequence number. When the slave device returns response information and a release address, the second control submodule matches the order preservation information with the release address and determines whether to send the response information and the corresponding command identifier to the master device based on the sequence number in the matched order preservation information. At least two commands with the same command identifier are sorted by the sequence number in the order preservation information, indicating the sending order of at least two commands with the same command identifier. Therefore, it can be guaranteed that response information with the same command identifier is returned to the master device in the sending order, solving the problem that multiple commands with the same command identifier cannot be uniquely matched when the response information only carries the command identifier. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings required in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a schematic diagram of the structure of a sequence-preserving processing device in one embodiment of this application.

[0028] Figure 2 This is a schematic diagram of the structure of a sequence management module in one embodiment of this application.

[0029] Figure 3 This is a schematic diagram of the structure of a sequence-preserving information storage submodule in one embodiment of this application.

[0030] Figure 4 This is a schematic diagram of the structure of a command caching module in one embodiment of this application.

[0031] Figure 5 This is a schematic diagram of the structure of a master-slave communication system in one embodiment of this application.

[0032] Figure label: 1- Sequence Preservation Processing Device; 11- Command Cache Module; 111- First Control Submodule; 1111- Comparison Logic Submodule; 1112- Write Address Translation Unit; 1113- Read Address Translation Unit; 1114- Release Address Translation Unit; 112- Command Storage Submodule; 12- Sequence Preservation Management Module; 121- Second Control Submodule; 122- Identifier Storage Submodule; 123- Sequence Preservation Information Storage Submodule; 1231- Sequence Preservation Tag Table; 1232- Sequence Count Table; 124- Response Information Cache Submodule; 125- Return Status Storage Submodule; 126- Response Vector Bitmap; 13- Write Interface Module; 14- Response Interface Module; 15- Read Interface Module; 16- Release Interface Module; 2- Master Device; 3- Slave Device. Detailed Implementation

[0033] The detailed description of the accompanying drawings is intended to illustrate embodiments of this application and is not intended to represent only the forms in which this application can be implemented. It should be understood that the same or equivalent functionality can be achieved by different embodiments intended to be included within the spirit and scope of this application.

[0034] Please see Figure 1 One embodiment of this application proposes an order-preserving processing device, including a command caching module and an order-preserving management module; The command caching module includes a first control submodule and a command storage submodule; The first control submodule is used to receive the current command and current command identifier issued by the master device, obtain the current write address, write the current command into the command storage submodule according to the current write address, and send the current write address and the current command identifier to the order preservation management module; it is also used to obtain the current read address and send the current read address to the slave device; The command storage submodule is used to store the current command and to send the current command to the slave device in response to a read request from the slave device; The sequence management module includes a second control submodule, an identifier storage submodule, and a sequence information storage submodule; The second control submodule is used to write the current command identifier into the identifier storage submodule according to the current write address, generate the order preservation information of the current command according to the number of current command identifiers in the identifier storage submodule, and store the order preservation information of the current command into the order preservation information storage submodule; wherein the order preservation information of the current command includes the current write address, the current command identifier, and the sequence number; The second control submodule is also used to receive response information and release address returned by the device, match the release address with the write address in each sequence information in the sequence information storage submodule, and if there is a matching sequence information, determine whether to send the response information and the corresponding command identifier to the master device according to the sequence number in the matching sequence information.

[0035] Specifically, the sequence preservation processing device is coupled between the master device and the slave device, and the workflow of the sequence preservation processing device includes the command issuance stage, the command reading stage, and the response return stage.

[0036] The command issuance phase includes: The master device issues the current command and its identifier. Upon receiving the current command and identifier, the first control submodule of the command cache module allocates a free storage address for the current command; this address is called the current write address. The first control submodule then writes the current command into the command storage submodule based on the current write address. Simultaneously, the first control submodule sends the current write address and the current command identifier to the sequence management module.

[0037] After receiving the current write address and the current command identifier, the second control submodule of the sequence management module writes the current command identifier to the identifier storage submodule based on the current write address. After writing, the second control submodule counts the number of the current command identifier in the identifier storage submodule and determines whether to generate sequence information for the current command based on this count. If so, the generated sequence information is stored in the sequence information storage submodule. This sequence information includes the current write address, the current command identifier, and a sequence number, where the sequence number corresponds to the number of current command identifiers in the identifier storage submodule. This application does not limit the specific implementation method for determining whether to generate sequence information based on this count; it can be implemented through various specific logic.

[0038] For example, in the first implementation, the master device sends three commands consecutively. The command identifier for the first command is A, the command identifier for the second command is B, and the command identifier for the third command is A. When the second control submodule receives the first command, it writes command identifier A into the identifier storage submodule, counts the number of command identifier A in the identifier storage submodule as 1, and generates the order-preserving information for the first command based on this count, with a sequence number of 0. When the second control submodule receives the second command, it writes command identifier B into the identifier storage submodule, counts the number of command identifier B in the identifier storage submodule as 1, and generates the order-preserving information for the second command based on this count, with a sequence number of 0. When the second control submodule receives the third command, it writes command identifier A into the identifier storage submodule, counts the number of command identifier A in the identifier storage submodule as 2, and generates the order-preserving information for the third command based on this count, with a sequence number of 1. In this implementation, each command has order-preserving information. The order-preserving information can be matched with the returned response information, and the sequence number of the matched order-preserving information determines whether to return the response information to the master device.

[0039] For example, in the second implementation, the master device sends three commands consecutively. The command identifier for the first command is A, the command identifier for the second command is B, and the command identifier for the third command is A. When the second control submodule receives the first command, it writes command identifier A to the identifier storage submodule, counts the number of command identifier A in the identifier storage submodule as 1, and does not generate sequence information. When the second control submodule receives the second command, it writes command identifier B to the identifier storage submodule, counts the number of command identifier B in the identifier storage submodule as 1, and does not generate sequence information. When the second control submodule receives the third command, it writes command identifier A to the identifier storage submodule, counts the number of command identifier A in the identifier storage submodule as 2, and generates sequence information for the third command with a sequence number of 1. In this implementation, if the returned response information does not match sequence information, the response information corresponds to a command for which no sequence information was generated. If the returned response information matches sequence information, the sequence number of the matched sequence information determines whether to return the response information to the master device.

[0040] For example, in the third implementation, the master device consecutively issues three commands: the first command is identified by command identifier A, the second by command identifier B, and the third by command identifier A. When the second control submodule receives the first command, it writes command identifier A to the identifier storage submodule, counts the number of command identifiers A in the identifier storage submodule as 1, and does not generate sequence information. When the second control submodule receives the second command, it writes command identifier B to the identifier storage submodule, counts the number of command identifiers B in the identifier storage submodule as 1, and does not generate sequence information. When the second control submodule receives the third command, it writes command identifier A to the identifier storage submodule, counts the number of command identifiers A in the identifier storage submodule as 2, generates sequence information for the third command with a sequence number of 1, and simultaneously generates sequence information for the first command with a sequence number of 0. In this implementation, commands with conflicting command identifiers have sequence information, while commands without conflicting command identifiers do not have sequence information.

[0041] The command reading phase includes: The first control submodule obtains the current read address and sends it to the slave device. The slave device sends a read request to the command storage submodule based on the current read address. In response to the read request, the command storage submodule retrieves the corresponding target command from its storage and sends it to the slave device. The slave device receives and executes the target command.

[0042] The response return phase includes: After executing the target command, the slave device returns the corresponding response information and release address to the second control submodule. This release address is the current read address obtained by the slave device when executing the target command. The second control submodule searches for matching sequence information in the sequence information storage submodule based on this release address. If the release address is the same as the write address in the sequence information, a match is found. If a matching sequence information is found, the second control submodule determines whether to send the response information and the corresponding command identifier to the master device based on the sequence number in the matching sequence information.

[0043] Continuing from the previous example, in the first implementation, each command has sequence information. The sequence information can be matched based on the currently returned response information. Other sequence information with the same command identifier can be found based on the command identifier of the matched sequence information. The sequence number of the matched sequence information and the sequence number of other sequence information with the same command identifier can be compared to determine whether to return the currently returned response information to the master device. Continuing from the previous example, in the second implementation, the first command that did not send a command identifier conflict or had a command identifier conflict does not have order preservation information. The order preservation information can be matched based on the currently returned response information. If no matching order preservation information exists, it means that the command corresponding to the currently returned response information did not send a command identifier conflict or is the first command that had a command identifier conflict. Therefore, the corresponding command identifier can be obtained from the identifier storage submodule based on the release address, and then the currently returned response information and the corresponding command identifier can be directly returned to the master device. If matching order preservation information exists, other order preservation information with the same command identifier can be searched based on the command identifier of the matching order preservation information. The sequence number of the matching order preservation information and the sequence number of other order preservation information with the same command identifier are compared to determine whether to return the currently returned response information to the master device. Continuing the previous example, in the third implementation, commands without conflicting command identifiers do not have order preservation information, while commands with conflicting command identifiers each have order preservation information. Therefore, the processing method is the same as in the second implementation. Order preservation information can be matched against the currently returned response information. If no matching order preservation information exists, it means that the command corresponding to the currently returned response information did not have a conflicting command identifier. Therefore, the corresponding command identifier can be obtained from the identifier storage submodule based on the release address, and then the currently returned response information and the corresponding command identifier can be directly returned to the master device. If matching order preservation information exists, other order preservation information with the same command identifier is searched based on the command identifier of the matching order preservation information. The sequence number of the matching order preservation information is compared with the sequence number of other order preservation information with the same command identifier to determine whether to return the currently returned response information to the master device.

[0044] In this embodiment, the second control submodule writes the current command identifier to the identifier storage submodule based on the current write address, and generates sequence information containing the current write address, the current command identifier, and a sequence number based on the number of current command identifiers in the identifier storage submodule. When the slave device returns response information and a release address, the second control submodule matches the sequence information with the release address, and determines whether to send the response information and the corresponding command identifier to the master device based on the sequence number in the matched sequence information. At least two commands with the same command identifier are sorted by the sequence number in the sequence information. Since the sequence number identifies the sending order of at least two commands with the same command identifier, it can be guaranteed that response information with the same command identifier is returned to the master device in the sending order, solving the problem that multiple commands with the same command identifier cannot be uniquely matched when the response information only carries the command identifier.

[0045] In some embodiments, the second control submodule is specifically used for: If the number of current command identifiers in the identifier storage submodule is greater than or equal to 2, then the sequence number is determined according to the number of current command identifiers, and the order preservation information of the current command is generated according to the sequence number, the current write address, and the current command identifier; otherwise, the order preservation information of the current command is not generated.

[0046] Specifically, after writing the current command identifier to the identifier storage submodule, the second control submodule counts the number of such current command identifiers in the identifier storage submodule. If the count is greater than or equal to 2, the second control submodule determines the sequence number of the current command based on this count. The sequence number is used to identify the sending order of multiple commands with the same command identifier. The second control submodule generates the order-keeping information for the current command based on the current write address, the current command identifier, and the sequence number, and stores it in the order-keeping information storage submodule. If the count of the current command identifier in the identifier storage submodule is 1, the second control submodule does not generate the order-keeping information for the current command.

[0047] For example, the master device issues three commands consecutively. The command identifier for the first command is A, the command identifier for the second command is B, and the command identifier for the third command is A. When the second control submodule receives the first command, it writes command identifier A to the identifier storage submodule, counts the number of command identifier A in the identifier storage submodule as 1, and does not generate sequence information. When the second control submodule receives the second command, it writes command identifier B to the identifier storage submodule, counts the number of command identifier B in the identifier storage submodule as 1, and does not generate sequence information. When the second control submodule receives the third command, it writes command identifier A to the identifier storage submodule, counts the number of command identifier A in the identifier storage submodule as 2. Since the number is greater than or equal to 2, the second control submodule determines the sequence number of the current command as 1 based on this count, generates the sequence information for the third command, and stores it in the sequence information storage submodule. The sequence information for the third command includes the current write address, command identifier A, and sequence number 1.

[0048] For example, the master device sends four commands consecutively, with command identifiers A, B, A, and A respectively. When the second control submodule receives the fourth command, it counts the number of command identifier A in the identifier storage submodule and finds it to be 3, which is greater than or equal to 2. Based on this count, the second control submodule determines the current command's sequence number to be 2, generates the sequence information for the fourth command, and stores it in the sequence information storage submodule.

[0049] During the response return phase, after the slave device returns the response information and release address, the second control submodule matches the release address with the write addresses in each sequence information in the sequence information storage submodule. If a matching sequence information is found, the second control submodule determines whether to send the response information and the corresponding command identifier to the master device based on the sequence number in that sequence information. If the release address does not match the write addresses of any sequence information in the sequence information storage submodule, it indicates that no sequence information was generated when the command was sent, and the second control submodule directly sends the response information and the corresponding command identifier to the master device.

[0050] In this embodiment, the second control submodule generates sequence-keeping information only when the number of current command identifiers in the identifier storage submodule is greater than or equal to 2; otherwise, it does not generate it. By creating sequence-keeping information on demand, it avoids allocating sequence-keeping information storage resources for individual commands in transit, reducing the storage space requirements of the sequence-keeping information storage submodule. Furthermore, for commands for which no sequence-keeping information has been generated, their response information is sent directly to the master device via a fast path without requiring sequence-keeping checks, thus reducing processing latency.

[0051] In some embodiments, the second control submodule is specifically used for: In some embodiments, the second control submodule is specifically used for: If the number of current command identifiers in the identifier storage submodule is equal to 2, then a first write address is obtained based on the storage address of a previously stored current command identifier in the identifier storage submodule. The order preservation information of the previously stored command is generated based on the first write address and the current command identifier, and the order preservation information of the previously stored command is stored in the order preservation information storage submodule. The order preservation information of the previously stored command includes the first write address, the current command identifier, and the sequence number.

[0052] Specifically, when the second control submodule detects that the number of current command identifiers in the identifier storage submodule is 2, it indicates that the current command is the second command with that identifier, meaning a command identifier conflict has occurred for the first time. At this point, the identifier storage submodule has already stored an identical command identifier, which corresponds to the first command, and its storage location is the write address of the first command.

[0053] The second control submodule obtains the first write address based on the command identifier of the first command's storage location in the identifier storage submodule. This first write address is the storage address of the first command in the command storage submodule. The second control submodule then generates the order preservation information for the first command based on the first write address and the command identifier, and stores it in the order preservation information storage submodule. This order preservation information includes the first write address, the command identifier, and the sequence number.

[0054] Simultaneously, the second control submodule generates sequence-preserving information for the current command (the second command), including the current write address, command identifier, and sequence number. The sequence number of the first command is different from that of the second command, used to distinguish the order in which the two commands were sent.

[0055] For example, the master device issues two commands. The first command, identified as A, is written to address 3 of the command storage submodule, and command identifier A is stored at position 3 of the identifier storage submodule. The second command, also identified as A, is written to address 7 of the command storage submodule, and command identifier A is stored at position 7 of the identifier storage submodule. When the second control submodule receives the second command, it counts the number of command identifiers A in the identifier storage submodule as 2, assigns sequence number 0 to the first command, and sequence number 1 to the second command. The sequence information for the first command includes the write address 3, command identifier A, and sequence number 0. The sequence information for the second command includes the write address 7, command identifier A, and sequence number 1.

[0056] For example, the master device issues three commands: the first command is identified by command A, the second by command B, and the third by command A. When the second control submodule receives the third command, it counts that the number of commands with command identifier A in the identifier storage submodule is 2. It then adds sequence information for the first command (command identifier A) with a sequence number of 0, and simultaneously generates sequence information for the third command with a sequence number of 1. The second command (command identifier B) has a count of 1 in the identifier storage submodule, and no sequence information is generated.

[0057] During the response return phase, after the device returns the response information and release address, the second control submodule matches the release address with the write addresses in the sequence information stored in the sequence information storage submodule. Since the response information for both the first and second commands matches the corresponding sequence information, the second control submodule determines the sending order based on the sequence number, sending the response information with sequence number 0 first, followed by the response information with sequence number 1.

[0058] In this embodiment, when a command identifier conflict is detected for the first time (i.e., the current number of command identifiers in the identifier storage submodule is 2), the second control submodule adds order preservation information for the first command, ensuring that both the first command and the currently conflicting command have order preservation information. This order preservation information addition mechanism ensures that even if order preservation information is not generated when the first command is issued, subsequent response information can still be processed in order. Simultaneously, the addition mechanism ensures that the number of order preservation information entries for the same command identifier in the order preservation information storage submodule is consistent with the number of entries for that command identifier in the identifier storage submodule, ensuring that all commands with the same command identifier have order preservation information, facilitating order management during response return. In some embodiments, please refer to... Figure 2The order management module may further include a response information caching submodule; In the embodiment applying the above-mentioned mechanism for supplementing and maintaining order information, the second control submodule is specifically used for: Compare the release address with the write address in each sequence-preserving information in the sequence-preserving information storage submodule; If the release address does not match the write address in any of the order preservation information, the response information and the corresponding command identifier are sent to the master device. If the release address matches the write address in any of the sequence information in the sequence information storage submodule, then the response information is cached in the response information caching submodule. The sequence number in any of the sequence information is obtained. If the sequence number in any of the sequence information is the minimum value among all sequence information with the same command identifier, then the response information and the corresponding command identifier are sent to the master device. Otherwise, the response information and the corresponding command identifier are sent to the master device only after all response information with the same command identifier and a smaller sequence number have been sent to the master device.

[0059] Specifically, the second control submodule first compares the release address with the write addresses in the sequence-preserving information storage submodule. Based on the comparison result, the second control submodule selects either the fast path or the slow path.

[0060] If the release address does not match the write addresses of all sequence-keeping information in the sequence-keeping information storage submodule, it indicates that no command identifier conflict occurred during the transmission of the command, and no sequence-keeping processing is required. The second control submodule follows the fast path, directly sending the response information and the corresponding command identifier to the master device. The corresponding command identifier is read from the identifier storage submodule using the release address.

[0061] For example, if only one command with command identifier B is being processed, after the slave device returns the response information and release address of the command, if the second control submodule cannot find the sequence information that matches the release address in the sequence information storage submodule, it will directly send the response information and command identifier B to the master device.

[0062] If the release address matches the write address of a sequence-preserving message in the sequence-preserving information storage submodule, it indicates that a command identifier conflict occurred during the transmission of the command, requiring sequence preservation processing. The second control submodule follows the slow path, caching the response information in the response information cache submodule, and then retrieves the sequence number from the sequence-preserving information.

[0063] The second control submodule iterates through all sequence-preserving information entries with the same command identifier in the sequence-preserving information storage submodule and compares the sequence numbers in each sequence-preserving information entry. If the sequence number in the currently matched sequence-preserving information entry is the minimum value among all sequence-preserving information entries with the same command identifier, it means that the response information for that command should be returned first in order, and the second control submodule sends the response information and the corresponding command identifier to the master device.

[0064] If the sequence number in the currently matched sequence information is not the minimum value, it means that although the response information for this command has been returned, there are still commands with the same command identifier that were sent earlier and have not yet returned. The second control submodule does not send this response information temporarily, but keeps it in the response information cache submodule. It waits until all response information with the same command identifier and a smaller sequence number has been sent to the master device before sending this response information and its corresponding command identifier to the master device.

[0065] For example, three commands, each with the identifier A, are sequentially numbered 0, 1, and 2. The slave device first returns a response message with sequential number 1, which the second control submodule caches in the response message cache submodule without sending it. Subsequently, the slave device returns a response message with sequential number 0, which the second control submodule sends to the master device. Then, it retrieves the response message with sequential number 1 from the cache and sends it to the master device.

[0066] In this embodiment, by setting up a response information caching submodule, when response information has been returned but cannot be sent due to its out-of-order sequence, the response information is temporarily stored, ensuring that the feedback channel of the slave device is not blocked. The slave device can continue to process the return of subsequent commands, improving the system's concurrency performance. Simultaneously, through the splitting of fast and slow paths, response information without command identifier conflicts can be directly returned to the master device, reducing unnecessary sorting processing delays.

[0067] In some embodiments, please refer to Figure 2 The order management module may further include a return status storage submodule, which is used to store the return status value of the response information of each command; The return status includes at least a first status value, a second status value, and a third status value; the first status value indicates that the response information of the corresponding command has not yet been returned from the slave device; the second status value indicates that the response information of the corresponding command has been returned from the slave device, but is not yet allowed to be sent to the master device; the third status value indicates that the response information of the corresponding command has been returned from the slave device and is allowed to be sent to the master device.

[0068] Specifically, the return status storage submodule records the current return status of the response information for each command. The return status storage submodule has the same storage depth as the sequence preservation information storage submodule, and each status unit corresponds to one sequence preservation information.

[0069] The return status includes a first status value, a second status value, and a third status value. The first status value indicates that the response information for the corresponding command has not yet been returned from the slave device. When the second control submodule generates sequence information, it initializes the status unit corresponding to that sequence information to the first status value.

[0070] For example, if the master device issues a command with the identifier A, after the second control submodule generates the sequence information, it sets the status unit corresponding to the sequence information to the first status value, indicating that the response information of the command has not yet been returned from the slave device.

[0071] The second status value indicates that the response information for the corresponding command has been returned from the slave device, but it is not yet allowed to be sent to the master device. When the slave device returns the response information, and the second control submodule caches the response information in the response information cache submodule, the second control submodule updates the corresponding status unit to the second status value.

[0072] For example, if the device returns a response message with command identifier A and sequence number 1, but the response message with sequence number 0 has not yet been returned, the second control submodule will cache the response message and update the corresponding status unit to the second status value.

[0073] The third status value indicates that the response information for the corresponding command has been returned from the slave device and can be sent to the master device. When the second control submodule confirms that the sequence number of the command is the minimum value among all the sequence information of the same command identifier, the second control submodule updates the corresponding status unit to the third status value, and then sends the response information to the master device according to the status value.

[0074] The first, second, and third state values ​​can be encoded in binary; for example, the first state value is 00, the second state value is 01, and the third state value is 11. In the hardware implementation, the state values ​​are stored in a 2-bit register, allowing for state reading and updating within one clock cycle.

[0075] In this embodiment, the return status of each command's response information is recorded and tracked by the return status storage submodule. The second control submodule can know in real time whether the response information of the command corresponding to each order-keeping information has been returned and whether sending is allowed, providing a foundation for the state-driven chained wake-up mechanism. Simultaneously, the status value is stored using a 2-bit register, enabling status reading and updating to be completed within a single cycle, reducing processing latency.

[0076] In some embodiments, the second control submodule is specifically used for: After caching the response information in the response information caching submodule, the return status value corresponding to the response information is set to the second status value; If the release address matches the write address in any of the sequence information in the sequence information storage submodule, and the sequence number in any of the sequence information is the minimum value among all sequence information with the same command identifier, then the return status value corresponding to the response information is updated to the third status value, and the response information and the corresponding command identifier are sent to the master device according to the updated return status value.

[0077] Specifically, when the slave device returns response information and a release address, and the second control submodule matches the corresponding ordering information based on the release address, the second control submodule caches the response information in the response information cache submodule. After caching, the second control submodule sets the return status value corresponding to the response information to a second status value. The second status value indicates that the response information has been returned from the slave device, but it is not yet allowed to be sent to the master device.

[0078] Subsequently, the second control submodule obtains the sequence number from the matched sequence information, traverses all sequence information with the same command identifier, and determines whether the sequence number is the minimum value.

[0079] If the sequence number is the minimum value, the second control submodule updates the return status value corresponding to the response information from the second status value to the third status value. The third status value indicates that the response information has been returned from the slave device and can be sent to the master device. Then, the second control submodule sends the response information and the corresponding command identifier to the master device according to the updated third status value. The first control submodule releases the corresponding storage resource in the command storage submodule according to the release address.

[0080] If the sequence number is not the minimum value, the second control submodule maintains the return status value corresponding to the response information as the second status value and does not send it. The response information remains in the response information buffer submodule, waiting for all response information with the same command identifier and a smaller sequence number to be sent before sending it.

[0081] In this embodiment, the "returned but not sent" status of the response information and the "returned and allowed to send" status are distinguished by setting and updating the return status value. When the sequence number is the minimum value, the second control submodule updates the status value from the second status value to the third status value and triggers the sending, simplifying the decision to send the response information to the judgment of the status value. It eliminates the need to re-traverse and compare all sequence numbers every time the information is sent, thus reducing processing latency.

[0082] In some embodiments, the second control submodule is specifically used for: After sending each response message to the master device, the command identifier in the sequence information corresponding to the sent response message is obtained. All sequence information with the command identifier that has not yet been sent is traversed, and the sequence information with the smallest sequence number is obtained. The return status value of the response message corresponding to the sequence information is read. If the return status value is the second status value, the return status value is updated to the third status value, and the corresponding response message and command identifier are sent to the master device according to the updated return status value.

[0083] Specifically, after sending each response message to the master device, the second control submodule retrieves the command identifier from the sequence information corresponding to the sent response message. Then, the second control submodule iterates through all sequence information with that command identifier in the sequence information storage submodule, filters out the sequence information that has not yet been sent, and retrieves the sequence information with the smallest sequence number.

[0084] The second control submodule reads the return status value of the response information corresponding to the sequence information. If the return status value is the second status value, it means that the response information has been returned from the slave device and is cached in the response information cache submodule, but has not been sent because the order has not yet come. At this time, the second control submodule updates the return status value to the third status value, and sends the corresponding response information and command identifier to the master device according to the updated third status value.

[0085] For example, three commands with the same identifier "A" have sequence numbers 0, 1, and 2, respectively. After the response information with sequence number 0 is sent, the second control submodule iterates through all the sequence information with the identifier "A" in the sequence information storage submodule. It finds that the sequence information with sequence number 1 has not yet been sent and reads its return status value. If the return status value is the second status value, it indicates that the response information has been cached in the response information cache submodule. The second control submodule then updates this status value to the third status value and sends the response information to the master device.

[0086] After the transmission is completed, the second control submodule continues to perform the above traversal operation to find the next unsent sequence information with the smallest sequence number, thereby realizing the chained sequential transmission of response information with the same command identifier.

[0087] In this embodiment, a chained wake-up mechanism is used to automatically traverse and trigger the sending of the next response information with the smallest sequence number after each response information is sent. This achieves automatic sequential return of response information with the same command identifier without the need for additional intervention from the master or slave device, thus improving the system's automation processing capability.

[0088] In some embodiments, the return status further includes a fourth status value, which indicates that the response information for the corresponding command can be sent but has not yet been returned; The second control submodule is specifically used for: If the release address matches the write address in any of the order-preserving information in the order-preserving information storage submodule, then before caching the response information in the response information caching submodule, if the return status value corresponding to the response information is the fourth status value, then the return status value is updated to the third status value, and the response information and the corresponding command identifier are sent to the master device according to the updated return status value; otherwise, the response information is cached in the response information caching submodule, and the return status value corresponding to the response information is set to the second status value.

[0089] Specifically, the fourth status value indicates that the response information for the corresponding command can be sent, but the response information has not yet been returned. During the chained wake-up process, if the second control submodule encounters a sequence-keeping message with the current minimum sequence number, but its corresponding return status value is the first status value, it means that the command has been qualified to be sent, but the response information has not yet returned from the slave device. At this time, the second control submodule updates the return status value to the fourth status value. The fourth status value is a pre-acknowledgment status, indicating that the turn has come, but the data has not yet arrived.

[0090] For example, three commands, each with the identifier A, are numbered 0, 1, and 2 respectively. After the response information for command number 0 is sent, the second control submodule iterates through the system and finds that the return status value corresponding to the sequence-keeping information with command number 1 is the first status value, indicating that the response information for that command has not yet been returned from the slave device. The second control submodule updates this return status value to the fourth status value and stops iterating.

[0091] When the response information for the command is subsequently returned from the slave device, the second control submodule matches the corresponding ordering information based on the release address. Before caching the response information in the response information caching submodule, the second control submodule first reads the return status value corresponding to the ordering information.

[0092] If the returned status value is the fourth status value, it indicates that the command has been qualified to be sent, and there is no need to check the minimum sequence number again. The second control submodule directly updates the returned status value to the third status value and sends the response information and the corresponding command identifier to the master device based on the updated third status value. This eliminates the need to iterate and compare the sequence numbers again.

[0093] For example, when the response information with sequence number 1 returns from the slave device, if the second control submodule reads that the corresponding return status value is the fourth status value, it will directly update the status value to the third status value and send the response information.

[0094] If the returned status value is not the fourth status value, the second control submodule will process it according to the normal procedure, that is, cache the response information in the response information cache submodule, set the corresponding return status value to the second status value, and then perform the minimum value judgment of the sequence number.

[0095] In this embodiment, by introducing a fourth state value, the intermediate state of "the order has been reached but the data has not yet arrived" is recorded, thus decoupling "data arrival" from "sending qualification confirmation". When the response information is returned, if the corresponding state value is the fourth state value, there is no need to perform the minimum order number judgment again, and the response information is sent directly, reducing the overhead of repeated traversal and comparison, and reducing processing latency and power consumption.

[0096] In some embodiments, the second control submodule is specifically used for: After each response message is sent to the master device, the sequence information and return status value corresponding to the sent response message are marked as invalid, and the corresponding storage resources in the identifier storage submodule are released according to the release address corresponding to the sent response message, and the release address is sent to the command cache module. The first control submodule is used to release the corresponding storage resource in the command storage submodule according to the release address.

[0097] Specifically, the second control submodule performs the following operations after sending each response message to the master device.

[0098] First, the second control submodule marks the sequence information and return status value corresponding to the sent response information as invalid. The sequence information is stored in the sequence information storage submodule, and the return status value is stored in the return status storage submodule. Marking these stored entries as invalid sets them to an invalid state so that they can be reused by new sequence information later.

[0099] Secondly, the second control submodule releases the corresponding storage resource in the identifier storage submodule based on the release address corresponding to the sent response information. The identifier storage submodule stores the command identifiers of commands in transit. The release operation clears or marks the command identifier at the corresponding position in the identifier storage submodule as invalid.

[0100] Simultaneously, the second control submodule sends a release address to the command cache module. Upon receiving the release address, the first control submodule of the command cache module releases the corresponding storage resources in the command storage submodule according to the release address. The release operation clears or marks the command data at the corresponding location in the command storage submodule as free.

[0101] For example, if the release address is 3, the first control submodule marks the command unit corresponding to address 3 in the command storage submodule as free, and sets the free vector bitmap mark bit corresponding to the command unit to the first preset value.

[0102] Through the above release operation, the resources related to the command in the identifier storage submodule, the sequence information storage submodule, the return status storage submodule, and the command storage submodule are all released, and these storage resources can be reused by subsequently issued new commands. In some embodiments, the response information caching submodule includes M caching units, each caching unit is used to store the response information and transmission status of a command, wherein the transmission status is used to indicate whether the corresponding response information has been successfully returned to the master device; The return status storage submodule includes M status units, each status unit is used to store the return status value of the response information of a command; See Figure 2 The order preservation management module may further include a response vector bitmap, which includes M first flag bits; wherein, the M cache units, the M state units, and the M first flag bits correspond one-to-one, and M is a preset value; The second control submodule is also used for: When the return status value of the response information of any command is updated to the third status value, the first flag bit corresponding to the return status value of the response information of any command is set to the first preset value. When any first flag bit of the response vector bitmap is a first preset value, the response information and command identifier corresponding to the first flag bit are sent to the master device, and the release address is sent to the command cache module. After the response information, command identifier and release address are sent, the first flag bit is updated to a second preset value. Wherein, the first preset value indicates that the corresponding response information triggers a return to the main device, and the second preset value indicates that the corresponding response information does not trigger a return to the main device.

[0103] Specifically, the response information caching submodule includes M cache units, where M is a preset value. Each cache unit stores the response information for one command, which includes the data returned by the slave device and the transmission status. The transmission status is a flag indicating whether the response information was successfully returned to the master device. If the slave device executes the command successfully, the transmission status is successful; if the slave device fails to execute the command, the transmission status is failed.

[0104] The return status storage submodule includes M status units, each corresponding to a cache unit to store the return status value of the response information for the corresponding command. This return status value can be a first status value, a second status value, a third status value, or a fourth status value; for specific meanings, please refer to the aforementioned embodiments.

[0105] The order preservation management module also includes a response vector bitmap. The response vector bitmap consists of M first flag bits, each corresponding one-to-one with a buffer unit and a status unit. The response vector bitmap is used to mark which buffer units contain response information that is ready to be sent and is waiting to be sent.

[0106] When the return status value of the response information for any command is updated to the third status value, the second control submodule sets the first flag bit corresponding to that command to a first preset value. The first preset value is, for example, 1, indicating that the response information has met the sending conditions and triggers a return to the master device.

[0107] The second control submodule monitors the response vector bitmap. When any of the first flag bits in the response vector bitmap is a first preset value, the second control submodule performs the following operations: sends the response information and command identifier corresponding to the first flag bit to the master device, and sends the release address to the command cache module. After the response information, command identifier, and release address are sent, the second control submodule updates the first flag bit to a second preset value. The second preset value is, for example, 0, indicating that the response information has been sent and no return operation is triggered.

[0108] For example, the response vector bitmap has 8 first flag bits, each corresponding to one of the 8 cache units. Currently, the 3rd first flag bit is 1. The second control submodule sends the response information from the 3rd cache unit and the corresponding command identifier to the master device, and sends the release address to the command cache module. After sending, the second control submodule updates the 3rd first flag bit to 0.

[0109] By using a response vector bitmap, the second control submodule can uniformly manage and trigger the transmission of response information in a bitmap manner, simplifying the transmission control logic. Simultaneously, the one-to-one correspondence between the M cache units, M status units, and M first flag bits allows the second control submodule to simultaneously access the cache unit, status unit, and flag bit corresponding to the same command via an index, improving parallel processing efficiency.

[0110] In some embodiments, such as Figure 3 As shown, the sequence information storage submodule includes a sequence label table and a sequence count table; The order preservation tag table includes M tag units, each tag unit is used to store the write address and command identifier of an order preservation information; The sequential counting table includes M counting units, each of which stores a sequential number that preserves order information. Among them, the M cache units, the M state units, the M first flag bits, the M tag units, and the M calculation units correspond one-to-one.

[0111] Specifically, the write address is the storage address of the command in the command storage submodule, and the command identifier is the identifier carried by the master device when issuing the command.

[0112] The sequence number is a unique number assigned to a command by the second control submodule when a command identifier conflict is detected. It is used to distinguish the order in which multiple commands with the same command identifier are sent.

[0113] Each tag unit corresponds one-to-one with a counting unit, forming a sequence information entry. When the second control submodule generates a sequence information entry, the write address and command identifier of the sequence information are stored in a tag unit, and the sequence number of the sequence information is stored in the corresponding counting unit.

[0114] For example, the depth M of the sequence information storage submodule is 8. When the second control submodule generates sequence information for three commands with command identifier A, the three tag units store write address 3 and command identifier A, write address 7 and command identifier A, and write address 5 and command identifier A, respectively, and the three corresponding counting units store sequence numbers 0, 1, and 2, respectively.

[0115] Furthermore, each order-preserving information entry corresponds one-to-one with a cache unit, a status unit, and a first flag bit. Therefore, the M cache units, M status units, M first flag bits, M tag units, and M counting units are associated with the same index. By storing write addresses and command identifiers in the order-preserving tag table and sequence numbers in the sequence counting table, the identifier and sorting fields of the order-preserving information are stored separately. This allows the second control submodule to quickly match tag units by releasing addresses upon response and compare sequence numbers using the counting units during sorting, improving access efficiency. Simultaneously, the association of multiple tables with the same index supports parallel access and reduces processing latency.

[0116] In some embodiments, the second control submodule is further configured to send the release address to the command cache module when sending the response information and the corresponding command identifier to the master device; The first control submodule is used to release the corresponding storage resource in the command storage submodule according to the release address.

[0117] Specifically, when the second control submodule determines that a certain response information and its corresponding command identifier can be sent to the master device, the second control submodule performs a sending operation. The sending operation includes two parallel actions.

[0118] The first action is to send the response information and the corresponding command identifier to the master device. Upon receiving the response information and the corresponding command identifier, the master device knows that the command has been successfully executed.

[0119] The second action is to send the release address to the command cache module. This release address is the address returned after the command is executed by the device, and it is consistent with the storage address of the command in the command storage submodule. After receiving the release address, the first control submodule of the command cache module releases the corresponding storage resources in the command storage submodule according to the release address.

[0120] For example, if the address is 5, the first control submodule will release the command unit corresponding to address 5 in the command storage submodule, and this command unit can be written to by subsequent new commands.

[0121] Through the parallel operations described above, the sending of response information and the release of the command storage submodule occur simultaneously, reducing processing latency. The storage space released in the command storage submodule can be reused by subsequently issued commands, ensuring the continuous availability of storage resources and avoiding command issuance blockage due to storage resource exhaustion.

[0122] In some embodiments, the command storage submodule includes N command units, each command unit being used to store one command; The identifier storage submodule includes N identifier units, each identifier unit is used to store a command identifier; The N command units and the N identification units correspond one-to-one; N is a preset value.

[0123] Specifically, N is a preset value determined by the maximum number of Outstanding commands supported by the system. Each command unit stores one command issued by the master device. The N command units are arranged in address order, from 0 to N-1. The N identifier units are also arranged in address order, from 0 to N-1.

[0124] There is a one-to-one correspondence between the N command units and the N identifier units. Specifically, the command unit with index i corresponds to the identifier unit with index i. When a command is written to the command unit with index i, the command identifier of that command is written to the identifier unit with index i.

[0125] M represents the depth of the order preservation information storage submodule, determined by the maximum number of command identifier conflicts that may occur simultaneously in the system. M and N are independent and can be configured with different values. In hardware implementation, M can be less than or equal to N, depending on the system application scenario. Typically, M is less than N because not all in-transit commands will cause command identifier conflicts; order preservation information storage resources are only needed when multiple commands with the same command identifier are in transit simultaneously. For example, when the system supports 16 Outstanding commands (N), and the maximum number of commands with the same command identifier in transit simultaneously in the application is 4, M can be configured to 4, and the depth of the order preservation information storage submodule is only one-quarter of the depth of the command storage submodule.

[0126] Based on the above one-to-one correspondence, when the second control submodule needs to read the corresponding command identifier based on the release address, it can directly read it from the position with the same index as the release address in the identifier storage submodule without performing any additional lookup operations. Similarly, when the second control submodule needs to find the corresponding storage address based on the command identifier, it only needs to find the identifier unit where the command identifier is located in the identifier storage submodule, and the index of that identifier unit is the corresponding storage address.

[0127] In this embodiment, by decoupling the depth N of the command storage submodule and the depth M of the order-preserving information storage submodule, they can be configured with different values, resulting in a total storage requirement of N+M and a small chip area. Simultaneously, through the one-to-one correspondence between command units and identifier units, the second control submodule can directly index the corresponding command identifier through the release address, eliminating the need for additional lookup operations and improving processing efficiency during response return.

[0128] In some embodiments, please refer to Figure 4The first control submodule includes a comparison logic submodule, a write address translation unit, a read address translation unit, and a release address translation unit; The comparison logic submodule is used to maintain an idle vector bitmap and a valid vector bitmap, obtain the current write vector based on the idle vector bitmap, and obtain the current read vector based on the valid vector bitmap. The idle vector bitmap includes N second flag bits, each corresponding to one of the N command units. When a second flag bit is at a first preset value, it indicates that the corresponding command unit is idle; when a second flag bit is at a second preset value, it indicates that the corresponding command unit is occupied. The valid vector bitmap includes N third flag bits, each corresponding to one of the N command units. When a third flag bit is at a first preset value, it indicates that there is a command to be read in the corresponding command unit; when a third flag bit is at a second preset value, it indicates that there is no command to be read in the corresponding command unit.

[0129] The write address conversion unit is used to convert the current write vector from one-hot code to binary format to generate the current write address; The read address conversion unit is used to convert the current read vector from one-hot code to binary format to generate the current read address; The release address conversion unit is used to convert the release address from binary format to one-hot code to generate a release vector; The comparison logic submodule is further configured to update the free vector bitmap based on the release vector and the current write vector, and update the valid vector bitmap based on the current write vector and the current read vector.

[0130] Specifically, the idle vector bitmap includes N second flag bits, each corresponding to a command unit. When a second flag bit is a first preset value, such as 1, it indicates that the corresponding command unit is idle and can be written with a new command. When a second flag bit is a second preset value, such as 0, it indicates that the corresponding command unit is occupied and cannot be written with a new command.

[0131] The valid vector bitmap includes N third flag bits, each corresponding one-to-one with a command unit. When a third flag bit is a first preset value, such as 1, it indicates that there is a valid command waiting to be read by the slave device in the corresponding command unit. When a third flag bit is a second preset value, such as 0, it indicates that there is no valid command waiting to be read in the corresponding command unit.

[0132] The comparison logic submodule obtains the current write vector based on the free vector bitmap. The current write vector is in one-hot code format, meaning that only one bit out of N bits has a first preset value, and the remaining bits have a second preset value. This single bit indicates the target command unit for the next write operation. The comparison logic submodule obtains the current read vector based on the valid vector bitmap. The current read vector is also in one-hot code format, indicating the target command unit for the next read operation.

[0133] For example, the free vector bitmap is 8 bits, and the current value is 0b11111100, indicating that addresses 0 and 1 are occupied, and addresses 2 to 7 are free. The comparison logic submodule searches for the first bit that is 1 starting from the least significant bit, which is the bit corresponding to address 2, and generates the current write vector 0b00000100, indicating that the next write address is 2.

[0134] The write address translation unit receives the current write vector, converts it from one-hot code format to binary format, generates the current write address, and outputs it to the command storage submodule to control the address for write operations. The read address translation unit receives the current read vector, converts it from one-hot code format to binary format, generates the current read address, and outputs it to the command storage submodule and the slave device to control the address for read operations.

[0135] For example, if the current write vector is 0b00000100, the write address translation unit converts it to address 2 in binary format. If the current read vector is 0b00000010, the read address translation unit converts it to address 1 in binary format.

[0136] The release address translation unit receives the release address returned from the device, which is in binary format. The release address translation unit converts the binary format to one-hot code format, generates a release vector, and outputs it to the comparison logic submodule.

[0137] For example, if the release address is 3, the release address conversion unit converts it to 0b00001000 in one-hot code format.

[0138] The comparison logic submodule updates the free vector bitmap based on the release vector and the current write vector. Specifically, when a write operation is performed, the comparison logic submodule updates the second flag bit corresponding to the current write vector in the free vector bitmap to a second preset value, indicating that the command unit has been occupied. When a release operation is performed, the comparison logic submodule updates the second flag bit corresponding to the release vector in the free vector bitmap to a first preset value, indicating that the command unit has been released and is now free again.

[0139] For example, if the current free vector bitmap is 0b11111100 and the current write vector is 0b00000100, after the write operation is complete, the comparison logic submodule will update the free vector bitmap to 0b11111000, indicating that address 2 is occupied. When address 2 is released, the release vector is 0b00000100. After the release is complete, the comparison logic submodule will update the free vector bitmap to 0b11111100, indicating that address 2 is now free again.

[0140] The comparison logic submodule updates the valid vector bitmap based on the current write vector and the current read vector. Specifically, when a write operation is performed, the comparison logic submodule updates the third flag bit corresponding to the current write vector in the valid vector bitmap to a first preset value, indicating that there is a valid command to be read in this command unit. When a read operation is performed, the comparison logic submodule updates the third flag bit corresponding to the current read vector in the valid vector bitmap to a second preset value, indicating that the command in this command unit has been read and there are no more commands to be read.

[0141] For example, if the valid vector bitmap is currently 0b00000000, and the current write vector is 0b00000100, after the write operation is complete, the comparison logic submodule will update the valid vector bitmap to 0b00000100, indicating that there is a command to be read at address 2. If the current read vector is 0b00000100, after the read operation is complete, the comparison logic submodule will update the valid vector bitmap to 0b00000000, indicating that there is no longer a command to be read at address 2.

[0142] In this embodiment, the free and valid states of memory addresses are managed by a free vector bitmap and a valid vector bitmap, respectively, enabling independent allocation and reclamation of write and read addresses. The release operation only requires setting the corresponding marker position in the free vector bitmap to a first preset value, eliminating the need to move subsequent command data forward as a whole, thus avoiding the power waste caused by frequent data movement in traditional schemes. Furthermore, using one-hot code format for write and read vectors as pointers eliminates the overhead of maintaining read / write pointer registers, simplifying the address allocation logic.

[0143] In some embodiments, the order preservation processing device described in this application can be implemented in the following hardware manner: The command storage submodule in the command cache module can be implemented using a dual-port static random access memory (SRAM) or a register file to store command data issued by the master device. The identifier storage submodule can be implemented using SRAM or a register array to store command identifiers, with a storage depth consistent with the command storage submodule. The order-preserving tag table and sequence count table in the order-preserving information storage submodule can be implemented using a register array to support single-cycle parallel comparison and fast read / write operations. The return status storage submodule and the release vector bitmap can be implemented using a register array. The response information cache submodule can be implemented using SRAM or a register array.

[0144] The write address translation unit, read address translation unit, and release address translation unit can be implemented using combinational logic circuits to perform format conversion between one-hot codes and binary codes. The comparison logic submodule can be implemented using combinational logic circuits to maintain the free vector bitmap and the valid vector bitmap, and to generate write vectors and read vectors.

[0145] By adopting the above hardware implementation method, the order-preserving processing device of this application embodiment can flexibly select the type of storage device according to the specific application scenario while meeting performance requirements, so as to optimize chip area and power consumption.

[0146] Another embodiment of this application proposes a master-slave communication system, including a master device, a slave device, and an order-preserving processing device as described in the above embodiments, wherein the order-preserving processing device is coupled between the master device and the slave device; the master-slave communication system is, for example, a system-on-a-chip (SoC). The master device is used to send the current command and the current command identifier to the sequence preservation processing device, and to receive the response information and the corresponding command identifier returned by the sequence preservation processing device. The slave device is used to receive the current read address output by the sequence-preserving processing device, send a read request to the sequence-preserving processing device according to the current read address to read the target command from the sequence-preserving processing device, execute the target command, and return the corresponding response information and release address to the sequence-preserving processing device; the release address is the current read address.

[0147] Specifically, such as Figure 5 As shown, the sequence preservation processing device is coupled between the master device and the slave device, serving as an intermediate layer between them. The sequence preservation processing device communicates with the master device through the write interface module and the response interface module, and communicates with the slave device through the read interface module and the release interface module.

[0148] In the command issuing direction, the master device issues commands and command identifiers to the sequence-keeping processing unit. The sequence-keeping processing unit receives and caches the commands and command identifiers, and allocates storage addresses for the commands.

[0149] In the command read direction, the sequence-preserving processing unit outputs the current read address to the slave device. The slave device sends a read request to the sequence-preserving processing unit based on the current read address, and the sequence-preserving processing unit responds to the read request by sending the corresponding command to the slave device. The slave device then executes the command.

[0150] In the response return direction, after executing the command, the slave device returns response information and a release address to the sequence-preserving processing device. This release address is the current read address obtained by the slave device when executing the command. The sequence-preserving processing device performs sequence-preserving processing on the response information based on the release address, and then sends the response information and the corresponding command identifier to the master device.

[0151] For example, the master device issues three commands, all identified as 'A', stored at addresses 3, 7, and 5 respectively. After the slave device executes these commands, it first returns the response information corresponding to address 7, then the response information corresponding to address 5, and finally the response information corresponding to address 3. The sequence-preserving processing device matches the sequence-preserving information according to addresses 7, 5, and 3 in sequence, and sends the response information to the master device in the order of sequence numbers 0, 1, and 2.

[0152] In some embodiments, the first control submodule is configured to output a full signal to the master device when all command units in the command storage submodule are occupied; The master device is also used to pause issuing commands and command identifiers to the sequence-keeping processing device based on the full signal.

[0153] Specifically, the first control submodule monitors the occupancy status of each command unit in the command storage submodule. When all N command units in the command storage submodule are occupied, it indicates that the command storage submodule is full and cannot receive new commands. At this time, the first control submodule outputs a full signal to the master device. A full signal indicates that the sequence-keeping processing device cannot currently receive new commands. After receiving the full signal, the master device suspends the issuance of new commands and command identifiers to the sequence-keeping processing device. The master device remains in a waiting state until the full signal becomes invalid before resuming command issuance.

[0154] For example, if the command storage submodule has a depth N of 16, and all 16 command units are occupied, the first control submodule outputs a high-level full signal. Upon detecting the high-level full signal, the master device stops issuing new commands. When a command is completed and released, the first control submodule pulls the full signal low, and the master device resumes command issuance. Through this reverse pressure mechanism, the master device will not continue issuing commands when the sequence-keeping processing device is unable to receive new commands, thus preventing command loss.

[0155] In some embodiments, the first control submodule is configured to output an empty signal to the slave device when there are no commands to be read in all command units of the command storage submodule; The slave device is also used to suspend sending read requests to the sequence-preserving processing device based on the empty signal.

[0156] Specifically, the first control submodule monitors the validity status of each command unit in the command storage submodule. When all N command units in the command storage submodule have no commands to read, it indicates that the command storage submodule is empty and there are no commands available for the slave device to read. At this time, the first control submodule outputs an empty signal to the slave device. The empty signal is valid, indicating that the sequence-keeping processing device currently has no commands available for reading. After receiving the empty signal, the slave device suspends sending read requests to the sequence-keeping processing device. The slave device remains in a waiting state until the empty signal becomes invalid before resuming sending read requests.

[0157] For example, if the command storage submodule has a depth N of 16, and none of the 16 command units have a command to read, the first control submodule outputs a high-level empty signal. Upon detecting the high-level empty signal, the slave device stops sending read requests. When a new command is written, the first control submodule pulls the empty signal low, and the slave device resumes sending read requests. Through this reverse pressure mechanism, the slave device will not continue sending read requests when the sequence-keeping processing device has no commands to read, thus avoiding invalid operations.

[0158] In some embodiments, the master device has an internal receive buffer for temporarily storing response information and command identifiers returned from the sequencing processing device. When the receive buffer is full or the master device is processing other transactions, the master device lacks the ability to receive data. When there is free space in the receive buffer, the master device has the ability to receive data.

[0159] When the second control submodule determines that a certain response information and its corresponding command identifier can be sent, it performs the following operations.

[0160] Specifically, the second control submodule places the response information to be sent on the information data line, places the corresponding command identifier on the identifier data line, and then sets the valid signal line to a valid state, such as a high level, indicating that the sequence-keeping processing device currently has valid data to be sent.

[0161] The master device monitors the status of the ready signal line. The master device determines the status of the ready signal line based on the idle state of its receive buffer. If the master device has receiving capability, it sets the ready signal line to an active state, such as a high level. If the master device does not have receiving capability, it sets the ready signal line to an inactive state, such as a low level.

[0162] When both the valid signal line and the ready signal line are valid (e.g., both are high), the response information and command identifier are successfully latched and received by the master device within that clock cycle. The master device stores the received response information and command identifier in the receive buffer.

[0163] When the ready signal line is invalid, it indicates that the master device cannot currently receive data. The second control submodule keeps the valid signal line valid, while also keeping the response information on the information data line and the command identifier on the identifier data line unchanged, until the ready signal line becomes valid. During this process, the response information and command identifier will not be lost, and the sequence-preserving processing device will not overwrite or remove the data.

[0164] For example, the second control submodule prepares to send response information with sequence number 0 and command identifier A to the master device. It places the response information on the information data line, the command identifier A on the identifier data line, and sets the valid signal line to high. The master device's current receive buffer is full, so it keeps the ready signal line low. The second control submodule detects the low level of the ready signal line, maintains the current data state, and waits for the master device's receive buffer to become free. When the master device completes processing the previous data and the receive buffer becomes free, it sets the ready signal line high. The second control submodule detects the high level of the ready signal line, completes the data transmission within that clock cycle, and the response information and command identifier A are successfully received by the master device.

[0165] In this embodiment, through the handshake protocol between the valid signal line and the ready signal line, the sequence-keeping processing device only sends response information and the corresponding command identifier when the master device has receiving capability, thus avoiding data loss or overwriting due to the master device's inability to receive in time. Simultaneously, when the ready signal line is invalid, the second control submodule maintains its output data unchanged, ensuring no data loss and improving the reliability of data transmission.

[0166] The various embodiments of this application have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical applications, or technological improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A sequence-preserving processing device, characterized in that, This includes a command caching module and an order preservation management module; The command caching module includes a first control submodule and a command storage submodule; The first control submodule is used to receive the current command and current command identifier issued by the master device, obtain the current write address, write the current command into the command storage submodule according to the current write address, and send the current write address and the current command identifier to the order preservation management module; it is also used to obtain the current read address and send the current read address to the slave device; The command storage submodule is used to store the current command and to send the current command to the slave device in response to a read request from the slave device; The sequence management module includes a second control submodule, an identifier storage submodule, and a sequence information storage submodule; The second control submodule is used to write the current command identifier into the identifier storage submodule according to the current write address, generate the order preservation information of the current command according to the number of current command identifiers in the identifier storage submodule, and store the order preservation information of the current command into the order preservation information storage submodule; wherein the order preservation information of the current command includes the current write address, the current command identifier, and the sequence number; The second control submodule is also used to receive response information and release address returned by the device, match the release address with the write address in each sequence information in the sequence information storage submodule, and if there is a matching sequence information, determine whether to send the response information and the corresponding command identifier to the master device according to the sequence number in the matching sequence information.

2. The sequence-preserving processing device according to claim 1, characterized in that, The second control submodule is specifically used for: If the number of current command identifiers in the identifier storage submodule is greater than or equal to 2, then the sequence number is determined according to the number of current command identifiers, and the order preservation information of the current command is generated according to the sequence number, the current write address, and the current command identifier; otherwise, the order preservation information of the current command is not generated.

3. The sequence-preserving processing device according to claim 2, characterized in that, The second control submodule is specifically used for: If the number of current command identifiers in the identifier storage submodule is equal to 2, then a first write address is obtained based on the storage address of a previously stored current command identifier in the identifier storage submodule. The order preservation information of the previously stored command is generated based on the first write address and the current command identifier, and the order preservation information of the previously stored command is stored in the order preservation information storage submodule. The order preservation information of the previously stored command includes the first write address, the current command identifier, and the sequence number.

4. The sequence-preserving processing apparatus according to any one of claims 1 to 3, characterized in that, The order preservation management module also includes a response information caching submodule; The second control submodule is specifically used for: Compare the release address with the write address in each sequence-preserving information in the sequence-preserving information storage submodule; If the release address does not match the write address in any of the order preservation information, the response information and the corresponding command identifier are sent to the master device. If the release address matches the write address in any of the sequence information in the sequence information storage submodule, then the response information is cached in the response information caching submodule. The sequence number in any of the sequence information is obtained. If the sequence number in any of the sequence information is the minimum value among all sequence information with the same command identifier, then the response information and the corresponding command identifier are sent to the master device. Otherwise, the response information and the corresponding command identifier are sent to the master device only after all response information with the same command identifier and a smaller sequence number have been sent to the master device.

5. The sequence-preserving processing device according to claim 4, characterized in that, The sequence management module also includes a return status storage submodule, which is used to store the return status value of the response information of each command; The return status includes at least a first status value, a second status value, and a third status value; the first status value indicates that the response information of the corresponding command has not yet been returned from the slave device; the second status value indicates that the response information of the corresponding command has been returned from the slave device, but is not yet allowed to be sent to the master device; the third status value indicates that the response information of the corresponding command has been returned from the slave device and is allowed to be sent to the master device.

6. The sequence-preserving processing device according to claim 5, characterized in that, The second control submodule is specifically used for: After caching the response information in the response information caching submodule, the return status value corresponding to the response information is set to the second status value; If the release address matches the write address in any of the sequence information in the sequence information storage submodule, and the sequence number in any of the sequence information is the minimum value among all sequence information with the same command identifier, then the return status value corresponding to the response information is updated to the third status value, and the response information and the corresponding command identifier are sent to the master device according to the updated return status value.

7. The sequence-preserving processing device according to claim 5, characterized in that, The second control submodule is specifically used for: After sending each response message to the master device, obtain the command identifier in the sequence information corresponding to the sent response message, traverse all sequence information with the command identifier that has not yet been sent, obtain the sequence information with the smallest sequence number, and read the return status value of the response message corresponding to the sequence information. If the returned status value is the second status value, then the returned status value is updated to the third status value, and the corresponding response information and command identifier are sent to the master device according to the updated returned status value.

8. The sequence-preserving processing device according to claim 5, characterized in that, The return status also includes a fourth status value, which indicates that the response information for the corresponding command can be sent but has not yet been returned; The second control submodule is specifically used for: If the release address matches the write address in any of the order-preserving information in the order-preserving information storage submodule, then before caching the response information in the response information caching submodule, if the return status value corresponding to the response information is the fourth status value, then the return status value is updated to the third status value, and the response information and the corresponding command identifier are sent to the master device according to the updated return status value; otherwise, the response information is cached in the response information caching submodule, and the return status value corresponding to the response information is set to the second status value.

9. The sequence-preserving processing device according to claim 5, characterized in that, The second control submodule is specifically used for: After each response message is sent to the master device, the sequence information and return status value corresponding to the sent response message are marked as invalid, and the corresponding storage resources in the identifier storage submodule are released according to the release address corresponding to the sent response message, and the release address is sent to the command cache module. The first control submodule is used to release the corresponding storage resource in the command storage submodule according to the release address.

10. The sequence-preserving processing device according to claim 5, characterized in that, The response information caching submodule includes M caching units, each caching unit is used to store the response information and transmission status of a command, and the transmission status is used to indicate whether the corresponding response information has been successfully returned to the master device; The return status storage submodule includes M status units, each status unit is used to store the return status value of the response information of a command; The order preservation management module further includes a response vector bitmap, which includes M first flag bits; wherein, the M cache units, the M state units, and the M first flag bits correspond one-to-one, and M is a preset value; The second control submodule is also used for: When the return status value of the response information of any command is updated to the third status value, the first flag bit corresponding to the return status value of the response information of any command is set to the first preset value. When any first flag bit of the response vector bitmap is a first preset value, the response information and command identifier corresponding to the first flag bit are sent to the master device, and the release address is sent to the command cache module. After the response information, command identifier and release address are sent, the first flag bit is updated to a second preset value. Wherein, the first preset value indicates that the corresponding response information triggers a return to the main device, and the second preset value indicates that the corresponding response information does not trigger a return to the main device.

11. The sequence-preserving processing device according to claim 10, characterized in that, The sequence-preserving information storage submodule includes a sequence-preserving tag table and a sequence count table; The order preservation tag table includes M tag units, each tag unit is used to store the write address and command identifier of an order preservation information; The sequential counting table includes M counting units, each of which stores a sequential number that preserves order information. Among them, the M cache units, the M state units, the M first flag bits, the M tag units and the M counting units correspond one-to-one.

12. The sequence-preserving processing device according to claim 1, characterized in that, The second control submodule is also used to send the release address to the command cache module when sending the response information and the corresponding command identifier to the master device; The first control submodule is used to release the corresponding storage resource in the command storage submodule according to the release address.

13. The sequence-preserving processing device according to claim 1, characterized in that, The command storage submodule includes N command units, each command unit is used to store one command; The identifier storage submodule includes N identifier units, each identifier unit is used to store a command identifier; The N command units and the N identification units correspond one-to-one; N is a preset value.

14. The sequence-preserving processing device according to claim 13, characterized in that, The first control submodule includes a comparison logic submodule, a write address translation unit, a read address translation unit, and a release address translation unit; The comparison logic submodule is used to maintain an idle vector bitmap and a valid vector bitmap, obtain the current write vector based on the idle vector bitmap, and obtain the current read vector based on the valid vector bitmap. The idle vector bitmap includes N second flag bits, each corresponding to one of the N command units. When a second flag bit is at a first preset value, it indicates that the corresponding command unit is idle; when a second flag bit is at a second preset value, it indicates that the corresponding command unit is occupied. The valid vector bitmap includes N third flag bits, each corresponding to one of the N command units. When a third flag bit is at a first preset value, it indicates that there is a command to be read in the corresponding command unit; when a third flag bit is at a second preset value, it indicates that there is no command to be read in the corresponding command unit. The write address conversion unit is used to convert the current write vector from one-hot code to binary format to generate the current write address; The read address conversion unit is used to convert the current read vector from one-hot code to binary format to generate the current read address; The release address conversion unit is used to convert the release address from binary format to one-hot code to generate a release vector; The comparison logic submodule is further configured to update the free vector bitmap based on the release vector and the current write vector, and update the valid vector bitmap based on the current write vector and the current read vector.

15. A master-slave communication system, characterized in that, It includes a master device, a slave device, and a sequence-keeping processing device as described in any one of claims 1 to 14, wherein the sequence-keeping processing device is coupled between the master device and the slave device; The master device is used to send the current command and the current command identifier to the sequence preservation processing device, and to receive the response information and the corresponding command identifier returned by the sequence preservation processing device. The slave device is used to receive the current read address output by the sequence-preserving processing device, send a read request to the sequence-preserving processing device according to the current read address to read the target command from the sequence-preserving processing device, execute the target command, and return the corresponding response information and release address to the sequence-preserving processing device; the release address is the current read address.

16. The master-slave communication system according to claim 15, characterized in that, The first control submodule is used to output a full signal to the main device when all command units in the command storage submodule are occupied; The master device is also used to pause issuing commands and command identifiers to the sequence-keeping processing device based on the full signal.

17. The master-slave communication system according to claim 15, characterized in that, The first control submodule is configured to output an empty signal to the slave device when there are no commands to be read in all command units of the command storage submodule; The slave device is also used to suspend sending read requests to the sequence-preserving processing device based on the empty signal.

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