An isolation method and system for cross-architecture application migration of a Xiongchu platform

Abstract

The application relates to the technical field of computer architecture and dynamic binary translation, and discloses an isolation method and system for application migration across architectures of a China-specific platform, which comprises the following steps: obtaining a source application instruction sequence corresponding to a concurrent translation task, extracting an initial memory address set and an initial register state set; obtaining an instruction feature vector matrix through preset feature extraction model vectorization processing and classifying and determining an instruction conflict risk level; if the instruction conflict risk level is greater than or equal to a preset risk level threshold, allocating an isolated memory space and performing instruction conversion in the isolated memory space to obtain a target platform instruction sequence; and performing resource access monitoring and exception processing on the target platform instruction sequence to obtain a target instruction sequence after consistency verification.

Description

Technical Field

[0001] This invention relates to the fields of computer architecture and dynamic binary translation technology, and in particular to an isolation method and system for cross-architecture application migration on a domestic IT innovation platform. Background Technology

[0002] Currently, core business systems of enterprises are accelerating their migration from x86 architecture to domestically produced CPU platforms. During this process, existing x86 applications without source code, obtained through big data collection, need to be run on the target platform using Dynamic Binary Translation (DBT) technology to ensure business continuity. Industry data shows that the ExaGear dynamic binary translation engine can achieve over 80% of the performance of native AArch64 in source code-less migration scenarios, making it a key technology for migrating domestically developed applications.

[0003] However, existing mainstream DBT engines have shortcomings in instruction-level resource isolation under concurrent translation scenarios. Taking QEMUTCG (Tiny Code Generator) as an example, its translation process maintains a unified code cache, which is shared by multiple translation threads. When instruction sequences from different applications use the same virtual register number or similar memory addresses, register mapping relationships may become intertwined and disordered. For example, ExaGear relies on the process boundaries of the Guest file system for isolation, but process-level isolation cannot detect the differences in instruction behavior between different translation subtasks within an application. Using the same isolation strategy for low-risk routine computation tasks and high-risk floating-point accumulator-intensive tasks results in resource waste or insufficient protection.

[0004] In summary, existing technologies suffer from the problem of cross-interference of instruction-level resources between concurrent cross-architecture translation tasks. Summary of the Invention

[0005] This invention provides an isolation method and system for cross-architecture application migration on a domestic IT innovation platform, in order to solve the problem of cross-interference of instruction-level resources between concurrent cross-architecture translation tasks.

[0006] Firstly, in order to solve the above-mentioned technical problems, the present invention provides an isolation method for cross-architecture application migration on a domestic IT innovation platform, comprising:

[0007] Obtain the source application instruction sequence corresponding to the concurrently executed cross-architecture translation task, and extract the initial memory address set and initial register state set associated with the source application instruction sequence; The initial memory address set and the initial register state set are vectorized by a preset feature extraction model to obtain an instruction feature vector matrix. The instruction feature vector matrix is ​​then classified to determine the instruction conflict risk level. If the instruction conflict risk level is greater than or equal to the preset risk level threshold, then an isolated memory space is allocated for the source application instruction sequence, and instruction conversion processing is performed on the source application instruction sequence in the isolated memory space to obtain the target platform instruction sequence. Resource access monitoring is performed on the target platform instruction sequence. If cross-access behavior is found, address remapping is performed on the isolated memory space to obtain a remapped isolated space. The target platform instruction sequence is re-executed in the remapped isolated space to obtain the target instruction sequence output. The target instruction sequence output is then subjected to storage state detection and rollback processing to obtain the target instruction sequence after consistency verification.

[0008] Secondly, the present invention provides an isolation system for cross-architecture application migration of a domestically developed information technology platform, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the steps of the isolation method for cross-architecture application migration of a domestically developed information technology platform as described above.

[0009] Compared with the prior art, the present invention has the following beneficial effects: (1) This invention uses a preset feature extraction model to vectorize and fuse the memory address set and the register state set to obtain the instruction feature vector matrix. The decision tree algorithm is used to classify the instruction feature vector matrix to obtain the instruction conflict risk level. The instruction conflict risk level drives the allocation of isolated resources, and the secure isolation of concurrent cross-architecture translation tasks is realized from the dimension of instruction underlying behavior features. This solves the problem of cross-interference of concurrent translation instructions caused by shared code cache and virtual register pool in the prior art.

[0010] (2) By performing dynamic binary translation in an isolated memory space, the present invention decouples the instruction translation process from the shared runtime environment, so that each high-risk translation task has an independent address space and resource view, fundamentally avoiding register mapping conflicts and data crosstalk between different tasks.

[0011] (3) This invention monitors the resource access records during the execution of the target platform instruction sequence in real time, automatically triggers the address remapping mechanism to dynamically adjust the isolation space boundary when cross-access behavior is detected, and performs rollback processing after identifying data cross-reading anomalies through storage status detection, thus realizing a secure closed loop for the entire lifecycle of cross-architecture translation task execution. Attached Figure Description

[0012] Figure 1 A flowchart illustrating an isolation method for cross-architecture application migration on a domestic IT innovation platform, provided in an embodiment of the present invention. Figure 2This is a schematic diagram of resource access monitoring and address remapping provided in an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] Reference Figure 1 The first embodiment of the present invention provides an isolation method for cross-architecture application migration on a domestic IT innovation platform, comprising the following steps: S11, obtain the source application instruction sequence corresponding to the concurrently executed cross-architecture translation task, and extract the initial memory address set and initial register state set associated with the source application instruction sequence; S12, the initial memory address set and the initial register state set are vectorized by a preset feature extraction model to obtain an instruction feature vector matrix, and the instruction feature vector matrix is ​​classified to determine the instruction conflict risk level. S13, if the instruction conflict risk level is greater than or equal to the preset risk level threshold, then an isolated memory space is allocated for the source application instruction sequence, and instruction conversion processing is performed on the source application instruction sequence in the isolated memory space to obtain the target platform instruction sequence. S14, resource access monitoring is performed on the target platform instruction sequence. If cross-access behavior is found, address remapping is performed on the isolated memory space to obtain a remapped isolated space. The target platform instruction sequence is re-executed in the remapped isolated space to obtain the target instruction sequence output. The target instruction sequence output is then subjected to storage state detection and rollback processing to obtain the target instruction sequence after consistency verification.

[0015] In step S11, the source application instruction sequence corresponding to the concurrently executed cross-architecture translation task is obtained, and the initial memory address set and initial register state set associated with the source application instruction sequence are extracted.

[0016] In one implementation, obtaining the source application instruction sequence corresponding to the concurrently executed cross-architecture translation task includes: Dependency analysis and loop breaking are performed on the concurrent cross-architecture translation tasks to obtain a set of conflict-free instructions; The sequence of conflict-free instructions is reconstructed to obtain the source application instruction sequence.

[0017] Specifically, the process begins by collecting timestamps of operations in each cross-architecture translation task, with millisecond precision. The timestamps of each operation are extracted by parsing the transaction logs of the cross-architecture translation tasks and arranged chronologically to form an initial execution trajectory. Subsequently, a read-write conflict detection algorithm is used to traverse the initial execution trajectory. For read-write and write-write operations on the same data row, a directed dependency graph is constructed. Each node in the graph represents an operation, and directed edges indicate that subsequent operations depend on the completion of preceding operations. The pre-defined conflict detection rule is that if the timestamp of transaction A performing a write operation on data row D is later than the timestamp of transaction B performing a read operation on data row D, then a directed edge from B to A is established in the dependency graph.

[0018] It is worth noting that the loop breaking process performs topological sorting on the circular references detected in the dependency graph, identifies the set of nodes forming a closed loop, and removes the node with the lowest weight in the closed loop according to a preset loop breaking weight rule to break the deadlock. The preset loop breaking weight rule is to sort transactions in descending order of execution cost, and if the execution costs are the same, to sort them in ascending order of timestamp, removing the last node in the sorting. The execution cost is obtained by performing static analysis on the instruction sequence contained in the transaction, counting the number of CPU cycles corresponding to each instruction in the sequence and summing them to obtain the execution cost of the transaction. The number of CPU cycles for each instruction is determined by looking up the instruction cycle table of the target processor architecture; for indirect jump instructions whose execution cycle cannot be statically determined, the moving average of their historical execution cycles is used as an estimate. For example, if a concurrent cross-architecture translation task contains three transactions: transaction 1 updates the account balance field, transaction 2 reads the account balance field and then updates the interest field, and transaction 3 updates the account balance field and then reads the interest field, after generating a dependency graph using a read-write conflict detection algorithm, topological sorting detects that transactions 1, 2, and 3 form a directed cycle containing three nodes. Based on the cycle breaking weight rule, the execution costs of the three transactions are compared. If the execution cost of transaction 3 is 1500 CPU cycles, transaction 1 is 1200 CPU cycles, and transaction 2 is 800 CPU cycles, then the operation node corresponding to transaction 2 with the lowest execution cost is removed. The removed transaction operation is re-added to the cross-architecture translation task queue to wait for subsequent scheduling and processing, resulting in a set of conflict-free instructions.

[0019] Specifically, after removing the node, the remaining nodes are traversed in topological order, with nodes at the same level arranged according to their original timestamps, and the source application instruction sequence is output. For example, if the set of conflict-free instructions contains 10 instructions, after topological sorting, they are divided into 3 levels: level 1 contains 3 instructions, level 2 contains 4 instructions, and level 3 contains 3 instructions. Outputting them in level order yields a source application instruction sequence containing 10 instructions.

[0020] In one implementation, extracting the initial memory address set and the initial register state set associated with the source application instruction sequence includes: The source application instruction sequence is decoded and mapped to obtain the initial memory address set. The initial memory address set is analyzed using syntax tree analysis and state machine deduction to obtain the initial register state set.

[0021] Specifically, an instruction decoding algorithm is used to perform bit masking for each instruction's binary bits. The opcode field occupies the high 6 bits of the instruction, and the addressing mode field occupies bits 5 to 9. The opcode and addressing mode are extracted using a preset opcode mask of 0xFC00 and an addressing mode mask of 0x03E0, respectively. For base-indexed addressing, the effective address is obtained by summing the base register value and the index register value. For immediate addressing, the immediate field in the instruction is used as the operand address. For direct addressing, the address field in the instruction is directly used as the absolute memory address. Subsequently, a memory page table mapping algorithm is used to convert the absolute memory address into a physical page frame number. The page table size is 4096 bytes per page. The page table is indexed by shifting the absolute memory address right by 12 bits, and the lower 12 bits are used as the page offset, resulting in an initial set of memory addresses. For example, if the source application instruction sequence contains 50 instructions, and after decoding, 35 of them are load instructions and 15 are store instructions, the base address register value is 10000 and the offset is 200, then the absolute memory address is 10200, the page number after page table mapping is 2, the page offset is 2008, and the output contains an initial memory address set containing 50 physical page frame numbers and corresponding page offsets.

[0022] Specifically, a syntax tree is constructed for the instructions associated with each memory address in the initial memory address set. The root node of the syntax tree is the instruction type, and the child nodes are the source operand and the destination operand, respectively. By traversing the syntax tree, the register identifier corresponding to the source operand and the read or write flag of the memory operation performed by the instruction are extracted. Then, a state machine deduction algorithm is used to deduce the register state in reverse order according to the time sequence of read and write flags. The state machine includes four states: idle state, read state, write state, and read-write state. The state transition rule is that if the read / write flag of the current instruction is write, the value of the register before the write operation is recorded as the value read in the previous cycle; if the read / write flag of the current instruction is read, the value of the register is kept unchanged and backtracking is performed. For example, if register R1 is loaded with an immediate value of 500 in instruction cycle 1 and read in instruction cycle 3 to participate in arithmetic operations, the state machine deduction algorithm traverses the instruction sequence in reverse from back to front. By analyzing the source of the assignment of register R1 in cycle 1, it is determined that it is an immediate value assignment rather than the result of operation of other registers. Thus, the initial value of register R1 at the start of instruction sequence execution is determined to be 500, and the output is the initial register state set containing the initial values ​​of the 32 general-purpose registers in the processor and the program counter.

[0023] In step S12, the initial memory address set and the initial register state set are vectorized using a preset feature extraction model to obtain an instruction feature vector matrix. The instruction feature vector matrix is ​​then classified to determine the instruction conflict risk level.

[0024] In one implementation, the step of vectorizing the initial memory address set and the initial register state set using a preset feature extraction model to obtain an instruction feature vector matrix includes: Spatial clustering is performed on the initial memory address set to obtain a memory space feature sequence, and time series analysis is performed on the initial register state set to obtain a register time series feature sequence. The memory space feature sequence and the registered time sequence feature sequence are concatenated to obtain a fused feature sequence. The fused feature sequence is then processed by the preset feature extraction model to obtain a high-dimensional feature tensor. Calculate the matrix sparsity of the high-dimensional feature tensor. If the matrix sparsity is greater than a preset sparsity threshold, then normalize the high-dimensional feature tensor to obtain the instruction feature vector matrix.

[0025] Specifically, a density-based spatial clustering algorithm is used to cluster the initial set of memory addresses. The preset neighborhood radius eps is 4096 bytes to match the target platform's memory page size, and the preset minimum number of neighborhood points minPts is 3, determined according to the DBSCAN parameter selection criterion D+1, where D is the feature dimension 2. The algorithm traverses each memory address, calculating the number of addresses within the eps neighborhood. If the number is greater than or equal to minPts, it is marked as a core point and the cluster is expanded. If the number is less than minPts but within the neighborhood of a core point, it is marked as a boundary point. Addresses that are neither core nor boundary points are marked as noise points. Each cluster generates a memory page access frequency feature value, which is the number of addresses contained in that cluster. The span between the start and end addresses of each cluster is calculated, and the log2 value of the cluster span is used as the spatial distribution feature value. The spatial distribution feature values ​​of all clusters are sorted in ascending order of address to obtain the memory space feature sequence. For example, if the initial set of memory addresses contains 50 addresses, the spatial clustering algorithm divides it into 3 clusters. The first cluster contains 20 addresses with an address span of 65536 bytes and a log2 span of 16. The second cluster contains 18 addresses with an address span of 32768 bytes and a log2 span of 15. The third cluster contains 12 addresses with an address span of 16384 bytes and a log2 span of 14. The output memory space feature sequence is [16, 15, 14].

[0026] The first-order difference processing described above has a difference order of 1. The sliding window statistics extract the mean and standard deviation as time series feature values ​​within each window, thereby achieving a joint representation of the register state change trend and fluctuation amplitude.

[0027] The memory space feature sequence and the registered temporal feature sequence are directly concatenated in dimension. To convert the variable-length memory space feature sequence into a fixed dimension to adapt to the fixed input layer of the preset feature extraction model, the maximum number of clusters K=10 is set. The memory space feature sequence is padded with zeros to a length of 10, where Lr is the length of the registered temporal feature sequence (64). The fixed length of the fused feature sequence is 10+64=74. The number of nodes in the input layer of the preset feature extraction model is fixed at 74, containing 3 fully connected hidden layers. The first hidden layer contains 128 neurons with the ReLU activation function, the second hidden layer contains 256 neurons with the ReLU activation function, the third hidden layer contains 128 neurons with the ReLU activation function, and the output layer contains 128 neurons with a linear function activation function. The above network structure is determined by grid search to select the combination with the minimum validation set loss in the range of hidden layer width (64 to 512) and depth (2 to 4 layers). The weight parameters of the preset feature extraction model were trained before deployment. The training dataset contained 50,000 instruction sequence samples labeled with instruction conflict risk levels. These samples were sourced from actual information technology migration projects and labeled by domain experts according to operation sensitivity specifications. These specifications defined a three-level classification rule: general operation classes included arithmetic operation instructions and inter-register data transfer instructions; suspected high-risk operation classes included conditional branch jump instructions and indirect memory addressing instructions; and core sensitive operation classes included floating-point accumulator instructions, direct memory addressing instructions, and I / O port access instructions. Domain experts reviewed each instruction sequence according to these rules and assigned corresponding labels. The sequences were divided into training, validation, and test sets in a 7:2:1 ratio. The training run consisted of 200 rounds with a batch size of 64. The optimizer was Adam, with an initial learning rate of 0.001 that decayed to 0.0001 in the 100th round. The loss function was cross-entropy loss. The fused feature sequence was input into the preset feature extraction model, and after forward propagation, a 128-dimensional high-dimensional feature tensor was output.

[0028] The matrix sparsity of the high-dimensional feature tensor is calculated, defined as the percentage of zero-value elements in the tensor relative to the total number of elements. A preset sparsity threshold of 60% is used, determined by statistically analyzing the upper quartiles of sparsity for normal samples in the training dataset. If the matrix sparsity is greater than 60%, the high-dimensional feature tensor is processed using a max-min normalization algorithm. This normalization linearly scales non-zero eigenvalues ​​to the integer range of 0 to 100, truncating values ​​less than 0 to 0 and values ​​greater than 100 to 100. If the matrix sparsity is less than or equal to 60%, the high-dimensional feature tensor is directly output as the instruction feature vector matrix. For example, if a high-dimensional feature tensor contains 128 elements, of which 96 are zero values, and the matrix sparsity is 75%, which is greater than the preset sparsity threshold of 60%, then the tensor is subjected to max-min normalization. The maximum value in the tensor is 255 and the minimum value is 10. 10 is mapped to 0 and 255 is mapped to 100. The output is an instruction feature vector matrix with element values ​​of integers between 0 and 100.

[0029] In one implementation, classifying the instruction feature vector matrix to determine the instruction conflict risk level includes: Calculate the feature dimension information entropy for the instruction feature vector matrix, calculate the Gini coefficient based on the feature dimension information entropy, obtain the split threshold, and use the split threshold to divide the instruction feature vector matrix to obtain the decision tree branch path; Extract the initial classification labels from the decision tree branch paths, calculate the probability of the initial classification labels, and obtain the confidence scores. The initial classification label is mapped based on the confidence score to determine the instruction conflict risk level.

[0030] Specifically, the Shannon information entropy is calculated for each feature dimension of the instruction feature vector matrix, with the entropy value H(X) = -Σp(x) i )×log2p(x i ), where p(x) i The frequency distribution of values ​​for this dimension is used as an example. After traversing 128 feature dimensions, the information entropy set of each feature dimension is obtained. Then, the Gini impurity is calculated for each possible value of each feature dimension. The Gini impurity is defined as G = 1 - Σp(k)², where p(k) is the proportion of the k-th class sample in the subset after splitting at that value point. The feature dimension with the minimum Gini impurity and its corresponding value point are taken as the splitting threshold, which maximizes the purity of the split subset. For example, if the information entropy of the 5th dimension is 4.2, and the Gini impurity of this dimension reaches its minimum value of 0.23 at value point 15, then 15 is set as the splitting threshold.

[0031] For each row of the instruction feature vector matrix, compare its eigenvalue in the 5th dimension with the splitting threshold of 15. Eigenvalues ​​greater than 15 are split into the left subtree, and eigenvalues ​​less than or equal to 15 are split into the right subtree. Entropy calculation and Gini impurity evaluation are recursively performed on the split subsets. The maximum depth of the decision tree is preset to 5 layers, determined by the optimal depth selected on the training dataset using 5-fold cross-validation that maximizes validation accuracy without overfitting. The minimum number of samples for a leaf node is preset to 10. Splitting stops when the number of samples in a subset is less than 10, and that node is marked as a leaf node. After iterative splitting, a decision tree branch path of depth 5 is obtained, containing leaf nodes and their corresponding initial classification labels.

[0032] It is worth noting that the historical database access records are used to store the actual conflict results after the translation and execution of various instruction sequences during the system's historical operation, providing an empirical basis for Naive Bayes confidence calculation. Each record in the historical database access records includes an instruction sequence identifier, a decision tree classification path, a classification label, and an execution result flag indicating whether a resource conflict occurred after actual execution. This execution result flag is recorded in binary form, with 1 indicating a conflict and 0 indicating no conflict. During system operation, each time an instruction sequence is translated and executed, the actual conflict result of that instruction sequence is appended to the historical database access records. In Naive Bayes confidence calculation, the historical database access records are introduced as follows: based on the classification path of the current instruction sequence in the decision tree, historical entries with the same classification path are retrieved from the historical database access records. The proportion of actual conflicts corresponding to various labels in these historical entries is calculated. This empirical proportion is used to perform Bayesian correction on the initial posterior probability estimated from the training dataset distribution, thereby obtaining the corrected confidence score.

[0033] Initial classification labels are extracted from the leaf nodes of the decision tree. The label space contains three categories: general operations, suspected high-risk operations, and core sensitive operations. Each level is encoded in ascending order of sensitivity as follows: low-risk data level corresponds to a value of 0, medium-risk level corresponds to a value of 1, and high-risk level corresponds to a value of 2. The Naive Bayes algorithm is used to calculate the posterior probability of each initial classification label as a confidence score. The prior probability is set as the frequency of each label in the training dataset. In 50,000 training samples, there are 25,000 labels for general operations, 15,000 labels for suspected high-risk operations, and 10,000 labels for core sensitive operations. The likelihood function is estimated from the feature distribution corresponding to each label in the training dataset. For example, if 80% of the samples in a certain leaf node are initially labeled as suspected high-risk operations, the Naive Bayes algorithm, combined with historical database access records, calculates the posterior probability of this label to be 85%, and outputs a confidence score of 85. The initial classification labels are mapped to risk levels based on confidence scores. The preset mapping ranges are: 80-100 confidence scores are mapped to high risk, 50-79 to medium risk, and 0-49 to low risk. For example, a confidence score of 85 falls within the 80-100 range, thus mapping the suspected high-risk operation label to a high-risk level, completing the instruction conflict risk assessment of the source application instruction sequence.

[0034] In step S13, if the instruction conflict risk level is greater than or equal to the preset risk level threshold, then an isolated memory space is allocated for the source application instruction sequence, and instruction conversion processing is performed on the source application instruction sequence in the isolated memory space to obtain the target platform instruction sequence.

[0035] It should be noted that the preset risk level threshold is high-risk. This threshold is set based on the fact that, in the context of data migration for domestic IT innovation, the register operations and memory read / write operations involved in the instruction sequences corresponding to the medium-risk level are routine business logic, with a probability of resource conflict of less than 5%. The instruction sequences corresponding to the high-risk level contain high-risk operations such as floating-point accumulators, conditional branch jumps, and direct memory addressing, with a probability of resource conflict exceeding 30%. These probability values ​​were obtained by statistically analyzing the frequency of register mapping conflicts and memory address crossovers in instruction sequences of each sensitivity level under a simulated test environment of 1000 concurrent cross-architecture translation tasks. Therefore, the threshold is set to high-risk level, triggering isolation resource allocation only for high-risk source application instruction sequences, achieving a balance between security and system overhead. If the instruction conflict risk level does not meet the condition of being greater than or equal to the preset risk level threshold, then the source application instruction sequence undergoes routine instruction conversion processing to obtain the target platform instruction sequence.

[0036] In one implementation, allocating isolated memory space for the source application instruction sequence includes: Lexical analysis is performed on the source application instruction sequence to obtain an operand identifier set. Graph coloring register allocation is then performed on the operand identifier set to obtain a register allocation matrix. Calculate the physical address offset based on the register allocation matrix, and configure the access control permission policy based on the physical address offset; The isolated memory space is obtained by sandboxing and allocating memory according to the access control permission policy.

[0037] Specifically, a lexical analysis algorithm is used to scan each instruction in the source application instruction sequence, extracting the register identifiers corresponding to the source and destination operands to construct an operand identifier set. Each identifier in the operand identifier set is treated as a variable node. Interference edges are established between variable nodes with overlapping active regions, where the active region is the range of the variable from its definition to the last instruction it was used in, thus constructing a register allocation interference graph. Subsequently, a graph coloring algorithm is used to color the interference graph, with a preset number of available physical registers of K. reg =16, the coloring rule is that adjacent nodes have different colors. The algorithm traverses nodes in descending order of degree, assigning each node a color different from all its neighbors, and each color corresponds to a physical register number. If the degree of a node is greater than or equal to k, a register overflow mechanism is triggered, temporarily storing the variable in memory. The overflow penalty is an additional 3 CPU cycles of memory access latency. After coloring, a register allocation matrix of size 16×N is obtained. The matrix element (r, i) indicates whether the i-th operand identifier is allocated to physical register r, 1 for allocation and 0 for no allocation. For example, if the source application instruction sequence contains 50 instructions, lexical analysis extracts 32 operand identifiers, and the graph coloring algorithm colors and allocates them to 16 physical registers, generating a 16×32 register allocation matrix, where each column has only one element of 1.

[0038] The required memory isolation space size is calculated based on the number of allocated physical registers in the register allocation matrix. A 1024-byte context storage area is reserved for each allocated physical register to cover the complete context of general-purpose registers and floating-point / SIMD registers. Specifically, under the ARM64 architecture, 256 bytes (32×8 bytes) are needed for 32 general-purpose registers, and 512 bytes (32×16 bytes) are needed for 32 SIMD / floating-point registers. Under the x86-64 architecture, 128 bytes (16×8 bytes) are needed for 16 general-purpose registers, and 256 bytes (16×16 bytes) are needed for 16 XMM registers. The maximum value for each architecture is taken, and an expansion margin is reserved to determine 1024 bytes. Those skilled in the art can adjust this value in the same way according to the actual target platform register file size. Additional storage space is allocated for temporary data in the instruction sequence. The physical address offset is calculated from the starting address of the free physical memory pool and is aligned to an integer multiple of the number of bytes required for the isolation space. For example, if all 16 physical registers are allocated, the context storage area requires 16 × 1024 = 16384 bytes, and the temporary data area requires 12288 bytes (the size of this temporary data area is determined based on 3 memory pages, 3 × 4096 bytes = 12288 bytes, used to accommodate temporary storage of intermediate representation graphs during translation and temporary storage space for register overflow data), totaling 28672 bytes. After page alignment to 4096 bytes, 28672 bytes are taken, resulting in a physical address offset of 28672. Access control permission policies are configured based on the physical address offset. A bitmap access control algorithm is used to set permission bits for each memory page in the isolated memory space. The permission bits include read and write flags. The default permission in this space is read and write allowed and execution prohibited to prevent accidental execution of code in the isolated space before translation is complete. The bitmap access control algorithm sets the permission mask of the memory page corresponding to physical address offset 28672 to 0x06, i.e., binary 0110 represents read and write allowed and execution prohibited.

[0039] The sandbox boundary is determined by both the physical address offset and the size of the isolation space. All memory access requests within the sandbox are checked by a permission check unit before execution. If the access address exceeds the sandbox boundary or violates the permission policy, a hardware interrupt is triggered, and the access request is redirected to a no-operation handling function, preventing the exception from propagating to the host system. For example, the sandbox isolation algorithm allocates a contiguous physical memory region with a starting address of 0x00004000 and a size of 28672 bytes from the free physical memory pool, constructs a corresponding three-level page table structure to map virtual addresses 0 to 28671 to this physical region, and outputs the isolated memory space.

[0040] In one implementation, the source application instruction sequence is subjected to instruction translation processing in the isolated memory space to obtain the target platform instruction sequence, including: Control flow analysis is performed on the source application instruction sequence to obtain an intermediate representation graph. Active variable analysis is then performed on the intermediate representation graph to obtain a register state update sequence. Page table mapping is performed based on the register state update sequence to obtain virtual physical memory mapping relationship, and target architecture execution context is assembled based on virtual physical memory mapping relationship; Dynamic binary translation is performed in the isolated memory space according to the target architecture execution context to obtain the target platform instruction sequence.

[0041] Specifically, a control flow graph generation algorithm is used to scan the source application instruction sequence, constructing an intermediate representation graph using basic blocks as the basic unit. The basic block partitioning rule is that the entry point of a basic block is the target address of a jump instruction or the instruction following the jump instruction, and the exit point is the end of the jump instruction or the previous basic block. Instructions within each basic block are executed sequentially without branches. Active variable analysis is performed on each basic block. The active set of variables at the entry point of the basic block is defined as the set of variables that have not been redefined before being used within the basic block, and the active set of variables at the exit point of the basic block is defined as the set of variables that will be used in subsequent basic blocks. The entry and exit active variable sets of each basic block are obtained by iteratively solving the data flow equations. Changes in the entry and exit active variables of each basic block are recorded as register state update events, arranged according to the topological order of the basic blocks in the control flow graph, resulting in a register state update sequence. For example, if the source application instruction sequence contains 500 instructions, the control flow analysis divides it into 45 basic blocks, each containing an average of about 11 instructions, and the active variable analysis generates a register state update sequence containing 120 state update events.

[0042] For each memory access event involved in the register state update sequence, a corresponding page table entry is created in the page table structure of the isolated memory space. Each page table entry contains a virtual page number, a physical page frame number, an exist bit, a read permission bit, and a write permission bit. The virtual page number is obtained by right-shifting the virtual address of the memory access by 12 bits, and the physical page frame number is obtained by adding the page offset to the starting physical address of the isolated memory space. All created page table entries in the isolated memory space are summarized into a virtual-physical memory mapping table. Subsequently, based on the virtual-physical memory mapping table and the register snapshot of the last update event in the register state update sequence, the target architecture execution context is assembled. The target architecture execution context includes the program counter value, the values ​​of 32 general-purpose registers, and the page table base address register value.

[0043] Specifically, a dynamic binary translation algorithm is employed, using basic blocks as the translation granularity. For each instruction in the source basic block, three steps are performed: instruction decoding, intermediate representation generation, and target instruction issuance. The instruction decoding stage identifies the opcode and operands of the source instruction. The intermediate representation generation stage converts the source instruction into an intermediate representation independent of the target architecture. The target instruction issuance stage encodes the intermediate representation into target machine instructions according to the target architecture's instruction encoding format, and simultaneously maps the register numbers of the source architecture to the physical register numbers of the target architecture based on the register allocation matrix. Boundary checking code is added to memory access instructions during the translation process to verify whether the target address is within the boundary range of the isolated memory space before each memory read / write operation. The preset translation cache size is 2048 target instructions to cover the typical instruction size of a single translation task. When the translation cache is full, an in-first-out (FIFO) strategy is used to evict older translation blocks. For example, if the source application instruction sequence contains 500 x86 architecture instructions, the dynamic binary translation algorithm converts them into 650 ARM architecture instructions within the isolated memory space at the basic block granularity, outputting the target platform instruction sequence.

[0044] In step S14, resource access monitoring is performed on the target platform instruction sequence. If cross-access behavior is found, address remapping is performed on the isolated memory space to obtain a remapped isolated space. The target platform instruction sequence is re-executed in the remapped isolated space to obtain the target instruction sequence output. The target instruction sequence output is then subjected to storage state detection and rollback processing to obtain the target instruction sequence after consistency verification.

[0045] In one implementation, the address remapping process performed on the isolated memory space to obtain a remapped isolated space includes: Obtain the resource access records of the target platform instruction sequence, and extract memory page table entries and access permission identifiers; The memory page table entries and the access permission identifier are subjected to interval overlap detection and boundary alignment processing to obtain virtual address blocks and physical address blocks; The virtual address block and the physical address block are dynamically updated in the page table to obtain the remapped isolation space.

[0046] Specifically, a monitoring flag is pre-embedded in the page table entries of the isolated memory space. When the target platform instruction sequence accesses memory, the hardware memory management unit checks this flag. If the flag is 1, the virtual address, physical address, access type, and access timestamp of this access are recorded and written to the log area of ​​the isolated memory space. The log area has a preset size of 65536 bytes and is written cyclically. When the write pointer reaches the end of the log area, it automatically wraps back to the beginning and continues writing. The resource access records in the log area are periodically parsed to extract the memory page table entries and access permission identifiers from each record. For example, if 10,000 memory access records are generated during the execution of the target platform instruction sequence, 256 memory page table entries and corresponding access permission identifiers are extracted from them. The access permission identifiers include three types: read-only, read-write, and executable.

[0047] The extracted page table entries are grouped according to access permission identifiers. Page table entries within each permission group are compared pairwise to determine if their virtual address ranges overlap. The condition for overlapping ranges is that if the starting address of range A is less than or equal to the ending address of range B, and the ending address of range A is greater than or equal to the starting address of range B, then the two ranges overlap. Ranges that overlap but have different access permission identifiers are marked as conflicting address ranges. Subsequently, a boundary alignment algorithm is used to spatially partition the conflicting address ranges. The conflicting address ranges are aligned upwards by rounding to a page size of 4096 bytes. Each rounded page is sequentially divided into independent virtual address blocks, and corresponding physical address blocks of the same number of pages are allocated from the unused physical memory pool. For example, if three page table entries out of 256 page table entries are detected to indicate read-write interleaved access, and the conflicting address range is from the starting address 4096 to the ending address 12287, the boundary alignment algorithm divides this range into two 4096-byte pages, generating two independent virtual address blocks, and allocating two corresponding physical address blocks from the unused physical memory.

[0048] For each conflicting virtual address block, its physical page frame number field in the page table is modified, replacing the original physical page frame number with the page frame number corresponding to the new physical address block. Simultaneously, the access permission flag of the original physical page is set to inaccessible to isolate the old data. After the update, the processor's page table cache is refreshed to ensure that subsequent instructions use the new mapping. The refresh operation is completed by executing a page table cache invalidation instruction. For example, if the page table entries for two conflicting virtual address blocks are PTE1 and PTE2, and the original physical page frame numbers are PFN... old1 and PFN old2 The new physical page frame numbers are PFN. new1 and PFN new2 The dynamic page table update algorithm modifies the physical page frame number field of PTE1 to PFN. new1The physical page frame number field of PTE2 has been modified to PFN. new2 PFN old1 and PFN old2 The corresponding page permissions are set to inaccessible, and finally, the page table cache refresh instruction is executed, outputting the remapped isolation space. If the resource access record does not indicate any cross-access behavior, the execution output of the target platform instruction sequence is directly used as the target instruction sequence output.

[0049] In one implementation, the step of performing storage state detection and rollback processing on the target instruction sequence output to obtain a consistency-verified target instruction sequence includes: Boundary collision detection is performed on the target instruction sequence output to obtain the data string detection result; If the data cross-read detection result indicates that data cross-read exists, then the transaction log and undo record are obtained and the instructions are reversed to obtain the reverse operation sequence; The target instruction sequence is backtracked based on the reverse operation sequence to obtain the target instruction sequence after consistency verification.

[0050] Specifically, a memory mapping analysis algorithm is used to scan the distribution of the target instruction sequence output in the target memory space, extracting the base address, addressing offset, and memory boundary marker of the target instruction sequence output block. The base address is the starting address of the target instruction sequence output in physical memory, the addressing offset is the offset of each data block within the target instruction sequence output relative to the base address, and the memory boundary marker is the ending address of the remapped isolation space. Then, a boundary collision detection algorithm is used to take the sum of the base address and addressing offset of each data block as the actual access address of that data block and compare it with the memory boundary marker. If the actual access address is greater than the memory boundary marker, a data cross-read anomaly is determined. For example, if the total size of the target instruction sequence output is 81920 bytes, the base address is 4194304, the addressing offset is 4096, and the memory boundary marker is 4276224, the actual access address after adding the base address and offset is 4198400. This address is less than the memory boundary marker 4276224, so the data cross-read detection result is that no data cross-read occurs. If the actual access address is 4277248, which exceeds the boundary marker, the output will indicate that there is a data cross-read detection result.

[0051] When transaction log analysis detects a data read anomaly, it retrieves the transaction logs and undo records related to this cross-architecture translation task from the log area of ​​the isolated memory space. The transaction log records every memory write operation during the generation process of the target instruction sequence output. Each log entry includes the operation number, the target address to be written, the old value before writing, and the new value after writing. Undo records are generated synchronously during transaction log writing and are stored in the same isolated memory space's log area. Each undo record includes the corresponding log number and the register state required to restore the old value. The synchronous generation method is as follows: each time a memory write operation is performed, before writing the new value, the current value at the target address is read as the old value, and the old value and the current register state are written together into the undo record. Then, the transaction log write operation and the actual writing of the new value are executed. An instruction reverse algorithm is used to parse the old value in the undo record, traversing the transaction log in descending order of log number, converting each write operation in the log into a corresponding erase and overwrite instruction, generating a reverse operation sequence. For example, if the transaction log contains 50 write operations, and the undo record records the old value corresponding to each write operation, the instruction reverse algorithm traverses from 50 to 1 according to the log sequence number to generate a reverse operation sequence containing 50 overwrite instructions.

[0052] A state rollback algorithm is used to execute each overwrite instruction sequentially according to the reverse operation sequence, restoring the data in the target address to the old value recorded in the undo record. After each overwrite instruction is executed, the current value at that address is checked against the expected old value. If they do not match, a verification failure event is recorded, and the next instruction is executed. After all reverse operation sequences have been executed, the target instruction sequence after state rollback is output as the target instruction sequence after consistency verification. For example, the state rollback algorithm executes 50 overwrite instructions, restoring the 50 abnormally written data positions in the 81920-byte target instruction sequence output to their old values. After all 50 instructions have been executed, the data verification is consistent, and the target instruction sequence after consistency verification is output. If the data cross-read detection result indicates that there is no data cross-read, the target instruction sequence output is directly used as the target instruction sequence after consistency verification.

[0053] like Figure 2As shown in the figure, this figure illustrates the monitoring curve of memory access addresses changing with instruction cycles during the execution of the target platform's instruction sequence and the dynamic response effect of address remapping. A comparison clearly shows that after the resource access monitoring and dynamic page table update mechanism, the access addresses that were originally fluctuating stably below the isolated memory space boundary (red dashed line, 12287 bytes) (blue solid line, randomly distributed within the range of 4000~12000 bytes in the first 60 instruction cycles) were effectively migrated and clustered in a new neighborhood below the remapped isolated space (green dashed line, approximately 20000 bytes) (within the pink shaded area of ​​cycles 60~78, where access addresses are stably distributed within the range of 16000~20000 bytes). The peak address space was significantly improved, and no further out-of-bounds access occurred. This result intuitively demonstrates that the proposed solution, by pre-embedding monitoring flags in page table entries of isolated memory spaces, real-time parsing of memory page table entries and access permission identifiers in resource access records, and performing boundary alignment and dynamic page table updates for addresses with overlapping ranges and conflicting permissions, can effectively eliminate the potential resource isolation failure caused by cross-access of memory addresses during concurrent cross-architecture translation task execution. This provides a solid address space isolation data foundation for the consistency verification and status rollback processing of subsequent target instruction sequence output.

[0054] In summary, this invention discloses an isolation method for cross-architecture application migration on a domestic IT innovation platform. This invention uses a pre-defined feature extraction model to vectorize and fuse the memory address set and the registered state set, and utilizes a decision tree to classify instruction conflict risks. The classification results drive the allocation of isolated memory space and complete instruction translation within it, achieving secure isolation of instruction-level resources between concurrent cross-architecture translation tasks.

[0055] The second embodiment of the present invention provides an isolation system for cross-architecture application migration of a domestically developed platform, comprising: a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, it implements the steps of the isolation method for cross-architecture application migration of a domestically developed platform as described above.

[0056] It should be noted that the isolation system for cross-architecture application migration of a domestically developed platform provided in this embodiment of the invention is used to execute all the process steps of the isolation method for cross-architecture application migration of a domestically developed platform in the above embodiment. The working principles and beneficial effects of the two are one-to-one, so they will not be described again.

[0057] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. An isolation method for cross-architecture application migration of a Xiongguanneng platform, characterized in that, include: Obtain the source application instruction sequence corresponding to the concurrently executed cross-architecture translation task, and extract the initial memory address set and initial register state set associated with the source application instruction sequence; The initial memory address set and the initial register state set are vectorized by a preset feature extraction model to obtain an instruction feature vector matrix. The instruction feature vector matrix is ​​then classified to determine the instruction conflict risk level. If the instruction conflict risk level is greater than or equal to the preset risk level threshold, then an isolated memory space is allocated for the source application instruction sequence, and instruction conversion processing is performed on the source application instruction sequence in the isolated memory space to obtain the target platform instruction sequence. Resource access monitoring is performed on the target platform instruction sequence. If cross-access behavior is found, address remapping is performed on the isolated memory space to obtain a remapped isolated space. The target platform instruction sequence is re-executed in the remapped isolation space to obtain the target instruction sequence output. The target instruction sequence output is then subjected to storage state detection and rollback processing to obtain the target instruction sequence after consistency verification. The step of classifying the instruction feature vector matrix to determine the instruction conflict risk level includes: calculating the feature dimension information entropy of the instruction feature vector matrix; calculating the Gini coefficient based on the feature dimension information entropy to obtain a split threshold; using the split threshold to partition the instruction feature vector matrix to obtain decision tree branch paths; extracting initial classification labels from the decision tree branch paths; calculating the probability of the initial classification labels to obtain confidence scores; and mapping the initial classification labels based on the confidence scores to determine the instruction conflict risk level.

2. The method of claim 1, wherein the method further comprises: The acquisition of the source application instruction sequence corresponding to the concurrently executed cross-architecture translation task includes: Dependency analysis and loop breaking are performed on the concurrent cross-architecture translation tasks to obtain a set of conflict-free instructions; The sequence of conflict-free instructions is reconstructed to obtain the source application instruction sequence.

3. The method of claim 1, wherein the method further comprises: The extraction of the initial memory address set and initial register state set associated with the source application instruction sequence includes: The source application instruction sequence is decoded and mapped to obtain the initial memory address set. The initial memory address set is analyzed using syntax tree analysis and state machine deduction to obtain the initial register state set.

4. The isolation method for cross-architecture application migration in a domestic IT innovation platform according to claim 1, characterized in that, The step of vectorizing the initial memory address set and the initial register state set using a preset feature extraction model to obtain an instruction feature vector matrix includes: Spatial clustering is performed on the initial memory address set to obtain a memory space feature sequence, and time series analysis is performed on the initial register state set to obtain a register time series feature sequence. The memory space feature sequence and the registered time sequence feature sequence are concatenated to obtain a fused feature sequence. The fused feature sequence is then processed by the preset feature extraction model to obtain a high-dimensional feature tensor. Calculate the matrix sparsity of the high-dimensional feature tensor. If the matrix sparsity is greater than a preset sparsity threshold, normalize the high-dimensional feature tensor to obtain the instruction feature vector matrix. If the matrix sparsity is less than or equal to the preset sparsity threshold, output the high-dimensional feature tensor directly as the instruction feature vector matrix.

5. The isolation method for cross-architecture application migration of the domestic IT innovation platform according to claim 1, characterized in that, The allocation of isolated memory space for the source application instruction sequence includes: Lexical analysis is performed on the source application instruction sequence to obtain an operand identifier set. Graph coloring register allocation is then performed on the operand identifier set to obtain a register allocation matrix. Calculate the physical address offset based on the register allocation matrix, and configure the access control permission policy based on the physical address offset; The isolated memory space is obtained by sandboxing and allocating memory according to the access control permission policy.

6. The isolation method for cross-architecture application migration in a domestic IT innovation platform according to claim 1, characterized in that, In the isolated memory space, the source application instruction sequence is processed for instruction translation to obtain the target platform instruction sequence, including: Control flow analysis is performed on the source application instruction sequence to obtain an intermediate representation graph. Active variable analysis is then performed on the intermediate representation graph to obtain a register state update sequence. Page table mapping is performed based on the register state update sequence to obtain virtual physical memory mapping relationship, and target architecture execution context is assembled based on virtual physical memory mapping relationship; Dynamic binary translation is performed in the isolated memory space according to the target architecture execution context to obtain the target platform instruction sequence.

7. The isolation method for cross-architecture application migration of the domestic IT innovation platform according to claim 1, characterized in that, The process of remapping the isolated memory space to obtain a remapped isolated space includes: Obtain the resource access records of the target platform instruction sequence, and extract memory page table entries and access permission identifiers; The memory page table entries and the access permission identifier are subjected to interval overlap detection and boundary alignment processing to obtain virtual address blocks and physical address blocks; The virtual address block and the physical address block are dynamically updated in the page table to obtain the remapped isolation space.

8. The isolation method for cross-architecture application migration of the domestic IT innovation platform according to claim 1, characterized in that, The step of performing storage state detection and rollback processing on the target instruction sequence output to obtain the consistent target instruction sequence includes: Boundary collision detection is performed on the target instruction sequence output to obtain the data string detection result; If the data cross-read detection result indicates that data cross-read exists, then the transaction log and undo record are obtained and the instructions are reversed to obtain the reverse operation sequence; The target instruction sequence is backtracked based on the reverse operation sequence to obtain the target instruction sequence after consistency verification.

9. An isolation system for cross-architecture application migration on a domestic IT innovation platform, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the isolation method for cross-architecture application migration of the domestic IT innovation platform as described in any one of claims 1 to 8.

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