A method for optimizing cfet parasitic capacitance based on a physical model

Abstract

This invention discloses a method for optimizing CFET parasitic capacitance based on a physical model. This method optimizes CFET parasitic capacitance without relying on TCAD simulation trial and error and includes quantitative design guidance. First, this invention confirms the CFET device structure and five key physical dimension variables and their initial values. Then, the total parasitic capacitance is decomposed into multiple component capacitances according to the region correspondence between the gate and source / drain electrodes. An analytical expression containing dimension variables is established based on four basic capacitance models: parallel plates, parallel non-overlapping, coplanar, and perpendicular. The total parasitic capacitance is then summed to characterize it. Subsequently, the partial derivatives of the total parasitic capacitance for each dimension variable are calculated, and their monotonicity is determined. These are substituted into the initial process dimensions to obtain a numerical ranking of the component capacitances and the absolute values ​​of their partial derivatives. Finally, based on the ranking results, priority is given to adjusting dimension variables with larger absolute values ​​of their partial derivatives (positive partial derivatives decrease the corresponding dimension, negative partial derivatives increase the corresponding dimension), while simultaneously prioritizing the reduction of the dielectric constant of the inter-plate dielectric of the component capacitances with a higher proportion.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device parasitic capacitance optimization, specifically relating to a method for optimizing CFET parasitic capacitance based on a physical model. Background Technology

[0002] As Moore's Law continues to advance and semiconductor process nodes shrink, FinFETs and Gate-All-Around FETs (GAAFETs) have become core devices in advanced process nodes. To further address key bottlenecks such as excessive patterning complexity, deterioration of gate electrostatic control capabilities, and exacerbation of short-channel effects during process miniaturization, Complementary Field-Effect Transistors (CFETs) have emerged. The complex three-dimensional stacked geometry of CFETs leads to a sharp increase in parasitic capacitance, causing significant delay and power consumption issues, becoming a key bottleneck restricting CFET performance improvement. Therefore, systematic modeling, analysis, and optimization of CFET parasitic capacitance is a core research direction for CFET device design and performance improvement at advanced process nodes. Currently, research on CFET parasitic capacitance mainly revolves around capacitance modeling. Based on various basic capacitance models, high-precision three-dimensional edge-gate capacitance analytical models applicable to fin-based, nanosheet-based, and nanowire-based CFETs have been established. Some studies have used TCAD simulation to analyze the influence of physical parameters such as fin height, gate length, number of fins, channel width, and N / P isolation spacing on parasitic capacitance, verifying the capacitance reduction effect at the simulation level.

[0003] Existing technologies related to CFET parasitic capacitance have shortcomings, failing to meet the demands of efficient optimization design for advanced process devices. Current research is limited to the capacitance model itself, only achieving a precise description of CFET parasitic capacitance, without forming a complete, analytical model-based capacitance optimization methodology, thus failing to provide clear derating guidance for device structure design. Furthermore, current research only analyzes the correlation between physical parameters and parasitic capacitance and demonstrates the derating effect through full simulation, lacking analytical model-based mathematical derivations and parameter sensitivity quantitative analysis. The optimization process relies heavily on simulation iterations, resulting in high computational costs and low efficiency, making it difficult to achieve rapid search for the optimal structure in a multi-parameter space. Therefore, this paper proposes a physical model-based CFET parasitic capacitance optimization method, which can solve the technical problems of missing optimization methods, low efficiency, and lack of clear design guidance in existing technologies. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of existing technologies by proposing a method for optimizing the parasitic capacitance of CFETs based on a physical model. This method achieves precise optimization of parasitic capacitance through physical-level capacitance decomposition, analytical modeling, mathematical derivation, and parameter sensitivity quantification, while simultaneously reducing latency and power consumption. It eliminates the reliance on extensive TCAD simulation trial and error, reducing device design cycle time and computational costs. It clearly defines the influence, sensitivity, and optimization priority of each key structural parameter on the parasitic capacitance of CFETs, providing direct, quantifiable, and actionable guidance for device design.

[0005] The specific implementation scheme for achieving the objective of this invention is as follows:

[0006] A method for optimizing the parasitic capacitance of a CFET based on a physical model, the method comprising the following steps:

[0007] Step 1: Confirm the specific structure of the CFET device, confirm its five physical dimensional variables and initial values, and confirm the sidewall dielectric constant in the structure. dielectric constant of the internal isolation layer The values ​​of these two constants;

[0008] Step 2: Perform capacitance division on the CFET device confirmed in Step 1, dividing the total parasitic capacitance into multiple component capacitances formed between different regions of the gate structure and different regions of the source and drain structure.

[0009] Step 3: Model multiple component capacitors separately using four basic capacitor models; the established models are expressed in the form of mathematical analytical expressions, which include the CFET physical size variables described in Step 1; and the analytical expressions of all component capacitors are summed to obtain the mathematical analytical expression of the total parasitic capacitance.

[0010] Step 4: Using the mathematical analytical expression for the total parasitic capacitance established in Step 3, calculate the partial derivatives of the total parasitic capacitance with respect to the five physical size variables;

[0011] Step 5: Substitute the initial values ​​of the device physical dimensions in Step 1 into the mathematical analytical expressions of the multiple component capacitances established in Step 3 to obtain the specific values ​​of the multiple component capacitances, and sum them to obtain the specific value of the total capacitance; substitute the initial values ​​of the device physical dimensions in Step 1 into the partial derivatives of the total parasitic capacitance with respect to the five physical dimension variables obtained in Step 4 to obtain the specific values ​​of the five partial derivatives.

[0012] Step 6: Sort the component capacitors from largest to smallest according to the specific values ​​of the multiple component capacitors in Step 5; sort the absolute values ​​of the partial derivatives from largest to smallest according to the specific values ​​of the five partial derivatives in Step 5.

[0013] Step 7: Based on the specific values ​​of the partial derivatives of the total parasitic capacitance with respect to the five physical size variables in Step 5, determine the monotonicity of the total parasitic capacitance as a function of each physical size variable; and optimize the physical size variables in descending order based on the sorting results of the absolute values ​​of the partial derivatives in Step 6.

[0014] Step 8: Based on the sorting results of the multiple component capacitances in Step 6, decrease the dielectric constant of the dielectric between the plates of the corresponding component capacitances in descending order; where:

[0015] The physical dimensional variables mentioned in step 1 include the channel width Wns, channel thickness Tns, channel length Lg, sidewall thickness Tsp, and gate oxide thickness Tox; the sidewall dielectric constant mentioned in step 1 The dielectric constant of the internal isolation layer is 7.5*8.854e-12. It is 3.9 * 8.854e-12;

[0016] The four basic capacitance models mentioned in step 3 specifically include:

[0017] Parallel plate capacitors:

[0018] ;

[0019] In the formula, Let S be the dielectric constant of the medium between the parallel plates, S be the area of ​​the parallel plates facing each other, and d be the distance between the parallel plates.

[0020] Parallel non-overlapping capacitors:

[0021] ;

[0022] In the formula, Let W be the dielectric constant of the medium between the parallel plates, and W be the width of the capacitor plates. and These are the lengths of the two capacitor plates, respectively. This is the vertical center-to-center distance between the capacitor plates;

[0023] Coplanar capacitance:

[0024] ;

[0025] In the formula, Where is the dielectric constant of the medium surrounding the capacitor plates, and W is the width of the capacitor plates. L is the horizontal spacing between the coplanar plates, and L is the length of the capacitor plates.

[0026] Vertical capacitor:

[0027] ;

[0028] ;

[0029] ;

[0030] ;

[0031] ;

[0032] In the formula, x1 and x2 are the coordinates of the horizontal plate endpoints, and y1 and y2 are the coordinates of the vertical plate endpoints. 1 and 2 represents the dielectric constant of the different media between the plates; 1 and 2 is the fitting constant; This indicates the focal length of the confocal elliptical system between the electrodes. The ordinate represents the boundary between different media between the electrodes; The coordinates of the boundaries of different media after conformal transformation are ordinates. These are parameters used to assist in calculations and have no practical meaning.

[0033] Furthermore, step 7 specifically includes:

[0034] Step 7-1: Observe the specific values ​​of the partial derivatives of the total parasitic capacitance with respect to the five physical size variables. If the partial derivatives are greater than zero, the total parasitic capacitance increases monotonically with the increase of the physical size variable; if the partial derivatives are less than zero, the total parasitic capacitance decreases monotonically with the increase of the physical size variable.

[0035] Step 7-2: Optimize the physical size variables based on the ranking of the absolute values ​​of the partial derivatives of the total parasitic capacitance with respect to the five physical size variables. Specifically, under the premise that the device manufacturing process window and the basic electrical performance of the device meet the design specifications, adjust the size variable corresponding to the first-ranked partial derivative. If it is monotonically increasing, reduce the initial value of the size by 10%; if it is monotonically decreasing, increase the initial value of the size by 10%. After completing the current parameter adjustment, perform the same adjustment operation on the remaining physical size variables in descending order of the absolute values ​​of the partial derivatives. Stop when the total parasitic capacitance is reduced to the preset target value.

[0036] Furthermore, the optimization described in step 8 specifically involves: under the premise that the device manufacturing process window and the basic electrical performance of the device meet the design specifications, reducing the dielectric constant of the inter-plate dielectric of the first-ranked component capacitor by 10%; and performing the same dielectric constant reduction optimization operation on the dielectric of the remaining component capacitors in descending order of component capacitance values, stopping when the total parasitic capacitance is reduced to the preset target value.

[0037] The beneficial effects of this invention are:

[0038] 1) This invention replaces the traditional pure simulation trial-and-error method by combining physical analytical modeling with partial derivative quantitative analysis, which significantly reduces the computational cost and design cycle of parasitic capacitance optimization of CFET devices, and realizes fast, accurate and predictable optimization of parasitic capacitance.

[0039] 2) This invention can significantly reduce the parasitic capacitance of CFETs, while clarifying the priority of parameter optimization and collaborative design criteria. It can suppress parasitic effects while ensuring the electrical performance of the device, and effectively improve the overall performance of CFETs under advanced process nodes. Attached Figure Description

[0040] Figure 1 This is a flowchart of the present invention;

[0041] Figure 2 This is a schematic diagram of the device structure and capacitor division in this invention;

[0042] Figure 3 This is a schematic diagram of the basic capacitor model in this invention;

[0043] Figure 4 This is a schematic diagram of the numerical substitution results in this invention. Detailed Implementation

[0044] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0045] This invention is applicable to the optimization of parasitic capacitance of nanosheet-GAA-based CFET devices and other types of CFET devices.

[0046] Example

[0047] In this embodiment, a stacked GAA-type CFET transistor is used as an example. (See attached document.) Figure 2 An analytical model of its parasitic capacitance is constructed, and mathematical methods such as differentiation and numerical substitution are used to confirm its optimization direction, providing design guidance for low parasitic capacitance. (See also...) Figure 1 The specific steps are as follows:

[0048] Step 1: Confirm that the CFET device structure is a CFET structure composed of nanosheet-type GAA stacks, and the transistor structure is as follows. Figure 2 As shown. Figure 2 (a) in the figure is a 3D structural diagram of the device. Figure 2 (b) in the middle is Figure 2 The cross-sectional view of region ABCD in (a) of the image. Figure 2(c) is a top view of the device. The five physical dimension variables and their initial values ​​are taken from the IRDS-2020 standard: channel width Wns 25nm, channel thickness Tns 5nm, channel length Lg 12nm, sidewall thickness Tsp 5nm, and gate oxide thickness Tox 3.32nm. The constant in the structure is the gate width. 72nm, source / drain length 11nm, source / drain inner fitting length 3nm, sidewall dielectric constant 7.5*8.854e-12, dielectric constant of the internal isolation layer 3.9*8.854e-12.

[0049] Step 2: Classify the gate parasitic capacitance of the device based on its physical structure, into... , , , , , Six-component capacitors, capacitor division as follows Figure 2 As shown.

[0050] Step 3: Model each component capacitance from Step 2 using the four basic capacitance models. The basic capacitance models are as follows: Figure 3 As shown, Figure 3 (a) in the figure represents the parallel plate capacitor model. Figure 3 (b) in the model represents the parallel non-overlapping capacitor model. Figure 3 (c) in the figure represents the coplanar capacitance model. Figure 3 In the diagram, (d) represents the vertical capacitance model. The modeling results are as follows, showing the capacitance components: It consists of two basic models: parallel plate capacitors and parallel non-overlapping capacitors. for:

[0051] (1)

[0052] (1-2)

[0053] (1-3)

[0054] (1-4)

[0055] (1-5)

[0056] (1-6)

[0057] in Representative capacitor The capacitor components that are parallel and do not overlap. Representative capacitor The components of the parallel plate capacitor. This represents the area of ​​the source and drain sides of the transistor. S represents the effective area on the gate side of the transistor. S represents the plate area used to calculate the parallel plate capacitance. Since this structure produces an area mismatch between the plates on both sides of the source / drain and the gate, S is described by equation (1-6).

[0058] Composed of a vertical capacitance model, for:

[0059] (2)

[0060] (2-1)

[0061] (2-2)

[0062] (2-3)

[0063] in, express The ordinate of the boundary between different media between the electrodes. This represents the ordinate of the boundary between different media after conformal transformation. To assist in the calculation of parameters.

[0064] It consists of a parallel-plate capacitor model and a coplanar capacitor model. for:

[0065] (3)

[0066] (3-1)

[0067] (3-2)

[0068] in, Representative capacitor The section on the parallel plate capacitor. Representative capacitor The part of the Chinese-made surface capacitor.

[0069] Composed of a vertical capacitance model, , , These vertical capacitance model parameters were eliminated during simplification. for:

[0070] (4)

[0071] Composed of a vertical capacitance model, for:

[0072] (5)

[0073] (5-1)

[0074] (5-2)

[0075] (5-3)

[0076] (5-4)

[0077] in, express The ordinate of the boundary between different media between the electrodes. This represents the ordinate of the boundary between different media after conformal transformation. To assist in calculating parameters, The source / drain width.

[0078] Composed of a vertical capacitance model, , , These vertical capacitance model parameters were eliminated during simplification. for:

[0079] (6)

[0080] After modeling, total parasitic capacitance The analytical expression is:

[0081] (7)

[0082] Step 4: Based on the analytical expression for total parasitic capacitance established in Step 3, calculate the total parasitic capacitance. Partial derivatives with respect to the five physical size variables Wns, Tns, Lg, Tsp, and Tox.

[0083] Step 5: Substitute the specific values ​​of the initial physical dimensions mentioned in Step 1, namely Wns 25nm, Tns 5nm, Lg 12nm, Tsp 5nm, Tox 3.32nm, into the mathematical analytical expression for the six-component capacitance in Step 3. The result is as follows: Figure 4 As shown in (a); substituting the specific values ​​of the initial physical dimensions described in step 1 into the partial derivatives of the total parasitic capacitance with respect to the five physical dimension variables obtained in step 4, the results are as follows. Figure 4 As shown in (b) of the diagram.

[0084] Step 6: According to Figure 4 In (a), the six component capacitances are sorted from largest to smallest, and the result is as follows: Figure 4 As shown in (c); according to Figure 4 In (b), the partial derivatives of the total parasitic capacitance with respect to the five physical dimensional variables are sorted from largest to smallest, and the results are as follows: Figure 4 As shown in (d) in the figure.

[0085] Step 7: According to Figure 4 In (b), the partial derivative result is compared with zero to confirm the total parasitic capacitance. Since Wns, Tns, and Lg exhibit a monotonically increasing relationship, these three size variables should be reduced to optimize parasitic capacitance; total parasitic capacitance With Tsp, Tns exhibits a monotonically decreasing relationship; therefore, these three size variables should be added to optimize parasitic capacitance. Figure 4 In (a), the initial capacitance is 77.41aF. Optimization is performed based on monotonicity, adjusting the size variables corresponding to the partial derivatives by 10% sequentially. First, the top-ranked Tox is increased from 3.32nm to 3.65nm (rounded to two decimal places), and the result is recalculated. Reduced to 73.50aF; then the second-ranked Tsp was increased from 5nm to 6nm. Reduced to 68.55aF; then the third-ranked Tns was reduced from 5nm to 4nm. Reduced to 66.30aF; then the fourth-ranked Wns was reduced from 25nm to 23nm (keeping the integer part). Reduced to 62.17aF; finally, Lg, ranked fifth, was reduced from 12nm to 11nm (keeping the integer part). Reduced to 62.14 aF. This optimization process can be stopped when the total parasitic capacitance is reduced to the preset target value or when the process and other electrical characteristics reach their limits.

[0086] Step 8: According to Figure 2 Device structure, component capacitance of the device in this embodiment , and The dielectric between the plates is the same dielectric, and their relative permittivity is... Initial value is 7.5; component capacitance of the device. Relative permittivity of the dielectric between the plates Initial value is 3.9; component capacitance of the device. and The plates contain both of the aforementioned media simultaneously. Therefore, according to Figure 4 (c) Sorting results The largest proportion, firstly Decrease by 10% to 6.8 (rounded to one decimal place). The result from step 7, 62.14 aF, decreased to 56.82 aF; The second largest proportion is its medium. Same here, already adjusted, no further adjustments needed; Third in proportion, Decrease by 10% to 3.5 (rounded to one decimal place). Reduced to 56.29 aF. This optimization process can be stopped when the total parasitic capacitance is reduced to the preset target value or when the process and other electrical characteristics reach their limits.

Claims

1. A method for optimizing the parasitic capacitance of a CFET based on a physical model, characterized in that, The method includes the following steps: Step 1: Confirm the specific structure of the CFET device, confirm its five physical dimensional variables and initial values, and confirm the sidewall dielectric constant in the structure. dielectric constant of the internal isolation layer The values ​​of these two constants; Step 2: Perform capacitance division on the CFET device confirmed in Step 1, dividing the total parasitic capacitance into multiple component capacitances formed between different regions of the gate structure and different regions of the source and drain structure. Step 3: Model multiple component capacitors separately using four basic capacitor models; the established models are expressed in the form of mathematical analytical expressions, which include the CFET physical size variables described in Step 1; and the analytical expressions of all component capacitors are summed to obtain the mathematical analytical expression of the total parasitic capacitance. Step 4: Using the mathematical analytical expression for the total parasitic capacitance established in Step 3, calculate the partial derivatives of the total parasitic capacitance with respect to the five physical size variables; Step 5: Substitute the initial values ​​of the device physical dimensions in Step 1 into the mathematical analytical expressions of the multiple component capacitances established in Step 3 to obtain the specific values ​​of the multiple component capacitances, and sum them to obtain the specific value of the total capacitance; substitute the initial values ​​of the device physical dimensions in Step 1 into the partial derivatives of the total parasitic capacitance with respect to the five physical dimension variables obtained in Step 4 to obtain the specific values ​​of the five partial derivatives. Step 6: Sort the component capacitors from largest to smallest according to the specific values ​​of the multiple component capacitors in Step 5; sort the absolute values ​​of the partial derivatives from largest to smallest according to the specific values ​​of the five partial derivatives in Step 5. Step 7: Based on the specific values ​​of the partial derivatives of the total parasitic capacitance with respect to the five physical size variables in Step 5, determine the monotonicity of the total parasitic capacitance as a function of each physical size variable; and optimize the physical size variables in descending order based on the sorting results of the absolute values ​​of the partial derivatives in Step 6. Step 8: Based on the sorting results of the multiple component capacitances in Step 6, decrease the dielectric constant of the dielectric between the plates of the corresponding component capacitances in descending order; where: The physical dimensional variables mentioned in step 1 include the channel width Wns, the channel thickness Tns, the channel length Lg, the sidewall thickness Tsp, and the gate oxide layer thickness Tox; The four basic capacitance models mentioned in step 3 specifically include: Parallel plate capacitors: ； In the formula, Let S be the dielectric constant of the medium between the parallel plates, S be the area of ​​the parallel plates facing each other, and d be the distance between the parallel plates. Parallel non-overlapping capacitors: ； In the formula, Let W be the dielectric constant of the medium between the parallel plates, and W be the width of the capacitor plates. and These are the lengths of the two capacitor plates, respectively. This is the vertical center-to-center distance between the capacitor plates; Coplanar capacitance: ； In the formula, Where is the dielectric constant of the medium surrounding the capacitor plates, and W is the width of the capacitor plates. L is the horizontal spacing between the coplanar plates, and L is the length of the capacitor plates. Vertical capacitor: ； ； ； ； ； In the formula, x1 and x2 are the coordinates of the horizontal plate endpoints, and y1 and y2 are the coordinates of the vertical plate endpoints. 1 and 2 represents the dielectric constant of the different media between the plates; 1 and 2 is the fitting constant; This indicates the focal length of the confocal elliptical system between the electrodes. The ordinate represents the boundary between different media between the electrodes; The coordinates of the boundaries of different media after conformal transformation are ordinates. To assist in the calculation of parameters.

2. The method according to claim 1, characterized in that, Step 7 specifically includes: Step 7-1: Observe the specific values ​​of the partial derivatives of the total parasitic capacitance with respect to the five physical size variables. If the partial derivatives are greater than zero, the total parasitic capacitance increases monotonically with the increase of the physical size variable; if the partial derivatives are less than zero, the total parasitic capacitance decreases monotonically with the increase of the physical size variable. Step 7-2: Optimize the physical size variables based on the ranking of the absolute values ​​of the partial derivatives of the total parasitic capacitance with respect to the five physical size variables. Specifically, under the premise that the device manufacturing process window and the basic electrical performance of the device meet the design specifications, adjust the size variable corresponding to the first-ranked partial derivative. If it is monotonically increasing, reduce the initial value of the size by 10%; if it is monotonically decreasing, increase the initial value of the size by 10%. After completing the current parameter adjustment, perform the same adjustment operation on the remaining physical size variables in descending order of the absolute values ​​of the partial derivatives. Stop when the total parasitic capacitance is reduced to the preset target value.

3. The method according to claim 1, characterized in that, The optimization described in step 8 is as follows: under the premise that the device manufacturing process window and the basic electrical performance of the device meet the design specifications, the dielectric constant of the inter-plate dielectric of the first component capacitor is reduced by 10%; according to the component capacitance values ​​from largest to smallest, the same dielectric constant reduction optimization operation is performed on the dielectric of the remaining component capacitors in turn, and the operation stops when the total parasitic capacitance is reduced to the preset target value.

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