Coverage-driven ai-assisted digital logic simulation test case generation method

Abstract

This invention discloses a coverage-driven AI-assisted digital logic simulation test case generation method, comprising the following steps: coverage acquisition, state encoding, intelligent decision-making, test generation, feedback learning, and closed-loop iteration. In traditional coverage-driven verification methods, test stimuli mainly rely on random constraints or manual design, and the system lacks the ability to proactively analyze uncovered areas, making it difficult to effectively locate remaining uncovered paths at high coverage stages, resulting in a significant stagnation in coverage growth. This invention introduces an AI-assisted decision-making mechanism to perform semantic modeling and reasoning analysis on coverage data, automatically identifying potential triggering conditions for uncovered logic and predicting high-value exploration paths, thereby generating targeted test strategies. Compared to traditional random search methods, this invention avoids a large number of inefficient simulation attempts, concentrating test resources on the critical state space, maintaining a stable growth rate even at high coverage stages, and significantly shortening the verification cycle.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design verification and electronic design automation, specifically a coverage-driven AI-assisted digital logic simulation test case generation method. Background Technology

[0002] With the continuous increase in the scale and complexity of integrated circuits, modern chip designs typically include a large number of concurrent modules, complex control logic, and deep state spaces. Verification has become one of the most time-consuming and costly critical steps in the chip development cycle. In existing technologies, digital logic verification mainly relies on Coverage-Driven Verification (CDV) methods, which typically combine random stimuli with manually written test cases to gradually improve coverage. However, existing mainstream verification tools still have significant shortcomings in practical applications. First, while random stimulus-based testing methods can quickly improve coverage in the early stages of verification, once coverage reaches a high level, uncovered areas often correspond to complex boundary conditions or low-probability triggering paths, leading to a significant slowdown in coverage growth, or even long-term stagnation. This stage usually requires verification engineers to intervene by manually analyzing waveforms, writing targeted tests, or repeatedly adjusting constraints, heavily relying on engineering experience, resulting in low verification efficiency and difficulty in scaling. Second, while existing EDA verification tools (such as mainstream RTL simulation tools) provide statistical functions such as code coverage, functional coverage, and state coverage, their main capabilities are still limited to the collection and display of coverage data, lacking in-depth analysis capabilities for uncovered areas. For example, existing tools typically cannot automatically identify the triggering conditions of uncovered logic, infer potential reachable paths, or generate targeted optimization strategies based on historical test data, making it difficult for coverage information to directly guide subsequent test generation. Furthermore, the existing verification process lacks an effective linkage mechanism between different stages; coverage analysis, test generation, and strategy adjustment are usually completed manually in stages, failing to form a unified automated closed-loop optimization system. This results in high repetition in the verification process, low resource utilization efficiency, and difficulty in meeting the high-efficiency verification requirements of complex chip designs. With the continuous development of artificial intelligence technology in complex search, pattern recognition, and decision optimization, its introduction into the digital logic verification process is expected to achieve intelligent analysis of coverage data and automatic generation of test strategies, thereby overcoming the efficiency bottleneck of traditional random verification methods in the high-coverage stage. Therefore, there is an urgent need to propose an AI-based digital logic simulation coverage optimization method to achieve coverage-driven automated decision-making and closed-loop optimization, improving verification efficiency and reducing engineering costs. Summary of the Invention

[0003] The purpose of this invention is to provide a coverage-driven AI-assisted digital logic simulation test case generation method to solve the problems existing in the prior art.

[0004] To achieve the above objectives, the present invention provides the following technical solution: a coverage-driven AI-assisted digital logic simulation test case generation method, comprising the following steps: (1) Coverage acquisition: Load the RTL design file written in hardware description language into the simulation environment. During the simulation execution, collect code coverage, functional coverage, state coverage and cross coverage data in real time. Parse and convert the original coverage data to output standardized coverage data and information on uncovered logical areas. (2) State encoding: Extract key features from standardized coverage data, vectorize the features to construct a multidimensional coverage state vector, and optionally construct a coverage topology to obtain a structured state space containing the state vector, the set of uncovered areas, and topological relationships. (3) Intelligent decision-making: Input the structured state space into the AI ​​model, analyze the uncovered logical area through the model, predict the coverage improvement value of each exploration path and sort them, select the high priority exploration direction, and output the test incentive strategy; (4) Test generation: Parse the test stimulus strategy, combine the RTL design input signal definition and constraint rules, automatically generate test cases or simulation stimulus sequences, convert them into simulation executable format and inject them into the simulation environment for execution; (5) Feedback learning: Compare the coverage data of this round with the previous round to calculate the change in coverage, generate a reward signal based on the change, and feed the reward signal back to the AI ​​model to optimize the model parameters and policy weights; (6) Closed-loop iteration: Determine whether the current coverage rate has reached the preset target threshold. If it has, output the verification report and test case library. If it has not, repeat steps (1) to (5) until the termination condition is met.

[0005] Furthermore, in step (1), code coverage includes line coverage, branch coverage, condition coverage, and signal flip coverage; function coverage is the triggering state of predefined function points in the verification environment; state coverage is the access status of each state and state transition of the finite state machine; cross coverage is the joint coverage status of multiple signal combinations or function points; and the data format is converted to JSON structured file or database record format.

[0006] Furthermore, in step (2), the key features include the overall code coverage ratio, the coverage distribution of each submodule, the number of uncovered branches, the number of unvisited finite state machine states, and the number of untriggered function coverage points; the coverage topology is an RTL module call graph or a finite state machine transition graph.

[0007] Furthermore, in step (3), the AI ​​model is a large language model or a deep learning model; the uncovered logical regions include untriggered conditional branches, unvisited finite state machine states, unhit functional coverage points, and module regions with slow coverage growth; the test incentive strategies include priority exploration paths, input signal probability distribution adjustment strategies, test incentive constraints, and coverage improvement prediction results.

[0008] Furthermore, in step (4), the test case generation methods include constrained random test generation, directed test generation, and multi-cycle sequence test generation; the generated test cases are converted into test scripts or stimulus data that can be executed by the simulation platform.

[0009] A coverage-driven AI-assisted digital logic simulation test case generation system, including: Coverage acquisition module: used to load RTL design files, perform simulations, acquire multi-dimensional coverage data, complete data standardization and parsing, and output information on uncovered logical regions; State coding module: used to extract coverage features, construct multi-dimensional state vectors, optionally generate coverage topology structure, and output structured state space; Intelligent decision-making module: used to receive the structured state space, analyze the uncovered areas and evaluate the exploration value through AI models, and generate test incentive strategies; Test generation module: used to parse test stimulus strategies, automatically generate test cases and convert them into simulation executable format, and inject them into the simulation environment for execution; Feedback learning module: used to calculate coverage changes, generate reward signals, and optimize the AI ​​model parameters of the intelligent decision-making module; Closed-loop iterative control module: used to determine whether the coverage meets the standard, control the process to execute or terminate in a loop and output the verification results.

[0010] Furthermore, the coverage acquisition module reads data through the standard interface of the simulation tool or the coverage database, supporting two modes: periodic sampling and unified acquisition after a single round of simulation.

[0011] Furthermore, the intelligent decision-making module includes a state input unit, a strategy prediction unit, and a reward calculation unit. The output parameters include input signal distribution adjustment parameters, constraint change information, and random seed selection strategy.

[0012] Furthermore, the termination conditions of the closed-loop iterative control module include coverage reaching a preset threshold, coverage increasing below the threshold for multiple consecutive rounds, and reaching the maximum simulation round limit.

[0013] Compared with the prior art, the beneficial effects of the present invention are: (1) Significantly improves coverage convergence efficiency In traditional coverage-driven verification methods, test stimuli mainly rely on random constraints or manual design. The system lacks the ability to proactively analyze uncovered areas, making it difficult to effectively locate remaining uncovered paths at high coverage levels, resulting in a significant stagnation in coverage growth. This invention introduces an AI-assisted decision-making mechanism to perform semantic modeling and inference analysis on coverage data. This automatically identifies potential triggering conditions for uncovered logic and predicts high-value exploration paths, thereby generating targeted test strategies. Compared to traditional random search methods, this invention avoids numerous inefficient simulation attempts, concentrating test resources on the critical state space. It maintains a stable growth rate even at high coverage levels, significantly shortening the verification cycle.

[0014] (2) Reduce the cost of manual verification In existing verification processes, uncovered areas typically require verification engineers to handle them through waveform analysis, manually writing targeted tests, and repeatedly adjusting constraints. This process is highly dependent on personal experience, inefficient, and difficult to reuse. This invention uses an AI model to learn from coverage data and historical testing behavior, automatically analyzing verification bottlenecks and generating testing strategies, thus shifting from "human experience-driven" to "data-driven decision-making." The AI-assisted mechanism can automatically complete uncovered path analysis, test direction selection, and stimulus generation, significantly reducing the need for manual intervention. Compared to traditional methods, this invention not only reduces labor costs but also effectively reduces verification risks caused by human oversights or judgment biases.

[0015] (3) Enhance the ability to explore complex state spaces In complex SoC systems or multi-module concurrent designs, the state space grows exponentially. Traditional random testing struggles to cover low-probability paths or deep state transitions, resulting in some critical logic remaining unverified for extended periods. This invention uses AI to model coverage distribution and historical exploration paths, identifying "hard-to-cover areas" and inferring their potential trigger paths, thereby enabling targeted exploration of complex state spaces. Compared to traditional methods that rely on blind random stimuli, this invention possesses target-oriented search capabilities, effectively improving coverage of boundary conditions, abnormal paths, and deep states, thus enhancing overall verification quality.

[0016] (4) Achieve coverage-driven automated closed-loop optimization In existing technologies, coverage analysis, test generation, and strategy adjustment are typically completed manually in stages, lacking effective coordination between the various stages and failing to form an automated optimization mechanism. This invention introduces AI-assisted decision-making and feedback learning mechanisms to unify coverage analysis, test generation, and strategy optimization into a single closed-loop system. The system can automatically adjust the test strategy based on the results of each simulation round, achieving continuous learning and adaptive optimization. Compared to traditional verification processes, this invention achieves a shift from "static verification" to "dynamic optimization verification," enabling the verification process to possess adaptability and continuous optimization capabilities.

[0017] (5) Possesses good engineering adaptability and scalability. Traditional verification and optimization methods typically rely on specific tools or custom scripts, resulting in poor versatility and difficulty in adapting to different design scenarios. This invention employs a modular architecture design, where the AI ​​decision-making module interacts with simulation tools through a standard interface, allowing seamless integration into existing EDA toolchains without altering existing verification processes. Furthermore, the AI ​​model can continuously improve its performance through training and supports cross-project transfer and experience reuse. Compared to traditional methods, this invention not only possesses excellent engineering feasibility but also long-term evolution capabilities and greater application value. Attached Figure Description

[0018] Figure 1 This is a system architecture diagram of the present invention; Figure 2 This is a flowchart illustrating the execution process of the present invention; Figure 3 This is a diagram of the intelligent decision-making structure of the present invention; Figure 4 This is a flowchart of the feedback learning process of the present invention. Detailed Implementation

[0019] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0020] Please see Figure 1-4 This invention provides a coverage-driven AI-assisted digital logic simulation test case generation method, comprising the following steps: (1) Coverage data collection The RTL design file to be verified is loaded into the simulation environment of the integrated verification platform, test stimulus module, and coverage statistics tool. The RTL design file is written in Verilog, SystemVerilog, or VHDL hardware description language. During the simulation execution, multi-dimensional coverage data, including code coverage, functional coverage, state coverage, and cross coverage, are collected in real time through the standard interface of the simulation tool. The raw coverage data is uniformly parsed and format converted to generate standardized structured data. The information of the uncovered logical area in the current round is extracted simultaneously and output to the state coding module.

[0021] Code coverage includes line coverage, branch coverage, condition coverage, and signal toggle coverage; functional coverage characterizes the triggering states of predefined functional points in the verification environment; state coverage records the access status of each state and state transition of the finite state machine (FSM); and cross coverage reflects the joint coverage status between multiple signal combinations or functional points. Data format conversion can use JSON structured files or database records to ensure efficient reading and processing by subsequent modules.

[0022] (2) Status coding Key features are extracted from the standardized data output by the coverage acquisition module. These features include the overall code coverage ratio, coverage distribution of each module and sub-module, number of uncovered branches, number of unvisited state machine states, and number of untriggered function coverage points. The extracted features are then vectorized to construct a multi-dimensional coverage state vector. The vector elements include core metrics such as code coverage, branch coverage, state coverage, function coverage, number of uncovered paths, and coverage distribution of each module. Optional coverage topology structures, such as RTL module call graphs or state machine transition graphs, are constructed to represent the dependencies and coverage propagation paths between logical modules. Finally, a structured state space representation containing the coverage state vector, the set of uncovered regions, and the coverage topology relationships is generated, serving as input data for the intelligent decision-making module.

[0023] (3) Intelligent decision-making Using a Large Language Model (LLM) or deep learning model as the core decision-making unit, it receives structured state space information output by the state coding module and performs three core operations in conjunction with historical test results data: First, it performs a global analysis of the current verification state to accurately identify uncovered logical regions such as untriggered conditional branches, unvisited state machine states, missed functional coverage points, and module regions with slow coverage growth; Second, through model inference analysis, it predicts the combination of input conditions that can trigger uncovered regions and quantifies the potential coverage improvement value of each candidate exploration path; Finally, through value scoring and ranking, it selects the highest priority exploration direction and outputs a standardized test incentive strategy, including the priority logical paths or functional points to explore, input signal probability distribution adjustment strategies, constraints for new test incentives, and coverage improvement prediction results.

[0024] (4) Test generation The test stimulus strategy output by the intelligent decision-making module is analyzed, and combined with the input signal definition and constraint rules of the RTL design, test cases or simulation stimulus sequences are automatically generated in three ways: first, constraint random test generation, which dynamically adjusts random constraints to increase the probability of occurrence of target signal combinations; second, targeted test generation, which constructs exclusive test sequences for specific uncovered paths; and third, sequence test generation, which constructs multi-cycle input sequences to trigger complex state transition logic. The generated test cases are converted into test scripts or stimulus data that can be executed by the simulation platform and automatically loaded into the verification environment for simulation.

[0025] (5) Feedback Learning The coverage data after the current simulation is completed is collected and compared with the coverage result of the previous simulation to calculate the change in coverage: ΔCoverage = current coverage - previous coverage. A reward signal is generated based on the change in coverage: a positive reward signal is output if the coverage increases significantly, and a low or negative reward signal is output if the coverage increases slightly or does not change. The reward signal is fed back to the AI ​​model in the intelligent decision-making module to update the model parameters and policy weights, enabling the model to continuously learn, efficiently test and generate strategies, and gradually optimize and verify decision-making capabilities.

[0026] (6) Closed-loop iteration The closed-loop iterative control unit monitors the current coverage data in real time and determines whether it has reached the preset target threshold (such as 95% or above). If the current coverage meets the target, the verification process is terminated, and the final verification report and complete test case library are output. If the target is not met, a new round of optimization process is automatically triggered, and the steps of coverage collection, status coding, intelligent decision-making, test generation, and feedback learning are executed in sequence, and the process is continuously iterated until the termination condition is met.

[0027] The coverage-driven AI-assisted digital logic simulation test case generation system corresponding to this invention specifically includes: Coverage acquisition module: responsible for RTL design loading, simulation execution control, multi-dimensional coverage data acquisition, raw data standardization and parsing, and extraction of uncovered areas; State coding module: responsible for coverage feature extraction, state vector construction, coverage topology generation, and structured state space output; Intelligent decision-making module: includes a status input unit, a strategy prediction unit, and a reward calculation unit, responsible for analyzing uncovered areas, evaluating the value of exploration paths, and generating test incentive strategies; Test generation module: responsible for strategy parsing, automatic test case generation, stimulus data format conversion, and simulation injection execution; Feedback learning module: responsible for calculating coverage change, generating reward signals, and optimizing AI model parameters; Closed-loop iterative control module: responsible for coverage achievement judgment, process loop control, verification termination and result output.

[0028] Example: This invention defines an AI-assisted digital logic simulation coverage optimization closed-loop system based on a large language model. The overall process is divided into seven stages: simulation execution, coverage acquisition, state modeling, intelligent decision-making, test generation, adaptive feedback learning, and closed-loop iterative control.

[0029] I. Simulation Execution Select the RTL design file to be verified. This file is written in Verilog, SystemVerilog or VHDL hardware description language and covers the core logic design of complex digital circuits, SoC, FPGA or ASIC. Deploy the RTL design file to a standard simulation environment that integrates a verification platform, a test stimulus module, and a coverage statistics tool. The verification platform supports multiple rounds of iterative simulation, the test stimulus module can receive externally input stimulus data, and the coverage statistics tool has real-time statistical capabilities for code coverage, functional coverage, state coverage, and cross coverage. The simulation execution module receives the excitation signal or input sequence output by the test generation module, starts the logic simulation operation, outputs simulation waveform data and coverage statistics in real time, and transmits the coverage data to the coverage acquisition module through the standard interface of the simulation tool.

[0030] II. Coverage Data Collection The coverage acquisition module collects multi-dimensional coverage data periodically or uniformly after a single simulation cycle through the standard interface of simulation tools or a coverage database, ensuring strict coverage of the collected dimensions: (1) Code coverage: line coverage, branch coverage, condition coverage, signal inversion coverage; (2) Functional coverage: Verify the triggering status of all predefined functional points in the environment; (3) State coverage: The access status of all states and state transition paths of the finite state machine (FSM); (4) Cross coverage rate: The combined coverage status of multiple control signals, data signals, and function points.

[0031] The collected raw coverage data is standardized and parsed to remove redundant data, unify the data format, and convert it into a JSON structured file or database record format to ensure efficient reading and parsing by subsequent modules. Based on standardized coverage data, information on uncovered logical regions in the current simulation round is extracted, including unexecuted lines of code, untriggered branches, unaccessed FSM states, missed function points, and unimplemented cross-coverage combinations. The uncovered region information and standardized coverage data are then synchronously output to the state coding module.

[0032] III. State Modeling Feature extraction: Accurately extracting core features from coverage data, specifically including: (1) The overall code coverage, branch coverage, state coverage, and functional coverage values ​​of the current verification task; (2) The coverage distribution data and the number of uncovered points of each top-level module and sub-module in the RTL design; (3) Total number of uncovered condition branches, total number of unaccessed FSM states, and total number of untriggered function coverage points; (4) Coverage growth rate of each module and identification of verification bottleneck areas.

[0033] State vectorization: Converting the extracted discrete features into continuous multidimensional state vectors, in vector form: S = [Code coverage, branch coverage, state coverage, feature coverage, number of uncovered paths, module A coverage, module B coverage, ..., module N coverage, weight of uncovered branches, weight of unvisited states] The weight parameters are dynamically allocated based on the verification difficulty and design importance of the uncovered points, ensuring that the vector accurately represents the verification status.

[0034] Topology Construction: For complex multi-module RTL designs, a directed graph of RTL module calls and an FSM state transition graph are constructed. The module call graph represents the call relationships and data flow between modules, and the state transition graph represents the state jump logic of the FSM. By supplementing the contextual information of coverage through graph structure, the accuracy of intelligent decision-making is improved.

[0035] State output: The constructed coverage state vector, the set of uncovered areas, and the coverage topology are integrated into a structured state space and transmitted completely to the intelligent decision-making module.

[0036] IV. Intelligent Decision Making The intelligent decision-making module of this invention is the core unit of the system, which internally includes a state input unit, a strategy prediction unit, and a reward calculation unit. The specific execution flow is as follows: State Input Unit: Receives structured state space information output by the state coding module, performs data cleaning, format verification, and feature normalization, and converts the data into an input format that the AI ​​model can directly process; Policy prediction unit: Employing a large language model or deep learning model as the core inference unit, it performs the following operations: (1) Uncovered area analysis: Traverse the set of uncovered points in the state space, classify and identify untriggered conditional branches, unvisited FSM states, missed function points, and low-growth coverage modules, and mark the verification bottleneck area; (2) Triggering condition reasoning: Based on the RTL design logic and historical test data, reason about the combination of input signals, timing constraints and triggering preconditions for each uncovered point; (3) Value assessment: Calculate the coverage improvement potential, verification importance, and exploration difficulty of each uncovered area, and generate a quantitative value score; (4) Strategy generation: Based on the value score ranking, select the highest priority exploration direction and output the test incentive strategy, including the target exploration path, input signal probability distribution adjustment rules, test constraints, and expected coverage improvement value.

[0037] Reward Calculation Unit: Pre-stores the previous round of coverage data and testing strategies, receives reward signals from the feedback learning module, completes the association mapping between reward values ​​and strategies, and provides data support for model optimization.

[0038] The strategy parameters output by the intelligent decision-making module are directly transmitted to the test generation module to guide the automatic generation of test cases.

[0039] V. Test Generation Strategy Analysis: The test generation module receives the test incentive strategy output by the intelligent decision-making module and breaks down the core parameters such as the target exploration path, signal distribution rules, and constraints. Stimulus Construction: Based on the input port definitions, timing rules, and logical constraints of the RTL design, test cases are generated using three modes: (1) Constraint random test generation: Based on the decision strategy, modify the random constraint file to increase the trigger probability of target signals, states and function points, and generate adaptive random excitations; (2) Targeted test generation: For a single uncovered branch or FSM state, construct a fixed input sequence to accurately trigger the target logic; (3) Multi-cycle sequence generation: For complex state transitions and cross-cycle logic, generate continuous input sequences with multiple clock cycles to trigger deep state space.

[0040] Format conversion: Converts the generated test cases into SystemVerilog test scripts, stimulus data files, or direct instructions supported by the simulation platform, and automatically loads them into the simulation environment; Simulation Startup: The test generation module triggers the simulation execution module to run a new round of simulation, and waits for the simulation to complete before collecting new coverage data.

[0041] VI. Adaptive Feedback Learning Coverage Comparison: The feedback learning module obtains the coverage data of this round of simulation and the baseline data of the previous round, and calculates the change ΔCoverage of code coverage, branch coverage, state coverage and function coverage in each dimension. Reward signal generation: Establish a mapping relationship between changes in coverage and reward values. The greater the increase in coverage, the larger the reward value; if coverage does not increase or decreases, the reward value is negative. Model optimization: The reward signal is fed back to the AI ​​model in the intelligent decision-making module. The model weights are updated and the policy parameters are adjusted through reinforcement learning algorithms, so that the model learns the correspondence between "high reward and efficient policy" and gradually improves the accuracy of decision-making. Data storage: The coverage data, testing strategies, and reward values ​​of this round are stored in the historical database to provide a reference for subsequent iterations.

[0042] VII. Closed-loop iterative control The closed-loop iterative control module monitors the verification process in real time and sets three types of termination conditions. The process terminates when any one of the conditions is met. Coverage target conditions: The current overall coverage rate reaches the user's preset target threshold; Convergence stagnation condition: The coverage improvement in N consecutive simulation rounds is less than the preset minimum threshold, and there is no effective optimization space; Resource constraints: Reach the preset maximum number of simulation rounds and maximum computation time limits.

[0043] If the termination condition is not met, the closed-loop iteration control module automatically triggers a process jump, returning to the coverage acquisition stage and starting a new round of optimization iteration; if the termination condition is met, the module terminates the simulation process, generates a complete verification report, which includes coverage data for each dimension, details of uncovered points, a test case list, and iteration process records, and outputs a reusable test case library, completing the entire verification process.

[0044] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A coverage-driven AI-assisted digital logic simulation test case generation method, characterized by: Includes the following steps: (1) Coverage acquisition: Load the RTL design file written in hardware description language into the simulation environment. During the simulation execution, collect code coverage, functional coverage, state coverage and cross coverage data in real time. Parse and convert the original coverage data to output standardized coverage data and information on uncovered logical areas. (2) State encoding: Extract key features from standardized coverage data, vectorize the features to construct a multidimensional coverage state vector, and optionally construct a coverage topology to obtain a structured state space containing the state vector, the set of uncovered areas, and topological relationships. (3) Intelligent decision-making: Input the structured state space into the AI ​​model, analyze the uncovered logical area through the model, predict the coverage improvement value of each exploration path and sort them, select the high priority exploration direction, and output the test incentive strategy; (4) Test generation: Parse the test stimulus strategy, combine the RTL design input signal definition and constraint rules, automatically generate test cases or simulation stimulus sequences, convert them into simulation executable format and inject them into the simulation environment for execution; (5) Feedback learning: Compare the coverage data of this round with the previous round to calculate the change in coverage, generate a reward signal based on the change, and feed the reward signal back to the AI ​​model to optimize the model parameters and policy weights; (6) Closed-loop iteration: Determine whether the current coverage rate has reached the preset target threshold. If it has, output the verification report and test case library. If it has not, repeat steps (1) to (5) until the termination condition is met.

2. The coverage-driven AI-assisted digital logic simulation test case generation method according to claim 1, characterized in that: In step (1), code coverage includes line coverage, branch coverage, condition coverage, and signal toggle coverage; function coverage is the triggering state of predefined function points in the verification environment; state coverage is the access status of each state and state transition of the finite state machine; cross coverage is the joint coverage status of multiple signal combinations or function points; and the data format is converted to JSON structured file or database record format.

3. The coverage-driven AI-assisted digital logic simulation test case generation method according to claim 1, characterized in that: In step (2), the key features include the overall code coverage ratio, the coverage distribution of each submodule, the number of uncovered branches, the number of unvisited finite state machine states, and the number of untriggered function coverage points; the coverage topology is an RTL module call graph or a finite state machine transition graph.

4. The coverage-driven AI-assisted digital logic simulation test case generation method according to claim 1, characterized in that: In step (3), the AI ​​model is a large language model or a deep learning model; the uncovered logical regions include untriggered conditional branches, unvisited finite state machine states, unhit functional coverage points, and module regions with slow coverage growth; the test incentive strategies include priority exploration paths, input signal probability distribution adjustment strategies, test incentive constraints, and coverage improvement prediction results.

5. The coverage-driven AI-assisted digital logic simulation test case generation method according to claim 1, characterized in that: In step (4), the test case generation methods include constrained random test generation, directed test generation, and multi-period sequence test generation; the generated test cases are converted into test scripts or stimulus data that can be executed by the simulation platform.

6. A coverage-driven AI-assisted digital logic simulation test case generation system, characterized in that, include: Coverage acquisition module: used to load RTL design files, perform simulations, acquire multi-dimensional coverage data, complete data standardization and parsing, and output information on uncovered logical regions; State coding module: used to extract coverage features, construct multi-dimensional state vectors, optionally generate coverage topology structure, and output structured state space; Intelligent decision-making module: used to receive the structured state space, analyze the uncovered areas and evaluate the exploration value through AI models, and generate test incentive strategies; Test generation module: used to parse test stimulus strategies, automatically generate test cases and convert them into simulation executable format, and inject them into the simulation environment for execution; Feedback learning module: used to calculate coverage changes, generate reward signals, and optimize the AI ​​model parameters of the intelligent decision-making module; Closed-loop iterative control module: used to determine whether the coverage meets the standard, control the process to execute or terminate in a loop and output the verification results.

7. The coverage-driven AI-assisted digital logic simulation test case generation system according to claim 6, characterized in that: The coverage acquisition module reads data through the standard interface of the simulation tool or the coverage database, supporting two modes: periodic sampling and unified acquisition after a single round of simulation.

8. The coverage-driven AI-assisted digital logic simulation test case generation system according to claim 6, characterized in that: The intelligent decision-making module includes a state input unit, a strategy prediction unit, and a reward calculation unit. The output parameters include input signal distribution adjustment parameters, constraint change information, and random seed selection strategy.

9. The coverage-driven AI-assisted digital logic simulation test case generation system according to claim 6, characterized in that: The termination conditions of the closed-loop iterative control module include coverage reaching a preset threshold, coverage increasing below the threshold for multiple consecutive rounds, and reaching the maximum simulation round limit.

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