A circuit verification method, device, storage medium and electronic equipment

Abstract

The application discloses a circuit verification method and device, a storage medium and an electronic equipment, and relates to the chip technical field.The method comprises the following steps: obtaining first input information of a to-be-verified circuit and second input information of a reference model; performing circuit processing logic of the to-be-verified circuit and model processing logic of the reference model respectively to obtain first output information and second output information; performing logical relationship verification on the to-be-verified circuit and the reference model respectively to obtain a first logical relationship between the first output information and the first input information and a second logical relationship between the second output information and the second input information; and performing consistency verification on the first output information and the second output information to obtain a target verification result of the to-be-verified circuit.The application independently performs logical relationship verification on the to-be-verified circuit and the reference model to obtain double-domain logical relationship, effectively determines the consistency of the circuit processing logic and the model processing logic, reduces verification time consumption, and improves verification efficiency.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a circuit verification method, apparatus, storage medium and electronic device. Background Technology

[0002] In the development of high-end AI chips, high-performance processors, and floating-point circuits, formal verification methods are needed to verify the correctness of the hardware circuit's operational logic.

[0003] Currently, the existing verification method is to directly construct a cross-domain equivalence assertion that simultaneously includes hardware output signals and reference model output signals, and then input the constructed cross-domain equivalence assertion into the high-definition proof solver (HDPS) engine of the Design Property Verification (DPV) tool for solving and verification.

[0004] However, using this method, the cross-domain equivalence assertions constructed contain both hardware signals and reference model signals. The HDPS arithmetic engine cannot recognize the arithmetic structure of the cross-domain equivalence assertions, causing HDPS to fail and switch to Boolean Satisfiability (SAT) mode, which in turn leads to long verification time and low verification efficiency. Summary of the Invention

[0005] In view of this, this application provides a circuit verification method, apparatus, storage medium and electronic device. The main purpose is to improve the technical problem that the cross-domain equivalence assertion constructed by the prior art contains both hardware signals and reference model signals. The HDPS arithmetic engine cannot recognize the arithmetic structure of the cross-domain equivalence assertion, causing HDPS to fail and switch to the SAT Boolean solver mode, which in turn leads to long verification time and low verification efficiency.

[0006] In a first aspect, this application provides a circuit verification method, including: Obtain the first input information of the circuit to be verified and the second input information of the reference model. The first input information is the set of signals corresponding to all input paths of the circuit to be verified, and the second input information is the set of all input variables of the reference model. Based on the first input information and the second input information, the circuit processing logic of the circuit to be verified and the model processing logic of the reference model are executed respectively to obtain the first output information of the circuit to be verified and the second output information of the reference model. The first output information is the hardware result signal output by the circuit to be verified after completing all input operations, and the second output information is the standard benchmark variable output by the reference model after operation. Logical relationship verification is performed on the circuit to be verified and the reference model respectively to obtain a first logical relationship between the first output information and the first input information, and a second logical relationship between the second output information and the second input information. The first logical relationship is an arithmetic equivalence equation in the hardware domain of the circuit to be verified that the input and output always hold true, and the second logical relationship is an arithmetic equivalence equation in the model domain of the reference model that the input and output always hold true. Based on the first input information, the second input information, the first logical relationship, and the second logical relationship, the consistency verification of the first output information and the second output information is performed to obtain the target verification result of the circuit to be verified. The target verification result is used to verify whether the circuit processing logic and the model processing logic are consistent.

[0007] Optionally, the step of verifying the logical relationship between the circuit to be verified and the reference model to obtain a first logical relationship between the first output information and the first input information, and a second logical relationship between the second output information and the second input information, includes: In the hardware domain of the circuit to be verified, the first output information and the first input information are verified to have an equivalent logical relationship, and the first logical relationship is obtained. In the model domain of the reference model, the second output information and the second input information are verified to have an equivalent logical relationship, thereby obtaining the second logical relationship.

[0008] Optionally, the method further includes: In the hardware domain of the circuit to be verified, the first operation result obtained after logical operation of the multiple signals in the first input information is determined, and the first output information is verified to be equal to the first operation result to obtain the first logical relationship; In the model domain of the reference model, the second operation result obtained after logical operation of the multiple signals in the second input information is determined, and the second output information is verified to be equal to the second operation result, thereby obtaining the second logical relationship.

[0009] Optionally, the step of performing consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship, and the second logical relationship to obtain the target verification result of the circuit to be verified includes: When there is a corresponding equality relationship between the first input information and the second input information, based on the first logical relationship and the second logical relationship, the first output information and the second output information are deduced by algebraic substitution to obtain the deduction result of whether the first output information and the second output information are equivalent; Based on the derivation results, verify whether the first output information and the second output information are consistent, and obtain the target verification result of the circuit to be verified.

[0010] Optionally, the method further includes: Obtain the first identification information corresponding to each of the multiple signals in the first input information, and the second identification information corresponding to each of the multiple signals in the second input information; Based on the sequence number correspondence between the first identification information and the second identification information, it is determined that the first input information and the second input information have the corresponding equality relationship.

[0011] Optionally, before performing consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship, and the second logical relationship to obtain the target verification result of the circuit to be verified, the method further includes: Obtain the operational status flags of the circuit to be verified and the reference model; Based on the operation status flag, abnormal information in the first input information and the second input information is determined and removed.

[0012] Secondly, this application provides a circuit verification apparatus, comprising: The acquisition module is configured to acquire the first input information of the circuit to be verified and the second input information of the reference model; The execution module is configured to execute the circuit processing logic of the circuit to be verified and the model processing logic of the reference model based on the first input information and the second input information, respectively, to obtain the first output information of the circuit to be verified and the second output information of the reference model. The verification module is configured to perform logical relationship verification on the circuit to be verified and the reference model respectively, to obtain a first logical relationship between the first output information and the first input information, and a second logical relationship between the second output information and the second input information; The verification module is also configured to perform consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship and the second logical relationship, to obtain the target verification result of the circuit to be verified. The target verification result is used to verify whether the circuit processing logic and the model processing logic are consistent.

[0013] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the circuit verification method described in the first aspect.

[0014] Fourthly, this application provides an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement the circuit verification method described in the first aspect.

[0015] By means of the above technical solution, this application provides a circuit verification method, apparatus, storage medium, and electronic device, comprising: acquiring first input information of a circuit to be verified and second input information of a reference model; executing circuit processing logic of the circuit to be verified and model processing logic of the reference model based on the first input information and the second input information, respectively, to obtain first output information of the circuit to be verified and second output information of the reference model; performing logical relationship verification on the circuit to be verified and the reference model respectively, to obtain a first logical relationship between the first output information and the first input information, and a second logical relationship between the second output information and the second input information; and performing consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship, and the second logical relationship, to obtain the target verification result of the circuit to be verified. Compared with existing technologies, this application achieves independent operation and output acquisition of dual-domain arithmetic logic by separately executing the circuit processing logic of the circuit to be verified and the model processing logic of the reference model and obtaining the first output information and the second output information accordingly; by separately verifying the logical relationship between the circuit to be verified and the reference model and obtaining the corresponding logical relationship between the two domains, the failure of the HDPS arithmetic engine caused by directly constructing cross-domain equivalence assertions is avoided; by combining the dual-domain input information and the dual-domain logical relationship to complete the consistency verification of output information, the consistency between the circuit processing logic and the model processing logic is effectively determined, reducing the time consumption of circuit formal verification and improving the overall efficiency of circuit verification. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1A schematic flowchart of a circuit verification method provided in an embodiment of this application is shown; Figure 2 A flowchart illustrating another circuit verification method provided in an embodiment of this application is shown; Figure 3 A schematic diagram of the structure of a circuit verification device provided in an embodiment of this application is shown; Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0019] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0020] To address the issue that current technologies constructing cross-domain equivalence assertions that simultaneously incorporate hardware signals and reference model signals, the HDPS arithmetic engine cannot recognize the arithmetic structure of these assertions, causing HDPS to malfunction and switch to the SAT Boolean solver mode. This results in long verification times and low verification efficiency. This embodiment provides a circuit verification method, such as... Figure 1 As shown, the method includes: Step 101: Obtain the first input information of the circuit to be verified and the second input information of the reference model.

[0021] The first input information is the set of signals corresponding to all input paths of the circuit to be verified, and the second input information is the set of all input variables of the reference model.

[0022] In this embodiment of the application, the circuit to be verified may be a design-under-test (DUT) hardware module of an integrated circuit that requires functional equivalence verification. For example, the circuit to be verified in this embodiment may specifically include a 32-channel 56-bit signed fixed-point adder tree hardware circuit, or it may include arithmetic hardware circuits such as 16-channel or 64-channel input multiply-accumulate arrays and floating-point arithmetic units.

[0023] In the embodiments of this application, the reference model can be a software program used to provide a hardware operation benchmark. The reference model can be written in C language, and its internal operation logic can correspond one-to-one with the hardware logic of the circuit to be verified. For example, the reference model in the embodiments of this application can specifically be a C language addition operation model that matches a 32-way 56-bit addition tree, i.e., a reference specification model (Spec).

[0024] In this embodiment, the first input information can be a set of signals corresponding to all input paths on the hardware side of the circuit to be verified. The first input information can include multiple operational input signals and circuit abnormal state flag signals. For example, the first input information in this embodiment can specifically include 32 input signals on the DUT side, and can also include status signals such as Not a Number (NaN) flag, Infinity (Inf) flag, and zero value flag.

[0025] In the embodiments of this application, the second input information may be the complete set of input variables on the reference model software side. The second input information corresponds one-to-one with the first input information, and may include multi-channel computation input variables and abnormal state flag variables that match the hardware. For example, in the embodiments of this application, the second input information may specifically include 32 input variables on the Spec side, and NaN, Inf, and zero-value state flag variables that correspond one-to-one with the hardware.

[0026] In this embodiment, the embodiment can be executed in the Synopsys VC Formal DPV formal verification tool. The DPV can load the HDPS dedicated arithmetic engine, which can efficiently parse arithmetic expressions of a single design domain. Specifically, the loading and environment binding of the DUT Register Transfer Level (RTL) file and Spec C model file can be completed first, and then all input signals and status flags can be extracted in batches from the dual-domain design to form the first input information and the second input information. This acquisition method can be adapted to arithmetic circuits with any number of input channels and any bit width.

[0027] Step 102: Based on the first input information and the second input information, execute the circuit processing logic of the circuit to be verified and the model processing logic of the reference model respectively to obtain the first output information of the circuit to be verified and the second output information of the reference model.

[0028] The first output information is the hardware result signal output by the circuit to be verified after completing all input operations, and the second output information is the standard reference variable output after the reference model operation.

[0029] In this embodiment, the circuit processing logic can be an internal hardware arithmetic operation link of the circuit to be verified, and the circuit processing logic can be an addition tree hardware logic that accumulates multiple inputs layer by layer. For example, the circuit processing logic in this embodiment can specifically be a hardware operation process that adds 32 inputs level by level.

[0030] In the embodiments of this application, the model processing logic can be the arithmetic operation code of the reference model's internal software, and the model processing logic can be completely equivalent to the circuit processing logic. For example, the model processing logic in the embodiments of this application can specifically be a 32-channel input accumulation operation program that corresponds one-to-one with the hardware.

[0031] In this embodiment, the first output information may be the hardware result signal output by the circuit to be verified after completing all input operations. For example, in this embodiment, the first output information may specifically be the total hardware output signal of a 32-channel adder tree.

[0032] In the embodiments of this application, the second output information can be a standard benchmark variable output after the reference model calculation. For example, in the embodiments of this application, the second output information can specifically be the total result variable of the Spec addition operation.

[0033] In this embodiment, the DPV tool can independently run its complete computational logic in the hardware domain and software domain, without pre-constructing cross-domain unified computational assertions. This avoids the defects of the HDPS engine degradation in traditional direct cross-domain verification schemes. The HDPS arithmetic engine is maintained in working state throughout the execution of the operation, and the addition operation is not decomposed into half-adder and full-adder gate-level Boolean logic. It is compatible with various arithmetic circuits with different input scales of 16, 32, and 64 channels and different bit widths of 32, 56, and 128 bits.

[0034] Step 103: Perform logical relationship verification on the circuit to be verified and the reference model respectively to obtain the first logical relationship between the first output information and the first input information, and the second logical relationship between the second output information and the second input information.

[0035] The first logical relation is an arithmetic equivalence equation that holds true for both input and output within the hardware domain of the circuit to be verified, and the second logical relation is an arithmetic equivalence equation that holds true for both input and output within the model domain of the reference model.

[0036] In the embodiments of this application, the first logical relationship can be an arithmetic equivalence equation in which the input and output are always true within the hardware domain, and the first logic can serve as a prerequisite condition for cross-domain derivation.

[0037] In the embodiments of this application, the second logical relation can be an arithmetic equivalence equation in which the input and output always hold true within the software reference model domain. The second logic can be combined with the first logic to form a dual-domain derivation basis.

[0038] In this embodiment, step 103 is limited to the verification operation within the hardware domain and the model domain, respectively. No cross-domain arithmetic expressions are generated, and the HDPS arithmetic engine can maintain a high-efficiency solution state without switching to the SAT Boolean solver. This process is fundamentally different from the native iterative abstraction (iter_abstraction) of DPV. Iter_abstraction only supports single-domain bit-by-bit splitting and cannot achieve dual-domain splitting and logical association. It is also superior to traditional optimization methods such as node truncation (Cutpoint) and case splitting (Case Splitting). Cutpoint only simplifies the logic locally, while Case Splitting increases the verification scenarios exponentially with the input scale.

[0039] Optionally, after completing the proof of the two-domain equality, the first and second logical relations can be bound together as globally effective underlying assumptions.

[0040] Step 104: Based on the first input information, the second input information, the first logical relationship, and the second logical relationship, perform consistency verification on the first output information and the second output information to obtain the target verification result of the circuit to be verified.

[0041] The target verification result is used to verify whether the circuit processing logic and the model processing logic are consistent.

[0042] In this embodiment of the application, consistency verification can be a derivation process based on a single-domain proven equality and input matching constraints, which uses algebraic substitution to determine whether the hardware and software outputs are equal.

[0043] In this embodiment of the application, the target verification result can be the final conclusion determining whether the hardware circuit operation logic is equivalent to the reference model operation logic. The target verification result can be divided into two categories: verification passed and logic inconsistency error. For example, in this embodiment of the application, the target verification result can specifically be the conclusion that the 32-channel 56-bit adder tree hardware output is completely equivalent to the C model.

[0044] Optionally, traditional direct cross-domain verification schemes directly generate operational expressions containing two-domain variables, causing HDPS engine failure and SAT solution state explosion, with verification time reaching several hours or even failing to converge. However, the embodiments of this application are based on the divide-and-conquer single-domain proof approach, which can shorten the verification process time to several minutes and improve verification efficiency by tens of thousands of times. At the same time, this step only modifies the DPV verification script and does not require modification of RTL hardware code and C reference model, so there is no risk of introducing new defects by modifying the design. It can be extended to adapt to multiply-accumulate and various arithmetic circuits for floating-point operations.

[0045] Compared with existing technologies, this application achieves independent operation and output acquisition of dual-domain arithmetic logic by separately executing the circuit processing logic of the circuit to be verified and the model processing logic of the reference model and obtaining the first output information and the second output information accordingly; by separately verifying the logical relationship between the circuit to be verified and the reference model and obtaining the corresponding logical relationship between the two domains, the failure of the HDPS arithmetic engine caused by directly constructing cross-domain equivalence assertions is avoided; by combining the dual-domain input information and the dual-domain logical relationship to complete the consistency verification of output information, the consistency between the circuit processing logic and the model processing logic is effectively determined, reducing the time consumption of circuit formal verification and improving the overall efficiency of circuit verification.

[0046] As an optional approach, when performing the task of "performing logical relationship verification on the circuit to be verified and the reference model separately to obtain the first logical relationship between the first output information and the first input information, and the second logical relationship between the second output information and the second input information," the following methods can be used, but are not limited to them: Figure 2 As shown, it includes: Step 201: In the hardware domain of the circuit to be verified, verify the equivalent logic relationship between the first output information and the first input information to obtain the first logic relationship.

[0047] In this embodiment, the hardware domain can be an independent design space containing only the RTL hardware design of the circuit to be verified, and all operational expressions within the hardware domain can be recognized by the HDPS engine. For example, in this embodiment, the hardware domain can specifically be a DPV hardware design partition after loading the addition tree DUTRTL.

[0048] In this embodiment, equivalence logic verification can be a process of constructing an equality assertion within a single design domain and calling the HDPS engine to prove that the sum of the inputs equals the output. For example, in this embodiment, equivalence logic verification can specifically be accomplished by writing lemma addition assertions in both the hardware and software domains.

[0049] For example, when the first logical relation is the hardware operation equivalent logical relation of the adapting multi-input arithmetic addition tree, the calculation formula corresponding to the first logical relation can be as shown in Formula 1, where Lemma_DUT can represent the hardware domain addition equivalent logic, DUT_A can represent the hardware total output, and DUT_A_0~DUT_A_31 can represent the hardware side input signals.

[0050] Lemma_DUT=DUT_A=DUT_A_0+DUT_A_1+…+DUT_A_31 (Formula 1) It should be noted that this step only constructs the addition equation in the pure hardware domain and does not introduce software domain variables. The HDPS engine can fully recognize the addition tree arithmetic structure and quickly complete the proof.

[0051] Step 202: In the model domain of the reference model, verify the equivalent logical relationship between the second output information and the second input information to obtain the second logical relationship.

[0052] In the embodiments of this application, the model domain can be an independent software design space containing only a C language reference model, and the arithmetic operations within the model domain can be directly solved by the HDPS engine. For example, the model domain in the embodiments of this application can specifically be a DPV software design partition after loading the Spec addition code.

[0053] For example, when the second logical relation is the software operation equivalent logical relation of the adapting multi-input arithmetic addition tree, the calculation formula corresponding to the second logical relation can be as shown in Formula 2, where Lemma_Spec can represent the software domain addition equivalent logic, Spec_B can represent the total output of the reference model, and Spec_B_0~Spec_B_31 can represent the input variables of each path on the software side.

[0054] Lemma_Spec = Spec_B = Spec_B_0 + Spec_B_1 + ... + Spec_B_31 (Formula 2) It should be noted that this step only constructs the addition equation in the pure software model domain, and does not generate cross-domain operation expressions throughout the process, ensuring that the solution engine does not degrade.

[0055] Optionally, the first and second logical relationships can be bound as global basic assumptions. The calculation formula for the basic assumptions can be as shown in Formula 3. In this formula, Assume_Base can represent the global basic pre-assumptions, which are used to lock the fixed operation relationship between the two domains and avoid repeated solving by the tool. This optional implementation method is different from the existing Cutpoint node truncation and CaseSplitting case splitting optimization methods. The standardized divide-and-conquer process can be reused to various multi-channel arithmetic circuits.

[0056] Assume_Base=Lemma_DUT∧Lemma_Spec (Formula 3) As an optional approach, the following method may be used, but is not limited to: in the hardware domain of the circuit to be verified, determining the first operation result obtained after logical operation of the multiple signals in the first input information, and verifying that the first output information is equal to the first operation result, thereby obtaining a first logical relationship; in the model domain of the reference model, determining the second operation result obtained after logical operation of the multiple signals in the second input information, and verifying that the second output information is equal to the second operation result, thereby obtaining a second logical relationship.

[0057] In this embodiment, the multiple signals can be all independent input path signals within the same hardware / software domain. For example, in this embodiment, the multiple signals can specifically be 32 parallel inputs on the DUT side.

[0058] In the embodiments of this application, the first calculation result can be the total calculation value obtained by accumulating all input signals on the hardware side, and the second calculation result can be the total calculation value obtained by accumulating all input variables on the software side.

[0059] In this embodiment, the dual-domain verification process can be completely symmetrical, and the number of input channels can be 16, 32, 64, etc. Adaptation can be completed simply by synchronously adding or subtracting input items in the first and second logical relationships (i.e., Formula 1 and Formula 2 in this embodiment). The hardware domain and software domain equation proof processes are unified, reducing the workload of writing verification scripts.

[0060] As an optional approach, when performing the "consistency verification of first output information and second output information based on first input information, second input information, first logical relation, and second logical relation to obtain the target verification result of the circuit to be verified," the following method can be used, but is not limited to: When there is a corresponding equality relationship between the first input information and the second input information, based on the first logical relation and the second logical relation, perform algebraic substitution derivation on the first output information and the second output information to obtain a derivation result on whether the first output information and the second output information are equivalent; based on the derivation result, verify whether the first output information and the second output information are consistent to obtain the target verification result of the circuit to be verified.

[0061] In the embodiments of this application, the corresponding equality relationship can be an equivalence constraint condition that matches hardware inputs and software inputs one by one, which can build a logical bridge between the hardware domain and the software domain.

[0062] In the embodiments of this application, the algebraic substitution derivation can be a logical operation method that relies on the fixed two-domain addition equation and input equivalence constraints to determine whether the hardware output and the software output are equal through pure algebraic substitution. The embodiments of this application do not require to carry out large-scale Boolean solving again, but only reuse the two previously proven single-domain arithmetic equations, which greatly reduces the computational overhead of the DPV tool.

[0063] As an optional approach, the following method may be used, but is not limited to: obtaining first identification information corresponding to the multiple signals in the first input information, and second identification information corresponding to the multiple signals in the second input information; determining that there is a corresponding equality relationship between the first input information and the second input information based on the sequence number correspondence between the first identification information and the second identification information.

[0064] In this embodiment, the first identification information can be a sequence number corresponding to each input signal on the hardware side. For example, in this embodiment, the first identification information can specifically be a numeric sequence number with the suffix 0 to 31 in the DUT_A class.

[0065] In the embodiments of this application, the second identification information can be a sequence number corresponding to each input variable on the software side, and the second identification information corresponds one-to-one with the first identification. For example, in the embodiments of this application, the second identification information can specifically be a numeric sequence number with the suffix Spec_B from 0 to 31.

[0066] In this embodiment, input equivalence constraints can be automatically established by matching identifier sequence numbers, eliminating the need for manual writing of matching rules for each path. When the number of inputs to the addition tree changes, adaptation can be completed simply by adjusting the sequence number range synchronously, resulting in greater reusability of the verification environment.

[0067] As an optional approach, before performing the "consistency verification of the first output information and the second output information based on the first input information, the second input information, the first logical relationship and the second logical relationship, to obtain the target verification result of the circuit to be verified", the following methods can be used, but not limited to these: obtaining the operation status flag bits of the circuit to be verified and the reference model; determining the abnormal information in the first input information and the second input information based on the operation status flag bits, and removing the abnormal information.

[0068] In this embodiment, the operation status flag can be a signal or variable used to identify illegal operation conditions of the circuit. The operation status flag can include three types: NaN flag, Infinity flag, and Zero value flag. For example, the normal operation condition constraint calculation formula in this embodiment can be as shown in Formula 4, where Condition can represent a legal operation scenario constraint, and a flag equal to 0 can indicate that there are no abnormal values ​​in the current operation.

[0069] Condition = (NaN flag = 0) ∧ (Inf flag = 0) ∧ (Zero value flag = 0) (Formula 4) For the embodiments of this application, abnormal information can be non-compliant input conditions such as NaN invalid values, infinite Inf, abnormal zero values, etc. Removing abnormal information can refer to shielding all illegal scenarios through the constraints of Formula 4 and only performing equivalence proofs on legal values.

[0070] In this embodiment, adding an anomaly filtering step can improve verification robustness, conform to the real operating conditions of industrial chips, and standardize the entire verification framework, which can be applied to various arithmetic circuits such as AI chips and floating-point arithmetic units.

[0071] Compared with existing technologies, the embodiments of this application achieve accurate derivation of logic relationships in a single design domain by independently verifying the equivalent logic relationships between the two domains in the hardware domain and the model domain, respectively; achieve standardized verification of output information consistency by performing algebraic substitution derivation based on the logic relationships between the two domains when corresponding equality relationships exist; achieve automatic determination of the matching relationship between the two domains by determining the equality relationship of the inputs based on the sequence correspondence of the two domain input identifiers; and achieve the elimination of invalid verification conditions by removing abnormal input information based on the operation status flag bit before consistency verification, thereby improving the reliability of circuit verification results.

[0072] Furthermore, as Figure 1 and Figure 2 The specific implementation of the method shown in this embodiment provides a circuit verification device, such as... Figure 3 As shown, the device includes: an acquisition module 31, an execution module 32, and a verification module 33.

[0073] The acquisition module 31 is configured to acquire the first input information of the circuit to be verified and the second input information of the reference model. The first input information is the set of signals corresponding to all input paths of the circuit to be verified, and the second input information is the set of all input variables of the reference model. The execution module 32 is configured to execute the circuit processing logic of the circuit to be verified and the model processing logic of the reference model based on the first input information and the second input information, respectively, to obtain the first output information of the circuit to be verified and the second output information of the reference model. The first output information is the hardware result signal output by the circuit to be verified after completing all input operations, and the second output information is the standard reference variable output by the reference model after operation. The verification module 33 is configured to perform logical relationship verification on the circuit to be verified and the reference model respectively, to obtain the first logical relationship between the first output information and the first input information, and the second logical relationship between the second output information and the second input information. The first logical relationship is an arithmetic equivalence equation in which the input and output of the circuit to be verified are always true within the hardware domain, and the second logical relationship is an arithmetic equivalence equation in which the input and output of the reference model are always true within the model domain. The verification module 33 is also configured to perform consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship and the second logical relationship, to obtain the target verification result of the circuit to be verified. The target verification result is used to verify whether the circuit processing logic and the model processing logic are consistent.

[0074] In some examples of this embodiment, the verification module 33 is specifically configured to perform equivalent logic relationship verification on the first output information and the first input information in the hardware domain of the circuit to be verified to obtain a first logic relationship; and to perform equivalent logic relationship verification on the second output information and the second input information in the model domain of the reference model to obtain a second logic relationship.

[0075] In some examples of this embodiment, the verification module 33 is further configured to determine, in the hardware domain of the circuit to be verified, the first operation result obtained after logical operation of the multiple signals in the first input information, and verify that the first output information is equal to the first operation result to obtain a first logical relationship; and in the model domain of the reference model, determine the second operation result obtained after logical operation of the multiple signals in the second input information, and verify that the second output information is equal to the second operation result to obtain a second logical relationship.

[0076] In some examples of this embodiment, the verification module 33 is further configured to, when there is a corresponding equality relationship between the first input information and the second input information, perform algebraic substitution derivation on the first output information and the second output information based on the first logical relationship and the second logical relationship to obtain a derivation result on whether the first output information and the second output information are equivalent; and verify whether the first output information and the second output information are consistent based on the derivation result to obtain the target verification result of the circuit to be verified.

[0077] In some examples of this embodiment, the verification module 33 is further configured to obtain the first identification information corresponding to the multiple signals in the first input information and the second identification information corresponding to the multiple signals in the second input information; and determine that the first input information and the second input information have a corresponding equality relationship based on the sequence number correspondence between the first identification information and the second identification information.

[0078] In some examples of this embodiment, the verification module 33 is further configured to acquire the operation status flag bits of the circuit to be verified and the reference model; based on the operation status flag bits, determine the abnormal information in the first input information and the second input information, and remove the abnormal information.

[0079] It should be noted that other corresponding descriptions of the functional units involved in the circuit verification device provided in this embodiment can be found in [reference]. Figure 1 and Figure 2 The corresponding description in [the document] will not be repeated here.

[0080] Based on the above, Figure 1 and Figure 2 Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figure 1 and Figure 2 The method shown.

[0081] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0082] like Figure 4 The diagram shown is a hardware structure schematic of an electronic device according to the present invention, comprising: At least one processor 401; and, A memory 402 connected to the processing of at least one processor 401 terminal device; wherein, The memory 402 stores instructions that can be executed by at least one processor to enable the at least one processor to perform the circuit verification method as described above.

[0083] Figure 4 Take a processor 401 as an example.

[0084] The electronic device may also include an input device 403 and an output device 404.

[0085] The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 4 Taking the example of a connection between China and Israel via a bus.

[0086] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the circuit verification method in the embodiments of this application, for example, Figure 1 and Figure 2 The method flow is shown. The processor 401 executes various functional applications and terminal device processing by running non-volatile software programs, instructions, and modules stored in the memory 402, thereby implementing the circuit verification method in the above embodiments.

[0087] Memory 402 may include a program storage area and a data storage area, wherein the program storage area may store an operating system and an application program required for at least one function; the data storage area may store data created according to the use of the circuit verification method, etc. Furthermore, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and these remote memories may be connected to the apparatus performing the circuit verification method via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, processing networks of mobile terminal devices, and combinations thereof.

[0088] Input device 403 can receive user clicks and generate signal inputs related to user settings and function control for circuit verification methods. Output device 404 may include display devices such as a display screen.

[0089] One or more modules are stored in memory 402, and when run by one or more processors 401, the circuit verification method in any of the above method embodiments is executed.

[0090] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0091] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0092] The storage medium may also include an operating system and a processing module for network terminal devices. The operating system is a program that manages the hardware and software resources of the aforementioned physical devices, supporting the operation of information processing programs and other software and / or programs. The processing module for network terminal devices is used to enable terminal device processing between the various components within the storage medium, as well as terminal device processing with other hardware and software within the information processing physical device.

[0093] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented using software plus necessary general-purpose hardware platforms, or it can be implemented in hardware. By applying the scheme of this embodiment, compared with the prior art, this application embodiment achieves independent operation and output acquisition of dual-domain operation logic by separately executing the circuit processing logic of the circuit to be verified and the model processing logic of the reference model and obtaining the first output information and the second output information accordingly; by separately performing independent logical relationship verification on the circuit to be verified and the reference model and obtaining the corresponding logical relationship between the two domains, the failure of the HDPS arithmetic engine caused by directly constructing cross-domain equivalence assertions is avoided; by combining the dual-domain input information and the dual-domain logical relationship to complete the output information consistency verification, the consistency between the circuit processing logic and the model processing logic is effectively determined. This approach reduces the time required for formal circuit verification and improves the overall efficiency of circuit verification. It achieves accurate derivation of logic relationships within a single design domain by independently verifying dual-domain equivalent logic relationships in both the hardware and model domains. It enables standardized verification of output information consistency by performing algebraic substitution derivation based on dual-domain logic relationships when corresponding equality relationships exist among the dual-domain inputs. It automatically determines dual-domain input matching relationships by identifying the corresponding sequence numbers of the dual-domain input identifiers. Finally, it removes invalid verification conditions by removing abnormal input information based on the operation status flags before consistency verification, thereby improving the reliability of circuit verification results.

[0094] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0095] The above are merely specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A circuit verification method, characterized in that, include: Obtain the first input information of the circuit to be verified and the second input information of the reference model. The first input information is the set of signals corresponding to all input paths of the circuit to be verified, and the second input information is the set of all input variables of the reference model. Based on the first input information and the second input information, the circuit processing logic of the circuit to be verified and the model processing logic of the reference model are executed respectively to obtain the first output information of the circuit to be verified and the second output information of the reference model. The first output information is the hardware result signal output by the circuit to be verified after completing all input operations, and the second output information is the standard benchmark variable output by the reference model after operation. Logical relationship verification is performed on the circuit to be verified and the reference model respectively to obtain a first logical relationship between the first output information and the first input information, and a second logical relationship between the second output information and the second input information. The first logical relationship is an arithmetic equivalence equation in the hardware domain of the circuit to be verified that the input and output always hold true, and the second logical relationship is an arithmetic equivalence equation in the model domain of the reference model that the input and output always hold true. Based on the first input information, the second input information, the first logical relationship, and the second logical relationship, the consistency verification of the first output information and the second output information is performed to obtain the target verification result of the circuit to be verified. The target verification result is used to verify whether the circuit processing logic and the model processing logic are consistent.

2. The method according to claim 1, characterized in that, The step of verifying the logical relationship between the circuit to be verified and the reference model to obtain a first logical relationship between the first output information and the first input information, and a second logical relationship between the second output information and the second input information, includes: In the hardware domain of the circuit to be verified, the first output information and the first input information are verified to have an equivalent logical relationship, and the first logical relationship is obtained. In the model domain of the reference model, the second output information and the second input information are verified to have an equivalent logical relationship, thereby obtaining the second logical relationship.

3. The method according to claim 2, characterized in that, The method further includes: In the hardware domain of the circuit to be verified, the first operation result obtained after logical operation of the multiple signals in the first input information is determined, and the first output information is verified to be equal to the first operation result to obtain the first logical relationship; In the model domain of the reference model, the second operation result obtained after logical operation of the multiple signals in the second input information is determined, and the second output information is verified to be equal to the second operation result, thereby obtaining the second logical relationship.

4. The method according to claim 1, characterized in that, The step of performing consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship, and the second logical relationship to obtain the target verification result of the circuit to be verified includes: When there is a corresponding equality relationship between the first input information and the second input information, based on the first logical relationship and the second logical relationship, the first output information and the second output information are deduced by algebraic substitution to obtain the deduction result of whether the first output information and the second output information are equivalent; Based on the derivation results, verify whether the first output information and the second output information are consistent, and obtain the target verification result of the circuit to be verified.

5. The method according to claim 4, characterized in that, The method further includes: Obtain the first identification information corresponding to each of the multiple signals in the first input information, and the second identification information corresponding to each of the multiple signals in the second input information; Based on the sequence number correspondence between the first identification information and the second identification information, it is determined that the first input information and the second input information have the corresponding equality relationship.

6. The method according to claim 5, characterized in that, Before performing consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship, and the second logical relationship to obtain the target verification result of the circuit to be verified, the method further includes: Obtain the operational status flags of the circuit to be verified and the reference model; Based on the operation status flag, abnormal information in the first input information and the second input information is determined and removed.

7. A circuit verification device, characterized in that, include: The acquisition module is configured to acquire first input information of the circuit to be verified and second input information of the reference model. The first input information is the set of signals corresponding to all input paths of the circuit to be verified, and the second input information is the set of all input variables of the reference model. The execution module is configured to execute the circuit processing logic of the circuit to be verified and the model processing logic of the reference model based on the first input information and the second input information, respectively, to obtain the first output information of the circuit to be verified and the second output information of the reference model. The first output information is the hardware result signal output by the circuit to be verified after completing all input operations, and the second output information is the standard benchmark variable output by the reference model after operation. The verification module is configured to perform logical relationship verification on the circuit to be verified and the reference model respectively, to obtain a first logical relationship between the first output information and the first input information, and a second logical relationship between the second output information and the second input information. The first logical relationship is an arithmetic equivalence equation in which the input and output of the circuit to be verified are always true within the hardware domain, and the second logical relationship is an arithmetic equivalence equation in which the input and output of the reference model are always true within the model domain. The verification module is also configured to perform consistency verification on the first output information and the second output information based on the first input information, the second input information, the first logical relationship and the second logical relationship, to obtain the target verification result of the circuit to be verified. The target verification result is used to verify whether the circuit processing logic and the model processing logic are consistent.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

9. An electronic device, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 6.

10. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 6.

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