CXL switch chip and the motherboard layout topology optimization method of nearby CXL type 2 type 3 device

Abstract

The application discloses a CXL Switch chip and a mainboard layout topology optimization method of a nearby CXL Type 2 Type 3 device, comprising the following steps: acquiring type information of the connected CXL device; based on the type information, the Switch peripheral PCB layout is divided into partitions, forming a Type 3 device partition closer to the chip; according to the port connection device type difference, link budget, wiring constraint and chip internal resource priority are allocated, and the Type 3 port is required to be more stringent than the Type 2 port; high-frequency peer-to-peer communication pairs between devices are identified, and the physical layout order in the partition and the chip internal communication path are optimized; and a mainboard layout plan is generated and implemented. By shortening the Type 3 wiring, the memory delay is reduced, the differential link budget guarantees the signal integrity, the P2P communication is optimized, and the efficiency is improved.

Description

Technical Field

[0001] This invention relates to a method for optimizing the motherboard layout topology of a CXL switch chip and nearby CXL Type 2 and Type 3 devices, and particularly relates to the field of high-speed digital circuit design and server motherboard hardware layout technology. Background Technology

[0002] CXL (Compute Express Link), a high-speed cache coherent interconnect protocol built on the PCIe physical layer, has seen its SerDes rate increased to 64 GT / s in CXL 3.0. On a typical computing server motherboard, the CXL Switch chip serves as the core switching node of the CXL Fabric, requiring simultaneous connection to multiple CPU Root Ports and various types of CXL devices.

[0003] Current motherboard layouts typically place the CXL Switch chip in the center of the motherboard, with all Type 2 and Type 3 devices arranged radially around it. However, Type 2 devices (such as GPUs and FPGA accelerators) are characterized by high power consumption, high heat generation, and require a large PCB area and independent power planes, while Type 3 devices (such as CXL memory expanders) are extremely sensitive to latency, requiring the shortest possible trace distances to reduce CXL.mem access latency. The current "one-size-fits-all" layout does not consider the fundamental differences in power consumption, heat dissipation, trace length, and signal integrity requirements between the two types of devices, resulting in Type 3 devices potentially being placed far from the Switch, increasing memory access latency. Furthermore, the current layout design uses a uniform insertion loss budget for all downlink ports, failing to allocate differentiated link budgets based on device type, and lacks topology optimization for high-frequency peer-to-peer (P2P) communication between Type 2 and Type 3 devices, impacting P2P communication efficiency in scenarios such as AI training. Summary of the Invention

[0004] This invention provides a motherboard layout topology optimization method for CXL Switch chips and nearby CXL Type 2 and Type 3 devices to overcome the shortcomings of existing technologies, such as motherboard layout not distinguishing device types, not allocating link budgets differently, and not optimizing P2P communication between Type 2 and Type 3 devices.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0006] This invention discloses a motherboard layout topology optimization method for a CXL switch chip and nearby CXL Type 2 and Type 3 devices. The method includes obtaining device type information of multiple CXL devices connected to the CXL switch chip on a server motherboard, where the device types include Type 2 and Type 3 devices; based on the device type information, partitioning the PCB layout area surrounding the CXL switch chip to form a first partition and a second partition, wherein the first partition is dedicated to laying out Type 2 devices, and the second partition is dedicated to laying out Type 3 devices, with the second partition being closer to the CXL switch chip than the first partition; according to the device type connected to each downlink port on the CXL switch chip, differentially allocating link budget, routing parameter constraints, and internal chip resource priorities to each port, wherein the link budget for ports connected to Type 3 devices is stricter than that for ports connected to Type 2 devices; identifying high-frequency peer-to-peer communication pairs between the Type 2 and Type 3 devices, and based on the identification results, optimizing the physical layout order of the devices involved in the high-frequency peer-to-peer communication pairs within their respective partitions and the communication paths within the CXL switch chip; and generating a CXL switch chip based on the partitioning plan, differential allocation, and communication pair optimization results. The layout of the Switch motherboard is planned, and the physical implementation and chip configuration are carried out according to the layout plan.

[0007] Furthermore, the first partition is a computationally intensive region, and the second partition is a memory latency-sensitive region.

[0008] Furthermore, within the second partition, the trace length from the CXL Switch chip to the Type 3 device does not exceed a preset first distance threshold.

[0009] Furthermore, the differentiated allocation of link budgets for each port includes: allocating a first link budget to ports connected to Type 3 devices; and allocating a second link budget to ports connected to Type 2 devices that carry consistent traffic, wherein the second link budget is wider than the first link budget.

[0010] Furthermore, the first link budget is an insertion loss of no more than 12dB at a frequency of 32GHz, and the second link budget is an insertion loss of no more than 15dB at a frequency of 32GHz.

[0011] Furthermore, the identification of high-frequency peer-to-peer communication pairs includes: periodically collecting actual communication bandwidth data between each Type 2 device and each Type 3 device; smoothing the collected actual communication bandwidth data; comparing the smoothed bandwidth data with preset activation thresholds and release thresholds, and dynamically marking or removing high-frequency peer-to-peer communication pairs.

[0012] Furthermore, the smoothing process employs an exponentially weighted moving average method with a forgetting factor.

[0013] Furthermore, the motherboard layout topology optimization method for the CXL Switch chip and nearby CXL Type 2 and Type 3 devices also includes the step of feeding back the results of dynamically marking or removing high-frequency peer communication pairs to the physical layout order of the devices involved in the optimized high-frequency peer communication pairs within their respective partitions and the communication path within the CXL Switch chip, so as to update the layout optimization.

[0014] Furthermore, the calculation formula for the exponentially weighted moving average method with forgetting factor is as follows: ,in, Let be the smooth bandwidth between the i-th Type 2 device and the j-th Type 3 device after the t-th sampling period. Let be the communication bandwidth measured in the t-th sampling period. Forgetting factor, The forgetting factor This can be configured during system initialization, with a value such as 0.2. This formula clearly describes the fusion process of old and new data in the smoothing calculation, providing a mathematical basis for the calculation of new weights.

[0015] Furthermore, the release threshold is less than the activation threshold.

[0016] Furthermore, the partitioning and planning of the PCB layout area around the CXL Switch chip also includes: calculating the equivalent heat dissipation conflict degree of the candidate layout position of the Type 2 device in the first partition relative to the CXL Switch chip; when the equivalent heat dissipation conflict degree exceeds a preset conflict threshold, calculating a physical offset for the candidate layout position.

[0017] Furthermore, the equivalent heat dissipation conflict degree The calculation formula is: ,in, The number of Type 2 devices that have a thermal effect on candidate location k. For the first Thermal impact weighting coefficient for each Type 2 device For the first The transient power consumption of a Type 2 device within a sampling period t. For candidate position k and the first The distance between Type 2 devices To point from candidate position k to the first The azimuth angle of a Type 2 device, The direction angle of the main heat dissipation airflow. This formula quantifies the intensity of the power source ( ), distance decay effect ( ), and the coupling effect between the airflow and the heat source in relative directions ( This provides an objective and calculable basis for evaluating the heat dissipation of the layout location.

[0018] Furthermore, the motherboard layout topology optimization method for the CXL Switch chip and nearby CXL Type 2 / Type 3 devices also includes: monitoring the real-time insertion loss of each downlink port of the CXL Switch chip; calculating the link budget slack of each port based on the link budget allocated to each port and the real-time insertion loss; and dynamically adjusting the internal resource priority of the corresponding port using a proportional-integral controller based on the deviation between the link budget slack and the target slack.

[0019] Furthermore, the calculation formula for the proportional-integral controller is as follows: ,in, Let $p$ be the priority adjustment amount for port $p$ in the $t$-th update cycle. Let p be the link budget slack in the t-th update cycle. For target relaxation, This is the proportionality coefficient. The integral coefficient is... For the update cycle.

[0020] Furthermore, to ensure the first link budget of the port connecting the Type 3 device, a mechanical compensation structure is set between the packaging substrate and the PCB of the CXLSwitch chip for the differential traces of the port connecting the Type 3 device. The mechanical compensation structure includes a shape memory alloy spring and a non-equidistant helical spring linked with the spring, which is used to adaptively compensate for the delay changes caused by the thermal expansion of the traces at high temperatures.

[0021] This application provides a motherboard layout topology optimization method for a CXL switch chip and nearby CXL Type 2 and Type 3 devices, comprising: an information acquisition module for acquiring device type information of multiple CXL devices connected to the CXL switch chip on a server motherboard, wherein the device types include Type 2 devices and Type 3 devices; a partitioning planning module for partitioning the PCB layout area around the CXL switch chip based on the device type information, forming a first partition and a second partition, wherein the first partition is dedicated to laying out Type 2 devices, the second partition is dedicated to laying out Type 3 devices, and the second partition is closer to the CXL switch chip than the first partition; a budget allocation module for allocating link budgets, routing parameter constraints, and chip internal resource priorities to each port based on the device type connected to each downlink port on the CXL switch chip, wherein the link budget for ports connected to Type 3 devices is stricter than that for ports connected to Type 2 devices; and a communication pair optimization module for identifying high-frequency peer-to-peer communication pairs existing between the Type 2 devices and the Type 3 devices, and optimizing the physical layout order of the devices involved in the high-frequency peer-to-peer communication pairs within their respective partitions and the layout order of the CXL switch chip based on the identification results. The internal communication path of the Switch chip; the layout implementation module is used to generate the CXL Switch motherboard layout plan based on the partitioning plan, differentiated allocation and communication pair optimization results, and to perform physical implementation and chip configuration according to the layout plan.

[0022] This application provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement a method for optimizing the motherboard layout topology of a CXL Switch chip and nearby CXL Type 2 and Type 3 devices.

[0023] This application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a method for optimizing the motherboard layout topology of a CXL Switch chip and nearby CXL Type 2 / Type 3 devices.

[0024] The beneficial effects achieved by this invention are as follows: By partitioning the PCB surrounding the CXL Switch based on device type, Type 3 devices are placed in the second partition closer to the Switch, significantly shortening the trace length and thus reducing CXL.mem access latency; By differentially allocating link budgets to the ports connecting Type 3 and Type 2 devices, Type 3 device ports receive a more stringent link budget (e.g., 12dB@32GHz) to ensure signal integrity meets low latency requirements, while Type 2 device ports receive a moderately more lenient budget (e.g., 15dB@32GHz) to balance routing flexibility; By identifying and optimizing high-frequency P2P communication pairs between Type 2 and Type 3 devices, the device layout order and internal communication paths of the Switch chip are further optimized based on partitioning, enabling high-frequency P2P communication pairs to achieve the shortest physical path and lowest internal switching latency. Furthermore, by employing additional methods such as dynamic smoothing identification of P2P communication pairs, layout offset based on thermal conflict metric, dynamic priority adjustment based on link budget slack, and mechanical compensation structure, the robustness of the system in terms of dynamic load, thermal transients, and signal integrity is further enhanced. This achieves a comprehensive and beneficial effect of significantly reduced memory access latency, targeted protection of signal integrity, substantial improvement in P2P communication efficiency, and coordinated optimization of heat dissipation and signal integrity. Attached Figure Description

[0025] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0026] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0027] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0028] Example 1

[0029] Terminology Explanation:

[0030] CXL Switch chip: refers to a switching chip built based on the CXL protocol, which has multiple downlink ports for connecting CXL terminal devices.

[0031] CXL devices refer to external devices that conform to the CXL protocol. Downlink connection types in CXL Switches are mainly divided into Type 2 devices and Type 3 devices.

[0032] Type 2 devices: refer to CXL devices that support the CXL.io, CXL.cache and CXL.mem protocols, such as GPUs and FPGA accelerators, which usually come with local high-bandwidth memory.

[0033] Type 3 devices: These are CXL devices that support the CXL.io and CXL.mem protocols, typically such as CXL memory expansion cards or memory pooling devices, which primarily provide memory expansion functionality.

[0034] Equipment type information: refers to the classification information that identifies whether a specific CXL equipment belongs to Type 2 or Type 3.

[0035] First zone: refers to the physical area on the PCB (printed circuit board) surrounding the CXL Switch chip that is dedicated to the layout of Type 2 devices, also known as the compute-intensive zone.

[0036] The second partition refers to the physical area on the PCB surrounding the CXL Switch chip that is dedicated to the layout of Type 3 devices. It is closer to the CXL Switch chip than the first partition and is also known as the memory latency sensitive area.

[0037] Link budget: refers to the maximum allowable loss (such as insertion loss) of a signal from the transmitter to the receiver at a specific frequency (such as 32GHz).

[0038] Trace parameter constraints: These refer to the physical parameters of the signal traces on the PCB that connect the CXL device and the CXL Switch chip, such as trace length, width, and spacing.

[0039] High-frequency peer-to-peer communication pair: refers to a pair of communication partners between a Type 2 device and a Type 3 device whose communication bandwidth exceeds a preset threshold and needs to be optimized.

[0040] like Figure 1 As shown, a method for optimizing the motherboard layout topology of a CXL switch chip and nearby CXL Type 2 / Type 3 devices includes the following steps:

[0041] S101, Obtain device type information of multiple CXL devices connected to the CXL Switch chip on the server motherboard. The device types include Type 2 devices and Type 3 devices;

[0042] S102, based on the device type information, the PCB layout area around the CXL Switch chip is partitioned to form a first partition and a second partition. The first partition is dedicated to laying out Type 2 devices, and the second partition is dedicated to laying out Type 3 devices. The second partition is closer to the CXL Switch chip than the first partition.

[0043] S103, based on the device type connected to each downlink port on the CXL Switch chip, allocate link budget, routing parameter constraints and chip internal resource priority to each port in a differentiated manner. Among them, the link budget of the port connected to the Type 3 device is stricter than that of the port connected to the Type 2 device.

[0044] S104, identify the high-frequency peer communication pair between the Type 2 device and the Type 3 device, and based on the identification result, optimize the physical layout order of the devices involved in the high-frequency peer communication pair in their respective partitions and the communication path inside the CXL Switch chip;

[0045] S105 generates a CXL Switch motherboard layout plan based on the partitioning plan, differentiated allocation, and communication pair optimization results, and performs physical implementation and chip configuration based on the layout plan.

[0046] In this embodiment, steps S101 to S105 work together to form a complete three-level collaborative optimization logic (DPL-P2P) of "partition layout-budget allocation-topology optimization". The partitioning plan formed in step S102 is based on the device type identified in S101, establishing a physical space foundation for subsequent steps (budget allocation and P2P optimization). The differentiated budget allocation in step S103 ensures that the Type 3 port, which is most sensitive to latency, receives the most stringent signal integrity guarantee, while the Type 2 port, which has higher requirements for wiring flexibility, receives a moderately relaxed constraint. Step S104 optimizes the high-frequency data exchange requirements in typical application scenarios (such as AI training) at both the physical layout and internal chip path levels to minimize P2P communication latency. Ultimately, the layout plan generated in step S105 integrates the results of partitioning, budgeting, and topology optimization, providing clear and consistent guidance for actual PCB layout, routing design, and port configuration of the CXL Switch chip. This collectively solves the technical problems of existing layout methods failing to meet the differentiated needs of Type 2 and Type 3 devices and poor P2P communication performance, achieving a comprehensive technical effect of reducing memory access latency, ensuring signal integrity, and improving P2P communication efficiency.

[0047] Taking a specific application scenario of an AI training server as an example, in the design phase, the first step, S101, is to obtain a list of CXL devices that will be connected to the CXL Switch, including 4 GPUs (Type 2 devices) and 2 CXL memory expansion cards (Type 3 devices). Then, in step S102, the area of ​​the motherboard closest to the CXL Switch chip is designated as a memory latency-sensitive area (i.e., the second partition), and the area further from the Switch but closer to the motherboard edge and heat dissipation duct is designated as a compute-intensive area (i.e., the first partition). Next, in step S103, based on the device attributes, stringent insertion loss budgets (e.g., ≤12dB@32GHz) and short trace length constraints (e.g., ≤8 inches) are set for the ports connecting the memory expansion cards, while relatively lenient budgets (e.g., ≤15dB@32GHz) and medium distance constraints (e.g., ≤12 inches) are set for the ports connecting the GPUs. Based on this, step S104 identifies a high-frequency P2P communication requirement between GPU-A and memory card-1. Therefore, the layout is optimized by placing memory card-1 closer to GPU-A and configuring a direct path between the internal ports of the Switch. Finally, in step S105, the above optimization decisions are integrated into a detailed layout scheme and chip configuration script to guide motherboard hardware design and system deployment.

[0048] In one embodiment, regarding the aforementioned partitioning plan, the first partition is specifically called the compute-intensive zone, and the second partition is specifically called the memory latency-sensitive zone. The compute-intensive zone is specifically designed to accommodate high-power computing acceleration devices such as Type 2, while the memory latency-sensitive zone is specifically designed to accommodate memory expansion devices such as Type 3, which are extremely sensitive to access latency. The partition naming directly reflects their functional attributes and optimization goals, making the layout design intent clearer. Furthermore, this naming method allows the optimization principles to be intuitively reflected in PCB layout drawings and related technical documents, facilitating team member collaboration and solution review.

[0049] In one embodiment, a strict proximity rule is set for the aforementioned second partition: within the second partition, the trace length from the CXL Switch chip to the Type 3 device does not exceed a preset first distance threshold. This first distance threshold, for example, is reliably less than 500 mil (approximately 12.7 mm). This rule aims to force the Type 3 device to be placed in an adjacent area of ​​the CXL Switch chip. Furthermore, combining the above principles, the beneficial effects of this approach are: strictly limiting the physical location of the Type 3 device, thereby minimizing the memory access propagation latency of the CXL.mem protocol at the physical level, directly solving the core problem of the Type 3 device's latency sensitivity, and significantly improving the overall system performance in memory expansion scenarios.

[0050] In one embodiment, the step S103, which involves differentially allocating link budgets to each port as mentioned above, specifically includes: allocating a first link budget to ports connected to Type 3 devices; and allocating a second link budget, which is wider than the first link budget, to ports in Type 2 devices that carry consistency traffic. It should be clarified that some ports on Type 2 devices may simultaneously carry both CXL.cache consistency traffic and CXL.mem memory bandwidth traffic, and their jitter requirements are lower than those for pure memory access, thus allowing for a wider budget allocation. Furthermore, based on the above principles, the beneficial effects of this approach are: it achieves device protocol-driven, application-demand-oriented link budget allocation, avoiding the waste or insufficiency of resources through a "one-size-fits-all" approach, ensuring that Type 3 ports receive the low-latency guarantee they most need, while providing reasonable cabling flexibility for Type 2 ports.

[0051] In one embodiment, the first link budget is specifically defined as an insertion loss of no more than 12dB at a frequency of 32GHz, and the second link budget is specifically defined as an insertion loss of no more than 15dB at a frequency of 32GHz. These two values ​​are empirical thresholds determined based on the signal integrity model of CXL 3.0 at a rate of 64 GT / s. The first link budget (12dB) is 3dB lower than the second link budget (15dB), imposing stricter requirements on trace length, board material, and the number of vias. Furthermore, based on the above principles, the beneficial effects of this approach are: providing clear, quantifiable, and verifiable performance indicators for different types of ports, enabling PCB design engineers to route according to a unified standard, ensuring the reliability and consistency of the design scheme.

[0052] In one embodiment, the identification of high-frequency peer-to-peer communication pairs in step S104 mentioned above specifically includes: periodically collecting actual communication bandwidth data between each Type 2 device and each Type 3 device; smoothing the collected actual communication bandwidth data; comparing the smoothed bandwidth data with preset activation and release thresholds, and dynamically marking or removing high-frequency peer-to-peer communication pairs. This dynamic identification mechanism overcomes the shortcomings of static identification only performed once during the system design phase. Furthermore, based on the above principles, the beneficial effects of this approach are: it can adapt to changes in actual business load, ensuring that the optimization target is always the device pair with truly high-frequency communication, avoiding performance waste or bottlenecks caused by optimization based on outdated or inaccurately predicted data, and significantly enhancing the adaptability and real-time performance of P2P topology optimization to dynamic loads.

[0053] In one embodiment, the smoothing process described above can employ an exponentially weighted moving average (EWMA) method with a forgetting factor. As a specific implementation, this method assigns higher weights to new data through a forgetting factor, causing the smoothing result to gradually decrease its dependence on historical data, thereby better reflecting recent changes in communication patterns.

[0054] In one embodiment, the motherboard layout topology optimization method for the CXL Switch chip and nearby CXL Type 2 / Type 3 devices further includes: feeding back the results of dynamically marking or removing high-frequency peer communication pairs to the step of optimizing the physical layout order of the devices involved in the high-frequency peer communication pairs within their respective partitions and the communication paths within the CXL Switch chip, in order to update the layout optimization. This closed-loop feedback mechanism means that P2P optimization is a continuous and adaptive adjustment process. Furthermore, based on the above principles, the beneficial effects of this approach are: it enables the P2P optimization strategy to respond in real time to changes in the runtime environment, and can adjust the device layout order (such as recalculating the sorting through simulated annealing) and the internal path configuration of the Switch as needed, providing a mechanism to ensure that the system maintains optimal P2P communication performance during long-term operation.

[0055] In one embodiment, the calculation formula for the above-mentioned exponentially weighted moving average method with a forgetting factor is as follows: ,in, Let be the smooth bandwidth between the i-th Type 2 device and the j-th Type 3 device after the t-th sampling period. Let be the communication bandwidth measured in the t-th sampling period. Forgetting factor, As a specific implementation method, this forgetting factor This can be configured during system initialization, with a value such as 0.2. This formula clearly describes the fusion process of old and new data in the smoothing calculation, providing a mathematical basis for the calculation of new weights.

[0056] In one embodiment, the release threshold is lower than the activation threshold. By setting the release threshold below the activation threshold, a hysteresis interval is formed. Furthermore, based on the above principle, the beneficial effects of this method are: it can avoid frequent changes in the marking state of high-frequency P2P communication pairs when the communication bandwidth fluctuates slightly around the activation threshold, thereby reducing unnecessary layout optimization computational overhead and system configuration disturbances caused by frequent state switching, and improving the stability of system operation.

[0057] In one embodiment, the step S102, which involves partitioning the PCB layout area surrounding the CXL Switch chip as mentioned above, further includes: calculating the equivalent thermal conflict degree of a candidate layout position of the Type 2 device relative to the CXLSwitch chip within the first partition; and calculating a physical offset for the candidate layout position when the equivalent thermal conflict degree exceeds a preset conflict threshold. This introduces a quantitative constraint on thermal factors for precise layout within the partition. Furthermore, based on the above principles, the beneficial effects of this approach are: it can accurately locate and quantify the impact of the Type 2 device's heat dissipation airflow on the CXL Switch chip and its sensitive ports, and provide precise quantitative guidance for layout adjustments by calculating the offset, thereby physically minimizing the negative impact of high heat on the signal integrity of the CXL Switch chip and achieving synergistic optimization of heat dissipation and signal integrity.

[0058] In one embodiment, the aforementioned equivalent heat dissipation conflict degree The calculation formula is: ,in, The number of Type 2 devices that have a thermal effect on candidate location k. For the first Thermal impact weighting coefficient for each Type 2 device For the first The transient power consumption of a Type 2 device within a sampling period t. For candidate position k and the first The distance between Type 2 devices To point from candidate position k to the first The azimuth angle of a Type 2 device, The direction angle of the main heat dissipation airflow. As a specific implementation method, this formula quantifies the intensity of the power source ( ), distance decay effect ( ), and the coupling effect between the airflow and the heat source in relative directions ( This provides an objective and calculable basis for evaluating the heat dissipation of the layout location.

[0059] In one embodiment, the motherboard layout topology optimization method for the CXL Switch chip and nearby CXL Type 2 / Type 3 devices further includes: monitoring the real-time insertion loss of each downlink port of the CXL Switch chip; calculating the link budget slack of each port based on the link budget allocated to each port and the real-time insertion loss; and dynamically adjusting the internal resource priority of the corresponding port using a proportional-integral controller based on the deviation between the link budget slack of each port and the target slack. This achieves dynamic and closed-loop port resource management. Furthermore, based on the above principles, the beneficial effects of this approach are: it can adjust port priorities in real time according to the actual link quality (which may change due to factors such as temperature and aging), ensuring that ports with tight link budget margins receive more support from internal Switch resources (such as arbitration queue weight and buffer depth), thereby optimizing the utilization efficiency of limited internal resources while ensuring signal quality, and improving the robustness and adaptability of the system.

[0060] In one embodiment, the calculation formula for the proportional-integral controller is as follows: ,in, Let $p$ be the priority adjustment amount for port $p$ in the $t$-th update cycle. Let p be the link budget slack in the t-th update cycle. For target relaxation, This is the proportionality coefficient. The integral coefficient is... The update cycle is specified. As a specific implementation, the controller can automatically calculate the priority adjustment compensation based on the current deviation (proportional term) and the historical cumulative deviation (integral term). The integral term can eliminate steady-state error and avoid frequent and unnecessary priority jumps caused by minor fluctuations in the link, making the adjustment process smoother and more stable.

[0061] In one embodiment, to ensure the first link budget of the port connecting to the Type 3 device, a mechanical compensation structure is set between the packaging substrate of the CXL Switch chip and the PCB for the differential traces of the port connecting to the Type 3 device. This mechanical compensation structure includes a shape memory alloy spring and a non-equidistant helical spring linked to the spring, used to adaptively compensate for delay changes caused by thermal expansion of the traces at high temperatures. This structure provides a passive physical layer compensation scheme. Furthermore, based on the above principles, the beneficial effects of this approach are: direct passive and adaptive compensation for signal delay changes caused by thermal expansion, without the need for external power supply or control logic, helping to maintain a strict link budget (≤12dB) for the P-Mem port under all temperature conditions (especially high temperatures), and enhancing system stability in thermal transient environments.

[0062] It should be noted that, in some optional implementations, the motherboard layout topology optimization methods for the CXL Switch chip and nearby CXL Type 2 / Type 3 devices include, but are not limited to:

[0063] The first distance threshold can be 500 mil or other values ​​optimized according to process and design requirements.

[0064] Forgetting factor The value can range from 0.1 to 0.3.

[0065] Activation threshold and release threshold It can be set according to the total system bandwidth and expected load, for example 70% of the peak bandwidth can be used. Desirable 50%.

[0066] Parameters in the calculation of equivalent heat dissipation conflict degree, such as the conflict threshold It can be calibrated experimentally, for example, by setting it to 5W / inch.

[0067] Target slack in dynamic priority adjustment It can be set to 1.5dB.

[0068] The material for shape memory alloy springs can be nickel-titanium alloy (NiTi), and its austenitic phase transformation completion temperature Af can be selected at around 85℃ according to design requirements. The relationship between the spring's deformation displacement and temperature can be designed based on the material properties. Non-equidistant helical springs are designed with a gradually changing pitch to provide non-linear inductance changes.

[0069] Furthermore, the specific implementation of the technical solutions described in the above embodiments can rely on software, hardware, or a combination of both.

[0070] Information can be retrieved by reading VPD (Very Important Product Data or Virtual Commodity Data) from the system BMC (Baseboard Management Controller) or by being issued by Fabric Manager.

[0071] Computationally intensive operations such as zoning planning, budget allocation, P2P communication for identification and optimization can run on dedicated layout planning software, system management software, or dedicated FPGA logic.

[0072] Layout planning and chip configuration can be output as Gerber files (PCB production), constraint files (routing tools), and switch configuration register scripts.

[0073] Example of CXL Switch motherboard layout optimization device

[0074] This application also provides a CXL Switch motherboard layout optimization device. The CXL Switch motherboard layout optimization device includes:

[0075] The information acquisition module is used to acquire the device type information of multiple CXL devices connected to the CXL Switch chip on the server motherboard. The device types include Type 2 devices and Type 3 devices.

[0076] The partitioning planning module is used to partition the PCB layout area around the CXL Switch chip based on the device type information, forming a first partition and a second partition. The first partition is dedicated to laying out Type 2 devices, and the second partition is dedicated to laying out Type 3 devices. The second partition is closer to the CXL Switch chip than the first partition.

[0077] The budget allocation module is used to allocate link budget, routing parameter constraints and chip internal resource priorities to each port based on the type of device connected to each downlink port on the CXL Switch chip. Among them, the link budget of the port connected to the Type 3 device is stricter than that of the port connected to the Type 2 device.

[0078] The communication pair optimization module is used to identify high-frequency peer communication pairs between the Type 2 device and the Type 3 device, and based on the identification results, optimize the physical layout order of the devices involved in the high-frequency peer communication pair in their respective partitions and the communication path inside the CXL Switch chip.

[0079] The layout implementation module is used to generate the CXLSwitch motherboard layout plan based on the partitioning plan, differentiated allocation and communication pair optimization results, and to perform physical implementation and chip configuration based on the layout plan.

[0080] This device achieves all the functions of the aforementioned method embodiments through the coordinated operation of its various modules, and possesses the same technical effects.

[0081] This application also provides an electronic device, including a memory and a processor. The memory stores a computer program, and the processor executes the program to implement a motherboard layout topology optimization method for CXL Switch chips and nearby CXL Type 2 and Type 3 devices. This electronic device can be a server, workstation, personal computer, or other device with computing capabilities.

[0082] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a motherboard layout topology optimization method for the CXL Switch chip and nearby CXL Type 2 / Type 3 devices. The storage medium can be any medium capable of storing program code, such as a disk, optical disk, or semiconductor memory.

[0083] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A method for optimizing the motherboard layout topology of CXL switch chips and nearby CXL Type 2 / Type 3 devices, characterized in that... This includes obtaining device type information of multiple CXL devices connected to the CXL Switch chip on the server motherboard, the device types including Type 2 devices and Type 3 devices; based on the device type information, partitioning the PCB layout area around the CXL Switch chip to form a first partition and a second partition, wherein the first partition is dedicated to laying out Type 2 devices, the second partition is dedicated to laying out Type 3 devices, and the second partition is closer to the CXL Switch chip than the first partition; Based on the device type connected to each downlink port on the CXL Switch chip, link budget, routing parameter constraints, and chip internal resource priorities are allocated to each port in a differentiated manner. Among them, the link budget of the port connected to the Type 3 device is stricter than that of the port connected to the Type 2 device. Identify high-frequency peer-to-peer communication pairs existing between the Type 2 device and the Type 3 device, and based on the identification results, optimize the physical layout order of the devices involved in the high-frequency peer-to-peer communication pairs within their respective partitions and the communication path within the CXLSwitch chip; Based on the partitioning plan, differentiated allocation, and communication pair optimization results, a CXL Switch motherboard layout plan is generated, and physical implementation and chip configuration are carried out according to the layout plan.

2. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 1, characterized in that, The first partition is a computationally intensive area, and the second partition is a memory latency-sensitive area.

3. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 2, characterized in that, Within the second partition, the trace length from the CXL Switch chip to the Type 3 device does not exceed a preset first distance threshold.

4. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 1, characterized in that, The differentiated allocation of link budgets for each port includes: Allocate the first link budget to the port connecting the Type 3 device; A second link budget is allocated to the port carrying consistent traffic in the connected Type 2 device. The second link budget is wider than the first link budget.

5. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 4, characterized in that, The first link budget is an insertion loss of no more than 12dB at a frequency of 32GHz, and the second link budget is an insertion loss of no more than 15dB at a frequency of 32GHz.

6. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 1, characterized in that, The identification of high-frequency peer-to-peer communication pairs includes: Periodically collect actual communication bandwidth data between each Type 2 device and each Type 3 device; The collected actual communication bandwidth data is smoothed. The smoothed bandwidth data is compared with preset activation and release thresholds to dynamically mark or remove high-frequency peer communication pairs.

7. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 6, characterized in that, The smoothing process employs an exponentially weighted moving average method with a forgetting factor.

8. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 6, characterized in that, The method further includes: The results of dynamically marking or removing high-frequency peer communication pairs are fed back to the steps of optimizing the physical layout order of the devices involved in the high-frequency peer communication pairs within their respective partitions and the communication paths within the CXL Switch chip, in order to update the layout optimization.

9. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 8, characterized in that, The calculation formula for the exponentially weighted moving average method with forgetting factor is as follows: ,in, Let be the smooth bandwidth between the i-th Type 2 device and the j-th Type 3 device after the t-th sampling period. Let be the communication bandwidth measured in the t-th sampling period. Forgetting factor, .

10. The method for optimizing the motherboard layout topology of the CXL Switch chip and nearby CXL Type 2 / Type 3 devices according to claim 8, characterized in that, The release threshold is less than the activation threshold.

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