Chip, electronic device and chip performance optimization method
Patent Information
- Application Number
- CN202510330203.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-19
- Publication Date
- 2026-09-22
AI Technical Summary
[0002]传统的SOC(System-on-Chip)芯片大都集成在一个Die(芯片未封装前的晶粒)上，随着设计复杂度和电路规模的增加，在将不同功能模块集成在一个芯片上时，如果当芯片上的某个环节出错会导致整个芯片失效，进而导致生产难度增加，良率降低
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Figure CN122797441A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of electronic circuits, specifically relating to a chip, electronic device, and chip performance optimization method. Background Technology
[0002] Traditional SOC (System-on-Chip) chips are mostly integrated on a single die (the chip before packaging). As design complexity and circuit scale increase, when different functional modules are integrated on a single chip, if a certain part of the chip malfunctions, the entire chip will fail, leading to increased production difficulty and reduced yield.
[0003] Chiplet technology solves the problems faced by traditional SoCs by dividing modules with different functions into multiple dies and then integrating them through advanced packaging. However, it also introduces new problems. Due to the increase in paths between dies, the use of the original interrupt technology solution will lead to a decrease in computer performance. Summary of the Invention
[0004] Therefore, the purpose of this application is to provide a chip, an electronic device, and a chip performance optimization method to reduce chip interrupt latency and improve processing performance.
[0005] The embodiments of this application are implemented as follows:
[0006] In a first aspect, embodiments of this application provide a chip, including: an I / O module and multiple computing modules; the I / O module is configured to broadcast an interrupt request corresponding to the current data read / write request to all computing modules each time a data read / write request is sent; and to send the next data read / write request after receiving an interrupt response returned by a target computing module in response to the interrupt request, without waiting for all interrupt requests to return interrupt responses; wherein, the target computing module is the computing module among the multiple computing modules responsible for processing the interrupt request.
[0007] In the above embodiments, after the IO module broadcasts the interrupt request corresponding to the current data read / write request to all computing modules, it sends the next data read / write request as soon as it receives the interrupt response returned by the target computing module (the computing module responsible for handling the interrupt request) and does not need to wait for all interrupt requests to return interrupt responses. Compared to the method that requires all interrupt requests to return interrupt responses after broadcasting the interrupt request before sending the next data read / write request, the method shown in this application can reduce the waiting time for reading and writing subsequent data, reduce existing interrupt latency, and improve processing performance because it does not need to wait for all interrupt requests to return interrupt responses.
[0008] In one possible implementation of the first aspect embodiment, the I / O module receives the interrupt response returned by each computing module in response to the interrupt request at different times; the I / O module is further configured to detect whether the received interrupt response is the interrupt response returned by the target computing module each time it receives the interrupt response returned by the computing module in response to the interrupt request.
[0009] In the above embodiments, since the I / O module receives the interrupt response returned by each computing module at different times, the I / O module can detect whether the received interrupt response is returned by the target computing module as soon as it receives the interrupt response. This helps to determine in a timely manner whether the interrupt response returned by the target computing module (the computing module responsible for handling the interrupt request) has been received, so as to send the next data read / write request in a timely manner, which helps to reduce the waiting time for reading and writing subsequent data and reduce the existing interrupt latency.
[0010] In one possible implementation of the first aspect embodiment, the IO module is further configured to detect the content contained in each received interrupt response, and when the content contained in the interrupt response contains a definite status bit, determine that the interrupt response returned by the target computing module has been received; or when the content contained in the interrupt response contains a negative status bit, determine that the current interrupt response is not an interrupt response returned by the target computing module.
[0011] In the above embodiments, since the interrupt response returned by the computing module responsible for handling interrupts is different from the interrupt response returned by the computing module not responsible for handling interrupts, the interrupt response can be quickly determined by analyzing the content contained in the interrupt response, thereby improving efficiency.
[0012] In one possible implementation of the first aspect embodiment, the chip further includes a timer configured to start timing when an interrupt request corresponding to the current data read / write request is sent; the IO module is configured to detect whether interrupt responses corresponding to all interrupt requests are received when the count of the timer is greater than a first threshold, and if no interrupt responses corresponding to all interrupt requests are received when the count of the timer is greater than the first threshold, an anomaly is recorded.
[0013] In the above embodiment, timing begins when an interrupt request is sent. After a preset time (i.e., a first threshold) following the sending of the interrupt request, it is also checked whether interrupt responses corresponding to all interrupt requests have been received. If no interrupt responses corresponding to all interrupt requests are received after the preset time, an anomaly is recorded, so that timely intervention can be made based on the recorded results, thereby ensuring the normal operation of the system.
[0014] In one possible implementation of the first aspect embodiment, the IO module is further configured to send an error message and suspend sending data read / write requests when the number of recorded anomalies is greater than or equal to a second threshold.
[0015] In the above embodiments, in order to reduce the impact of occasional events, error information is sent only when the number of recorded anomalies is greater than or equal to the second threshold (configurable, such as 2), and data read / write requests are suspended when the number of anomalies is greater than or equal to the second threshold, thereby saving power consumption.
[0016] In one possible implementation of the first aspect embodiment, the IO module includes: an IO device and an interrupt controller; the IO device is configured to send an interrupt request to the interrupt controller each time a data read / write request is sent; the interrupt controller is configured to broadcast the interrupt request to all computing modules upon receiving the interrupt request; and to send an interrupt response from the target computing module to the IO device upon receiving an interrupt response from the target computing module in response to the interrupt request, without waiting for all interrupt requests to return interrupt responses; the IO device is further configured to send the next data read / write request upon receiving the interrupt response from the interrupt controller.
[0017] In the above embodiments, the interrupt controller is used to broadcast interrupt requests to the computing module and to analyze and process the received interrupt responses. This is beneficial to improving efficiency. When the interrupt response is received from the target computing module in response to the interrupt request, and without waiting for all interrupt requests to return interrupt responses, the interrupt response from the target computing module is sent to the I / O device. This allows the I / O device to send the next data read / write request in a timely manner, thereby reducing the waiting time for subsequent data read / write, reducing existing interrupt latency, and improving processing performance.
[0018] Secondly, embodiments of this application also provide an electronic device, including: a chip as described in any possible manner in the first aspect of the embodiments above.
[0019] Thirdly, embodiments of this application also provide a chip performance optimization method, comprising: broadcasting an interrupt request corresponding to the current data read / write request to all computing modules in the chip each time a data read / write request is sent; detecting whether the received interrupt response is an interrupt response returned by a target computing module each time an interrupt response is received in response to the interrupt request; wherein the target computing module is the computing module responsible for processing the interrupt request; and sending the next data read / write request when an interrupt response is received from the interrupt request returned by the target computing module and without waiting for all interrupt requests to return interrupt responses.
[0020] In one possible implementation of the third aspect embodiment, detecting whether a received interrupt response is an interrupt response returned by the target computing module includes: detecting the content contained in each received interrupt response; determining that an interrupt response returned by the target computing module has been received when the content contained in the interrupt response contains a definite status bit, or determining that the current interrupt response is not an interrupt response returned by the target computing module when the content contained in the interrupt response contains a negative status bit.
[0021] In one possible implementation of the third aspect embodiment, the method further includes: after sending the interrupt request, detecting whether interrupt responses corresponding to all interrupt requests are received within a preset time; if no interrupt responses corresponding to all interrupt requests are received after the preset time, then an anomaly is recorded.
[0022] In one possible implementation of the third aspect embodiment, the method further includes: when the number of recorded anomalies is greater than or equal to a threshold, sending an error message and suspending the sending of data read / write requests.
[0023] Other features and advantages of this application will be set forth in the following description. The objectives and other advantages of this application can be realized and obtained through the structures specifically pointed out in the written description and the accompanying drawings. Attached Figure Description
[0024] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the accompanying drawings used in the embodiments will be briefly described below. Obviously, the drawings described below are only some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings.
[0025] Figure 1 A schematic diagram of the structure of the first type of chip provided in this application embodiment is shown.
[0026] Figure 2 A schematic diagram of the structure of the second type of chip provided in an embodiment of this application is shown.
[0027] Figure 3 A schematic diagram of the structure of the third type of chip provided in the embodiments of this application is shown.
[0028] Figure 4 This paper illustrates a schematic diagram of the chip provided in an embodiment of this application when handling interrupts.
[0029] Figure 5 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown.
[0030] Figure 6 A schematic flowchart of a chip performance optimization method provided in an embodiment of this application is shown. Detailed Implementation
[0031] The technical solutions of the embodiments of this application will now be described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. The following embodiments are provided as examples to more clearly illustrate the technical solutions of this application, and should not be used to limit the scope of protection of this application. Those skilled in the art will understand that, without conflict, the following embodiments and features can be combined with each other.
[0032] It should be noted that similar reference numerals and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus.
[0033] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0034] In the description of the embodiments of this application, unless otherwise expressly specified and limited, the technical term "connection" can be a direct connection or an indirect connection through an intermediate medium.
[0035] Given that traditional interrupt technologies used in SoC chips can degrade the performance of chips using chiplet technology, this application provides a method for optimizing chip performance. This method can reduce existing interrupt latency, thereby improving processing performance. The chip provided in this application's embodiments can be a chip using chiplet technology.
[0036] The following is combined Figure 1 The chip provided in the embodiments of this application will be described. This chip includes an I / O (Input / Output) module and multiple computing modules. For example, Figure 1 The chip shown includes six computing modules: computing module 0, computing module 1, computing module 2, computing module 3, computing module 4, and computing module 5.
[0037] Figure 1 The computing module shown can be a complex structure that integrates multiple processing cores, caches, interconnect modules and other key functional units on a single silicon die. Such a die can be called a CCD (Core Complex Die).
[0038] The IO module is configured to broadcast an interrupt request corresponding to the current data read / write request to all computing modules after each data read / write request is sent; and to send the next data read / write request only after receiving an interrupt response from the target computing module and without waiting for all interrupt requests to return interrupt responses. Compared to broadcasting an interrupt request and needing to receive interrupt responses from all interrupt requests before sending the next data read / write request, the method described in this application can reduce the waiting time for subsequent data read / write operations, reduce existing interrupt latency, and improve processing performance. The target computing module is the computing module responsible for handling interrupt requests among multiple computing modules.
[0039] Interrupts are an important mechanism in computer systems. When a computer is executing a normal program, it may need to temporarily suspend the current program's execution due to certain events. The interrupt service routine will then be used to handle the temporarily occurring events. After the interrupt service routine is completed, the computer will return to the normal program and continue running.
[0040] The aforementioned multiple data read / write requests can be multiple data read requests, multiple data write requests, or they can include both read and write requests. For example, they can include read / write requests that alternate between reading and writing.
[0041] In some possible implementations, each of the multiple computing modules is an independent die, and the transmission path length between each computing module and the I / O module is different. This causes the I / O module to receive the interrupt response returned by each computing module in response to the interrupt request at different times. That is, the I / O module does not receive the interrupt response returned by each computing module in response to the interrupt request at the same time.
[0042] In some implementations, multiple computing modules may include a first computing module and a second computing module. The first computing module is directly connected to the I / O module, and the second computing module is indirectly connected to the I / O module through the first computing module. The I / O module is configured to broadcast an interrupt request to the first computing module and, through the first computing module, to the second computing module. In this implementation, upon receiving an interrupt request, the first computing module broadcasts the interrupt request to the computing modules connected to it and sends interrupt responses from other computing modules to the I / O module.
[0043] The first computing module refers to the computing module directly connected to the I / O module, and the second computing module refers to the computing module indirectly connected to the I / O module. For example... Figure 1 Calculation modules 0 and 1 constitute the first calculation module, while calculation modules 2, 3, 4, and 5 constitute the second calculation module.
[0044] The IO module is also configured to detect whether the received interrupt response is returned by the target computing module each time it receives an interrupt response from the computing module in response to an interrupt request. As long as an interrupt response is received from the target computing module, the next data read / write request is sent.
[0045] Although the I / O module broadcasts interrupt requests to all computing modules, not all computing modules actually process the interrupt requests. The interrupt response returned by the computing module responsible for handling the interrupt is different from that returned by the computing module that is not responsible for handling the interrupt. By analyzing the contents of the interrupt response, it can be determined whether the interrupt response comes from the computing module that handles the interrupt or the computing module that is not responsible for handling the interrupt.
[0046] In some implementations, the IO module is also configured to detect the content contained in each received interrupt response, and if the content contained in the interrupt response contains a definite status bit, determine that the interrupt response returned by the target computing module has been received; or if the content contained in the interrupt response contains a negative status bit, determine that the current interrupt response is not an interrupt response returned by the target computing module.
[0047] The interrupt response may include status bits (such as ACK (short for Acknowledgment) or NACK (short for Negative Acknowledgment)). The status bits of the interrupt response returned by the computing module responsible for handling the interrupt may be different from those returned by the computing module not responsible for handling the interrupt. For example, the status bit of the interrupt response returned by the computing module responsible for handling the interrupt is ACK=1, while the status bit of the interrupt response returned by the computing module not responsible for handling the interrupt is NACK=1.
[0048] In some other implementations, it is also possible to detect whether the received interrupt response is an interrupt response returned by the target computing module in other ways. For example, after the target computing module completes the actual processing of the interrupt, it will pull the level of its connection line with the I / O module high or low. However, other computing modules that are not responsible for processing interrupts will not pull the level of their connection line with the I / O module high or low after returning the interrupt response. In this way, by analyzing the level state of the corresponding connection line, it can also be known whether the received interrupt response is an interrupt response returned by the target computing module.
[0049] In some implementations, the I / O module is also configured to check whether all interrupt responses for all interrupt requests have been received after sending the interrupt request corresponding to the current data read / write request. If no interrupt responses for all interrupt requests are received within a specified time, an exception is logged. Normally, the I / O module will receive interrupt responses for all interrupt requests within the specified time.
[0050] During the sending of multiple data read / write requests, multiple interrupt requests will be sent. Under normal circumstances, the IO module will receive the interrupt responses for all interrupt requests within a specified time. This application checks whether all interrupt responses have been received for each sent interrupt request. After checking the first sent interrupt request, it checks the second sent interrupt request, then the third sent interrupt request, and so on.
[0051] In some implementations, such as Figure 2 As shown, the chip also includes a timer, which is configured to start timing when an interrupt request corresponding to the current data read / write request is sent. The IO module is configured to check whether interrupt responses corresponding to all interrupt requests have been received when the timer count exceeds a first threshold. If no interrupt responses corresponding to all interrupt requests have been received when the timer count exceeds the first threshold, an exception is logged.
[0052] The aforementioned specified time can be a first threshold. The length of the transmission path between each computing module and the I / O module is fixed, and the corresponding time for each I / O module to receive the interrupt response returned by each computing module in response to an interrupt request is predictable. The first threshold can be determined based on the maximum time theoretically available among all the times when computing modules return interrupt responses to interrupt requests; for example, the first threshold is not less than this maximum time.
[0053] When logging exceptions, the IO module can record only the number of exceptions, or it can record the content of the exceptions, such as the calculation module that did not receive an interrupt response.
[0054] In some implementations, the I / O module is also configured to send an error message when the number of recorded exceptions is greater than or equal to a second threshold (configurable). To reduce the impact of occasional events, an error message is only sent when the number of recorded exceptions is greater than or equal to the second threshold (configurable, such as 2), thus improving the performance of the chip system. Furthermore, when the number of exceptions is greater than or equal to the second threshold, data read / write requests are paused, thereby saving power. When sending an error message, it can be sent to the central processing unit core.
[0055] The exception count refers to the number of times an exception is recorded. For example, if an exception is recorded for the first time, the exception count is 1. If no exception is recorded for the second time, the exception count is not updated and remains 1. If an exception is recorded for the first time and also for the second time, the exception count is 2, and so on.
[0056] In some possible implementations, the chip may also include a memory, and an I / O module is connected to the memory. The I / O module is configured to send data read / write requests to the memory. During the process of the I / O module sending multiple data read / write requests to the memory, each time a data read / write request is sent to the memory, an interrupt request corresponding to the current data read / write request is broadcast to all computing modules. As soon as an interrupt response is received from the computing module that handles the interrupt, the next data read / write request (let's say the second data read / write request) is immediately sent, and the interrupt request corresponding to the next data read / write request is broadcast to all computing modules, without waiting for all interrupt requests to return interrupt responses. Similarly, as soon as an interrupt response is received from the computing module that handles the next interrupt, the third data read / write request is immediately sent, and so on.
[0057] In some possible implementations, the memory may not be integrated into the chip; in this case, the I / O module is connected to the memory. The memory in the embodiments of this application may be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc.
[0058] In some possible implementations, such as Figure 3 As shown, the I / O module includes I / O devices and an interrupt controller, which can be connected via an interconnect network. I / O devices include, but are not limited to, PCIe (Peripheral Component Interconnect Express) cards (such as graphics cards), USB devices, etc.
[0059] The I / O device is configured to send an interrupt request to the interrupt controller each time a data read / write request is sent. The interrupt controller is configured to broadcast the interrupt request to all computing modules upon receiving it; and to send an interrupt response from the target computing module to the I / O device upon receiving an interrupt response from the target computing module, without waiting for all interrupt requests to return interrupt responses. The I / O device is also configured to send the next data read / write request upon receiving an interrupt response from the interrupt controller.
[0060] The interrupt controller is also configured to detect whether the received interrupt response is an interrupt response returned by the target computing module each time an interrupt response is received in response to an interrupt request from the computing module.
[0061] In one embodiment, the interrupt controller is further configured to detect the content contained in each received interrupt response, and if the interrupt response contains a definite status bit, determine that an interrupt response returned by the target computing module has been received; or if the interrupt response contains a negative status bit, determine that the current interrupt response is not an interrupt response returned by the target computing module.
[0062] In one embodiment, the interrupt controller is further configured to detect whether interrupt responses corresponding to all interrupt requests are received when the count of the timer is greater than a first threshold; if no interrupt responses corresponding to all interrupt requests are received when the count of the timer is greater than the first threshold, an anomaly is recorded.
[0063] In one embodiment, the interrupt controller is further configured to send an error message when the number of recorded exceptions is greater than or equal to a second threshold. When the number of recorded exceptions is greater than or equal to the second threshold, the I / O device is also configured to suspend sending data read / write requests.
[0064] In some possible implementations, the I / O devices in the aforementioned I / O module can be replaced with I / O interfaces. In this case, the I / O module includes an I / O interface and an interrupt controller, wherein the I / O interface is used to connect the I / O devices. The I / O devices send interrupt requests to the interrupt controller through the I / O interface.
[0065] The following is combined Figure 4The example shown illustrates how an I / O device sends data to memory, sends an interrupt request to the interrupt controller, and receives an interrupt response. Here, we use DDR (Double Data Rate) memory as an example to explain the principle of the above scheme, which is as follows:
[0066] 1) When an I / O device sends multiple data and interrupt requests (e.g., req0, req1, ..., reqn, where req0 represents the interrupt request corresponding to the first data sent by the I / O module, req1 represents the interrupt request corresponding to the second data sent by the I / O module, and so on, with reqn representing the interrupt request corresponding to the (n+1)th data sent), it first sends the first data and interrupt request req0 to the Internet, such as... Figure 4 Step ① is shown in the diagram. Among them, Figure 4 The document does not provide an example of the process of an I / O device sending data to the Internet; it only illustrates the process of sending an interrupt request. 2) The first piece of data sent by the I / O device is sent to the DDR via the Internet, and the first interrupt request req0 sent by the I / O device is sent to the interrupt controller via the Internet, such as... Figure 4 Step ② in the process.
[0067] 3) The interrupt controller broadcasts the interrupt request req0 to all computing modules, such as... Figure 4 The process involves steps ③ (req0_0), ④ (req0_1), ⑤ (req0_2), and ⑥ (req0_3), followed by waiting for the returned interrupt responses rsp0_0, req0_1, req0_2, and req0_3. Specifically, after receiving the interrupt request req0 from the I / O device, the interrupt controller first broadcasts the interrupt request req0 to computing modules 0 and 1. Computing modules 0 and 1, upon receiving the broadcast interrupt request from the interrupt controller, then broadcast the interrupt request to their connected computing modules 2 and 3. Upon receiving the interrupt request, each computing module returns the corresponding interrupt response rsp0. Computing modules 0 and 1 can directly return the corresponding interrupt responses rsp0_0 and req0_1 to the interrupt controller. Computing module 2 returns the interrupt response req0_2 to computing module 0, which then forwards it to the interrupt controller. Similarly, computing module 3 returns the interrupt response req0_3 to computing module 1, which then forwards it to the interrupt controller. Figure 4In the diagram, `req0_0` represents an interrupt request `req0` broadcast to computing module 0, `req0_1` represents an interrupt request `req0` broadcast to computing module 1, and so on. Similarly, `rsp0_0` represents the interrupt response `rsp0` returned by computing module 0 in response to interrupt request `req0`, `rsp0_1` represents the interrupt response `rsp0` returned by computing module 1 in response to interrupt request `req0`, and so on.
[0068] 4) Assuming the current interrupt handling module is computation module 0, when the interrupt controller receives the interrupt response rsp0_0 from computation module 0, it immediately returns rsp0_0 to the internet, and then returns rsp0_0 to the I / O device via the internet, without waiting to receive the other interrupt responses rsp0_1, rsp0_2, and rsp0_3. Figure 4 Step ⑦ in the process.
[0069] 5) After receiving the interrupt response rsp0_0 for the previous data, the I / O device sends the second data and interrupt request req1 to the Internet. It then waits for the second interrupt response to return before sending the third data and interrupt request, and so on. Because the I / O device does not need to wait for all interrupt requests from the previous data to return interrupt responses when sending the next data (e.g., when sending the second data), it only needs to receive the interrupt response rsp0_0 from the interrupt handling module 0 to send the next data and its corresponding interrupt request. This reduces the waiting time for reading and writing subsequent data, lowers existing interrupt latency, and improves processing performance.
[0070] for Figure 4 As illustrated, this technical solution theoretically reduces the latency between at least two dies during the transmission of two adjacent data packets. For example, in the example above, the IO module only needs to receive the interrupt response returned by the computing module 0 to send the next data packet and interrupt request to the Internet, without waiting for the interrupt response returned by the computing module 2 or computing module 3. The interrupt response returned by the computing module 2 or computing module 3, compared to the interrupt response returned by the computing module 0, has a latency that increases by at least two dies. Since each data packet transmission reduces the latency by at least two dies, the cumulative latency increases with the number of data transmissions, resulting in a more and more significant performance improvement.
[0071] Figure 4 The data shown can be read data, write data, or both. For example, the first data is read data and the second data is write data, or the first data is write data and the second data is read data, etc.
[0072] To prevent system errors, this application checks whether all interrupt responses corresponding to interrupt requests req0 (such as rsp0_0, req0_1, req0_2, and req0_3) have been received after a preset time following the sending of interrupt request req0. If no interrupt response is received within the preset time, an exception is logged. Similarly, after interrupt request req1, the application checks whether all interrupt responses corresponding to interrupt requests req1 (such as rsp1_0, req1_1, req1_2, and req1_3) have been received within a preset time. If no interrupt response is received within the preset time, an exception is logged, and so on. When the number of logged exceptions exceeds or equals a threshold, an error message is promptly sent, and data read / write requests are suspended to ensure normal system operation.
[0073] The aforementioned chip can be, but is not limited to, a processor. It can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), a Graphics Processing Unit (GPU), an Accelerated Processing Unit (ACCU), a Multimedia Application Processor (MAP), a microprocessor, etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. Alternatively, the processor can also be any conventional processor.
[0074] This application also provides an electronic device that includes the aforementioned chip. When the chip is a processor, one possible implementation is as follows: Figure 5 As shown, the electronic device includes: a transceiver, a memory, a communication bus, and a processor.
[0075] The transceiver, memory, and processor are electrically connected directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected through one or more communication buses or signal lines. The transceiver is used to send and receive data. The memory stores computer programs, and the processor executes the software functional modules or computer programs stored in the memory. The aforementioned electronic devices include, but are not limited to, mobile phones, tablets, computers, and servers.
[0076] This application also provides a chip performance optimization method, which can be applied to the I / O module in the chip, that is, the I / O module can execute the method. The following describes the method in conjunction with... Figure 6 The methods provided in the embodiments of this application will be described.
[0077] S1: Each time a data read / write request is sent, the interrupt request corresponding to the current data read / write request is broadcast to all computing modules in the chip.
[0078] During the process of sending multiple data read / write requests, an interrupt request corresponding to the current data read / write request is broadcast to all computing modules in the chip each time a data read / write request is sent.
[0079] S2: Detect whether the received interrupt response is an interrupt response returned by the target computing module.
[0080] Each time an interrupt response is received from a computing module in response to an interrupt request, it is checked whether the received interrupt response is an interrupt response returned by the target computing module. The target computing module is the computing module responsible for handling the interrupt request.
[0081] When detecting whether a received interrupt response is an interrupt response returned by the target computing module, the process may involve detecting the content contained in each received interrupt response. If the content contained in the interrupt response contains a definite status bit, it is determined that an interrupt response returned by the target computing module has been received. Alternatively, if the content contained in the interrupt response contains a negative status bit, it is determined that the current interrupt response is not an interrupt response returned by the target computing module.
[0082] S3: Upon receiving the interrupt response from the interrupt request of the target computing module, and without waiting for all interrupt requests to return interrupt responses, send the next data read / write request.
[0083] In some possible implementations, the above method further includes: after sending the interrupt request, detecting whether all interrupt responses corresponding to the interrupt requests have been received within a preset time; if no interrupt responses corresponding to all interrupt requests are received after the preset time, then an exception is recorded.
[0084] In some possible implementations, the above method further includes: when the number of recorded anomalies is greater than or equal to a threshold, sending an error message and suspending the sending of data read / write requests.
[0085] The solution provided in the method embodiment has the same implementation principle and technical effect as the aforementioned chip embodiment. For the sake of brevity, any parts not mentioned in the method embodiment can be referred to the corresponding content in the aforementioned chip embodiment.
[0086] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0087] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0088] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A chip, characterized in that, include: Multiple computing modules; The IO module is configured to broadcast the interrupt request corresponding to the current data read / write request to all computing modules every time a data read / write request is sent; And, upon receiving an interrupt response from the target computing module in response to the interrupt request, and without waiting for all interrupt requests to return interrupt responses, send the next data read / write request; The target computing module is the computing module responsible for processing the interruption request among the plurality of computing modules.
2. The chip according to claim 1, characterized in that, The I / O module receives the interrupt response returned by each computing module in response to the interrupt request at different times; The IO module is further configured to detect whether the received interrupt response is an interrupt response returned by the target computing module each time it receives an interrupt response from the computing module in response to the interrupt request.
3. The chip according to claim 2, characterized in that, The IO module is configured to detect the content contained in each received interrupt response, and if the content contained in the interrupt response contains a definite status bit, determine that the interrupt response returned by the target computing module has been received; or if the content contained in the interrupt response contains a negative status bit, determine that the current interrupt response is not an interrupt response returned by the target computing module.
4. The chip according to claim 1, characterized in that, The chip also includes a timer configured to start timing when an interrupt request corresponding to the current data read / write request is sent; The IO module is also configured to detect whether all interrupt responses corresponding to interrupt requests are received when the count of the timer is greater than a first threshold. If no interrupt responses corresponding to all interrupt requests are received when the count of the timer is greater than the first threshold, an exception is recorded.
5. The chip according to claim 4, characterized in that, The IO module is also configured to send an error message and suspend sending data read / write requests when the number of recorded exceptions is greater than or equal to a second threshold.
6. The chip according to any one of claims 1-5, characterized in that, The I / O module includes: I / O devices and an interrupt controller; The I / O device is configured to send an interrupt request to the interrupt controller every time a data read / write request is sent; The interrupt controller is configured to broadcast the interrupt request to all computing modules upon receiving the interrupt request; and to send an interrupt response from the target computing module to the I / O device upon receiving an interrupt response from the target computing module in response to the interrupt request, without waiting for all interrupt requests to return interrupt responses. The I / O device is also configured to send the next data read / write request upon receiving an interrupt response from the interrupt controller.
7. An electronic device, characterized in that, include: The chip as described in any one of claims 1-6.
8. A chip performance optimization method, characterized in that, include: Each time a data read / write request is sent, the interrupt request corresponding to the current data read / write request is broadcast to all computing modules in the chip. Each time an interrupt response is received from the computing module in response to the interrupt request, it is checked whether the received interrupt response is an interrupt response returned by the target computing module; wherein, the target computing module is the computing module responsible for processing the interrupt request; Upon receiving an interrupt response from the target computing module's interrupt request, and without waiting for all interrupt requests to return interrupt responses, the next data read / write request is sent.
9. The method according to claim 8, characterized in that, Detecting whether the received interrupt response is an interrupt response returned by the target computing module includes: The content of each received interrupt response is inspected; If the interrupt response contains a definite status bit, it is determined that the interrupt response returned by the target computing module has been received; or, if the interrupt response contains a negative status bit, it is determined that the current interrupt response is not an interrupt response returned by the target computing module.
10. The method according to claim 8, characterized in that, The method further includes: After a preset time following the sending of the interrupt request, it is checked whether interrupt responses corresponding to all interrupt requests have been received; If no interrupt response is received for all interrupt requests within the preset time, an exception will be logged.