A system and method for data implementation simulation using a logic analyzer

Abstract

The application provides a system and method for simulating data using a logic analyzer, comprising the following steps: parsing an export file of the logic analyzer and generating a signal data file and a delay data file; wherein the export file comprises an input signal part, an output signal part and a delay part; the signal data file is generated based on the input signal part and the output signal part, and the delay data file is generated based on the delay part; calling the delay data file and the signal data file, and generating an excitation using the input signal part and the delay part; and performing simulation operation on a unit under test based on the excitation, and obtaining a simulation operation result. The application also provides a simulation system.

Description

Technical Field

[0001] This application relates to the field of integrated circuit verification and testing, and in particular to a system and method for simulation using data from a logic analyzer. Background Technology

[0002] In the field of chip design and verification, with the continuous expansion of integrated circuit scale and the increasing complexity of systems, functional verification has become a crucial step in ensuring successful chip tape-out. In traditional chip verification processes, verification engineers typically need to manually write test stimuli based on the chip's specifications and use simulation tools to model various operating scenarios to verify the functional correctness of the chip design. However, this method has inherent limitations: manually written stimuli often fail to fully reproduce the actual signal timing that the chip might encounter in real-world applications or prototype verification. This is especially true when the chip interacts with external devices, where the actual waveforms at the interface may contain complex timing relationships, glitches, jitter, and other non-ideal characteristics that are easily overlooked in actual testing. In addition, after the chip is delivered, customers may encounter various problems during use, requiring the manufacturer to help locate the cause. In most cases, due to various reasons, customers can only provide the logic analyzer waveform at the time of the problem. If the stimulus is manually programmed, it is impossible to guarantee that the timing of the operation is completely consistent. Moreover, when the waveform is very long, manual implementation is often impractical. This conversion process is not only tedious and time-consuming, but also very easy to introduce human error. Especially when processing multi-channel, long-term continuous waveforms, the efficiency and accuracy of manual processing are difficult to guarantee.

[0003] While some methods have attempted to convert logic analyzer waveforms into simulation stimuli, these methods are primarily geared towards microcontroller system simulation platforms such as Proteus, with the output intended for educational demonstrations or system-level debugging, rather than industry-standard chip verification simulation environments. Furthermore, the stimulus formats they generate (such as Easy HDL scripts and microcontroller hex files) cannot be directly applied to mainstream chip verification toolchains (such as Synopsys VCS, Cadence Xcelium, and Mentor Questa), and they have limitations in handling complex timing synchronization and multi-channel correlation issues.

[0004] Therefore, the current chip verification field still lacks a universal method to automatically convert measured waveforms from logic analyzers (such as those in common txt and csv formats) into simulation stimuli that conform to industry-standard simulation test platforms. Achieving this automated process would significantly shorten the verification cycle, improve the accuracy of stimulus generation, enable chip designs to expose potential problems, and reduce tape-out risks. Simultaneously, it would allow for rapid debugging during prototype verification and delivery, reproducing the actual physical stimuli as accurately as possible in the verification environment.

[0005] This application addresses this technological gap by proposing an automated analysis method to provide a more efficient and realistic means of generating stimulus for chip functional verification, aiming to break down the barrier between measured waveforms and chip verification simulation. Summary of the Invention

[0006] This application proposes a method for simulation using data from a logic analyzer, comprising the following steps: parsing the exported file of the logic analyzer and generating a signal data file and a delay data file; wherein the exported file includes an input signal portion, an output signal portion, and a delay portion; the signal data file is generated based on the input signal portion and the output signal portion, and the delay data file is generated based on the delay portion; calling the delay data file and the signal data file, and generating stimuli using the input signal portion and the delay portion; performing simulation operation using the unit under test based on the stimuli to obtain simulation results.

[0007] In particular, the method for simulation using data from a logic analyzer proposed in this application also includes comparing and analyzing the simulation results of the unit under test with the output signal portion of the corresponding logic analyzer's exported file.

[0008] Specifically, the simulation method proposed in this application uses data from a logic analyzer. The parsing method performs unit normalization conversion on the delay portion in the delay data file during the parsing process based on the time scale parameters of the simulation test platform, so that the delay portion is consistent with the simulation time unit.

[0009] Specifically, the simulation method using data from a logic analyzer proposed in this application, when the logic analyzer exports a file that only records transition time information, includes the following steps for parsing the exported file: extracting the input signal portion and output signal portion of each transition time from the exported file, deleting all delimiters, and writing them into the signal data file; subtracting the time of the previous transition time from the time of the current transition time to obtain the relative delay time, and writing the relative delay time into the delay data file.

[0010] Specifically, the method for simulation using data from a logic analyzer proposed in this application, when the logic analyzer exports a file in the form of information recorded by sampling points, includes the following steps for parsing the exported file: sequentially traversing all sampling points in the exported file, and when a signal transition is detected in the input signal portion or the output signal portion, writing the input signal portion and the output signal portion at the transition moment into the signal data file; subtracting the time of the previous transition moment from the time of the current transition moment to obtain the relative delay time, and writing the relative delay time into the delay data file.

[0011] In particular, the simulation method using data from a logic analyzer proposed in this application, when the unit under test includes multiple input ports and / or output ports, has each line of the signal data file containing all input signal portions and output signal portions binary numbers after removing signal channel separators.

[0012] This application also proposes a simulation system, including a parsing module configured to parse the exported file of a logic analyzer and generate a signal data file and a delay data file. The exported file includes an input signal portion, an output signal portion, and a delay portion. When the exported file only records transition time information, the system extracts the input signal portion and output signal portion for each transition time from the exported file, removes all delimiters, and writes them into the signal data file. The system then subtracts the time of the previous transition time from the time of the current transition time and writes the relative delay time into the delay data file. When the exported file records information according to sampling points, the system sequentially traverses all sampling points in the exported file and detects... When a signal transition occurs in the input signal portion or the output signal portion, the input signal portion and the output signal portion at the transition moment are written into the signal data file. The relative delay time is obtained by subtracting the time of the previous transition moment from the time of the current transition moment, and the relative delay time is written into the delay data file. The simulation test platform includes an excitation module configured to be signal-connected to the parsing module, which calls the signal data file and the delay data file, generates an excitation using the input signal portion and the delay portion, and assigns the generated excitation to the port of the unit under test. The unit under test is configured to be signal-connected to the excitation module, performs simulation operation based on the excitation generated by the excitation module, and obtains the simulation operation results.

[0013] In particular, the simulation system proposed in this application further includes a simulation test platform that compares and analyzes the simulation results of the unit under test with the output signal portion of the exported file of the corresponding logic analyzer.

[0014] Specifically, in the simulation system proposed in this application, when the exported file is in the form of only recording transition time information, the parsing module is configured to extract the input signal portion and output signal portion of each transition time from the exported file, delete all delimiters and write them into the signal data file, and write the relative delay time into the delay data file by subtracting the time of the previous transition time from the time of the current transition time. Wherein, when the unit under test includes multiple input ports and / or output ports, each line of the signal data file contains the binary numbers of all input signal portions and output signal portions after removing signal channel delimiters.

[0015] Specifically, in the simulation system proposed in this application, when the exported file is in the form of recording information according to sampling points, the parsing module is configured to sequentially traverse all sampling points in the exported file. When a signal transition occurs in the input signal part or the output signal part, the input signal part and the output signal part at the transition moment are written into the signal data file. The relative delay time is obtained by subtracting the time of the previous transition moment from the time of the current transition moment, and the relative delay time is written into the delay data file. When the unit under test includes multiple input ports and / or output ports, each line of the signal data file contains the binary numbers of all input signal parts and the binary numbers of all output signal parts after removing the signal channel separator.

[0016] This application automates the conversion of measured waveforms from a logic analyzer into simulation stimuli that conform to an industry-standard simulation test platform, breaking down the barriers between measured waveforms and chip verification simulation. It provides a more efficient and realistic means of generating stimuli for chip functional verification, accurately reproducing the customer's problem scenario, efficiently locating the root cause, significantly shortening the verification cycle, improving the accuracy of stimuli generation, enabling chip design to expose potential problems, and reducing tape-out risks. Attached Figure Description

[0017] Figure 1 This is a system block diagram for implementing simulation using data from a logic analyzer according to an embodiment of this application; Figure 2 This is a flowchart illustrating a method for implementing simulation using data from a logic analyzer according to an embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0019] In the following detailed description, reference can be made to the accompanying drawings, which form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to implement the technical solutions of the present application. It should be understood that other embodiments may also be utilized, or structural, logical, or electrical changes may be made to the embodiments of the present application.

[0020] Techniques, methods, and apparatus known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and apparatus should be considered part of the specification. The lines connecting the units in the accompanying drawings are merely for illustrative purposes, indicating that at least the units at both ends of the line are communicating with each other, and are not intended to prevent unconnected units from communicating. Furthermore, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the number of output terminals, and is not intended to limit communication between the two units to only the signals shown in the figures.

[0021] Prior to this application, reproducing the test phenomena of a logic analyzer in a simulation environment required manual analysis of waveform data and timing, followed by manual construction of simulation stimuli. This method was often impractical when dealing with long-duration test waveforms, forcing researchers to guess the cause and select a portion of the waveforms to construct the simulation. Furthermore, many issues are timing-related, and reproducing the timing of the measured waveforms using manually constructed waveforms required significant time and effort and was prone to errors. For these reasons, the efficiency of debugging and locating problems in the product under test was very low when actual tests did not meet expectations.

[0022] This application establishes a test environment for simulation using waveforms acquired by a logic analyzer. It constructs a three-layer collaborative architecture: a simulation test platform based on a general-purpose hardware description language, a parameterized stimulus module, and an automated parsing mechanism for logic analyzer exported files. This architecture automatically converts the measured waveforms from the logic analyzer into timing stimuli that can be directly loaded into the industrial-grade hardware description language simulation environment. During simulation, these stimuli are assigned to the unit under test (DUT). Compared to the traditional method of manually reproducing logic analyzer waveforms to generate stimuli, this approach more closely approximates the real test environment, enabling rapid and accurate reproduction of measured waveforms in the simulation test platform. It also allows for more efficient and accurate reproduction of stimuli for prototype verification or customer scenarios, thus improving the speed of chip design and iteration.

[0023] Figure 1 This is a system block diagram for implementing simulation using data from a logic analyzer according to one embodiment of this application.

[0024] like Figure 1 As shown, according to one embodiment, a system for generating simulation stimuli using waveforms acquired by a logic analyzer includes a parsing module and a simulation test platform. According to one embodiment, the simulation test platform includes a DUT (Design Under Test) and a stimulus module, wherein the DUT is the correct and error-free original code of the target design.

[0025] According to one embodiment, the parsing module is configured to be signal-connected to the excitation module and receive data files exported from the logic analyzer. The excitation module is configured to be signal-connected to the DUT and call the data file to generate excitations, assigning the excitations to the DUT. The DUT is configured to perform simulation and output simulation results. According to one embodiment, the data file includes a signal data file and a delay data file.

[0026] According to one embodiment, the simulation test platform can be a general-purpose simulation test platform. This makes the verification environment reusable, scalable, automated, and modular; that is, the same verification platform can be easily reused for different test cases with only simple configuration or inheritance, thereby significantly shortening the verification cycle of chip design. According to one embodiment, the simulation test platform can be written in Verilog / VHDL hardware description language.

[0027] Figure 2 This is a flowchart illustrating a method for implementing simulation using data from a logic analyzer according to an embodiment of this application.

[0028] like Figure 2 As shown, the method includes steps S101 to S105.

[0029] Step S101: Parse the file exported by the logic analyzer and generate a data file.

[0030] According to one embodiment, the data file includes a signal data file and a delay data file.

[0031] The logic analyzer's built-in software exports its waveforms to a general format. This general format has two organizational forms: one records only the transition time information, including the transition time and the signal at that time; the other records information according to sampling points, including the time of each sampling point and the signal at that sampling point. Taking a logic analyzer with two test signal channels, input port RX and output port TX, as an example, the exported files for both organizational forms are as follows: (1) Only record the transition time information: Time[s], RX, TX 0.000000000, 0, 1 0.000000012, 0, 0 0.000000020, 0, 1 0.000000028, 0, 0 The logic analyzer's exported file records only the transition times and their corresponding signals. The first line is named "Time[s], RX, TX". Each subsequent line records a transition time and the signals of the input port RX and the output port TX. For example, time 0.000000000 corresponds to input port RX and output port TX signals of 0 and 1; time 0.000000012 corresponds to input port RX and output port TX signals of 0 and 0; time 0.000000020 corresponds to input port RX and output port TX signals of 0 and 1; time 0.000000028 corresponds to input port RX and output port TX signals of 0 and 0. The signal in the above (1) form transitions 4 times.

[0032] (2) Record information according to sampling points (sampling frequency 2ns): Time[s], RX, TX 0.000000000, 0, 1 0.000000002, 0, 1 0.000000004, 0, 1 0.000000006, 0, 1 0.000000008, 0, 1 0.000000010, 0, 1 0.000000012, 1, 1 0.000000014, 1, 1 0.000000016, 1, 1 0.000000018, 1, 1 0.000000020, 1, 0 0.000000022, 1, 0 0.000000024, 1, 0 0.000000026, 1, 0 0.000000028, 1, 1 The logic analyzer exports a file that records the sampling times and their corresponding signals. The first row is named "Time[s], RX, TX", and the sampling frequency is 2ns. For example, the first record shows that the input port RX and output port TX signals at time 0.000000000 are 0 and 1, respectively. The second record shows that the input port RX and output port TX signals at time 0.000000002 are 0 and 1, respectively. This records information from time 0.000000000 to time 0.000000028, with each sampling time differing by 2ns. The signal in the above (2) form changes a total of 4 times, including the initial signal at time 0.000000000, the input port RX signal change at time 0.000000012, and the output port TX signal change at times 0.000000020 and 0.000000028. The initial signal is recorded to indicate the next change.

[0033] When the input port and / or output port have multiple signal channels, write the signals to the export file in the same way.

[0034] According to one embodiment, the logic analyzer can export files in txt or csv format, or other text formats such as tsv or dat.

[0035] Next, the exported file from the logic analyzer needs to be parsed to obtain signal data files recording the input or output signal portions that undergo transitions, as well as delay data files recording the delay portions. According to one embodiment, the delay portion includes a relative delay time obtained by subtracting the time of the previous transition from the time of the current transition in the input or output signal portion.

[0036] According to one embodiment, the parsing method first removes the file header information and redundant delimiters from the file exported by the logic analyzer.

[0037] According to one embodiment, the exported file of the logic analyzer only records the transition time information. The parsing method normalizes the delay part of the exported file of the logic analyzer according to the time unit set by the simulation test platform. The time of the current transition time is subtracted from the time of the previous transition time. The relative delay time of each transition time is converted into the time unit set by the simulation test platform and then written into the delay data file to ensure that the delay time is consistent with the simulation time unit. The binary number of the signal at the transition time after removing the signal channel separator is written into the signal data file. For example, the signal "0,1" of the input port RX and the output port TX is written as "01" in the signal data file.

[0038] According to one embodiment, the exported file of the logic analyzer is in the form of information recorded by sampling points. The parsing method is to sequentially traverse all sampling points in the exported file. When a signal transition is detected in the input signal part or the output signal part, the input signal part and the output signal part at the transition time are written to the signal data file after removing the signal channel separator. The time of the current transition time is subtracted from the time of the previous transition time, and the relative delay time between the two transition points is written to the delay data file according to the time unit set by the simulation test platform.

[0039] According to one embodiment, the number of transition times is written to the first line of the signal data file. According to another embodiment, the signal data file is formatted such that the first line is the total number of transition times, and each subsequent line can be a set of multi-bit binary numbers (excluding signal channel separators), whereby the multi-bit binary numbers may include multiple input signal portions and / or multiple output signal portions. According to another embodiment, each line of the delay data file can be a floating-point relative delay time.

[0040] According to one embodiment, the generated signal data file and delay data file are saved.

[0041] In step S102, the excitation module calls the data file to generate excitation and assigns it to the DUT.

[0042] By compiling the simulation test platform, the excitation module calls the signal data file and delay data file according to the data file directory path and file name information, and generates an excitation that can be directly used for simulation.

[0043] According to one embodiment, the simulation test platform can determine the assertion information of the stimulus during the stimulus application process, record whether the simulation result of the stimulus is correct or incorrect, and record and display the simulation results. According to one embodiment, the simulation test platform can specify the simulation time unit and precision, for example, specifying the simulation time unit as nanoseconds and the precision as picoseconds using the `timescale 1ns / 1ps` instruction. According to one embodiment, the simulation test platform can instantiate the DUT and initialize the internal signals of the DUT. For example, it can define a top-level module as `module tb_top`, create an entity named `DUT_INST` within `module tb_top` to complete the signal connections of each port of the DUT, and initialize the internal signals of the DUT through an `initial` block. According to one embodiment, the simulation test platform can call any stimulus module using the include syntax, where the name of the stimulus module is passed in through compile-time macro parameters or simulation command-line parameters. For example, the `include` syntax in `module tb_top` is used to pass the path of the stimulus module during compilation for calling the stimulus module.

[0044] The example Verilog simulation test platform is as follows: `timescale 1ns / 1ps module tb_top(); /

[0045] Signal variable definition / / / Instantiate DUT DUT DUT_INST( / / Connect DUT signal ); initial begin / / Initialize signal variables include 'Incentive Module Path' / / Record and display simulation results end endmodule Next, the excitation module processes the signal data file and delay data file to generate excitation, and assigns the excitation value to the DUT.

[0046] According to one embodiment, based on the input and output signals of the DUT, a set of two-dimensional signal arrays with the same bit width as the input and output signals are defined to store the input port signals and output port signals. At the same time, a delay two-dimensional array is defined to store the delay time. The depth of the signal two-dimensional array and the delay two-dimensional array are the same and are variables. Their values ​​are consistent with the number of signal transitions of the entire waveform output by the logic analyzer. They can be automatically imported when the excitation module is running. For example, the signal two-dimensional array is defined as dut_port by bit [deep:0] dut_port and the delay two-dimensional array is defined as delay by real delay [deep:0], where the variable deep is the depth of the two arrays.

[0047] According to one embodiment, the DUT may include two ports: an input port and an output port. It can also be expanded to multiple multi-channel, multi-bit-width input and output ports depending on the actual chip interface. When the DUT includes multiple input and / or output ports, each line of the signal data file contains all input and output signal portions after removing signal channel separators.

[0048] According to one embodiment, the excitation module uses file reading functions to read signal data files and delay data files into the signal two-dimensional array and delay two-dimensional array respectively according to the required base. When reading fails, an error message is output and the simulation is stopped. For example, the signal data file is read into the signal two-dimensional array in binary format and the delay data file is read into the delay two-dimensional array in floating-point format through the reading functions $fopen and $fscanf. When reading fails, an error message is output through $display and the simulation is stopped.

[0049] According to one embodiment, the excitation module maps its channel configuration to the input and output ports of the DUT according to the physical connection of the logic analyzer, and assigns the input port signals and output port signals in the two-dimensional signal array to the DUT.

[0050] According to one embodiment, the input port signal in the two-dimensional signal array is the excitation, and the input port signal in the two-dimensional signal array is assigned to the DUT according to the delay time of the two-dimensional delay array.

[0051] In a specific implementation, according to one embodiment, a loop is established. Within the loop, operations are performed based on the depth values ​​of the two-dimensional signal array. The input signal portion of the signal array corresponding to the logic analyzer's exported file is mapped to the DUT input port, and the output signal portion of the signal array corresponding to the logic analyzer's exported file is mapped to the DUT output port. For example, within the foreach loop, the 0th bit of the signal array `dut_port[i][0]` containing the input port signals is assigned to the input port `DUT_RX`, and the 1st bit of the signal array `dut_port[i][1]` containing the output port signals is assigned to the output port variable `Usr_TX`, where `i` ranges from 0 to the depth value minus 1. The first line of the signal data file contains the depth values ​​of the two-dimensional array, which are read by a function and then assigned to the array depth, enabling accurate reproduction of the measured timing sequence in the simulation environment. According to another embodiment, the loop also includes reading the delay two-dimensional array and delaying the corresponding time according to the appropriate syntax in the simulation test platform.

[0052] The example Verilog stimulus is as follows: begin bit [deep:0] dut_port; real delay [deep:0]; integer fp_r; integer fp_flag; / / Read data file fp_r = $fopen({"data_path","data_name"},"r'); if(fp_r == 0)begin $display("ref data read failed!"); $stop? end for(i=0;i<= deep;i++)begin fp_flag = $fscanf(fp_r,"%b", dut_port[i]); end $fclose(fp_r); / / Read delay information file fp_r = $fopen({"delay_path","delay_name"},"r'); if(fp_r == 0)begin $display("ref delay read failed!"); $stop? end for(i=0;i<= deep;i++)begin fp_flag = $fscanf(fp_r,"%f",delay[i]); end $fclose(fp_r); / / Issue incentives in sequence foreach(dut_port[i]) begin DUT_RX = dut_port[i][0]; Usr_TX = dut_port[i][1]; #(delay[i]); end end The excitation module converts the logic analyzer waveforms into excitations that can be directly loaded into the simulation environment and assigns them to the DUT.

[0053] Step S103: Based on the stimulus, perform simulation using the DUT to obtain the simulation results.

[0054] Optionally, in step S104, the simulation results of the DUT are compared with the output signal portion of the corresponding logic analyzer exported file.

[0055] According to one embodiment, in the loop established in step S102, after assigning the received stimulus to the DUT, the method further includes comparing the DUT simulation result from step S103 with the output signal portion. For example, the DUT simulation result is compared with the value of its output port variable Usr_TX. The comparison result can be a custom-generated numerical value or a waveform. According to one embodiment, step S104 can be executed in the stimulus module or the DUT.

[0056] Optionally, in step S105, the reason for the inconsistency can be found based on the comparison results, which can enable the reproduction of the error in the actual test.

[0057] To address the aforementioned issues and requirements, this application generates signal data files and delay data files by parsing the files exported from the logic analyzer. The simulation test platform loads the excitation module during compilation and automatically generates hardware description language excitations based on the signal data files and delay data files. During simulation, the excitations are cyclically assigned to the unit under test, forming a fully automated data flow from the acquisition of measured waveforms to the generation of data files to the extraction of excitation signals, and finally to the simulation test platform simulation, enabling the measured timing sequence to be accurately reproduced in the simulation environment.

[0058] The above embodiments are for illustrative purposes only and are not intended to limit the scope of this application. Those skilled in the art can make various changes and modifications without departing from the scope of this application. Therefore, all equivalent technical solutions should also fall within the scope of this application.

Claims

1. A method for simulation using data from a logic analyzer, characterized in that, Includes the following steps: Parse the exported files from the logic analyzer and generate signal data files and delay data files; The exported file includes an input signal portion, an output signal portion, and a delay portion; the signal data file is generated based on the input signal portion and the output signal portion, and the delay data file is generated based on the delay portion. The delay data file and signal data file are invoked, and the excitation is generated using the input signal portion and the delay portion; Based on the aforementioned stimulus, the unit under test is used to perform a simulation operation, and the simulation results are obtained.

2. The method for implementing simulation according to claim 1, characterized in that, Also includes The simulation results of the unit under test are compared and analyzed with the output signal section of the corresponding logic analyzer's exported file.

3. The method for implementing simulation according to claim 1 or 2, characterized in that, The parsing method performs unit normalization conversion on the delay portion of the delay data file during the parsing process based on the time scale parameters of the simulation test platform, so that the delay portion is consistent with the simulation time unit.

4. The method for implementing simulation according to claim 3, characterized in that, When the logic analyzer exports a file that only records transition time information, the steps for parsing the exported file include: Extract the input signal portion and output signal portion for each transition moment from the exported file, delete all delimiters, and write them into the signal data file; The relative delay time is obtained by subtracting the time of the previous transition from the time of the current transition, and the relative delay time is written into the delay data file.

5. The method for implementing simulation according to claim 3, characterized in that, When the logic analyzer exports a file in the form of sample point recorded information, the steps for parsing the exported file include: The entire sampling point in the exported file is sequentially traversed. When a signal transition is detected in the input signal part or the output signal part, the input signal part and the output signal part at the transition moment are written into the signal data file. The relative delay time is obtained by subtracting the time of the previous transition from the time of the current transition, and the relative delay time is written into the delay data file.

6. The method for implementing simulation according to claim 4 or 5, characterized in that, When the unit under test includes multiple input ports and / or output ports, each line of the signal data file contains the binary numbers of all input signal portions and the binary numbers of all output signal portions after removing the signal channel separator.

7. A simulation system, characterized in that, include: The parsing module is configured to parse the exported file of the logic analyzer and generate a signal data file and a delay data file. The exported file includes an input signal part, an output signal part, and a delay part. When the exported file only records transition time information, the module extracts the input signal part and output signal part of each transition time from the exported file, deletes all delimiters, and writes them into the signal data file. The module also writes the relative delay time into the delay data file by subtracting the time of the previous transition time from the time of the current transition time. When the exported file is in the form of recording information by sampling points, all sampling points in the exported file are sequentially traversed. When a signal transition occurs in the input signal part or the output signal part, the input signal part and the output signal part at the transition time are written into the signal data file. The relative delay time is obtained by subtracting the time of the previous transition time from the time of the current transition time. The relative delay time is written into the delay data file. Simulation testing platform, including, The excitation module is configured to be signal-connected to the parsing module, calls the signal data file and the delay data file, generates excitation using the input signal part and the delay part, and assigns the generated excitation to the unit under test. The unit under test is configured to be connected to the excitation module signal, and performs simulation operation based on the excitation generated by the excitation module to obtain the simulation operation results.

8. The simulation system according to claim 7, characterized in that, The simulation test platform also includes comparing and analyzing the simulation results of the unit under test with the output signal portion of the corresponding logic analyzer's exported file.

9. The simulation system according to claim 7 or 8, characterized in that, When the exported file is in the form of only recording transition time information, the parsing module is configured to extract the input signal part and output signal part of each transition time from the exported file, delete all delimiters and write them into the signal data file, and write the relative delay time into the delay data file by subtracting the time of the previous transition time from the time of the current transition time. When the unit under test includes multiple input ports and / or output ports, each line of the signal data file contains the binary numbers of all input signal parts and output signal parts after removing signal channel delimiters.

10. The simulation system according to claim 7 or 8, characterized in that, When the exported file is in the form of recording information according to sampling points, the parsing module is configured to sequentially traverse all sampling points in the exported file. When a signal transition is detected in the input signal part or the output signal part, the input signal part and the output signal part at the transition time are written into the signal data file. The relative delay time is obtained by subtracting the time of the previous transition time from the time of the current transition time, and the relative delay time is written into the delay data file. When the unit under test includes multiple input ports and / or output ports, each line of the signal data file contains the binary numbers of all input signal parts and the binary numbers of all output signal parts after removing the signal channel separator.

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