A buffer insertion method and system based on a graphics processor and dynamic programming mechanism

Abstract

This invention relates to a buffer insertion method and system based on a parallel dynamic programming mechanism for graphics processing units (GPUs). The method includes: analyzing the integrated circuit routing topology design, constructing a routing Steiner tree, and dividing nodes into several computational levels, wherein the nodes are classified as sinks, connection points, and Steiner points; performing memory layout pre-computation on the GPU based on the set of computational levels, allocating physical memory space for candidate solutions of nodes; generating initial candidate solutions for each sink, using the initial candidate solutions as starting input to update candidate solutions from bottom to top on the GPU, and storing the candidate solution set in the physical memory space, wherein the candidate solutions represent the load capacitance and timing margin of the node; and extracting the optimal buffer insertion scheme by performing parallel backtracking from top to bottom on the GPU based on the candidate solution set of each node. This invention achieves efficient timing convergence in the physical design stage of integrated circuits.

Description

Technical Field

[0001] This invention relates to the fields of electronic design automation and VLSI physical design technology, and in particular to a buffer insertion method and system based on a graphics processor parallel dynamic programming mechanism. Background Technology

[0002] As VLSI (Very Large Scale Integration) process nodes continue to evolve towards advanced nanometer scales (such as 7nm, 5nm and below), the cross-sectional area and spacing of interconnects within the chip continue to shrink, leading to a sharp increase in parasitic resistance and capacitance of the interconnects. In modern advanced process chip design, interconnect delay accounts for a larger proportion of the total chip delay than logic gate delay, becoming a core bottleneck restricting chip operating frequency and overall performance. In the timing optimization stage after physical design and routing of integrated circuits, buffer insertion is the most standard and effective technique for reducing interconnect delay, correcting setup and hold time violations, and resolving signal transition times.

[0003] Currently, the industry widely uses the Van Ginneken (VG) algorithm and its variants, based on dynamic programming, to solve the buffer insertion problem on complex wirelines. This type of traditional algorithm typically constructs the physical topology of the target wireline as a wiring Steiner tree and performs a bottom-up topology traversal from the receiver sink node to the driver root node. During the traversal, the algorithm calculates the timing state at each connection point and Steiner branch point for inserting different types of buffers or not inserting buffers, and maintains a Pareto optimal candidate solution set at each node, consisting of load capacitance and timing margin data pairs.

[0004] With the increasing scale of modern system-on-chip (SoC) designs, the number of nodes in a single critical path or complex multi-fan outgoing network has increased significantly. In the traditional dynamic programming propagation process, the size of the candidate solution set expands exponentially with the increase of topology level. Since the traditional VG algorithm mainly relies on the central processing unit (CPU) for serial execution, it suffers from computational bottlenecks in handling the timing propagation, state calculation, and dominated solution pruning of massive candidate solutions due to limitations in the number of CPU cores and control flow optimization characteristics, thus increasing the development cycle of chip timing convergence.

[0005] In recent years, the industry has begun to explore optimizations using the concurrent computing power of graphics processing units (GPUs). However, existing GPU acceleration solutions have limitations in their underlying hardware architecture mapping and concurrency control mechanisms, preventing the full realization of the GPU's data-level parallelism advantages. Specific technical shortcomings are concentrated in the following three aspects: First, the static fixed memory allocation mechanism leads to resource waste or solution space overflow: In traditional dynamic programming propagation, since the number of candidate solutions generated by each node is unknown before actual computation, existing GPU acceleration solutions typically adopt a strategy of uniformly pre-allocating a fixed-size solution space for each node. This static allocation mechanism has limitations: if the allocated solution space is too large, it will cause the GPU's global memory to be idle and wasted, limiting the scale of the routing network that can be processed; if the allocated solution space is too small, capacity overflow will occur when encountering nodes with expanded solution spaces, causing some Pareto optimal solutions to be discarded, affecting the final buffer insertion quality.

[0006] Second, the branch merging process relies on mutexes, leading to serialization blocking: When merging candidate solutions for Steiner points, existing technologies often employ distributed merging strategies based on data containers (such as bucket sort). To prevent data contention when multiple concurrent threads write to the same shared memory container simultaneously, existing solutions require frequent acquisition of mutexes. This concurrency control mechanism causes thread serialization blocking, weakening the computational efficiency of multi-threaded concurrency.

[0007] Third, insufficient utilization of the underlying hardware features during the candidate solution generation stage leads to memory access latency: In the dynamic programming process of connection point propagation and candidate solution selection, existing GPU solutions typically employ a conventional single-threaded processing mapping mechanism, heavily relying on global memory for intermediate data read and write. This mechanism fails to effectively utilize the GPU's multi-level memory architecture (such as shared memory) and hardware-level thread cooperation instructions (such as thread bundle shuffling instructions for register-level local reduction). When faced with a large sequence of candidate solutions, frequent global memory accesses and a lack of local collaborative computation patterns can lead to limited memory bandwidth, reducing data throughput in high-concurrency environments.

[0008] Therefore, there is a need in this field for a buffer insertion method that can fully utilize the high concurrency computing power of GPUs and optimize the underlying memory layout, lock-free merging mechanism, and fine-grained thread collaborative computing, so as to solve the performance bottleneck of traditional serial algorithms, improve the memory access and concurrency efficiency of existing GPU solutions, and achieve efficient timing convergence of integrated circuit physical design. Summary of the Invention

[0009] The purpose of this invention is to provide a buffer insertion method and system based on the parallel dynamic programming mechanism of a graphics processor, which solves the problems in the prior art such as resource waste or solution space overflow caused by static video memory allocation, serialization blocking caused by the reliance on lock mechanisms in the branch merging process, and memory access delay caused by insufficient utilization of underlying multi-level memory and hardware-level instructions, thereby achieving efficient timing convergence in the physical design stage of integrated circuits.

[0010] To achieve the above objectives, the present invention provides the following solution: A buffer insertion method based on a graphics processor parallel dynamic programming mechanism includes: The integrated circuit routing topology design is analyzed, a routing Steiner tree is constructed, and the nodes are divided into several sets of computational levels, namely sinks, connection points and Steiner points. Based on the set of computational levels, pre-calculation of memory layout is performed on the GPU to allocate physical memory space for candidate solutions of nodes; For each sink node, an initial candidate solution is generated. The initial candidate solution is used as the starting input to update the candidate solution from bottom to top on the GPU. The set of candidate solutions is stored in the physical video memory space. The candidate solution represents the load capacitance and timing margin of the node. Based on the candidate solution set of each node, the optimal buffer insertion scheme is extracted by backtracking in parallel from top to bottom on the GPU.

[0011] Optionally, a wiring Steiner tree can be constructed, and the nodes can be divided into several sets of computational levels, including: The Flute algorithm is used to construct the integrated circuit wiring topology into a wiring Steiner tree; The depth of the node relative to the root node is calculated by breadth-first search. Based on the maximum depth in the Steiner tree and the depth of the node relative to the root node, the computational level of the node is calculated, and nodes with the same level are grouped into the same computational level set.

[0012] Optionally, memory layout pre-computation can be performed on the GPU side, allocating physical memory space for candidate solutions of nodes, including: Controls the number of candidate solutions to be assigned to each node in the current computing hierarchy after dynamic programming propagation in parallel computing on the GPU. The number of candidate solutions to be assigned is scanned in parallel using the GPU's device-level exclusive prefix sum algorithm to generate the global memory offset for each node. Based on the global memory offset, a contiguous physical memory space is allocated to the candidate solutions of the corresponding node, which is used as a high-concurrency read / write buffer.

[0013] Optionally, calculating the number of candidate solutions to be assigned for each node within the current computational hierarchy after dynamic programming propagation includes: For the connection point, the number of candidate solutions to be assigned is equal to the sum of the number of candidate solutions for the unique child node and the number of candidate buffer types; for the Steiner point, the number of candidate solutions to be assigned is equal to the sum of the number of candidate solutions for the left branch child node and the number of candidate solutions for the right branch child node.

[0014] Optionally, updating the candidate solutions from the bottom up on the GPU using the initial candidate solutions as starting input includes: The candidate solution sequence corresponding to the child nodes of the connection point is loaded into the shared memory of the GPU; the concurrent threads of the GPU are used to calculate the net delay propagation solution of the connection point in the state without buffer insertion, and the buffer insertion solution in the state with multiple candidate buffers; the thread bundle reduction operation of the GPU is used to filter out the maximum timing margin solution corresponding to each candidate buffer in parallel; based on the binary search algorithm, the net delay propagation solution and the filtered buffer insertion solution are merged in parallel to generate a unified candidate solution sequence arranged in ascending order of load capacitance, and written into the physical memory space according to the global memory offset; For the Steiner point, the candidate solution sequences corresponding to the left and right branches are loaded into the shared memory of the GPU in the form of data tiles. The local merge boundary of each concurrent thread is determined by calculating the intersection of the merge diagonals. Under the premise of maintaining the weak order relationship between timing margin and load capacitance, solution combinations are screened in parallel. The target timing margin and load capacitance in the solution combination are accumulated to generate the merged candidate solution sequence of the Steiner point. Suboptimal solutions are pruned based on Pareto optimality conditions, and the retained candidate solutions are written into the physical memory space.

[0015] Optionally, the method further includes: performing Pareto optimality condition pruning on the unified candidate solution sequence or the merged candidate solution sequence of the Steiner points to obtain suboptimal solutions.

[0016] Optionally, on the GPU side, a top-down parallel backtracking approach can be used to extract the optimal buffer insertion scheme, including: A target solution index array is established in the physical memory space of the GPU to record the target solution index corresponding to each node; According to the calculation hierarchy set, traversing from top to bottom, if it is determined that the current node is on the backtracking path generated by the target solution and its history contains the buffer insertion identifier, then the extraction state of the current node is activated. The GPU's thread bundle-level aggregation atomic operation is used to collect nodes in the current thread bundle that are in the active extraction state in parallel through hardware-level synchronization instructions; The first thread in the current thread bundle performs a global atomic addition operation to reserve an output memory segment. The active thread in the current thread bundle writes the buffer type and node number in parallel into the output memory segment according to the local ranking index.

[0017] The present invention also provides a buffer insertion system based on a parallel dynamic programming mechanism of a graphics processor, comprising: a memory and a processor; The memory is used to non-volatilely store wiring topology data of integrated circuits, buffer physical property library, and computer program instructions for implementing buffer insertion, such as a graphics processor-based parallel dynamic programming mechanism. The processor includes a multi-core central processing unit and a graphics processing unit, and is communicatively connected to the memory via a high-speed system bus.

[0018] The beneficial effects of this invention are as follows: First, this invention proposes a precise memory layout pre-computation mechanism based on device-level prefix sums, avoiding the resource waste and solution space overflow risks associated with fixed memory allocation. Before kernel computation, this invention accurately determines the number of candidate solutions for all nodes at the current level through memory layout pre-computation and pre-defines the global memory offset for each node using a device-level prefix sum algorithm. This mechanism allows the GPU to allocate contiguous physical memory on demand and compactly, avoiding the global memory waste caused by uniformly allocating large arrays and solving the problem of optimal solution loss due to solution space expansion in complex nodes. This significantly improves the algorithm's processing capacity and timing optimization quality for ultra-large-scale wiring networks.

[0019] Second, a completely lock-free branch merging mechanism based on the merge path algorithm is introduced, avoiding the strong dependence of traditional parallel algorithms on mutex locks. When handling multi-branch merging of Steiner points, this invention abandons the distributed bucket sorting strategy, which is prone to data races, and directly determines the independent working space of each concurrent thread by calculating the intersection point in the two-dimensional merge matrix. This mechanism ensures absolute isolation of massive threads during parallel merging and writing to shared memory, eliminates thread serialization blocking and mutex lock overhead, thereby improving the efficiency of parallel merging.

[0020] Third, the deep integration of GPU multi-level memory architecture and fine-grained thread collaboration instructions significantly improves the utilization of underlying memory access bandwidth and data throughput. This invention delves into the underlying dynamic programming operator: during the connection point propagation phase, a data tile mechanism is employed to maximize the utilization of shared memory, and hardware-level thread bundle shuffling instructions are invoked for register-level local reduction, reducing the frequency of global memory access; during the optimal solution backtracking extraction phase, thread bundle-level aggregated atomic operations are used to reserve memory in batches through a single global atomic addition, avoiding global atomic lock contention and memory congestion bottlenecks. This hardware-software co-design achieves extremely high computational performance and shortens the timing convergence cycle of ultra-large-scale chip physical designs. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram illustrating the overall implementation process of a buffer insertion method based on GPU parallel dynamic programming according to an embodiment of the present invention. Figure 2 This is a schematic diagram illustrating the specific implementation process of the memory layout pre-calculation step in an embodiment of the present invention; Figure 3 This is a schematic diagram illustrating the specific implementation process of the candidate solution generation and update steps for connecting points in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the specific implementation process of the parallel backtracking step based on GPU thread bundle aggregation atomic operation in an embodiment of the present invention; Figure 5 This is a hardware structure block diagram of a buffer insertion system based on GPU parallel dynamic programming according to an embodiment of the present invention. Detailed Implementation

[0023] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0024] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0025] In this invention, the buffer insertion refers to: in a given wiring topology With buffer physical property library Under constraints, to reduce interconnect latency or repair timing violations, a bottom-up dynamic programming algorithm is used at each node. Iterative maintenance of candidate solution set The process involves determining the optimal buffer insertion position at the root node. Each candidate solution is represented as a binary tuple. ,in This is the load capacitance of the node. This represents the timing margin for that node. The Pareto optimal selection mechanism is defined as follows: for any two solutions in the set... and If satisfied and Then it is called Dominate , need to Elimination. This filtering mechanism eliminates suboptimal states that are dominated, thereby enabling the extraction of the target solution with the largest time margin at the root node based on time constraints.

[0026] like Figure 1As shown, this embodiment proposes a buffer insertion method based on the parallel dynamic programming mechanism of a graphics processing unit (GPU), applied to a computing device containing a central processing unit (CPU) and a graphics processing unit (GPU), including: S1. Initialize integrated circuit routing topology design conditions and divide computational levels: Analyze the integrated circuit routing topology design, construct a routing Steiner tree, and divide the nodes into several sets of computational levels, wherein the nodes are divided into sinks, connection points, and Steiner points; S2. Based on the set of computational levels, perform pre-calculation of the video memory layout on the GPU side to allocate physical video memory space for the candidate solutions of the nodes; S3. Generate an initial candidate solution for each sink node, use the initial candidate solution as the starting input to update the candidate solution from bottom to top on the GPU, and store the candidate solution set in the physical video memory space, wherein the candidate solution represents the load capacitance and timing margin of the node; S4. Based on the candidate solution set of each node, backtrack in parallel from top to bottom on the GPU to extract the optimal buffer insertion scheme.

[0027] Furthermore, a wiring Steiner tree is constructed, and the nodes are divided into several sets of computational levels, including: The Flute algorithm is used to construct the integrated circuit wiring topology into a wiring Steiner tree; The depth of the node relative to the root node is calculated by breadth-first search. Based on the maximum depth in the Steiner tree and the depth of the node relative to the root node, the computational level of the node is calculated, and nodes with the same level are grouped into the same computational level set.

[0028] Specifically, initializing the integrated circuit routing topology design conditions and dividing the computational hierarchy includes: Step S101. Parse the routing netlist output by the integrated circuit physical design tool, and use the Flute algorithm to construct the routing topology into a routing Steiner tree. Traverse the tree structure and classify the nodes into sinks (i.e., signal receivers), Steiner points (i.e., physical intersections of multiple routing branches), and wire nodes (i.e., internal nodes derived after discretizing and cutting long nets, used to characterize segmented parasitic parameters and serve as candidate insertion positions for buffers).

[0029] Step S102. Based on the signal flow direction and topological dependencies between nodes, and to adapt to the bottom-up dynamic programming propagation logic, a topology-flipping-based hierarchical partitioning strategy is adopted. First, breadth-first search (BFS) is used to calculate the depth of all nodes relative to the root node. .make Given the maximum depth of this Steiner tree, the computational level of each node is defined as the maximum topological distance from that node to the sink: .

[0030] Step S103. Represent those with the same level Nodes are grouped into the same computational level set. Due to the bottom-up nature of dynamic programming, when calculating the hierarchy... At that time, all its child nodes belong to The hierarchy has been calculated and stored in GPU memory. This partitioning method ensures that all nodes within the same hierarchy are topologically independent, thus enabling the GPU to start high-concurrency thread processing for a massive number of nodes within the same hierarchy when executing subsequent kernel functions, eliminating data contention and maximizing hardware throughput.

[0031] Furthermore, on the GPU side, memory layout pre-calculation is performed to allocate physical memory space for candidate solutions of nodes, including: Controls the number of candidate solutions to be assigned to each node in the current computing hierarchy after dynamic programming propagation in parallel computing on the GPU. The number of candidate solutions to be assigned is scanned in parallel using the GPU's device-level exclusive prefix sum algorithm to generate the global memory offset for each node. Based on the global memory offset, a contiguous physical memory space is allocated to the candidate solutions of the corresponding node, which is used as a high-concurrency read / write buffer.

[0032] Specifically, such as Figure 2 As shown, the memory layout pre-calculation on the GPU side includes: To eliminate the significant performance loss and memory fragmentation caused by dynamic memory allocation during GPU kernel function execution, this embodiment employs a static pre-allocation mechanism: Step S201. Control the GPU to perform parallel computation on the number of candidate solutions to be assigned to each node within the current computation level after dynamic programming propagation: For a connected node, the number of candidate solutions to be assigned is equal to the sum of the number of candidate solutions of its unique child node and the number of candidate buffer types, i.e. ,in This represents the number of types of the optional buffer physical library; for a Steiner point, the number of candidate solutions to be assigned is equal to the sum of the number of candidate solutions in its left branch child nodes and the number of candidate solutions in its right branch child nodes, i.e. .

[0033] Step S202. Use the GPU's device-level exclusive prefix sum algorithm to process the array. Perform parallel scanning to generate a global memory offset array. The formula for calculating its offset is: ,in .

[0034] Step S203. Based on Arrays provide address indices, allowing for the allocation of contiguous physical space in the GPU's global memory in a single transaction. This space serves as a dedicated read / write buffer for dynamic programming calculations, ensuring the continuity and efficiency of memory access operations.

[0035] Furthermore, updating the candidate solutions from the bottom up on the GPU using the initial candidate solutions as starting input includes: The candidate solution sequence corresponding to the child nodes of the connection point is loaded into the shared memory of the GPU; the concurrent threads of the GPU are used to calculate the net delay propagation solution of the connection point in the state without buffer insertion, and the buffer insertion solution in the state with multiple candidate buffers; the thread bundle reduction operation of the GPU is used to filter out the maximum timing margin solution corresponding to each candidate buffer in parallel; based on the binary search algorithm, the net delay propagation solution and the filtered buffer insertion solution are merged in parallel to generate a unified candidate solution sequence arranged in ascending order of load capacitance, and written into the physical memory space according to the global memory offset; For the Steiner point, the candidate solution sequences corresponding to the left and right branches are loaded into the shared memory of the GPU in the form of data tiles. The local merge boundary of each concurrent thread is determined by calculating the intersection of the merge diagonals. Under the premise of maintaining the strict weak order relationship between timing margin and load capacitance, solution combinations are screened in parallel. The target timing margin and load capacitance in the solution combination are accumulated to generate the merged candidate solution sequence of the Steiner point. Suboptimal solutions are pruned based on Pareto optimality conditions, and the retained candidate solutions are written into the physical memory space.

[0036] Furthermore, the method also includes: performing Pareto optimality condition pruning on the unified candidate solution sequence or the merged candidate solution sequence of the Steiner points to obtain suboptimal solutions.

[0037] The suboptimal solutions based on Pareto optimality conditions include: Using the GPU’s block-level exclusive prefix scan, the historical maximum time margin before the current candidate solution is calculated in parallel. The time margin of the current candidate solution is compared with the historical maximum time margin in parallel. Candidate solutions whose time margin of the current candidate solution is greater than the historical maximum time margin are retained, and the remaining candidate solutions are marked as dominated solutions and eliminated.

[0038] Specifically, the candidate solution set is generated and updated in parallel on the GPU. The specific implementation steps are as follows: Before generating and updating candidate solutions for connection points and Steiner points, a candidate solution set is first initialized for each sink point. For each sink point, an initial candidate solution is generated based on its load capacitance and receiver timing constraints. The initial candidate solution represents the load capacitance and timing margin of the sink point without buffer insertion and serves as the starting input for subsequent bottom-up dynamic programming propagation.

[0039] Following a bottom-up order of the various computational levels, computational kernel functions customized for different node types are called in parallel on the GPU side to iteratively calculate the load capacitance and timing margin of each node: Step S301. For the connection points (e.g.) Figure 3 (as shown) 1. Divide the candidate solution sequence corresponding to the child nodes of the connection point into data tiles and load them into the low-latency shared memory of the GPU.

[0040] 2. Utilize GPU concurrent threads to compute the net delay propagation solution in parallel based on the Elmore delay model, without inserting a buffer. For any candidate solution for a child node, calculate the load capacitance after propagation to the current connection point. With timing margin The calculation formula is as follows: ; .in, and These represent the load capacitance and timing margin of the candidate solutions for the child nodes, respectively. and These are the parasitic resistance and parasitic capacitance of the current connection point, respectively.

[0041] 3. Parallel computation of buffer insertion solutions under various physical library candidate buffer states. Insertion of a specific buffer. Timing margin after The calculation formula is: .in, buffer The intrinsic delay, buffer The driving resistor. To quickly select the optimal insertion solution for each buffer, this invention utilizes the GPU's underlying thread bundle reduction instructions (such as the __shfl_down_sync instruction) to parallelly select the maximum timing margin solution for each candidate buffer within the current thread bundle at the register level with logarithmic time complexity.

[0042] 4. Based on the binary search algorithm, determine the insertion position of the buffered solution in the unbuffered solution sequence, and merge the wire delay propagation solution and the selected buffered insertion solution in parallel to generate a unified candidate solution sequence arranged in ascending order of load capacitance, and write it into the global memory of the GPU according to the global memory offset.

[0043] Step S302. For the Steiner point, the merge path algorithm is used to merge the candidate solution sequences corresponding to the left and right branches of the Steiner point in parallel: 1. Load the candidate solution sequences corresponding to the left and right branches into the shared memory of the GPU in the form of data tiles. Let the length of the left branch sequence be... The length of the right branch sequence is Each concurrent thread solves the diagonal The mathematical model of the intersection points with the merge paths determines their respective local merge boundaries without locking. and This ensures that the total number of elements processed by each execution thread of the GPU is consistent, thus achieving load balancing.

[0044] 2. While maintaining the timing margin and ensuring the load capacitance satisfies a strict weak-order relationship, parallel screening of Pareto optimal solution combinations is conducted. For candidate solutions in the left branch... With right branch candidate solutions The load capacitance of the merged node Timing margin That is, the timing margin corresponding to the solution combination is taken as the smaller value and the load capacitance is accumulated to generate the merged candidate solution sequence of the Steiner point, and written into the global memory of the GPU in the same order as the ordered merge.

[0045] Step S303. To suppress the exponential expansion of the solution space, the candidate solution sequence after S301 or S302 is pruned using Pareto optimal conditions using GPU block-level prefix scanning. Assume that the solution is pruned according to capacitance. The candidate sequences arranged in ascending order are : 1. Utilize the GPU's block-level exclusive prefix scan to compute the maximum time margin before the current candidate solution in parallel. .

[0046] 2. Combine the time margin of the current candidate solution with... Compare, if the current solution Then mark (Reserved); otherwise, a better solution dominates the current solution, marked as... (Removed).

[0047] 3. Calculate the target storage offset for retaining candidate solutions using the block-level summation scan of the GPU. The reserved candidate solutions are compactly rearranged into the contiguous physical memory space to suppress the exponential expansion of the solution space.

[0048] Furthermore, on the GPU side, a top-down parallel backtracking process is used to extract the optimal buffer insertion scheme, including: A target solution index array is established in the physical memory space of the GPU to record the target solution index corresponding to each node; According to the calculation hierarchy set, traversing from top to bottom, if it is determined that the current node is on the backtracking path generated by the target solution and its history contains the buffer insertion identifier, then the extraction state of the current node is activated. The GPU's thread bundle-level aggregation atomic operation is used to collect nodes in the current thread bundle that are in the active extraction state in parallel through hardware-level synchronization instructions; The first thread in the current thread bundle performs a global atomic addition operation to reserve an output memory segment. The active thread in the current thread bundle writes the buffer type and node number in parallel into the output memory segment according to the local ranking index.

[0049] Specifically, based on the candidate solution set of each node, the optimal buffer insertion scheme is extracted. The specific implementation steps are as follows (e.g.) Figure 4 (as shown) Step S401. Evaluate all candidate solutions at the root node of the wired Steiner tree, and select the solution that satisfies the Pareto optimality front from the set of candidate solutions. optimal solution Furthermore, a target solution index array is established in the global video memory of the GPU to record the target solution index corresponding to each node.

[0050] Step S402. Traverse from top to bottom according to the computational hierarchy. If it is determined that the current node is on the backtracking path generated by the target solution and its historical record contains a buffer insertion identifier, then activate the extraction state of the current node. .

[0051] Step S403. Perform conflict-free write using the GPU's thread-beam-level aggregated atomic operations: via hardware-level synchronization instructions. Collects nodes in the active extraction state within the current thread bundle in parallel. This instruction returns a 32-bit (or 64-bit, depending on the hardware architecture) unsigned integer mask. Each bit in the mask corresponds to a thread within the thread bundle. If that thread is in the active extraction state (i.e., ...), ... If the bit is true, then the bit is set to 1; otherwise, it is set to 0.

[0052] Step S404. Generate a low-order mask using the current thread's local ID (Lane ID). (That is, all bits before this number are 1), using instructions The number of 1s in the result is counted to determine the local write position of the current thread within its thread bundle. Subsequently, the first thread within the thread bundle performs a single global atomic addition. This reserves output space for all activated nodes within the thread bundle at once. The activated thread then calculates... Writing the buffer type and node number in parallel to the output memory segment eliminates atomic lock contention and memory congestion during large-scale concurrent backtracking.

[0053] This embodiment also provides a buffer insertion system based on a parallel dynamic programming mechanism of a graphics processor, including: a memory and a processor; The memory is used to non-volatilely store the wiring topology data of the integrated circuit, the buffer physical characteristic library, and the computer program instructions for implementing the buffer insertion method based on the parallel dynamic programming mechanism of the graphics processor. The processor includes a multi-core central processing unit and a graphics processing unit, and is communicatively connected to the memory via a high-speed system bus.

[0054] Specific examples Figure 5 As shown, the memory is used to non-volatilely store the wiring topology data of the integrated circuit, the buffer physical characteristic library, and the computer program instructions for implementing the above method. The processor unit includes a multi-core central processing unit (CPU) and a graphics processing unit (GPU), which are communicatively connected to the memory via a high-speed system bus. When the processor unit collaboratively executes the computer program instructions, the CPU is responsible for topology resolution and system scheduling, while the GPU is responsible for high-concurrency memory pre-allocation, dynamic programming propagation, suboptimal solution pruning, and parallel backtracking calculation, thereby jointly implementing the GPU-based parallel dynamic programming-based buffer insertion method in the above embodiments.

[0055] The embodiments described above are merely preferred embodiments of the present invention and are not intended to limit the scope of the present invention. Various modifications and improvements made to the technical solutions of the present invention by those skilled in the art without departing from the spirit of the present invention should fall within the protection scope defined by the claims of the present invention.

Claims

1. A buffer insertion method based on a parallel dynamic programming mechanism of a graphics processor, characterized in that, include: The integrated circuit routing topology design is analyzed, a routing Steiner tree is constructed, and the nodes are divided into several sets of computational levels, namely sinks, connection points and Steiner points. Based on the set of computational levels, pre-calculation of memory layout is performed on the GPU to allocate physical memory space for candidate solutions of nodes; For each sink node, an initial candidate solution is generated. The initial candidate solution is used as the starting input to update the candidate solution from bottom to top on the GPU. The set of candidate solutions is stored in the physical video memory space. The candidate solution represents the load capacitance and timing margin of the node. Based on the candidate solution set of each node, the optimal buffer insertion scheme is extracted by backtracking in parallel from top to bottom on the GPU.

2. The buffer insertion method based on the parallel dynamic programming mechanism of a graphics processor according to claim 1, characterized in that, Constructing a wiring Steiner tree and dividing the nodes into several sets of computational levels includes: The Flute algorithm is used to construct the integrated circuit wiring topology into a wiring Steiner tree; The depth of the node relative to the root node is calculated by breadth-first search. Based on the maximum depth in the Steiner tree and the depth of the node relative to the root node, the computational level of the node is calculated, and nodes with the same level are grouped into the same computational level set.

3. The buffer insertion method based on the parallel dynamic programming mechanism of a graphics processor according to claim 1, characterized in that, On the GPU side, memory layout pre-calculation is performed, and physical memory space is allocated for candidate solutions of nodes, including: Controls the number of candidate solutions to be assigned to each node in the current computing hierarchy after dynamic programming propagation in parallel computing on the GPU. The number of candidate solutions to be assigned is scanned in parallel using the GPU's device-level exclusive prefix sum algorithm to generate the global memory offset for each node. Based on the global memory offset, a contiguous physical memory space is allocated to the candidate solutions of the corresponding node, which is used as a high-concurrency read / write buffer.

4. The buffer insertion method based on the parallel dynamic programming mechanism of a graphics processor according to claim 3, characterized in that, Calculating the number of candidate solutions to be assigned for each node in the current computational hierarchy after dynamic programming propagation includes: For the connection point, the number of candidate solutions to be assigned is equal to the sum of the number of candidate solutions for the unique child node and the number of candidate buffer types; for the Steiner point, the number of candidate solutions to be assigned is equal to the sum of the number of candidate solutions for the left branch child node and the number of candidate solutions for the right branch child node.

5. The buffer insertion method based on the parallel dynamic programming mechanism of a graphics processor according to claim 4, characterized in that, Using the initial candidate solution as the starting input, updating the candidate solution on the GPU from bottom to top includes: The candidate solution sequence corresponding to the child nodes of the connection point is loaded into the shared memory of the GPU; the concurrent threads of the GPU are used to calculate the net delay propagation solution of the connection point in the state without buffer insertion, and the buffer insertion solution in the state with multiple candidate buffers; the thread bundle reduction operation of the GPU is used to filter out the maximum timing margin solution corresponding to each candidate buffer in parallel; based on the binary search algorithm, the net delay propagation solution and the filtered buffer insertion solution are merged in parallel to generate a unified candidate solution sequence arranged in ascending order of load capacitance, and written into the physical memory space according to the global memory offset; For the Steiner point, the candidate solution sequences corresponding to the left and right branches are loaded into the shared memory of the GPU in the form of data tiles. The local merge boundary of each concurrent thread is determined by calculating the intersection of the merge diagonals. Under the premise of maintaining the weak order relationship between timing margin and load capacitance, solution combinations are screened in parallel. The target timing margin and load capacitance in the solution combination are accumulated to generate the merged candidate solution sequence of the Steiner point, which is then written into the physical memory space.

6. The buffer insertion method based on the parallel dynamic programming mechanism of a graphics processor according to claim 5, characterized in that, The method further includes: performing Pareto optimality condition pruning on the unified candidate solution sequence or the merged candidate solution sequence of the Steiner point to obtain suboptimal solutions.

7. The buffer insertion method based on the parallel dynamic programming mechanism of a graphics processor according to claim 1, characterized in that, On the GPU side, a top-down parallel backtracking approach is used to extract the optimal buffer insertion scheme, including: A target solution index array is established in the physical memory space of the GPU to record the target solution index corresponding to each node; According to the calculation hierarchy set, traversing from top to bottom, if it is determined that the current node is on the backtracking path generated by the target solution and its history contains the buffer insertion identifier, then the extraction state of the current node is activated. The GPU's thread bundle-level aggregation atomic operation is used to collect nodes in the current thread bundle that are in the active extraction state in parallel through hardware-level synchronization instructions; The first thread in the current thread bundle performs a global atomic addition operation to reserve an output memory segment. The active thread in the current thread bundle writes the buffer type and node number in parallel into the output memory segment according to the local ranking index.

8. A buffer insertion system based on a parallel dynamic programming mechanism of a graphics processor, characterized in that, include: Memory and processor; The memory is used to non-volatilely store wiring topology data of the integrated circuit, a buffer physical characteristic library, and computer program instructions for implementing the method as described in any one of claims 1-7. The processor includes a multi-core central processing unit and a graphics processing unit, and is communicatively connected to the memory via a high-speed system bus.

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