Display device

Abstract

A display device is disclosed. The display device includes a timing controller, a gate driver, a source driver, and a pixel array. The pixel array has a plurality of pixel groups. The timing controller provides a plurality of pixel data and pixel event data based on image data. The gate driver provides a plurality of gate signals that are enabled row by row. The source driver provides a plurality of pixel voltages based on the pixel data and a plurality of group control signals based on the pixel event data. The pixels of each pixel group collectively receive one of the group control signals, and each of the pixels receives a corresponding one of the pixel voltages based on the received gate signal and the received group control signal.

Description

Technical Field

[0001] This invention relates to a display device, and more particularly to a display device with a partial screen update function. Background Technology

[0002] Variable Refresh Rate (VRR) display technology effectively eliminates screen tearing, stuttering, and lag in games by synchronizing the screen refresh rate with the frame rate output by the graphics card / game console, achieving smooth dynamic images. However, VRR technology adjusts the refresh rate on a frame-by-frame basis, limiting its power-saving effects and the times when it can be used. Therefore, how to make VRR technology more effective is a key issue in reducing monitor power consumption. Summary of the Invention

[0003] The present invention provides a display device that can divide a display panel into multiple groups (or areas), and each group can independently set the screen refresh rate.

[0004] The display device of the present invention includes a timing controller, a gate driver, a source driver, and a pixel array. The pixel array has a plurality of pixels and is divided into a plurality of pixel groups. The timing controller receives image data to provide a plurality of pixel data and pixel motion data based on the image data. The gate driver is coupled to the pixels to provide a plurality of gate signals to the pixels for row-by-row enable. The source driver is coupled to the pixels to provide a plurality of pixel voltages to the pixels based on the pixel data and to provide a plurality of group control signals based on the pixel motion data. Pixels in each pixel group jointly receive one of the group control signals, and each pixel receives a corresponding pixel voltage based on the received gate signal and the received group control signal.

[0005] Based on the above, the display device of this embodiment divides pixels into multiple pixel groups, and each pixel group is controlled by its own independent group control signal in addition to the gate signal. Therefore, under the control of the group control signal, each pixel group can independently determine the pixel update frequency, so as to achieve the independence of the variable update rate of each pixel group.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a system schematic diagram of a display device according to an embodiment of the present invention.

[0008] Figure 2 This is a schematic diagram of the driving waveform of a display device according to an embodiment of the present invention.

[0009] Figure 3A This is a circuit diagram of a pixel in a display device according to an embodiment of the present invention.

[0010] Figure 3B This is a circuit diagram of a pixel of a display device according to another embodiment of the present invention.

[0011] Figure 4 This is a system schematic diagram of a display device according to another embodiment of the present invention.

[0012] Figure 5 This is a circuit diagram of a multiplexer circuit and a pixel array according to an embodiment of the present invention.

[0013] Figure 6 This is a schematic diagram of the driving waveform of a display device according to another embodiment of the present invention.

[0014] In the attached figures, the following labels are used:

[0015] 100, 200: Display devices

[0016] 110: Timing Controller

[0017] 120: Gate driver

[0018] 130: Source Driver

[0019] 140: pixel array

[0020] 210: Multiplexer Circuit

[0021] C1: Capacitor

[0022] Clc: Liquid crystal capacitor

[0023] CORpixel: Pixel Anomaly Data

[0024] Cst: Storage capacitor

[0025] DATAimg: Image data

[0026] DATApixel: pixel data

[0027] Fcur: Current screen

[0028] Fpre: Previous screen

[0029] GDCS: Gate Control Signal

[0030] GT1~GT3, GT: Gate signal

[0031] LD1: Light Emitting Diode

[0032] Lgt1~Lgt3: Gate lines

[0033] Lpt1, Lpt2: Group control lines

[0034] Lsrc1~Lsrc4: Source lines

[0035] M1~M5, Mx1~Mx6: Transistors

[0036] MUXA, MUXB: Multiplexing control signals

[0037] PRE1, PRE2: Pixel groups

[0038] PTr1, PTr2, PT: Group control signals

[0039] PX: pixel

[0040] PXa: Liquid crystal pixel

[0041] PXb: Light-emitting diode pixel

[0042] Vcom: Common Voltage

[0043] Vdd: System high voltage

[0044] Vpixel1~Vpixel4, Vpixel: pixel voltage

[0045] Vss: System low voltage Detailed Implementation

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology and this invention, and will not be interpreted as having idealized or overly formal meanings unless expressly defined herein.

[0047] It should be understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, "first element," "component," "region," "layer," or "part" discussed below may be referred to as a second element, component, region, layer, or part without departing from the teachings of this document.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not restrictive. As used herein, unless the content clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms, including “at least one.” “Or” signifies “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It should also be understood that, when used in this specification, the terms “comprising” and / or “comprising” specify the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or combinations thereof.

[0049] Figure 1 This is a system schematic diagram of a display device according to an embodiment of the present invention. Please refer to... Figure 1 In this embodiment, the display device 100 includes a timing controller 110, a gate driver 120, a source driver 130, and a pixel array 140. The timing controller 110 receives image data DATAimg, provides multiple pixel data DATApixel and pixel anomaly data CORpixel based on the image data DATAimg, and provides a gate control signal GDCS based on timing.

[0050] Gate driver 120 is coupled to timing controller 110 to receive gate control signal GDCS and is also coupled to pixel array 140 to provide multiple gate signals (such as GT1~GT3) for row-by-row enable to pixel array 140 based on gate control signal GDCS. Source driver 130 is coupled to timing controller 110 to receive multiple pixel data DATApixel and pixel change data CORpixel corresponding to pixel PX of pixel array 140 and is also coupled to pixel array 140 to provide multiple pixel voltages (such as Vpixel1~Vpixel4) to pixel array 140 based on pixel data DATApixel and to provide multiple group control signals (such as PTr1, PTr2) based on pixel change data CORpixel.

[0051] The pixel array 140 has multiple pixels PX, multiple gate lines (such as Lgt1~Lgt3), multiple source lines (such as Lsrc1~Lsrc4), and multiple group control lines (such as Lpt1, Lpt2), and the pixels PX are divided into multiple pixel groups (such as PRE1, PRE2). Pixels PX in the same row are coupled to the same gate line (such as Lgt1~Lgt3) to receive the same gate signal (such as GT1~GT3) via the same gate line. Pixels PX in the same column are coupled to the same source line (such as Lsrc1~Lsrc4) to receive the same pixel voltage (such as Vpixel1~Vpixel4) via the same source line. Pixels PX in each pixel group (such as PRE1, PRE2) are coupled to the same group control line (Lpt1, Lpt2) to receive the same group control signal (PTr1, PTr2). Furthermore, each pixel PX receives one of the pixel voltages (such as Vpixel1 to Vpixel4) based on the received gate signal (such as GT1 to GT3) and the received group control signal (such as PTr1 and PTr2).

[0052] Based on the above, according to the division of pixel groups, each pixel group is controlled not only by the gate signal but also by its own independent group control signal. Therefore, under the control of the group control signal, each pixel group can independently determine the pixel update frequency, thereby achieving the independence of the variable update rate of each pixel group.

[0053] In this embodiment of the invention, the pixel change data CORpixel can represent at least one location among all pixels PX where the display grayscale needs to be changed; that is, the pixel change data CORpixel can represent that the display grayscale of the marked pixel PX needs to be changed. The pixel change data CORpixel can be a table representing whether the display grayscale of each pixel PX needs to be changed, or it can only record the location of the pixel PX whose display grayscale needs to be changed. This depends on the circuit design, and this embodiment of the invention is not limited thereto.

[0054] In dynamic images, the pixel change data CORpixel indicates that the grayscale of all pixels PX needs to be changed, meaning that the position of all pixels PX needs to be adjusted to change the grayscale. In static images (i.e., displaying pictures), the pixel change data CORpixel indicates that the grayscale of all pixels PX does not need to be changed, meaning that the position of no pixel PX needs to be adjusted to change the grayscale.

[0055] In this embodiment of the invention, the timing controller 110 can provide pixel change data CORpixel based on a comparison of the display grayscale (or pixel data DATApixe) of the same pixel PX in the current frame Fcur and the previous frame Fpre. Furthermore, when the display grayscale of one of the pixels PX in the current frame Fcur differs from the display grayscale of the same pixel PX in the previous frame Fpre, the pixel change data CORpixel can indicate that the display grayscale of the compared pixel PX needs to be changed.

[0056] In this embodiment of the invention, when the pixel change data CORpixel indicates that the display grayscale of one of the pixels PX in each pixel group (such as PRE1, PRE2) needs to be changed, the group control signals (such as PTr1, PTr2) corresponding to each pixel group (such as PRE1, PRE2) are enabled; when the pixel change data CORpixel indicates that the display grayscale of multiple pixels PX in each pixel group (such as PRE1, PRE2) does not need to be changed, the group control signals (such as PTr1, PTr2) corresponding to each pixel group (such as PRE1, PRE2) are disabled. For example, if the display grayscale of any pixel PX in pixel group PRE1 needs to be changed, the group control signal PTr1 will be enabled; conversely, if the display grayscale of no pixel PX in pixel group PRE1 needs to be changed, the group control signal PTr1 will remain disabled.

[0057] In this embodiment of the invention, when the group control signals (such as PTr1, PTr2) corresponding to each pixel group (such as PRE1, PRE2) are disabled, the pixel voltages (such as Vpixel1~Vpixel4) received by the pixels PX of each pixel group (such as PRE1, PRE2) remain at a previous voltage level (that is, the voltage level does not change). This reduces the power consumption of the source driver 130.

[0058] In this embodiment of the invention, pixel groups (such as PRE1, PRE2) are distinguished by columns. For example, N columns are divided into one pixel group, but this embodiment is not limited to this, and N can be a positive integer greater than or equal to 1. For example, an array of I x J can be divided into one pixel group, where I and J can be positive integers greater than or equal to 1. Furthermore, if there are no circuit design issues, one pixel PX can be controlled as a pixel group (such as PRE1, PRE2), depending on the circuit design, and this embodiment is not limited to this.

[0059] In this embodiment of the invention, each of these pixels PX is disabled based on at least one of the received gate signals (such as GT1~GT3) and the received group control signals (such as PTr1, PTr2), and does not receive a corresponding pixel voltage (such as Vpixel1~Vpixel4). Furthermore, each of the pixels PX is enabled based on all of the received gate signals (such as GT1~GT3) and the received group control signals (such as PTr1, PTr2), and receives a corresponding pixel voltage (such as Vpixel1~Vpixel4).

[0060] In this embodiment of the invention, the pixel PX can be either a liquid crystal pixel or a light-emitting diode pixel, depending on the circuit design, and this embodiment of the invention is not limited thereto.

[0061] Figure 2 This is a schematic diagram of the driving waveform of a display device according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 In this embodiment, it is assumed that the group control signal PTr1 is enabled (e.g., at a high voltage level) and the group control signal PTr2 is disabled (e.g., at a low voltage level). During the enable period of the gate signal GT1 (e.g., during the high voltage level period), the pixel voltages Vpixel1 and Vpixel2 can vary their voltage levels (e.g., from low voltage level to high voltage level) to update the display grayscale of the pixel PX in the pixel group PRE1. Conversely, during the enable period of the gate signal GT1, the voltage levels of the pixel voltages Vpixel3 and Vpixel4 can remain unchanged (e.g., remain at a high voltage level) to keep the display grayscale of the pixel PX in the pixel group PRE1 constant.

[0062] The pixel voltages Vpixel1 to Vpixel4 are high voltage levels / low voltage levels used to indicate whether the voltage level changes, rather than representing the actual write voltage. In other words, the pixel voltages Vpixel1 to Vpixel4 can be changed from one analog voltage to another or maintained at this analog voltage, depending on the circuit design. This embodiment of the present invention is not limited thereto.

[0063] Figure 3A This is a circuit diagram of a pixel in a display device according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 3AIn this embodiment, it is assumed that pixel PX is liquid crystal pixel PXa, wherein the same or similar elements are referred to by the same or similar designations. In this embodiment, liquid crystal pixel PXa includes transistors M1 and M2, storage capacitor Cst, and liquid crystal capacitor Clc, wherein liquid crystal capacitor Clc is formed by liquid crystal electrode (not shown), common electrode (not shown), and liquid crystal material located between the two.

[0064] Transistor M1's first terminal receives the gate signal GT, and its control terminal receives the group control signal PT. Transistor M2's first terminal receives the pixel voltage Vpixel, and its control terminal is coupled to the second terminal of transistor M1. Storage capacitor Cst is coupled between the second terminal of transistor M2 and the common voltage Vcom transmitted via a common electrode (not shown). Liquid crystal capacitor Clc is coupled between the second terminal of transistor M2 and the common voltage Vcom transmitted via a common electrode (not shown).

[0065] Figure 3B This is a circuit diagram of a pixel in a display device according to another embodiment of the present invention. Please refer to... Figure 1 and Figure 3B In this embodiment, it is assumed that pixel PX is a light-emitting diode pixel PXb, wherein the same or similar components are labeled with the same or similar designations. In this embodiment, the light-emitting diode pixel PXb includes transistors M3~M5, capacitor C1, and light-emitting diode LD1.

[0066] Transistor M3's first terminal receives the gate signal GT, and its control terminal receives the group control signal PT. Transistor M4's first terminal receives the pixel voltage Vpixel, and its control terminal is coupled to the second terminal of transistor M3. Transistor M5's first terminal receives the system high voltage Vdd, and its control terminal is coupled to the second terminal of transistor M4. Capacitor Cst is coupled between the control terminal and the second terminal of transistor M5. Light-emitting diode LD1 is coupled between the second terminal of transistor M5 and the system low voltage Vss.

[0067] Figure 4 This is a system schematic diagram of a display device according to another embodiment of the present invention. Please refer to... Figure 1 and Figure 4 In this embodiment, the display device 200 is substantially the same as the display device 100, except that the display device 200 further includes a multiplexer circuit 210, wherein the same or similar components are labeled with the same or similar reference numerals. In this embodiment, the multiplexer circuit 210 is coupled between the pixel array 140 and the source driver 130, and is coupled to the timing controller 110 to receive multiplexing control signals (such as MUXA, MUXB).

[0068] In this embodiment, the multiplexer circuit 210 provides pixel voltages (e.g., Vpixel1~Vpixel4) and group control signals (e.g., PTr1, PTr2) to these pixels PX via time-division multiplexing based on multiplexing control signals (e.g., MUXA, MUXB). Furthermore, via two multiplexing control signals (e.g., MUXA, MUXB), the multiplexer circuit 210 can receive two signals via the same line, for example, receiving pixel voltages Vpixel1 and Vpixel2 via the same line, receiving group control signals PTr1 and PTr2 via the same line, and receiving pixel voltages Vpixel3 and Vpixel4 via the same line. Then, these signals are separated according to timing and sequentially transmitted to the pixel array 140. This reduces the number of signals (i.e., output endpoints) provided by the source driver 130, thereby reducing the hardware cost of the source driver 130.

[0069] Figure 5 This is a circuit diagram of a multiplexer circuit and a pixel array according to an embodiment of the present invention. Please refer to... Figure 1 , Figure 4 and Figure 5 In this embodiment, the multiplexer circuit 210 is exemplified by multiplexer circuit 210a. In this embodiment, multiplexer circuit 210a includes multiple transistors (such as Mx1 to Mx6), wherein the transistors (such as Mx1 to Mx6) are paired in pairs. For example, transistors Mx1 and Mx2 are paired, transistors Mx3 and Mx6 are paired, and transistors Mx4 and Mx5 are paired.

[0070] Furthermore, the first terminals of the paired transistors Mx1 and Mx2 jointly receive signals / lines transmitting pixel voltages Vpixel1 and Vpixel2. The control terminals of transistors Mx1 and Mx2 respectively receive multiplexing control signals MUXA and MUXB, and the second terminals of transistors Mx1 and Mx2 are respectively coupled to source lines Lsrc1 and Lsrc2. Similarly, the first terminals of the paired transistors Mx3 and Mx6 jointly receive signals / lines transmitting group control signals PTr1 and PTr2. The control terminals of transistors Mx3 and Mx6 respectively receive multiplexing control signals MUXA and MUXB, and the second terminals of transistors Mx3 and Mx6 are respectively coupled to group control lines Lpt1 and Lpt2. The first terminals of the paired transistors Mx4 and Mx5 jointly receive the signal / line that transmits the pixel voltages Vpixel3 and Vpixel4. The control terminals of transistors Mx4 and Mx5 respectively receive the multiplexing control signals MUXA and MUXB. The second terminals of transistors Mx4 and Mx5 are respectively coupled to the source lines Lsrc3 and Lsrc4.

[0071] Figure 6This is a schematic diagram of the driving waveform of a display device according to another embodiment of the present invention. Please refer to... Figure 5 and Figure 6 In this embodiment, it is assumed that the group control signal PTr1 is enabled (e.g., at a high voltage level) and the group control signal PTr2 is disabled (e.g., at a low voltage level). During the enable period of the gate signal GT1 (e.g., during the high voltage level period), the signals transmitting the group control signals PTr1 and PTr2 are enabled during the enable period of the multiplexing control signal MUXA (e.g., during the high voltage level period) and disabled during the enable period of the multiplexing control signal MUXB (e.g., during the high voltage level period). During the enable period of the multiplexing control signal MUXA, the pixel voltages Vpixel1 and Vpixel2 can change their voltage levels (e.g., from low voltage level to high voltage level) to update the display grayscale of the pixel PX in the pixel group PRE1. Conversely, during the enable period of the multiplexing control signal MUXB, the voltage levels of the pixel voltages Vpixel3 and Vpixel4 can remain unchanged (e.g., remain at a low voltage level) to keep the display grayscale of the pixel PX in the pixel group PRE1 unchanged.

[0072] In summary, the display device of this invention, based on the division of pixel groups, allows each pixel group to be controlled not only by the gate signal but also by its own independent group control signal. Therefore, under the control of the group control signal, each pixel group can independently determine the pixel update frequency, thereby achieving independent variable update rates for each pixel group.

[0073] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A display device, characterized in that, include: A pixel array having multiple pixels, and these pixels being divided into multiple pixel groups; A timing controller receives image data and provides multiple pixel data and one pixel anomaly data based on the image data; A gate driver, coupled to the pixels, provides multiple gate signals to the pixels for row-by-row enable; as well as A source driver, coupled to the pixels, provides multiple pixel voltages to the pixels based on pixel data, and provides multiple group control signals based on pixel anomaly data. The pixels in each of the pixel groups jointly receive one of the group control signals, and each of the pixels receives a corresponding pixel voltage based on the received gate signal and the received group control signal.

2. The display device as claimed in claim 1, characterized in that, The timing controller provides pixel anomaly data based on a comparison between a current frame and a previous frame.

3. The display device as claimed in claim 2, characterized in that, When the pixel anomaly data indicates that the display grayscale of one of the pixels in each of the pixel groups needs to be changed, the group control signal corresponding to each of the pixel groups is enabled, and When the pixel anomaly data indicates that multiple display grayscale values ​​of pixels in each pixel group do not need to be changed, the group control signal corresponding to each pixel group is disabled.

4. The display device as claimed in claim 3, characterized in that, When the group control signal corresponding to each of the pixel groups is disabled, the pixel voltages received by the pixels of each of the pixel groups remain at a previous voltage level.

5. The display device as claimed in claim 3, characterized in that, When the grayscale of one of the pixels in the current frame is different from the grayscale of one of the pixels in the previous frame, the pixel anomaly data indicates that the grayscale of one of the pixels needs to be changed.

6. The display device as claimed in claim 2, characterized in that, The pixel anomaly data indicates that at least one position in these pixels needs to have its display grayscale changed.

7. The display device as claimed in claim 1, characterized in that, It also includes a multiplexer circuit coupled between the pixel array and the source driver, wherein the multiplexer circuit provides the pixel voltages and the group control signals to the pixels via a time-division multiplexing based on the multiplexing control signals.

8. The display device as claimed in claim 1, characterized in that, These pixel groups are distinguished by columns.

9. The display device as claimed in claim 1, characterized in that, Each of these pixels is disabled based on at least one of the received gate signal and the received group control signal, and does not receive a corresponding one of the pixel voltages. Each of these pixels receives a corresponding pixel voltage based on the fact that both the received gate signal and the received group control signal are enabled.

10. The display device as claimed in claim 1, characterized in that, These pixels are either a liquid crystal pixel or a light-emitting diode pixel.

Images