LED driving circuit, driving chip, display device and electronic equipment

Abstract

This application discloses an LED driving circuit, a driving chip, a display device, and an electronic device. The LED driving circuit includes: a first voltage generation module for generating a control voltage and a feedback voltage; a second voltage generation module for receiving the control voltage and the feedback voltage and generating a second voltage based on a negative feedback loop; and an output module for providing an initial potential to the control terminal of the driving transistor according to the second voltage and controlling the opening and closing of the output driving current according to a PWM signal. The output module includes a first operational amplifier connected in the form of a buffer. When the PWM signal is at a first level, the negative feedback loop in the second voltage generation module and the first operational amplifier in the output module operate normally, providing an initial potential to the gate of the driving transistor. When the PWM signal switches to the second level, the driving transistor establishes an output current based on the initial potential. By providing a preset initial potential to the driving transistor, voltage fluctuations and output current overshoot are effectively reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically, to an LED driving circuit, a driving chip, a display device, and an electronic device. Background Technology

[0002] In the field of LED (Light Emitting Diode) display driver chips, ensuring accurate, stable, and fast response of the output current is crucial for improving display quality. Traditional driver circuits typically employ a constant current source structure based on a current mirror and operational amplifier. The core principle is to generate a constant output current to drive the LED by replicating a main reference current through a proportionally configured transistor network. When the control signal is valid, the op-amp loop is established, forcing the output transistors to accurately replicate the reference current, thus achieving constant current drive. However, this classic structure faces inherent challenges in dynamic performance when dealing with PWM (Pulse Width Modulation) dimming, especially for low grayscale displays.

[0003] Specifically, traditional designs have significant drawbacks during the transient process of control signal switching. When the output needs to switch from a turned-off state to a turned-on state, the voltage at critical nodes in the control loop undergoes a build-up process involving a significant pull-down from the supply voltage. Figure 1 As shown, when the PWM signal is invalid (PWM=0, PWMN=1), the switching transistor MSW is off, the drain of transistor M4 is pulled high to AVDD, and the output of operational amplifier AMP2 is connected to the gate of transistor MVCAS, with the gate potential of transistor MVCAS being 0V. When the PWM signal is valid (PWM=1, PWMN=0), transistor MSW is on, the output of operational amplifier AMP2 causes the gate voltage of transistor MVCAS to rise from 0V, transistor MVCAS is on, and the drain potential of transistor M4 is pulled down from the power supply voltage AVDD to a lower level, causing the output current IOUT1 to generate a large overshoot current during the startup phase. The time it takes for the output current IOUT1 to establish a stable value is entirely limited by the response speed of the feedback loop in which operational amplifier AMP2 is located. The aforementioned structure has two drawbacks: First, it generates a large overcurrent during the startup phase. Since bonding wires are typically used in chip packaging, this large overcurrent introduces significant noise at the ground terminal due to the parasitic inductance of the bonding wires, causing common ground coupling and severely impacting the performance of other circuits within the chip. Second, the long time it takes for the current to build up and stabilize deteriorates the current response characteristics during low-grayscale display, leading to display anomalies such as color blocks or vertical stripes in low-grayscale areas. These problems severely restrict further improvements in display performance.

[0004] Therefore, optimizing the circuit to suppress current overshoot and accelerate the turn-on transient response has become an important technical issue for improving the performance of display devices. Summary of the Invention

[0005] The purpose of this invention is to provide an LED driving circuit, a driving chip, a display device, and an electronic device, which aim to improve the display effect.

[0006] According to one aspect of the present invention, an LED driving circuit is provided, comprising: a first voltage generating module for generating a control voltage and a feedback voltage; a second voltage generating module connected to the first voltage generating module for receiving the control voltage and the feedback voltage, and generating a second voltage based on a negative feedback loop; and an output module connected to the first voltage generating module and the second voltage generating module for receiving the control voltage and the second voltage, providing an initial potential to the control terminal of a driving transistor according to the second voltage, and controlling the opening and closing of an output driving current according to the state of a PWM signal; wherein the output module includes a first operational amplifier connected in the form of a buffer, its first input terminal receiving the second voltage, its second input terminal connected to its output terminal, and its output terminal connected to the control terminal of the driving transistor.

[0007] Optionally, the first voltage generation module includes: a second operational amplifier, whose first input terminal receives a first voltage; a first transistor, whose control terminal is connected to the output terminal of the second operational amplifier, whose first terminal is connected to a power supply voltage or ground, and whose second terminal is connected to the second input terminal of the second operational amplifier; a current generation unit, connected to the second terminal of the first transistor, for generating a reference current; and a buffer, whose input terminal is connected to the output terminal of the second operational amplifier, and whose output terminal provides the control voltage; wherein the voltage at the second terminal of the first transistor is the feedback voltage.

[0008] Optionally, the second voltage generating module includes: a second transistor, whose control terminal receives the control voltage, and whose first terminal is connected to a power supply voltage or ground; a third operational amplifier, whose first input terminal is connected to the second terminal of the second transistor, and whose second input terminal receives the feedback voltage; a third transistor, whose control terminal is connected to the output terminal of the third operational amplifier, whose first terminal is connected to the second terminal of the second transistor, and whose second terminal is connected to ground; wherein the output voltage of the third operational amplifier is used as the second voltage.

[0009] Optionally, the output module further includes: a fourth transistor, whose control terminal receives the control voltage, whose first terminal is connected to the power supply voltage or ground, and whose second terminal is connected to the first terminal of the driving transistor; and a fifth transistor, whose first terminal is connected to the second terminal of the driving transistor, whose second terminal is used to output the driving current, and whose control terminal receives the inverse signal of the PWM signal.

[0010] Optionally, the first voltage generation module further includes a third adjustment unit, which is connected to the first operational amplifier and is used to adjust the input offset voltage of the first operational amplifier.

[0011] Optionally, the second voltage generation module further includes a first adjustment unit, which is connected to the second operational amplifier and is used to adjust the input offset voltage of the second operational amplifier.

[0012] Optionally, the second voltage generation module further includes a second adjustment unit, which is connected to the third operational amplifier and is used to adjust the input offset voltage of the second operational amplifier.

[0013] Optionally, the first transistor, the second transistor, and the fourth transistor are MOS transistors of the same type and have the same unit size, and their quantities are configured according to a first preset ratio; the third transistor and the driving transistor are MOS transistors of the same type and have the same unit size, and their quantities are configured according to a second preset ratio.

[0014] Optionally, the output module includes multiple modules, each of which is connected to the first voltage generating module and the second voltage generating module.

[0015] Optionally, the drive circuit adopts a common cathode or common anode design.

[0016] According to another aspect of the present invention, a driver chip is provided, comprising the above-described driver circuit.

[0017] Optionally, the driving circuit includes a plurality of output modules, each output module corresponding to a driving channel.

[0018] According to another aspect of the present invention, a display device is provided, comprising the aforementioned driver chip.

[0019] According to another aspect of the present invention, an electronic device is provided, including the display device described above.

[0020] This invention effectively solves two key problems of current overshoot and excessively long settling time in traditional LED driver circuits through innovative circuit structure design. Specifically, by adding a second voltage generation module and connecting the operational amplifier in the output module in a buffer configuration, both the second voltage generation module and the operational amplifier in the output module can operate normally in their respective loops when the PWM signal is invalid. This provides the gate of the driver transistor with a stable potential as its initial potential after the transistor is turned on. Therefore, when the PWM signal switches to an effective level, the gate of the driver transistor does not need to start from zero potential, shortening the time for the current to reach a stable value and significantly improving display performance. Furthermore, the reduction in current overshoot reduces grounding noise caused by the parasitic inductance of the bonding wires, ensuring the stable operation of other circuits within the chip and reducing the impact of other circuits on the stability of the output current of this module. The faster current settling speed optimizes the current response at low grayscale levels, effectively eliminating low grayscale display anomalies such as color blocks and vertical stripes that may appear in the display, thereby comprehensively improving display uniformity and image quality.

[0021] Furthermore, by setting a first adjustment unit, a second adjustment unit, and a third adjustment unit in the first voltage generation module, the second voltage generation module, and the output module respectively, the input offset voltage of the corresponding operational amplifiers is adjusted. This eliminates the output current deviations between different chips and the consistency deviations between channels within the chip caused by process variations. Simultaneously, it optimizes the inflection point potential of the output current, ensuring the consistency of the turn-on edge between different chips and different channels. For large-size displays requiring multi-chip splicing, this significantly reduces brightness and color differences between modules, improving the overall display effect. At the same time, this design enhances tolerance to process variations, improves chip yield and reliability, and has good value for mass production applications. Attached Figure Description

[0022] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings.

[0023] Figure 1 A schematic diagram of an existing LED driver circuit is shown;

[0024] Figure 2 A schematic diagram of an LED driving circuit according to a first embodiment of the present invention is shown;

[0025] Figure 3 A schematic diagram of an LED driving circuit according to a second embodiment of the present invention is shown. Detailed Implementation

[0026] The present invention will now be described in more detail with reference to the accompanying drawings. To facilitate understanding of this application, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application may be implemented in different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0027] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0028] In the description of this application, the words "exemplary" or "for example" are used to indicate that they are examples, illustrations, or descriptions. Any embodiment described as "exemplary" or "for example" in this application should not be construed as being more preferred or advantageous than other embodiments. "And / or" in this document describes an association relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. "Connection" describes a connection relationship between related objects. For example, A and B are connected, which can indicate a direct connection between A and B, or an indirect connection between A and B through other devices / units / modules. "Multiple" refers to two or more. Furthermore, to facilitate a clear description of the technical solutions of the embodiments of this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function and effect. Those skilled in the art will understand that the terms "first," "second," etc., do not limit the quantity or execution order, and that "first," "second," etc., do not necessarily imply differences.

[0029] Furthermore, the same reference numerals in the figures denote the same or similar structures, thus repeated descriptions of them will be omitted. That is, the various parts in this specification are described using a combination of parallel and progressive methods, with each part focusing on its differences from the others. Similar or identical parts can be referred to interchangeably. Terms expressing position and direction described in this application are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of this application. The accompanying drawings in this application are for illustrating relative positional relationships only and do not represent actual scale.

[0030] This application describes many specific details of the invention, such as the specific structure, dimensions, connection relationships, and techniques of the modules, in order to provide a clearer understanding of the invention. However, as those skilled in the art will understand, the invention may be implemented without following these specific details.

[0031] In this application, a MOS transistor (Metal-Oxide-Semiconductor Field-Effect Transistor) includes a first terminal, a second terminal, and a control terminal. For example, the first terminal, second terminal, and control terminal of a P-type MOS transistor can be the source, drain, and gate, respectively, and the first terminal, second terminal, and control terminal of an N-type MOS transistor can be the drain, source, and gate, respectively.

[0032] This invention can be presented in various forms, some of which will be described below.

[0033] Figure 2 A schematic diagram of an LED driving circuit according to a first embodiment of the present invention is shown. The driving circuit includes a first voltage generation module 110, a second voltage generation module 120, and an output module 130. The first voltage generation module 110 generates a VGATE voltage based on a first voltage VCRES1 and a VFB voltage used as a feedback voltage. The VGATE voltage is, for example, a control voltage. The second voltage generation module 120 provides a second voltage VCRES2 to the output module 130. The output module 130 provides a preset gate voltage to the gate of the driving transistor based on the second voltage VCRES2. By setting the negative feedback control in the second voltage generation module 120 and then using an operational amplifier AMP3 connected in a buffer configuration in the output module 130, the gate voltage fluctuation of the driving transistor can be effectively reduced, preventing the gate voltage of the driving transistor from starting from 0V, thereby reducing drain voltage fluctuations and output current overshoot.

[0034] The first voltage generation module 110 includes: an operational amplifier AMP1, a transistor MP1, a first adjustment unit, a current generation unit, and a buffer BUF. The transistor MP1 is, for example, a P-type MOSFET. The first input terminal of the operational amplifier AMP1 receives a first voltage VCRES1. The second input terminal of the operational amplifier AMP1 is connected to the drain of the transistor MP1 and receives the VFB voltage as a feedback voltage. The source of the transistor MP1 is connected to the power supply voltage AVDD. The gate of the transistor MP1 is connected to the output terminal of the operational amplifier AMP1. The drain of the transistor MP1 is connected to the current generation unit via node A, which provides a reference current IDC. This first voltage generation module 110 is used to provide subsequent modules with the VGATE voltage after passing through the buffer BUF at the output terminal of the operational amplifier AMP1 and the VFB voltage at node A. Furthermore, the first adjustment unit is connected to the operational amplifier AMP1 to adjust the input offset voltage (VOS) of the operational amplifier AMP1, reducing the deviation caused by the input offset voltage.

[0035] The second voltage generation module 120 includes: transistor MP2, operational amplifier AMP2, transistor MP3, a second adjustment unit, and transistor MP5. Transistors MP2, MP3, and MP5 are, for example, P-type MOSFETs. The gate of transistor MP2 receives the VGATE voltage, the source of transistor MP2 is connected to the power supply voltage AVDD, and the drain of transistor MP2 is connected to the source of transistor MP3. The first input terminal of operational amplifier AMP2 receives the drain signal of transistor MP2, and the second input terminal of operational amplifier AMP2 is connected to the drain of transistor MP1 via node A, receiving the VFB voltage. The output terminal of operational amplifier AMP2 is connected to the gate of transistor MP3, providing a second voltage VCRES2 to the gate of transistor MP3. The drain of transistor MP3 is connected to the source of transistor MP5, and the gate of transistor MP5 is connected to ground AVSS. The drain of transistor MP5 is also connected to ground AVSS. Furthermore, the second adjustment unit is connected to operational amplifier AMP2 to adjust the input offset voltage of operational amplifier AMP2, reducing the deviation caused by the input offset voltage.

[0036] Output module 130 includes: operational amplifier AMP3, transistor MP4, transistor MVCAS, NOT gate NG, transistor MSW, and a third tuning unit. Transistors MP4, MVCAS, and MSW are, for example, P-type MOSFETs. The source of transistor MP4 is connected to the power supply voltage AVDD, the gate of transistor MP4 receives the voltage VGATE, and the drain of transistor MP4 is connected to the source of transistor MVCAS. Transistor MVCAS serves as the driving transistor in the LED driving circuit. The gate of transistor MVCAS is connected to the output of operational amplifier AMP3. The first input of operational amplifier AMP3 receives the second voltage VCRES2, and the second input of operational amplifier AMP3 is connected to its output, allowing operational amplifier AMP3 to be connected as a buffer, providing a preset potential to the gate of transistor MVCAS. The gate of transistor MSW is connected to the output of NOT gate NG. The input of NOT gate NG receives a PWM signal, and the output of NOT gate NG provides a PWMN signal, which is the inverted signal of the PWM signal. The drain of transistor MSW provides the output current IOUT. The switching of this branch is, for example, controlled by transistor MSW.

[0037] Furthermore, in Figure 2 In the LED driving circuit of the first embodiment shown, the first voltage generating module 110 and the second voltage generating module 120 are separately configured circuits, and the output module 130 includes, for example, multiple modules. Figure 2 The example shown is only of a single output module 130; for a display device, it may include multiple chips having the above-described driving circuitry.

[0038] Compared to traditional LED driving circuits, in the LED driving circuit of the first embodiment of the present invention, when the PWM signal is at the first level (PWM=0), the operational amplifier AMP2 operates normally in the current mirror loop of the second voltage generation module 120, providing the second voltage VCRES2 to the operational amplifier AMP3. The output terminal of the operational amplifier AMP3 provides the initial potential to the gate of the transistor MVCAS. When the PWM signal is at the second level (PWM=1), the transistor MSW is turned on. Because the gate of the transistor MVCAS has an initial potential, the drain of the transistor MP4 can quickly respond to a stable potential, that is, the transistor MP4 can quickly output the correct current value without generating a large current spike.

[0039] Specifically, transistors MP1, MP2, and MP4 have the same unit size, and their numbers are configured in the ratio of m1:m2:m3. Transistor MP3 and transistor MVCAS have the same unit size, and their numbers are configured in the ratio of m2:m3. When PWM=0 and PWMN=1, operational amplifiers AMP2 and AMP3 operate normally in their respective loops, and the current of transistor MP2 precisely replicates the current of transistor MP1 proportionally. When PWM=1 and PWMN=0, transistor MSW is turned on. Once the loop containing operational amplifier AMP3 stabilizes, the current of transistor MP4 precisely replicates the current of transistor MP1 proportionally.

[0040] Since transistors MP2 and MP4 have the same unit size, and transistors MP3 and MVCAS have the same unit size, and the ratio of transistors MP2 and MP4 is the same as the ratio of transistors MP3 and MVCAS, the gate voltage of transistor MVCAS is the same as the gate voltage of transistor MP3. This method allows the gate of transistor MVCAS to be set to the expected potential after PWM=1 stabilization when PWM=0 is used as the initial potential. This design can reduce the overshoot problem of output current IOUT when the PWM signal switches from 0 to 1, improve the current turn-on edge setup speed, and shorten the ripple time.

[0041] To ensure the consistency of current between channels within the chip containing the aforementioned driving circuit, the consistency of current between different chips, and the inflection point of the output current, corresponding tuning units are set up for each operational amplifier in the circuit.

[0042] Specifically, the input offset voltage of operational amplifier AMP1 causes the drain-source voltage VDS of transistors MP1 and MP4 to deviate from the potential of the first voltage VCRES1, resulting in deviations in the current inflection point of the output IOUT of different chips and inconsistencies in the reference current IDC. Furthermore, the different input offset voltages of operational amplifier AMP1 across different chips lead to different potentials at the VA point, resulting in different potentials at the second voltage VCRES2. This causes deviations in the gate voltage of transistor MP3, i.e., the initial value setting of transistor MVCAS across different chips, thus affecting the consistency of the turn-on edge between chips. To optimize the inflection point potential deviations and the consistency of the turn-on edge between chips, a first adjustment unit is provided for operational amplifier AMP1 to eliminate the potential difference between the first voltage VCRES1 at the input terminal of operational amplifier AMP1 and the input voltage VIN.

[0043] The input offset voltage of operational amplifier AMP2 also causes the drain-source voltage VDS of transistor MP4 to deviate from the potential of the first voltage VCRES1, resulting in a deviation in the current inflection point of the output IOUT of different chips. Furthermore, the input offset voltage of operational amplifier AMP2 causes inaccurate current values ​​in transistor MP1, which is replicated by transistor MP2, leading to deviations in the initial value settings of the gate voltage of transistor MP3 (i.e., the initial value of transistor MVCAS between different chips), affecting the consistency of the turn-on edge between chips. To optimize the inflection point potential deviation between different chips and the consistency of the turn-on edge between chips, a second adjustment unit is set for operational amplifier AMP2. The function of the second adjustment unit is to eliminate the potential difference between the two input terminals of operational amplifier AMP2.

[0044] A single chip may include a first voltage generation module 110, a second voltage generation module 120, and multiple output modules 130, forming multiple channels through the multiple output modules 130 to drive the corresponding light-emitting units respectively. Figure 2 The single output module 130 is merely an example; for a display device, it may include multiple chips with the aforementioned driving circuitry. Deviations in the first voltage generation module 110 and the second voltage generation module 120 within a chip can cause current deviations between different chips; deviations in the output module 130 can affect current deviations between different channels (branches) within a single chip. Therefore, the output module 130 also includes a third adjustment unit connected to the operational amplifier AMP3 to adjust the input offset voltage of the operational amplifier AMP3.

[0045] The input offset voltage of operational amplifier AMP3 can cause deviations in the initial value settings of transistors MVCAS across different channels within the chip, affecting the consistency of the turn-on edges across these channels. To optimize the consistency of the output current IOUT across different channels and the current inflection point of IOUT, a third trimming unit is provided for operational amplifier AMP3. This third trimming unit eliminates the potential difference between the two input terminals of operational amplifier AMP3.

[0046] Figure 3 The diagram shows a schematic of an LED driving circuit according to a second embodiment of the present invention. The second embodiment is similar to the first embodiment, except that the driving circuit of the second embodiment adopts a common anode design. Accordingly, the circuit connection is partially changed, and each transistor adopts an N-type MOS transistor.

[0047] like Figure 3As shown, the LED driving circuit of this second embodiment includes a first voltage generation module 110, a second voltage generation module 120, and an output module 130. The first voltage generation module 110 generates a VGATE voltage based on a first voltage VCRES1 and a VFB voltage. The second voltage generation module 120 provides a second voltage VCRES2 to the output module 130. The output module 130 provides a preset gate voltage to the gate of the driving transistor based on the second voltage VCRES2. By setting the negative feedback control in the second voltage generation module 120 and then connecting the operational amplifier AMP3 in the output module 130 in a buffer configuration, the gate voltage fluctuation of the driving transistor can be effectively reduced, preventing the gate voltage of the driving transistor from starting from 0V, thereby reducing the drain voltage fluctuation and output current overshoot of the driving transistor.

[0048] The first voltage generation module 110 includes: an operational amplifier AMP1, a transistor MN1, a first adjustment unit, a current generation unit, and a buffer BUF. The transistor MN1 is, for example, an N-type MOSFET. The first input terminal of the operational amplifier AMP1 is connected to the drain of the transistor MN1, receiving the VFB voltage. The second input terminal of the operational amplifier AMP1 receives a first voltage VCRES1. The source of the transistor MN1 is connected to ground AVSS. The gate of the transistor MN1 is connected to the output terminal of the operational amplifier AMP1. The drain of the transistor MN1 is connected to the current generation unit via node B, which provides a reference current IDC. This first voltage generation module 110 is used to provide subsequent modules with the VGATE voltage after passing through the buffer BUF at the output terminal of the operational amplifier AMP1 and the VFB voltage at node B. Furthermore, the first adjustment unit is connected to the operational amplifier AMP1 to adjust the input offset voltage (VOS) of the operational amplifier AMP1, reducing the deviation caused by the input offset voltage.

[0049] The second voltage generation module 120 includes: transistor MN2, operational amplifier AMP2, transistor MN3, a second adjustment unit, and transistor MN5. Transistors MN2, MN3, and MN5 are, for example, N-type MOSFETs. The gate of transistor MN2 receives the VGATE voltage, the source of transistor MN2 is connected to ground AVSS, and the drain of transistor MN2 is connected to the source of transistor MN3. The first input terminal of operational amplifier AMP2 is connected to the drain of transistor MN1 via node B, receiving the VFB voltage. The second input terminal of operational amplifier AMP2 receives the drain signal of transistor MN2. The output terminal of operational amplifier AMP2 is connected to the gate of transistor MN3, providing a second voltage VCRES2 to the gate of transistor MN3. The drain of transistor MN3 is connected to the source of transistor MN5, and the gate of transistor MN5 is connected to the power supply voltage AVDD. The drain of transistor AMP5 is also connected to the power supply voltage AVDD. Furthermore, the second adjustment unit is connected to operational amplifier AMP2 to adjust the input offset voltage of operational amplifier AMP2, reducing the deviation caused by the input offset voltage.

[0050] Output module 130 includes: operational amplifier AMP3, transistor MN4, transistor MVCAS, NOT gate NG, transistor MSW, and a third tuning unit. Transistors MN4, MVCAS, and MSW are, for example, N-type MOSFETs. The source of transistor MN4 is connected to ground AVSS. The gate of transistor MN4 receives the VGATE voltage, and the drain of transistor MN4 is connected to the source of transistor MVCAS. Transistor MVCAS serves as the driving transistor in the LED driving circuit. The gate of transistor MVCAS is connected to the output of operational amplifier AMP3. The first input of operational amplifier AMP3 is connected to its output. The second input of operational amplifier AMP3 receives a second voltage VCRES2, allowing AMP3 to be connected as a buffer, providing a preset potential to the gate of transistor MVCAS. The gate of transistor MSW is connected to the output of NOT gate NG. The input of NOT gate NG receives a PWM signal, and the output of NOT gate NG provides a PWMN signal, which is the inverted signal of the PWM signal. The drain of transistor MSW provides the output current IOUT. The switching of this branch is, for example, controlled by transistor MSW.

[0051] Furthermore, in Figure 3 In the LED driving circuit of the second embodiment shown, a single chip may include a first voltage generating module 110, a second voltage generating module 120, and multiple output modules 130. Figure 3The single output module 130 in the example is merely an example; for a single driver chip, the driver circuit in the chip may have multiple output modules 130; for a display device, it may include multiple chips with the above-mentioned driver circuit.

[0052] Specifically, transistors MN1, MN2, and MN4 have the same unit size, and their numbers are configured in the ratio of m1:m2:m3. Transistor MN3 and transistor MVCAS have the same unit size, and their numbers are configured in the ratio of m2:m3. When PWM=0 and PWMN=1, operational amplifiers AMP2 and AMP3 operate normally in their respective loops, and the current of transistor MN2 precisely replicates the current of transistor MN1 proportionally. When PWM=1 and PWMN=0, transistor MSW is turned on. Once the loop containing operational amplifier AMP3 is stable, the current of transistor MN4 precisely replicates the current of transistor MN1 proportionally.

[0053] Since transistors MN2 and MN4 have the same unit size, and transistors MN3 and MVCAS have the same unit size, and the ratio of transistors MN2 and MN4 is the same as the ratio of transistors MN3 and MVCAS, the gate voltage of transistor MVCAS is the same as the gate voltage of transistor MN3. This allows the gate of transistor MVCAS to be set to the expected potential after PWM=1 stabilization when PWM=0 is used as the initial potential. This design can reduce the overshoot problem of the output current IOUT when the PWM signal switches from 0 to 1, improve the setup speed of the current turn-on edge, and shorten the ripple time.

[0054] In order to optimize the consistency of current between channels within the chip containing the above-mentioned driving circuit, the consistency of current between different chips, and the inflection point of output current, corresponding first adjustment unit, second adjustment unit, and third adjustment unit are set for the operational amplifiers AMP1, AMP2, and AMP3 in the circuit, respectively. Their specific functions are similar to those of the adjustment unit in the first embodiment, and will not be described again here.

[0055] Furthermore, the current generating unit in the first and second embodiments described above can obtain the reference current IDC by outputting the reference current source in the corresponding chip, or it can be designed with an external resistor. By applying the first voltage VCRES1 to the external resistor res, the corresponding reference current IDC = VCRES1 / res can be obtained according to Ohm's law.

[0056] This invention effectively solves two key problems of current overshoot and excessively long settling time in traditional LED driver circuits through innovative circuit structure design. Specifically, by adding a second voltage generation module and setting the negative feedback control within it, and connecting the operational amplifier in the output module in a buffer configuration, both the second voltage generation module and the operational amplifier in the output module can operate normally in their respective loops when the PWM signal is invalid. This provides the gate of the driver transistor with a stable potential as its initial potential after the transistor is turned on. Therefore, when the PWM signal switches to an effective level, the gate of the driver transistor does not need to start from zero potential, shortening the time for the current to reach a stable value and significantly improving display performance. Furthermore, the reduction in current overshoot reduces grounding noise caused by the parasitic inductance of the bonding wires, ensuring the stable operation of other circuits within the chip and reducing the impact of other circuits on the stability of the output current of this module. The faster current settling speed optimizes the current response at low grayscale levels, effectively eliminating low grayscale display anomalies such as color blocks and vertical stripes that may appear in the display, thereby comprehensively improving display uniformity and image quality.

[0057] Furthermore, by setting a first adjustment unit, a second adjustment unit, and a third adjustment unit in the first voltage generation module, the second voltage generation module, and the output module respectively, the input offset voltage of the corresponding operational amplifiers is adjusted. This eliminates the output current deviations between different chips and the consistency deviations between channels within the chip caused by process variations. Simultaneously, it optimizes the inflection point potential of the output current, ensuring the consistency of the turn-on edge between different chips and different channels. For large-size displays requiring multi-chip splicing, this significantly reduces brightness and color differences between modules, improving the overall display effect. At the same time, this design enhances tolerance to process variations, improves chip yield and reliability, and has good value for mass production applications.

[0058] As described above, these embodiments of the present invention do not exhaustively describe all details, nor do they limit the invention to specific embodiments. Clearly, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to effectively utilize the invention and its modifications. The scope of protection of this invention should be determined by the scope defined in the claims of this invention.

Claims

1. An LED driving circuit, characterized in that, include: The first voltage generation module is used to generate control voltage and feedback voltage; The second voltage generation module is connected to the first voltage generation module and is used to receive the control voltage and the feedback voltage, and generate a second voltage based on the negative feedback loop. as well as The output module, connected to the first voltage generation module and the second voltage generation module, is used to receive the control voltage and the second voltage, provide an initial potential to the control terminal of the drive transistor according to the second voltage, and control the opening and closing of the output drive current according to the state of the PWM signal. The output module includes a first operational amplifier connected in the form of a buffer. Its first input terminal receives the second voltage, its second input terminal is connected to its output terminal, and its output terminal is connected to the control terminal of the driving transistor.

2. The driving circuit according to claim 1, characterized in that, The first voltage generation module includes: The second operational amplifier receives a first voltage at its first input terminal; The first transistor has its control terminal connected to the output terminal of the second operational amplifier, its first terminal connected to the power supply voltage or ground terminal, and its second terminal connected to the second input terminal of the second operational amplifier. A current generating unit, connected to the second terminal of the first transistor, is used to generate a reference current; A buffer, the input of which is connected to the output of the second operational amplifier, and the output of which provides the control voltage; The voltage at the second terminal of the first transistor is the feedback voltage.

3. The driving circuit according to claim 2, characterized in that, The second voltage generation module includes: The second transistor has a control terminal that receives the control voltage, and its first terminal that is connected to the power supply voltage or ground. The third operational amplifier has its first input terminal connected to the second terminal of the second transistor, and its second input terminal receives the feedback voltage. The third transistor has its control terminal connected to the output terminal of the third operational amplifier, its first terminal connected to the second terminal of the second transistor, and its second terminal connected to ground. The output voltage of the third operational amplifier is used as the second voltage.

4. The driving circuit according to claim 3, characterized in that, The output module also includes: A fourth transistor, whose control terminal receives the control voltage, whose first terminal is connected to the power supply voltage or ground, and whose second terminal is connected to the first terminal of the driving transistor; and The fifth transistor has its first terminal connected to the second terminal of the driving transistor, its second terminal being used to output the driving current, and its control terminal receiving the inverse signal of the PWM signal.

5. The driving circuit according to claim 1, characterized in that, The first voltage generation module further includes a third adjustment unit, which is connected to the first operational amplifier and is used to adjust the input offset voltage of the first operational amplifier.

6. The driving circuit according to claim 2, characterized in that, The second voltage generation module further includes a first adjustment unit, which is connected to the second operational amplifier and is used to adjust the input offset voltage of the second operational amplifier.

7. The driving circuit according to claim 3, characterized in that, The second voltage generation module further includes a second adjustment unit, which is connected to the third operational amplifier and is used to adjust the input offset voltage of the second operational amplifier.

8. The driving circuit according to claim 4, characterized in that, The first transistor, the second transistor, and the fourth transistor are the same type of MOS transistor and have the same unit size, and their quantities are configured according to a first preset ratio; the third transistor and the driving transistor are the same type of MOS transistor and have the same unit size, and their quantities are configured according to a second preset ratio.

9. The driving circuit according to any one of claims 1 to 8, characterized in that, The output module includes multiple modules, and each output module is connected to the first voltage generating module and the second voltage generating module.

10. The driving circuit according to claim 1, characterized in that, The drive circuit adopts a common cathode or common anode design.

11. A driver chip, characterized in that, Includes the drive circuit as described in any one of claims 1 to 10.

12. The driver chip according to claim 11, characterized in that, The driving circuit includes multiple output modules, each of which corresponds to a driving channel.

13. A display device, characterized in that, Includes the driver chip as described in claim 11 or 12.

14. An electronic device, characterized in that, Includes the display device as described in claim 13.

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