Multilayer electrical component

CN122800435APending Publication Date: 2026-09-22KNOWLES UK LTD
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Patent Information

Application Number
CN202610331607.0
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Priority Date
2025-03-21
Filing Date
2026-03-18
Publication Date
2026-09-22

AI Technical Summary

Technical Problem

遗憾的是,这些垂直间隙不能最佳地防止应变的累积

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Abstract

The present application relates to a multilayer electrical component. A plurality of parallel plate internal electrodes form a stack of electrode layers embedded in a dielectric body. A first set of internal electrodes and a second set of internal electrodes of the plurality of parallel plate internal electrodes. Each set includes a first internal electrode and an adjacent second internal electrode. A first gap of the first internal electrode is offset relative to a second gap of the second internal electrode. A portion of the first internal electrode overlaps a portion of the second internal electrode to form a capacitance region in each set of internal electrodes. A collection of at least two third internal electrodes of the plurality of parallel plate internal electrodes is positioned between the first set of internal electrodes and the second set of internal electrodes. The third internal electrodes are stacked adjacent to each other and form a negligible capacitance region.
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Description

Technical Field

[0001] This disclosure generally relates to multilayer electrical components (such as capacitors and rheostats) with improved robustness and performance. Background Technology

[0002] Multilayer ceramic capacitors (MLCCs) typically consist of multiple parallel-plate electrodes (also referred to here as “electrodes”) embedded in a ceramic dielectric. Sections of the dielectric separate adjacent electrodes with oppositely polarized conductive ends connected to the ends covering the dielectric. MLCC capacitors can be surface-mounted on printed circuit boards using reflow soldering or other surface mount techniques for a variety of applications, including high-voltage and high-frequency applications.

[0003] Existing technology Figure 1 An MLCC 100 is shown, comprising a plurality of parallel plate electrodes embedded in a dielectric 102, which is covered by conductive ends 104 and 106. Each electrode includes a plurality of electrically insulating plate portions 108 and 110 located in a common plane. The last plate of the odd-numbered electrodes is connected to conductive end 104, while the last plate of the even-numbered electrodes is connected to another conductive end 106. The overlapping plate portions of adjacent electrodes form a series arrangement of capacitors (e.g., C1, C3, and C5) between the conductive ends, which is connected in parallel with another series arrangement of capacitors (e.g., C2, C4, and C6) between the conductive ends. Each series capacitor reduces a portion of the voltage applied to the conductive end.

[0004] These and other MLCCs are susceptible to stress fracture due to piezoelectric or electrostrictive forces along a common boundary between adjacent series capacitors (e.g., the boundary between capacitors C1, C3, and C5 aligns with the boundary between capacitors C2, C4, and C6), which is associated with gap 111 (the plate portion separating the common plane). Stress fracture is more severe in applications where MLCCs are subjected to higher voltages and higher frequencies.

[0005] For example, alternating electrodes create overlapping regions that generate capacitance, such as capacitors C1 through C6. These capacitive regions experience strain, especially when a high-voltage pulse is applied to the MLCC 100. This strain can lead to piezoelectric breakage.

[0006] To elaborate, a common failure mode in ceramic capacitors subjected to sudden voltage applications is due to the piezoelectric properties of the ceramic. Sudden dimensional changes caused by the piezoelectric effect lead to high internal strain accumulation, resulting in cracking in or near the center of the MLCC. Pulse testing for safety capacitors is one such test in which a sudden voltage pulse is applied. The capacitance density within the MLCC increases the risk of piezoelectric breakage, and this issue limits the maximum capacitance that can pass the test.

[0007] Additional thick dielectric layers can be inserted between the electrode assemblies to provide vertical gaps that prevent localized strain accumulation. Unfortunately, these vertical gaps do not optimally prevent strain accumulation. Moreover, to be effective, these vertical gaps need to be many times thicker than typical dielectric layers, which occupies additional space. Therefore, there is a need for multilayer capacitors with improved robustness and performance.

[0008] The methods described in this section are implementable methods, but not necessarily methods that have been previously conceived or implemented. Therefore, unless otherwise stated, no method described in this section should be assumed to be background qualified solely by virtue of its inclusion in this section. Furthermore, no method described in this section should be considered well-known, conventional, or routine simply because it is included in this section. Summary of the Invention

[0009] One aspect of this application relates to a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: Dielectric; A first conductive terminal and a second conductive terminal are separated by the dielectric. Multiple parallel plate internal electrodes, the multiple parallel plate internal electrodes forming a stack of electrode layers embedded in the dielectric; The plurality of parallel plate internal electrodes include a first group of internal electrodes and a second group of internal electrodes. Each group includes a first internal electrode and separate adjacent second internal electrodes, wherein a first gap between the first internal electrodes is offset relative to a second gap between the separate adjacent second internal electrodes in a first direction between the first conductive end and the second conductive end. Wherein, a portion of the first internal electrode overlaps with a portion of the second internal electrode to form a capacitance region in each set of internal electrodes; and A set of at least two third internal electrodes among the plurality of parallel plate internal electrodes, the set of at least two third internal electrodes being located between the first group of internal electrodes and the second group of internal electrodes. The at least two third internal electrodes are stacked adjacent to each other to form a region with negligible capacitance.

[0010] The first internal electrode has a different voltage potential than the second internal electrode, and wherein the at least two third internal electrodes have the same voltage potential as each other.

[0011] The at least two third internal electrodes have the same voltage potential as the first internal electrode.

[0012] Each of the three internal electrodes in the set of at least two third internal electrodes includes a gap that overlaps with the gaps of the other three internal electrodes in the first direction to form overlapping plate segments, with the negligible capacitance region between the overlapping plate segments.

[0013] The gap between the third internal electrode overlaps with the gap between the first internal electrode.

[0014] The interaction between the first and second internal electrodes stacked in adjacent layers produces a piezoelectric effect with corresponding internal strain in the multilayer ceramic capacitor, wherein the stacked third internal electrode reduces the corresponding internal strain.

[0015] The internal electrodes of the plurality of parallel plates are stacked in a second direction perpendicular to the first direction.

[0016] Each of the internal electrodes in the plurality of parallel plates is separated from each other by a dielectric layer.

[0017] At least one of the plurality of parallel plate internal electrodes includes a plate portion that is electrically insulated from each other in the first direction by at least one gap.

[0018] The first group of internal electrodes and the second group of internal electrodes include a plurality of first group internal electrodes and a plurality of second group internal electrodes, wherein the set of at least two third internal electrodes includes a plurality of sets of at least two third internal electrodes, each set of at least two third internal electrodes being located between each corresponding first group of internal electrodes and each corresponding second group of internal electrodes.

[0019] Each group includes a plurality of first internal electrodes, which are stacked with a plurality of second internal electrodes in a second direction perpendicular to the first direction, wherein at least one first internal electrode alternates with at least one second internal electrode in the second direction.

[0020] The multilayer ceramic capacitor further includes multiple sets of internal electrodes, which include: a first set of internal electrodes, a second set of internal electrodes, and at least one set of internal electrodes.

[0021] The at least one set of internal electrodes includes at least one fourth internal electrode and at least one separate, adjacent fifth internal electrode, wherein the at least one fifth internal electrode is stacked with the fourth internal electrode in a second direction perpendicular to the first direction.

[0022] Another aspect of this application relates to a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: Dielectric; A first conductive terminal and a second conductive terminal are separated by the dielectric. A plurality of parallel plate internal electrodes, the plurality of parallel plate internal electrodes forming an electrode layer stack embedded in the dielectric, each of the plurality of parallel plate internal electrodes including a plate portion, the plate portions being electrically insulated from each other by at least one gap; The plurality of parallel plate internal electrodes include a first group of internal electrodes and a second group of internal electrodes, wherein a first gap in the first internal electrode is offset relative to a second gap in a separately adjacent second internal electrode in each group. Wherein, a section of the plate portion of the first internal electrode overlaps with a section of the plate portion of the second internal electrode to form a capacitor region in each set of internal electrodes; and A set of at least two third internal electrodes among the plurality of parallel plate internal electrodes, the set of at least two third internal electrodes being located between the first group of internal electrodes and the second group of internal electrodes. The at least two third internal electrodes are stacked adjacent to each other to form a region with negligible capacitance.

[0023] The first internal electrode has a different polarity than the second internal electrode, and the third internal electrodes have the same polarity as each other.

[0024] The third internal electrode has the same polarity as the first internal electrode.

[0025] Each of the at least two sets of third internal electrodes includes a gap that overlaps with the gaps of the other third internal electrodes to form overlapping plate segments, with the negligible capacitance region between the overlapping plate segments.

[0026] The first internal electrode alternates with the second internal electrode that is directly adjacent to the first group of internal electrodes and the second group of internal electrodes.

[0027] The interaction between the plate portions of the first and second internal electrodes stacked in adjacent layers produces a piezoelectric effect with corresponding internal strain in the multilayer ceramic capacitor, wherein the stacked third internal electrode reduces the corresponding internal strain.

[0028] Another aspect of this application relates to a multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: Dielectric; A first conductive terminal and a second conductive terminal are separated by the dielectric. A first internal electrode of a parallel plate, the first internal electrode of the parallel plate being embedded in a dielectric, wherein at least one first gap in each first internal electrode forms a first plate portion electrically isolated from each other; A second internal electrode of a parallel plate is embedded in the dielectric, wherein at least one second gap in each second internal electrode forms a second plate portion that is electrically isolated from each other; The at least one second gap is offset from the at least one first gap in a first direction extending between the first conductive end and the second conductive end, the second plate portion overlaps with the at least one first gap, and the first plate portion overlaps with the at least one second gap; The first set of electrodes includes a first set of the first internal electrodes and a second set of the second internal electrodes. Each first internal electrode in the first set of the first internal electrodes is separated from each second internal electrode in the second set of the second internal electrodes by a dielectric layer; The second set of electrodes includes a third set of the first internal electrodes and a fourth set of the second internal electrodes. Each first internal electrode in the third set of the first internal electrodes is separated from each second internal electrode in the fourth set of the second internal electrodes by a dielectric layer; and The fifth set of the first internal electrodes separated from each other by the dielectric layer The fifth set of the first internal electrodes is located between the first set of electrodes and the second set of electrodes. Attached Figure Description

[0029] To illustrate how the advantages and features of this disclosure can be obtained, the description of this disclosure is presented with reference to specific embodiments of the disclosure shown in the accompanying drawings. These drawings depict only exemplary embodiments of the disclosure and are therefore not intended to limit its scope. For clarity, the drawings may have been simplified and are not necessarily drawn to scale.

[0030] Figure 1 This is a schematic cross-sectional view of a multilayer ceramic capacitor in the prior art.

[0031] Figure 2 This is a cross-sectional view of a multilayer electrical component including multiple capacitor layers according to a possible embodiment.

[0032] Figure 3 This is a schematic cross-sectional view of a multilayer electrical component including multiple capacitor layers according to a possible embodiment.

[0033] Figure 4 This is a cross-sectional view of a multilayer electrical component including multiple capacitor layers according to a possible embodiment.

[0034] Figure 5 This is a schematic cross-sectional view of a multilayer electrical component including multiple capacitor layers according to a possible embodiment.

[0035] Figure 6 This is a schematic cross-sectional view of a multilayer electrical component including multiple capacitor layers according to a possible embodiment. Detailed Implementation

[0036] This disclosure generally relates to multilayer electronic components, such as capacitors and rheostats, and other components, with improved robustness and performance. Multilayer electronic components typically include a dielectric that separates conductive ends connected to multiple parallel-plate electrodes embedded within the dielectric. Representative implementations are further described herein.

[0037] The composition of dielectric materials is typically selected based on operating temperature range, temperature stability, energy density, loss factor, relative permittivity, and other requirements or specifications of multilayer electrical components. Suitable dielectric materials include ceramics and dense ceramics, as well as other known and future materials. Representative ceramics include barium titanate and additives (such as glass and rare earth materials). Another representative ceramic includes bismuth ferrite, strontium titanate, and additives (such as barium titanate) as well as other elements and compounds. Other representative ceramics may include magnesium titanate, neodymium titanate, strontium titanate, or calcium zirconate, as well as other compounds. Currently, ceramics are favored due to their ability to be formed into powders through sintering during the manufacture of electrical components.

[0038] Electrodes can be formed of noble or base metals. Conductive terminals can be implemented as caps formed on the opposite side or end of the dielectric. Conductive terminals can also comprise alkali or noble metals. Representative examples include electroplated silver, copper, and palladium / silver, as well as other metals and alloys. Conductive terminals can also comprise combinations of metallic and non-metallic materials. Multilayer electrical components (e.g., capacitors, rheostats, etc.) can be configured for surface mounting, with or without leads for through-hole mounting or for some other known or future mounting techniques.

[0039] Overview

[0040] At least some embodiments provide a paired electrode distribution for resistance to piezoelectric cracking. The electrodes are paired in the stacking direction of the MLCC. The paired electrodes are two electrodes with the same polarity, which results in no substantial piezoelectric effect occurring within the ceramic. In one implementation, the paired electrodes are distributed at regular intervals within a regular internal electrode pattern stack.

[0041] Electrode pairs forming negligible capacitance regions can be located anywhere between electrode pairs forming capacitance regions within the dielectric. Additional paired electrodes can also be used at the top and bottom of the MLCC structure to prevent flashover. Vertical gaps (e.g., wider spacing between vertically stacked electrodes in a structure) have a similar effect but are less efficient and less volumetrically efficient compared to electrode pairs forming negligible capacitance regions.

[0042] The embodiments relate to any MLCC and other MLCCs that require pulse testing performance. Testing shows a significant improvement in pulse performance compared to current standard designs, where the paired electrode design exhibits piezoelectric resistance. The embodiments drive capacitances higher than currently permitted by technology, such as those used in safety capacitors. The embodiments also improve reliability in applications experiencing rapid transients.

[0043] According to a possible embodiment, the MLCC includes a dielectric. The MLCC includes a first conductive end and a second conductive end separated by the dielectric. The MLCC includes a plurality of parallel-plate internal electrodes forming a stack of electrode layers embedded in the dielectric. The MLCC includes a first set of internal electrodes and a second set of internal electrodes from the plurality of parallel-plate internal electrodes. Each set includes a first internal electrode and separate, adjacent second internal electrodes. A first gap between the first internal electrodes is offset relative to a second gap between the second internal electrodes in a first direction between the first and second conductive ends. A portion of the first internal electrode overlaps with a portion of the second internal electrode to form a capacitive region in each set of internal electrodes. The MLCC includes a set of at least two third internal electrodes located between the first and second sets of internal electrodes from the plurality of parallel-plate internal electrodes. The at least two third internal electrodes are stacked adjacent to each other and form a negligible capacitive region.

[0044] Vertical gap

[0045] Figure 2 This is a cross-sectional view of a multilayer electrical component 200 (e.g., an MLCC) comprising multiple capacitor layers according to a possible embodiment. Alternating electrodes 202 have overlapping regions 210 that generate capacitance. The capacitor regions 210 generate strain, which can lead to piezoelectric fracturing. Vertical gaps (e.g., gap 220) in the electrode layers reduce this strain.

[0046] Figure 3 This is a schematic cross-sectional view of a multilayer electrical component 300 (e.g., MLCC 200) including multiple capacitor layers according to a possible embodiment. The MLCC 300 includes an assembly of a first internal electrode 302 and a second internal electrode 304, a dielectric layer 306, and a capacitor region RC. The first internal electrode 302 may be a first type 1 internal electrode, for example, having a first voltage potential and / or polarity. The second internal electrode 304 may be a second type 2 internal electrode, for example, having a second voltage potential and / or polarity. The dielectric layer 306 may be a ceramic layer located vertically between the first internal electrode 302 and the second internal electrode 304. The segments of the first internal electrode 302 that overlap with segments of the second internal electrode 304 form the capacitor region RC.

[0047] In particular, when a high-voltage pulse is applied to the MLCC300, the capacitor region RC generates strain. At least one additionally thick dielectric layer 308 (e.g., a vertical gap) between the assembly of the first internal electrode 302 and the second internal electrode 304 prevents localized strain accumulation. Such a vertical gap is not optimally designed to prevent strain accumulation and requires a dielectric layer many times thicker than usual to be effective, which occupies additional space.

[0048] Paired electrodes with multiple plate sections

[0049] Figure 4 This is a cross-sectional view of a multilayer electrical component 400 (e.g., an MLCC) including multiple capacitor layers according to a possible embodiment. The MLCC 400 includes stacked internal electrodes 402, dielectrics 404, and conductive terminals 406 and 408. Multiple sets of internal electrodes 402 overlap to create a capacitor region 410.

[0050] The inclusion of paired internal electrodes 412 throughout the construction reduces the capacitance region 410 in the stacking direction, thereby preventing localized strain accumulation that would otherwise promote piezoelectric fracture failure. The paired internal electrodes 412 are located between the capacitance regions 410. The paired internal electrodes 412 are designed not to generate capacitance.

[0051] Figure 5This is a schematic cross-sectional view of a multilayer electrical component 500 (e.g., MLCC 400) including multiple capacitor layers according to a possible embodiment. The MLCC includes a dielectric 502, conductive terminals (e.g., first conductive terminal 504 and second conductive terminal 506), internal electrodes (e.g., first internal electrode 510, second internal electrode 520, third internal electrode 530, and fourth internal electrode 580), a capacitance region RC, and a negligible capacitance region R-NC. Dielectric layers 570 (e.g., ceramic layers) are located between adjacent electrodes. The conductive terminals (e.g., first conductive terminal 504 and second conductive terminal 506) are external electrodes. The internal electrodes (e.g., first internal electrode 510 and third internal electrode 530) can be internal electrodes of type 1, for example, having a first voltage potential and / or polarity. The internal electrodes (e.g., second internal electrode 520 and fourth internal electrode 580) can be internal electrodes of type 2, for example, having a second voltage potential and / or polarity. By repeating the same type of electrodes, at least one set of the third internal electrode 530 and / or the fourth internal electrode 580 is paired to generate a negligible capacitance region R-NC.

[0052] According to a possible embodiment, the MLCC 500 includes a dielectric 502. The MLCC 500 also includes a first conductive end 504 and a second conductive end 506 separated by the dielectric 502. The MLCC 500 also includes a plurality of parallel-plate internal electrodes (e.g., a first internal electrode 510, a second internal electrode 520, and a third internal electrode 530) that form a stack of electrode layers embedded in the dielectric 502. Each parallel-plate internal electrode includes plate portions 514, 524, which are electrically isolated from each other by at least one gap (e.g., a first gap 512 and a second gap 522).

[0053] The MLCC 500 includes a first set of internal electrodes 542 and a second set of internal electrodes 544, comprising multiple parallel-plate internal electrodes. A first gap 512 in the first internal electrode 510 is offset along a first direction 562 between a first conductive end 504 and a second conductive end 506 relative to a second gap 522 in a separate adjacent second internal electrode 520 in each set (e.g., the first set of internal electrodes 542 and the second set of internal electrodes 544). The multiple parallel-plate internal electrodes (e.g., the first internal electrode 510, the second internal electrode 520, and the third internal electrode 530) form a stack of internal electrodes in a second direction 564 perpendicular to the first direction 562. The first and second directions can also be considered as a first dimension and a second dimension. A segment of the plate portion of the first internal electrode 510 overlaps 560 with a segment of the plate portion of the second internal electrode 520 to form a capacitance region RC in each set of internal electrodes (e.g., the first set of internal electrodes 542 and the second set of internal electrodes 544).

[0054] The MLCC 500 includes a set 546 of at least two third internal electrodes 530 among a plurality of parallel-plate internal electrodes. The set 546 of at least two third internal electrodes 530 is located between a first set of internal electrodes 542 and a second set of internal electrodes 544. The at least two third internal electrodes 530 are stacked adjacent to each other and form a negligible capacitance region R-NC.

[0055] There can be many gaps between each electrode layer. For example, there can be 2, 3, 5, 8, 16, or any other number of gaps in each electrode layer. There can also be many electrode layers.

[0056] Depending on the implementation, the first internal electrode 510 has a different polarity than the second internal electrode 520. The third internal electrode 530 has the same polarity as each other. For example, the first internal electrode 510 has a different voltage potential than the second internal electrode 520, and the third internal electrode 530 has the same voltage potential as each other. In some implementations, the third internal electrode 530 has the same polarity and / or the same voltage potential as the first internal electrode 510.

[0057] According to possible implementations, each of the third internal electrodes 530 in the set 546 includes a gap 532 that overlaps with the gaps 532 of the other third internal electrodes 530 to form overlapping plate segments 534 with a negligible capacitance region R-NC between them.

[0058] Depending on the possible implementation, in the first set of internal electrodes 542 and the second set of internal electrodes 544, the first internal electrode 510 alternates with the immediately adjacent second internal electrode 520. For example, in multiple sets of internal electrodes, a single first internal electrode 510 may alternate with a single second internal electrode 520.

[0059] In a possible embodiment, a gap (e.g., a first gap 512) in at least one upper first internal electrode 510 is offset from a gap (e.g., a first gap 512) in at least one lower first internal electrode 510, and gaps 532 in the upper and lower second internal electrodes 520 are similarly offset to form staggered plate portions.

[0060] Depending on the possible implementation, the interaction between the plate portions of the first internal electrode 510 and the second internal electrode 520 stacked in adjacent layers produces a piezoelectric effect with corresponding internal strain in the MLCC 500. The stacked third internal electrode 530 reduces the corresponding internal strain.

[0061] Depending on the possible implementation, each of the internal electrodes in the plurality of parallel plates is separated from each other by a dielectric layer 570.

[0062] Depending on the possible implementation, the first set of internal electrodes 542 and the second set of internal electrodes 544 are multiple sets of first and second sets of internal electrodes. A set 546 of at least two third internal electrodes is a plurality of sets 546 of at least two third internal electrodes. Each set 546 of at least two third internal electrodes 530 is located between the corresponding first set of internal electrodes 542 and the second set of internal electrodes 544.

[0063] The MLCC 500 may include other sets of paired internal electrodes (e.g., fourth internal electrodes 580). The paired fourth internal electrodes 580 are located between the other sets of first internal electrodes 510 and second internal electrodes 520, forming an additional negligible capacitance region R-NC to reduce internal strain. The paired third internal electrodes 530 may be of the same type as the first internal electrodes 510 (e.g., first type 1), and the paired fourth internal electrodes 580 may be of the same type as the second internal electrodes 520 (e.g., second type 2).

[0064] Paired electrodes with a single plate portion

[0065] Figure 6 This is a schematic cross-sectional view of a multilayer electrical component 600 (e.g., an MLCC) including multiple capacitor layers according to a possible embodiment. The MLCC 600 incorporates features of the MLCC 500, and the features of the MLCC 600 can also be used with the MLCC 500.

[0066] According to a possible embodiment, the MLCC 600 includes a dielectric 602. The MLCC 600 also includes a first conductive end 604 and a second conductive end 606 separated by the dielectric 602. The MLCC 600 further includes a plurality of parallel-plate internal electrodes (e.g., a first internal electrode 610, a second internal electrode 620, and a third internal electrode 630) forming a stack of electrode layers embedded in the dielectric 602.

[0067] The MLCC 600 includes a first group 642 internal electrodes and a second group 644 internal electrodes with multiple parallel-plate internal electrodes. Each group (e.g., the first group 642 and the second group 644) includes a first internal electrode 610 and separate, adjacent second internal electrodes 620. Each of the first group 642 and the second group 644 may include multiple first internal electrodes 610 and multiple second internal electrodes 620.

[0068] The first gap 612 of the first internal electrode 610 is offset relative to the second gap 622 of the separated adjacent second internal electrodes in a first direction 662 between the first conductive end 604 and the second conductive end 606. Gap 612 and 614 may be between at least one of the internal electrodes and conductive ends (e.g., the first conductive end 604 and the second conductive end 606), and / or may be gaps between plate portions of the internal electrodes, as shown in MLCC 500. A portion of the first internal electrode 610 overlaps 660 with a portion of the second internal electrode 620 to form a capacitance region RC in each group (e.g., the first group 642 and the second group 644) of internal electrodes.

[0069] The MLCC 600 includes a set 646 of at least two third internal electrodes 630 located between internal electrodes of a first group 642 and a second group 644 of a plurality of parallel-plate internal electrodes. The at least two third internal electrodes 630 are stacked adjacent to each other and form a negligible capacitance region R-NC.

[0070] Capacitance is defined as the fundamental capacitance used for the operation of a capacitor. Negligible capacitance is defined as the smallest capacitance compared to the operating capacitance of a capacitor, for example, in any range between 5%, 1%, 0.1%, 0.01%, or less than the operating capacitance. For example, the negligible capacitance region can be a region with no substantial capacitance and / or a region with virtually no capacitance, which is practically zero capacitance when compared to the operating capacitance, while considering that absolute zero capacitance may be physically impossible because there may always be tiny stray capacitances.

[0071] Some embodiments are shown in which the gaps and portions of a particular type of electrode directly overlap each other. Embodiments can also be used with staggered electrodes, wherein the gaps and portions of a particular type of electrode are offset relative to each other in a first direction 662. For example, the gaps and portions of the upper inner electrode of type 1 may be offset from the gaps and portions of the lower inner electrode of type 1.

[0072] Depending on the possible implementation, the first internal electrode 610 can be of type 1, having a different voltage potential than the second internal electrode 620 of type 2. The third internal electrode 630 can have the same voltage potential as the first internal electrode 610. The third internal electrode 630 can be of type 1 or type 2. For example, the third internal electrode 630 can have the same voltage potential as the first internal electrode 610.

[0073] According to possible implementations, each third internal electrode 630 may include a gap 632 that overlaps with the gaps 632 of other third internal electrodes 630 in a first direction 662 to form overlapping plate segments having a negligible capacitance region R-NC therebetween. The gaps 632 of the third internal electrodes 630 may overlap with the gaps 612 of the first internal electrodes 610. Alternatively, the gaps of the third internal electrodes may overlap with the gaps 622 of the second internal electrodes 620, or the additional electrodes 680 may be paired, wherein the gaps of the additional electrodes 680 overlap with each other and overlap with the gaps 622 of the second internal electrodes 620.

[0074] Depending on the possible implementation, the interaction between the plate portions of the first internal electrode 610 and the second internal electrode 620 stacked in adjacent layers generates a piezoelectric effect with corresponding internal strain in the MLCC 600. The stacked third internal electrode 630 reduces the corresponding internal strain. For example, the piezoelectric effect can lead to the accumulation of internal strain within the MLCC 600, which can cause the MLCC 600 to crack. The negligible capacitance region R-NC of the paired additional electrodes 680 also reduces the internal strain.

[0075] According to possible implementations, a plurality of parallel-plate internal electrodes (e.g., first internal electrode 610, second internal electrode 620, and third internal electrode 630) form a stack of internal electrodes in a second direction 664 perpendicular to the first direction 662. According to possible implementations, each of the plurality of parallel-plate internal electrodes (e.g., first internal electrode 610, second internal electrode 620, and third internal electrode 630) is separated from each other by a dielectric layer 670. The dielectric layers between all electrodes have the same dimensions in the second direction, for example, substantially the same dimensions. According to possible implementations, at least one of the parallel-plate internal electrodes (e.g., first internal electrode 610, second internal electrode 620, and third internal electrode 630) includes a plate portion electrically isolated from each other by at least one gap in the first direction, such as that shown in MLCC 500.

[0076] In various implementations, MLCC 400 and MLCC 500 are not limited to a specific number of internal electrode groups or sets, or a specific number of internal electrodes in each group or set. For example, a first group of internal electrodes and a second group of internal electrodes may include multiple first group internal electrodes and multiple second group internal electrodes. A set of at least two third internal electrodes may include multiple sets of at least two third internal electrodes. The at least two third internal electrodes in each set may be located between each corresponding first group of internal electrodes and each corresponding second group of internal electrodes. In another example, each group includes multiple first internal electrodes stacked with multiple second internal electrodes, wherein at least one first internal electrode alternates with at least one second internal electrode.

[0077] In another example, the MCLL includes multiple sets of internal electrodes. Each set of internal electrodes includes a first set of internal electrodes, a second set of internal electrodes, and at least one set of internal electrodes. The at least one set of internal electrodes may include at least one fourth internal electrode and at least one separate, adjacent fifth internal electrode, the at least one fifth internal electrode being stacked with the fourth internal electrode in a second direction perpendicular to the first direction.

[0078] Further example embodiments

[0079] According to a first additional exemplary embodiment, the multilayer ceramic capacitor includes: Dielectric; The first conductive terminal and the second conductive terminal, such as the external electrode, are separated by a dielectric. Parallel plate first internal electrodes, embedded in the dielectric, wherein at least one first gap in each first internal electrode forms a first plate portion electrically isolated from each other; A second internal electrode of a parallel plate is embedded in the dielectric, wherein at least one second gap in each second internal electrode forms a second plate portion that is electrically isolated from each other; The at least one second gap is offset from the at least one first gap in a first longitudinal direction extending between the first conductive end and the second conductive end, the second plate portion overlaps with the at least one first gap, and the first plate portion overlaps with the at least one second gap; The first set of electrodes includes a first set of first internal electrodes and a second set of second internal electrodes. Each of the first internal electrodes in the first set of first internal electrodes is separated from each of the second internal electrodes in the second set of second internal electrodes by a dielectric layer; The second set of electrodes includes a third set of the first internal electrodes and a fourth set of the second internal electrodes. Each first internal electrode in the third set of the first internal electrodes is separated from each second internal electrode in the fourth set of the second internal electrodes by a dielectric layer; and The fifth set, such as the set of the third internal electrodes of the first internal electrode, is separated from each other by a dielectric layer. The fifth set of the first internal electrodes is located between the first set of electrodes and the second set of electrodes.

[0080] In possible implementations, in the first and second groups, a specific first internal electrode is separated from a specific second internal electrode by a dielectric layer.

[0081] In the implementation of the multilayer ceramic capacitor of the first additional exemplary embodiment, the first plate portion of the first internal electrode overlaps with at least one second gap, and the second plate portion of the second internal electrode overlaps with at least one first gap in a latitudinal direction perpendicular to the first direction.

[0082] In a first additional exemplary embodiment of the multilayer ceramic capacitor, a segment of the first plate portion overlaps with a segment of the second plate portion in a corresponding first set of electrodes and a second set of electrodes to form a capacitance region. The segments of the first plate portion (overlapping with other segments of the first plate portion in the fifth set) form a negligible capacitance region.

[0083] In an implementation of the multilayer ceramic capacitor of the first additional exemplary embodiment, a fifth set of the first internal electrodes is located between the first set of electrodes and the second set of electrodes in a second direction perpendicular to the first direction, and the fifth set of the first internal electrodes is parallel to each other and separated from each other in the second direction.

[0084] In an implementation of a multilayer ceramic capacitor in a first additional exemplary embodiment, at least one first plate portion includes a floating electrode that is electrically isolated from other first plate portions in a first direction by a first gap on each side of the floating electrode.

[0085] In one implementation, the multilayer ceramic capacitor of the first additional exemplary embodiment further includes: A third set of electrodes, the third set of electrodes including a first internal electrode that alternates with the second internal electrode; A fourth set of electrodes, the fourth set of electrodes comprising a first internal electrode alternating with a parallel second internal electrode; and A sixth set of second internal electrodes, separated from each other by a dielectric layer, is located between the third set of electrodes and the fourth set of electrodes, forming a region with negligible capacitance.

[0086] There is no limit to the number of paired electrodes with negligible capacitance. For example, there can be repeated sets of electrodes with capacitive regions and repeated groups of electrodes with negligible capacitive regions in between. Various numbers of electrodes in groups and sets are possible. Moreover, various patterns of groups and sets are also possible.

[0087] In the implementation of the multilayer ceramic capacitor of the first additional exemplary embodiment, each first internal electrode of the first set of first internal electrodes is adjacent to and parallel to each second internal electrode of the second set of second internal electrodes, and each first internal electrode of the first set of first internal electrodes is separated from each second internal electrode of the second set of second internal electrodes by a single dielectric layer.

[0088] In the implementation of the multilayer ceramic capacitor in the first additional exemplary embodiment, the interaction between the plate portions of the first internal electrode and the second internal electrode produces a piezoelectric effect with corresponding internal strain in the multilayer ceramic capacitor, and the fifth set of the first internal electrode reduces the corresponding internal strain.

[0089] According to a second additional exemplary embodiment, the multilayer ceramic capacitor includes: Dielectric; The first conductive terminal and the second conductive terminal are, for example, external electrodes separated by a dielectric. A first internal electrode of a parallel plate is embedded in a dielectric material, and a first gap in each first internal electrode forms a first plate portion that is electrically isolated from each other. A second internal electrode of a parallel plate is embedded in the dielectric, wherein a second gap in each second internal electrode forms a second plate portion that is electrically isolated from each other; The second gap is offset from the first gap in a first longitudinal direction between the first conductive end and the second conductive end. Wherein, the second plate portion of the second plate portion overlaps with the first gap, and the first plate portion of the first plate portion overlaps with the second gap; A capacitor region, which is located between segments of the second plate portion that overlap with segments of the first plate portion; The first set of internal electrodes includes a first set of the first internal electrodes and a second set of the second internal electrodes stacked in a second direction perpendicular to the first direction; A second set of internal electrodes, comprising a third set of first internal electrodes stacked in the second direction and a fourth set of second internal electrodes; and A set of third internal electrodes of parallel plates, the set of third internal electrodes of parallel plates being embedded in a dielectric, wherein at least one third gap in each third internal electrode forms a third plate portion electrically isolated from each other. At least two third internal electrodes are adjacent to each other and form a region with negligible capacitance. The third set of internal electrodes is located between the first set of internal electrodes and the second set of internal electrodes.

[0090] In a second additional exemplary embodiment of the multilayer ceramic capacitor, the first gap includes a plurality of first gaps in the first internal electrode, and the second gap includes a plurality of second gaps in the second internal electrode.

[0091] The features of the first and second additional exemplary embodiments can be incorporated into any and / or all other disclosed embodiments.

[0092] While this disclosure has been described in conjunction with specific embodiments thereof, it will be apparent to those skilled in the art that many substitutions, modifications, and variations will be readily apparent. For example, various components of the embodiments may be interchanged, added, or substituted in other embodiments. Moreover, not all elements in each figure are necessary for operation of the disclosed embodiments. For example, those skilled in the art will be able to implement and use the teachings of this disclosure by simply employing the elements of the independent claims. Therefore, the embodiments of this disclosure set forth herein are intended to be illustrative and not restrictive. Various changes may be made without departing from the spirit and scope of this disclosure.

[0093] In this document, relational terms such as “first,” “second,” etc., may be used only to distinguish one entity or action from another, without necessarily requiring or implying any actual such relationship or order between these entities or actions. The phrases “at least one,” “at least one selected from,” or “at least one selected from” followed by a list are defined as referring to one, some, or all, but not necessarily all, elements in the list. The terms “comprising,” “including,” “containing,” or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements may include not only those elements but also other elements not expressly listed or inherent to such a process, method, article, or apparatus. Without further limitation, an element beginning with “a,” “an,” etc., does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes that element. Furthermore, the term “another” is defined as at least a second or more. The terms “comprising,” “having,” etc., as used herein, are defined as “including.” Approximation terms, such as “approximate,” “close to,” “substantially,” and / or other related terms, are defined, unless otherwise defined, as a range within + / - 5% of the approximate element, a range within + / - 10% of the approximate element, and / or a range sufficiently close to the approximate element to achieve the expected result. All elements of the disclosed embodiments may be modified using such terminology. Furthermore, the background section is not intended to be considered prior art, but is written as the inventor's own understanding of the context of some embodiments at the time of submission, and includes the inventor's own awareness of any problems with the prior art and / or problems experienced in the inventor's own work.

Claims

1. A multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: Dielectric; A first conductive terminal and a second conductive terminal are separated by the dielectric. Multiple parallel plate internal electrodes, the multiple parallel plate internal electrodes forming a stack of electrode layers embedded in the dielectric; The plurality of parallel plate internal electrodes include a first group of internal electrodes and a second group of internal electrodes. Each group includes a first internal electrode and separate adjacent second internal electrodes, wherein a first gap between the first internal electrodes is offset relative to a second gap between the separate adjacent second internal electrodes in a first direction between the first conductive end and the second conductive end. Wherein, a portion of the first internal electrode overlaps with a portion of the second internal electrode to form a capacitance region in each set of internal electrodes; and A set of at least two third internal electrodes among the plurality of parallel plate internal electrodes, the set of at least two third internal electrodes being located between the first group of internal electrodes and the second group of internal electrodes. The at least two third internal electrodes are stacked adjacent to each other to form a region with negligible capacitance.

2. The multilayer ceramic capacitor according to claim 1, in, The first internal electrode has a different voltage potential than the second internal electrode, and The at least two third internal electrodes have the same voltage potential as each other.

3. The multilayer ceramic capacitor according to claim 2, wherein, The at least two third internal electrodes have the same voltage potential as the first internal electrode.

4. The multilayer ceramic capacitor according to claim 1, in, Each of the three internal electrodes in the set of at least two third internal electrodes includes a gap that overlaps with the gaps of the other three internal electrodes in the first direction to form overlapping plate segments, with the negligible capacitance region between the overlapping plate segments.

5. The multilayer ceramic capacitor according to claim 4, in, The gap between the third internal electrode overlaps with the gap between the first internal electrode.

6. The multilayer ceramic capacitor according to claim 1, in, The interaction between the first and second internal electrodes stacked in adjacent layers generates a piezoelectric effect with corresponding internal strain in the multilayer ceramic capacitor, and The stacked third internal electrode reduces the corresponding internal strain.

7. The multilayer ceramic capacitor according to claim 1, wherein, The internal electrodes of the plurality of parallel plates are stacked in a second direction perpendicular to the first direction.

8. The multilayer ceramic capacitor according to claim 1, wherein, Each of the internal electrodes in the plurality of parallel plates is separated from each other by a dielectric layer.

9. The multilayer ceramic capacitor according to claim 1, wherein, At least one of the plurality of parallel plate internal electrodes includes a plate portion that is electrically insulated from each other in the first direction by at least one gap.

10. The multilayer ceramic capacitor according to claim 1, in, The first group of internal electrodes and the second group of internal electrodes each include a plurality of first group internal electrodes and a plurality of second group internal electrodes, and The set of at least two third internal electrodes includes multiple sets of at least two third internal electrodes, each set of at least two third internal electrodes being located between each corresponding first set of internal electrodes and each corresponding second set of internal electrodes.

11. The multilayer ceramic capacitor according to claim 1, wherein, Each group includes a plurality of first internal electrodes, which are stacked with a plurality of second internal electrodes in a second direction perpendicular to the first direction, wherein at least one first internal electrode alternates with at least one second internal electrode in the second direction.

12. The multilayer ceramic capacitor according to claim 1, wherein the multilayer ceramic capacitor further comprises a plurality of internal electrodes, the plurality of internal electrodes comprising: The first group of internal electrodes, the second group of internal electrodes, and at least one or more internal electrodes.

13. The multilayer ceramic capacitor according to claim 12, wherein, The at least one set of internal electrodes includes at least one fourth internal electrode and at least one separate, adjacent fifth internal electrode, wherein the at least one fifth internal electrode is stacked with the fourth internal electrode in a second direction perpendicular to the first direction.

14. A multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: Dielectric; A first conductive terminal and a second conductive terminal are separated by the dielectric. A plurality of parallel plate internal electrodes, the plurality of parallel plate internal electrodes forming an electrode layer stack embedded in the dielectric, each of the plurality of parallel plate internal electrodes including a plate portion, the plate portions being electrically insulated from each other by at least one gap; The plurality of parallel plate internal electrodes include a first group of internal electrodes and a second group of internal electrodes, wherein a first gap in the first internal electrode is offset relative to a second gap in a separately adjacent second internal electrode in each group. Wherein, a section of the plate portion of the first internal electrode overlaps with a section of the plate portion of the second internal electrode to form a capacitor region in each set of internal electrodes; and A set of at least two third internal electrodes among the plurality of parallel plate internal electrodes, the set of at least two third internal electrodes being located between the first group of internal electrodes and the second group of internal electrodes. The at least two third internal electrodes are stacked adjacent to each other to form a region with negligible capacitance.

15. The multilayer ceramic capacitor according to claim 14, in, The first internal electrode has a different polarity than the second internal electrode, and The third internal electrodes have the same polarity as each other.

16. The multilayer ceramic capacitor according to claim 15, wherein, The third internal electrode has the same polarity as the first internal electrode.

17. The multilayer ceramic capacitor according to claim 14, in, Each of the three internal electrodes in the set of at least two third internal electrodes includes a gap that overlaps with the gaps of the other three internal electrodes to form overlapping plate segments, with the negligible capacitance region between the overlapping plate segments.

18. The multilayer ceramic capacitor according to claim 14, in, The first internal electrode alternates with the second internal electrode that is directly adjacent to the first group of internal electrodes and the second group of internal electrodes.

19. The multilayer ceramic capacitor according to claim 14, in, The interaction between the plate portions of the first and second internal electrodes stacked in adjacent layers generates a piezoelectric effect with corresponding internal strain in the multilayer ceramic capacitor, and The stacked third internal electrode reduces the corresponding internal strain.

20. A multilayer ceramic capacitor, the multilayer ceramic capacitor comprising: Dielectric; A first conductive terminal and a second conductive terminal are separated by the dielectric. A first internal electrode of a parallel plate is embedded in the dielectric, wherein at least one first gap in each first internal electrode forms a first plate portion electrically isolated from each other. A second internal electrode of a parallel plate is embedded in the dielectric, wherein at least one second gap in each second internal electrode forms a second plate portion that is electrically isolated from each other; The at least one second gap is offset from the at least one first gap in a first direction extending between the first conductive end and the second conductive end, the second plate portion overlaps with the at least one first gap, and the first plate portion overlaps with the at least one second gap; The first set of electrodes includes a first set of the first internal electrodes and a second set of the second internal electrodes. Each first internal electrode in the first set of the first internal electrodes is separated from each second internal electrode in the second set of the second internal electrodes by a dielectric layer; The second set of electrodes includes a third set of the first internal electrodes and a fourth set of the second internal electrodes. Each first internal electrode in the third set of the first internal electrodes is separated from each second internal electrode in the fourth set of the second internal electrodes by a dielectric layer; and The fifth set of the first internal electrodes separated from each other by the dielectric layer The fifth set of the first internal electrodes is located between the first set of electrodes and the second set of electrodes.