Multilayer electronic component

Abstract

The present disclosure provides a multilayer electronic component including a main body including a capacitor forming portion including a dielectric layer including a plurality of dielectric grains and an internal electrode alternately disposed with the dielectric layer, and an external electrode disposed on the main body. According to the present disclosure, the occurrence frequency of a plurality of nano-domains in the capacitor forming portion according to the circularity is adjusted to have a maximum value in a range of greater than or equal to 0.85 and less than or equal to 1.00, or the occurrence frequency of a bubble domain having a circularity in a range of greater than or equal to 0.85 and less than or equal to 1.00 is adjusted to be greater than or equal to 0.2, thereby improving the capacitance per unit volume of the multilayer electronic component.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2025-0035372, filed on March 19, 2025, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] This disclosure relates to a multilayer electronic component. Background Technology

[0003] Multilayer ceramic capacitors (MLCCs, a type of multilayer electronic component) are chip capacitors mounted on printed circuit boards of various electronic devices, including display devices such as liquid crystal displays (LCDs and plasma display panels (PDPs), computers, smartphones, and mobile phones), to charge or discharge them.

[0004] Such multilayer ceramic capacitors are used as components in a variety of electronic devices due to their compact size, high capacitance, and ease of installation. As electronic devices such as computers and mobile devices have become smaller and have higher output, the demand for miniaturized and high-capacitance multilayer ceramic capacitors has increased.

[0005] In multilayer ceramic capacitors, forming thin dielectric layers to achieve miniaturization and high capacitance may degrade reliability. To improve reliability, methods using small-sized BaTiO3-based materials to form small dielectric grains can be employed. However, this may negatively reduce the effective capacitance of the multilayer ceramic capacitor.

[0006] Therefore, it is necessary to improve the microstructure of the dielectric layer so that the effective capacitance of the multilayer ceramic capacitor does not decrease even when the dielectric grains included in the dielectric layer are formed in small sizes.

[0007] [Related Technical Documents] [Patent Literature] (Patent Document 1) WO2013-146303A1 Summary of the Invention

[0008] One aspect of this disclosure is to provide a multilayer electronic component with improved capacitance per unit volume.

[0009] Another aspect of this disclosure is to provide a multilayer electronic component, the multilayer electronic component including a dielectric layer having improved dielectric properties by controlling the microstructure of the domain structure of dielectric grains.

[0010] However, the problems to be solved by this disclosure are not limited to those described above, and will be more readily understood when specific exemplary embodiments of this disclosure are described.

[0011] According to one aspect of this disclosure, a multilayer electronic component includes: a body including a capacitor forming portion, the capacitor forming portion including a dielectric layer and an inner electrode alternately disposed with the dielectric layer, the dielectric layer including a plurality of dielectric grains; and an outer electrode disposed on the body, wherein one or more of the plurality of dielectric grains include a plurality of nanodomains with a major axis greater than or equal to 1 nm and less than 100 nm, the plurality of nanodomains including a plurality of bubble domains with a roundness greater than or equal to 0.85 and less than or equal to 1.00, and the plurality of nanodomains in the capacitor forming portion having a maximum value in the range of roundness greater than or equal to 0.85 and less than or equal to 1.00 based on the frequency of occurrence of roundness.

[0012] According to another aspect of this disclosure, a multilayer electronic component includes: a body including a capacitor forming portion, the capacitor forming portion including a dielectric layer and an inner electrode alternately disposed with the dielectric layer, the dielectric layer including a plurality of dielectric grains; and an outer electrode disposed on the body, wherein one or more of the plurality of dielectric grains include a plurality of nanodomains with a major axis greater than or equal to 1 nm and less than 100 nm, wherein the plurality of nanodomains include a plurality of bubble domains with a roundness greater than or equal to 0.85 and less than or equal to 1.00, and the occurrence frequency of the bubble domains in the capacitor forming portion is greater than or equal to 0.2. Attached Figure Description

[0013] The above and other aspects, features and advantages of this disclosure will become clearer from the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a perspective view schematically illustrating a multilayer electronic assembly according to an exemplary embodiment of the present disclosure; Figure 2 This is an exploded perspective view schematically showing the stacked structure of the internal electrodes; Figure 3 It is along Figure 1 A cross-sectional view taken from line I-I'; Figure 4 It is along Figure 1 A cross-sectional view taken from line II-II'; Figure 5 yes Figure 3 A magnified view of region P; Figure 6A , Figure 6B and Figure 6C The dielectric grains comprising nanodomains are schematically shown. Figure 7A These are images of the domain regions measured using an AFM (atomic force microscope) measuring device when an electric field is applied to the dielectric microstructure, based on test number 1. Figure 7B It is using image processing software to Figure 7AThe image obtained after image visualization Figure 7C This is a graph showing the frequency of domain occurrence based on roundness in the dielectric microstructure according to test number 1; and Figure 8A It is an image of the domain region measured using an AFM measuring device when an electric field is applied to the dielectric microstructure, based on test number 2. Figure 8B It is using image processing software to Figure 8A The image obtained after image visualization Figure 8C This is a graph showing the frequency of occurrence of domains based on roundness in the dielectric microstructure according to test number 2. Detailed Implementation

[0014] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the inventive concept can be exemplified in many different forms and should not be construed as limited to the specific exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. In the drawings, the shape and size of elements may be exaggerated for clarity, and the same reference numerals will always be used to denote the same or similar elements.

[0015] To clarify this disclosure, irrelevant details have been omitted throughout the specification, and identical reference numerals denote the same elements. Furthermore, for clarity, the thickness of layers, films, plates, regions, etc., has been exaggerated in the drawings. Additionally, the same reference numerals shown in different drawings denote the same elements. Throughout the specification, unless explicitly stated otherwise, the word "comprising" and variations such as "including" or "containing" will be understood to imply inclusion of the stated elements but not exclusion of any other elements.

[0016] Throughout this specification and claims, parameter range definitions may be combined and / or interchanged. Unless the context otherwise requires, such parameter ranges may include all subranges contained herein. For example, all parameter ranges disclosed herein include endpoints, and said endpoints may be combined independently of each other.

[0017] As used herein, approximate language may be used to modify any quantitative description, which may vary without causing a change in the essential function associated with it. Therefore, values ​​modified by one or more terms (such as “about” and “substantially”) are not limited to the specified exact values.

[0018] In the accompanying drawings, the X direction may refer to a first direction or the thickness direction, the Y direction may refer to a second direction or the length direction, and the Z direction may refer to a third direction or the width direction. The stacking direction of the inner electrodes 121 and 122 with the dielectric layer 111 described herein may be the thickness direction or the width direction.

[0019] Figure 1 This is a perspective view schematically illustrating a multilayer electronic assembly according to an exemplary embodiment of the present disclosure.

[0020] Figure 2 This is an exploded perspective view schematically showing the stacked structure of the internal electrodes.

[0021] Figure 3 It is along Figure 1 The cross-sectional view taken from line I-I'.

[0022] Figure 4 It is along Figure 1 The cross-sectional view taken from line II-II'.

[0023] Figure 5 yes Figure 3 A magnified view of region P.

[0024] Figure 6A , Figure 6B and Figure 6C The dielectric grains comprising nanodomains are schematically shown.

[0025] Figure 7A It is an image of the domain region measured using an AFM measuring device when an electric field is applied to the dielectric microstructure, based on test number 1. Figure 7B It is using image processing software to Figure 7A The image obtained after image visualization Figure 7C This is a graph showing the frequency of occurrence of domains based on roundness in the dielectric microstructure according to test number 1.

[0026] Figure 8A It is an image of the domain region measured using an AFM measuring device when an electric field is applied to the dielectric microstructure, based on test number 2. Figure 8B It is using image processing software to Figure 8A The image obtained after image visualization Figure 8C This is a graph showing the frequency of occurrence of domains based on roundness in the dielectric microstructure according to test number 2.

[0027] In the following text, reference will be made to Figures 1 to 8CThis disclosure provides a detailed description of multilayer electronic components according to exemplary embodiments of the present disclosure, and various variant examples thereof. While multilayer ceramic capacitors are described as examples of multilayer electronic components, the multilayer electronic components of this disclosure can also be various other electronic products utilizing dielectric compositions, such as inductors, piezoelectric devices, varistors, or thermistors.

[0028] According to an example embodiment of this disclosure, a multilayer electronic component 100 may include a body 110 and external electrodes 131 and 132 disposed on the body 110. The body 110 may include a capacitor forming portion Ac. The capacitor forming portion Ac may include a dielectric layer 111 and internal electrodes 121 and 122 alternately disposed with the dielectric layer 111. The dielectric layer 111 may include a plurality of dielectric grains 10. At least one of the plurality of dielectric grains 10 may include a plurality of nanodomains LD and BD. The plurality of nanodomains LD and BD may have a major axis greater than or equal to 1 nm and less than 100 nm. The plurality of nanodomains LD and BD may include a plurality of bubble domains BD with a roundness greater than or equal to 0.85 and less than or equal to 1.00. The occurrence frequency of the plurality of nanodomains LD and BD in the capacitor forming portion Ac according to roundness may have a maximum value in the range of roundness greater than or equal to 0.85 and less than or equal to 1.00.

[0029] According to an example embodiment of this disclosure, a multilayer electronic component 100 may include a body 110 and external electrodes 131 and 132 disposed on the body 110. The body 110 may include a capacitor forming portion Ac. The capacitor forming portion Ac may include a dielectric layer 111 and internal electrodes 121 and 122 alternately disposed with the dielectric layer 111. The dielectric layer 111 may include a plurality of dielectric grains 10. At least one of the plurality of dielectric grains 10 may include a plurality of nanodomains LD and BD with a major diameter greater than or equal to 1 nm and less than 100 nm. The plurality of nanodomains LD and BD may include a plurality of bubble domains BD with a roundness greater than or equal to 0.85 and less than or equal to 1.00. The occurrence frequency of bubble domains BD in the capacitor forming portion Ac may be greater than or equal to 0.2.

[0030] The body 110 may have alternating stacked dielectric layers 111 and internal electrodes 121 and 122.

[0031] More specifically, the body 110 may include a capacitor forming portion Ac disposed within the body 110 and forming a capacitor by including a first inner electrode 121 and a second inner electrode 122 alternately arranged to face each other and a dielectric layer 111 disposed between the first inner electrode 121 and the second inner electrode 122.

[0032] Although there are no specific restrictions on the exact shape of the main body 110, however... Figure 1As shown, the main body 110 may be formed in a hexahedral shape or a shape similar to a hexahedral shape. Due to the shrinkage of the ceramic particles included in the main body 110 during the sintering process, the main body 110 may not have a completely straight hexahedral shape, but may have a substantially hexahedral shape.

[0033] The main body 110 may have a first surface 1 and a second surface 2 opposite to each other in a first direction, a third surface 3 and a fourth surface 4 connected to the first surface 1 and the second surface 2 and opposite to each other in a second direction, and a fifth surface 5 and a sixth surface 6 connected to the first surface 1, the second surface 2, the third surface 3 and the fourth surface 4 and opposite to each other in a third direction.

[0034] The plurality of dielectric layers 111 forming the main body 110 are in a sintered state, and adjacent dielectric layers 111 may be integrated such that it is difficult to identify the boundary between adjacent dielectric layers 111 without a scanning electron microscope (SEM).

[0035] The raw material for forming the dielectric layers 111 is not limited as long as sufficient capacitance can be obtained therewith. Generally, perovskite (ABO3)-based materials may be used, such as barium titanate-based materials, lead composite perovskite-based materials or strontium titanate-based materials. The barium titanate-based material may include BaTiO3-based ceramic particles. Examples of BaTiO3-based ceramic particles include BaTiO3 or (Ba 1-x Ca x )TiO3 (0<x<1), Ba(Ti 1-y Ca y )O3 (0<y<1), (Ba 1- x Ca x )(Ti 1-y Zr y )O3 (0<x<1, 0<y<1) or Ba(Ti 1-y Zr y )O3 (0<y<1). In addition, the raw material for forming the dielectric layers 111 may include particles of barium titanate (BaTiO3) or the like, and for the purpose of the present disclosure, various ceramic additives (organic solvents, binders, dispersants, etc.) may be added to the particles of barium titanate (BaTiO3) or the like.

[0036] Furthermore, since the dielectric layer 111 can be formed using a dielectric material such as barium titanate (BaTiO3), the dielectric layer 111 can include dielectric microstructures after sintering. The dielectric microstructures may include a plurality of dielectric grains 10, dielectric grain boundaries disposed between adjacent dielectric grains 10, and dielectric triple junctions disposed at the points where three or more dielectric grains 10 intersect, and each of the dielectric grains 10, dielectric grain boundaries, and dielectric triple junctions may be provided in multiples.

[0037] In this disclosure, "domain region" may refer to a specific region having the same polarization direction, and "domain size" may refer to the major axis passing through the center of the domain region as observed using a domain (polarization) measurement device.

[0038] Domain regions can be observed using the following measurement devices. These devices may be, but are not limited to, measurement equipment or modules capable of observing domain regions, such as atomic force microscopy (AFM), piezoelectric response force microscopy (PFM), scanning electron microscopy (SEM), transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), or polarization microscopy (PM).

[0039] Typically, to improve the reliability of multilayer electronic components, the size of the dielectric grains can be reduced by using smaller BaTiO3-based materials. However, this may decrease the effective capacitance of the multilayer electronic component.

[0040] Furthermore, Patent Document 1 introduces dielectric materials comprising nanodomains and describes a dielectric layer that exhibits a high relative permittivity even at high temperatures by adjusting the major axis of the nanodomains. However, Patent Document 1 does not describe how to alter the dielectric properties by adjusting a specific shape (such as the roundness of the nanodomains) or by adjusting the frequency of occurrence of very round nanodomains.

[0041] Additionally, at least one of the plurality of dielectric grains 10 included in the dielectric layer 111 comprises a plurality of nanodomains LD and BD with a major diameter greater than or equal to 1 nm and less than 100 nm, and the plurality of nanodomains LD and BD may include a plurality of bubble domains BD with a roundness greater than or equal to 0.85 and less than or equal to 1.00. The occurrence frequency of the plurality of nanodomains LD and BD in the capacitor forming portion Ac according to roundness may have a maximum value in the range of roundness greater than or equal to 0.85 and less than or equal to 1.00.

[0042] According to exemplary embodiments of this disclosure, bubble domains (BD) with a roundness greater than or equal to 0.85 and less than or equal to 1.00 have a higher piezoelectric coefficient d compared to nanodomains (labyrinth domains LD) with a roundness less than 0.85. 33 piezoelectric coefficient d 33This indicates the degree of polarization induced in the same direction when pressure is applied in a direction perpendicular to the piezoelectric material. Therefore, materials with a roundness greater than or equal to 0.85 and less than or equal to 1.00 have a high piezoelectric coefficient d. 33 The dielectric properties of bubble domains (BD) can be considered superior to those of nanodomains (LD) with a roundness of less than 0.85.

[0043] However, if the nanodomains LD and BD included in the dielectric layer 111 consist only of bubble domains BD with a roundness greater than or equal to 0.85 and less than or equal to 1.00, the capacitance per unit volume of the multilayer electronic component 100 may not be significantly improved.

[0044] Therefore, in the exemplary embodiments of this disclosure, the occurrence frequency of multiple nanodomains BD and LD in the capacitor forming section Ac is adjusted according to their roundness to have a maximum value in the range of roundness greater than or equal to 0.85 and less than or equal to 1.00, or the occurrence frequency of bubble domains BD with roundness greater than or equal to 0.85 and less than or equal to 1.00 is adjusted to greater than or equal to 0.2, thereby significantly improving the capacitance per unit volume of the multilayer electronic component 100. Therefore, even when nanodomains LD with roundness less than 0.85 are present in the dielectric layer 111, the capacitance per unit volume of the multilayer electronic component 100 can be improved by the excellent dielectric properties of the bubble domains BD.

[0045] In this disclosure, the “occurrence frequency” of nanodomains LD and BD based on roundness can refer to the relative frequency representing the proportion of individuals with a specific roundness value relative to the total number of individuals.

[0046] Reference Figure 5 The dielectric layer 111 may include grain boundaries between dielectric grains 10. Furthermore, refer to... Figures 6A to 6C The dielectric grains 10 included in the dielectric layer 111 may include one or more of dielectric grains 11, 12, and 13, each of which includes one or more of labyrinth domains (LD) and bubble domains (BD). In this disclosure, when the dielectric grains 10 are observed using an atomic force microscope (AFM) by applying a specific voltage at a specific frequency, the observed “nanodomains LD and BD” can be regions within the dielectric grains 10 that are set along a specific polarization direction. Among the multiple domains, domain regions with a major axis greater than or equal to 1 nm and less than 100 nm can be considered nanodomains LD and BD. Furthermore, the nanodomains LD and BD of this disclosure can be classified as labyrinth domains LD and bubble domains BD based on roundness. Specifically, according to an example embodiment of this disclosure, bubble domains BD can refer to nanodomains with a roundness greater than or equal to 0.85 and less than or equal to 1.00, and labyrinth domains can refer to nanodomains with a roundness greater than 0 and less than 0.85.

[0047] Furthermore, the labyrinth domains LD and bubble domains BD of this disclosure can refer to specific regions in the dielectric material forming the dielectric layer 111 that have the same polarization direction. Therefore, each of the labyrinth domains LD and bubble domains BD of this disclosure can include BaTiO3-based material as a main component. Here, including BaTiO3-based material as a "main component" can mean that the mole fraction of BaTiO3-based material included in each domain is greater than or equal to 0.5, but is not limited thereto.

[0048] The frequency of occurrence of multiple nanodomains BD and LD in the capacitor forming section Ac of this disclosure, according to roundness, can be measured by applying a 1V driving amplitude to a 1μm × 1μm region at the center of the capacitor forming section Ac using the DART transverse PFM mode of an atomic force microscope (AFM) with an Asyelec.01-R2 cantilever. The capacitor forming section Ac is a capacitor forming section in the first and second directions, polished to the center of the multilayer electronic assembly 100 in the third direction. The region where the nanodomains are formed can be measured in the transverse PFM mode at a frequency of 650kHz in the direction parallel to the inner electrodes 121 and 122. In PFM mode, the distribution of domains and domain walls in the sample can be examined using amplitude information, and information about the polarization direction can be examined using phase information. Using an image processing program, the major axis, perimeter, and area of ​​each nanodomain can be measured, and the frequency of occurrence of nanodomains LD and BD according to roundness can be calculated. Figure 7C and Figure 8C As shown, when the roundness of the horizontal axis is divided into 18 roundness segments with intervals of 0.05 from 0.1 to 1.0, the relative frequency (occurrence frequency) of nanodomains within the corresponding roundness segment range can be represented on the vertical axis. "The occurrence frequency of multiple nanodomains in the capacitor forming section according to roundness has a maximum value in the range where roundness is greater than or equal to 0.85 and less than or equal to 1.00" can be expressed as follows: Among the aforementioned 18 roundness segments, the roundness segment corresponding to the highest number of nanodomains is in the roundness segment where roundness is greater than or equal to 0.85 and less than or equal to 1.00. For example, as... Figure 7C and Figure 8C As shown, the nanodomains exhibit the highest frequency of occurrence within a roundness range of 0.85 to 0.9, meaning that the number of nanodomains is greatest in this roundness range. Furthermore, the roundness of the nanodomains LD and BD of this disclosure can be obtained using the following Equation 1: [Equation 1] Roundness = Furthermore, there are no particular limitations on the methods used to control the occurrence frequency of nanodomains LD and BD according to roundness in this disclosure. However, the occurrence frequency of nanodomains LD and BD according to roundness can be adjusted when samples having electrode layers applied to the host and coatings are subjected to different heat treatment temperatures. Specifically, when heat treatment is performed at a low temperature of less than or equal to 160°C for 1 hour, the occurrence frequency of labyrinth domains LD with a roundness of less than 0.85 may increase, and when heat treatment is performed at a high temperature of greater than or equal to 300°C for 1 hour, the occurrence frequency of bubble domains BD with a roundness of greater than or equal to 0.85 may increase.

[0049] The occurrence frequency of bubble domains BD in the capacitor forming section Ac exceeding the characteristic value may help improve the dielectric properties of dielectric layer 111 and increase the capacitance per unit volume of multilayer electronic component 100.

[0050] Specifically, in the example embodiment, the occurrence frequency of bubble domains BD in the capacitor forming part Ac can be greater than or equal to 0.2. Therefore, even when labyrinth domains LD with a roundness of less than 0.85 exist in the dielectric layer 111, the excellent dielectric properties of the bubble domains BD can further improve the capacitance per unit volume of the multilayer electronic component 100.

[0051] Furthermore, in the example embodiment, when the frequency of occurrence of bubble domains BD in the capacitor forming section Ac is greater than or equal to 0.24, compared to when the frequency of occurrence of bubble domains BD in the capacitor forming section Ac is less than 0.20, the capacitance per unit volume can be increased by 4.7% or more.

[0052] Furthermore, even if the occurrence frequency of multiple nanodomains LD and BD in the capacitor forming section Ac does not have a maximum value in the range of roundness from 0.85 to 1.00, if the occurrence frequency of bubble domains BD is greater than or equal to 0.2, the capacitance per unit volume of the multilayer electronic component 100 can be increased to a certain extent, and this effect can be further enhanced when the occurrence frequency of bubble domains BD in the capacitor forming section Ac is greater than or equal to 0.24.

[0053] The dielectric layer 111 may include a plurality of dielectric grains 10. In an example embodiment, the average size of the plurality of dielectric grains 10 may be in the range of 200 nm to 400 nm. Therefore, by adjusting the occurrence frequency of the plurality of nanodomains BD and LD in the capacitor forming portion Ac according to roundness to have a maximum value in the range of roundness from 0.85 to 1.00, the formation of nanodomains LD and BD within the dielectric grains 10 can be promoted, and the effect of increasing the capacitance per unit volume of the multilayer electronic component 100 can be enhanced.

[0054] The average size of the plurality of dielectric grains 10 included in the dielectric layer 111 can refer to the average diameter of the plurality of dielectric grains 10 observed in the corresponding region when a cross-section of the body 110 in the first and second directions at the center of the third direction is observed using a scanning electron microscope (SEM) or an atomic force microscope (AFM). Here, the diameter of the dielectric grain 10 can correspond to the diameter calculated using an image processing program. For example, the diameter of a dielectric grain 10 can be the average of the major and minor axes passing through the center of a single dielectric grain 10. After obtaining the diameter of each dielectric grain 10 in this way, the diameters of the plurality of dielectric grains 10 can be averaged to obtain the average diameter of the plurality of dielectric grains 10, and this average diameter can be referred to as the average diameter of the plurality of dielectric grains 10.

[0055] The thickness td of dielectric layer 111 is not specifically limited. For example, the average thickness td of one or more of the plurality of dielectric layers 111 may be less than or equal to 4 μm.

[0056] However, in order to promote the miniaturization and high capacitance of the multilayer electronic component 100, the thickness of the dielectric layer 111 can be less than or equal to 0.6 μm, more preferably less than or equal to 0.4 μm.

[0057] Here, the thickness td of the dielectric layer 111 can refer to the thickness td of the dielectric layer 111 disposed between the first inner electrode 121 and the second inner electrode 122.

[0058] Additionally, the thickness td of dielectric layer 111 can refer to the dimension of dielectric layer 111 in the first direction. Furthermore, the thickness td of dielectric layer 111 can refer to the average thickness td of dielectric layer 111, and can also refer to the average dimension of dielectric layer 111 in the first direction.

[0059] The average dimension in the first direction of the dielectric layer 111 can be measured by scanning images obtained using a scanning electron microscope (SEM) at 10,000x magnification of cross sections in the first and second directions of the body 110. More specifically, the average dimension in the first direction of a dielectric layer 111 can refer to the average value calculated by measuring the dimension in the first direction of a single dielectric layer 111 at five or more equally spaced points in the second direction in the scanning image. Five or more equally spaced points can be specified in the capacitance forming section Ac. Furthermore, the average dimension in the first direction of the dielectric layer 111 can be further generalized by extending the average value measurement to five or more dielectric layers 111 and measuring the average value.

[0060] Reference Figure 2 The inner electrodes 121 and 122 can be stacked alternately with the dielectric layer 111.

[0061] The inner electrodes 121 and 122 may include a first inner electrode 121 and a second inner electrode 122. The first inner electrode 121 and the second inner electrode 122 are alternately arranged to face each other, and a dielectric layer 111 is disposed between the first inner electrode 121 and the second inner electrode 122, and the first inner electrode 121 and the second inner electrode 122 may be exposed on the third surface 3 and the fourth surface 4 of the body 110, respectively.

[0062] More specifically, the first inner electrode 121 may be spaced apart from the fourth surface 4 and exposed through the third surface 3, and the second inner electrode 122 may be spaced apart from the third surface 3 and exposed through the fourth surface 4. The first outer electrode 131 may be disposed on the third surface 3 of the body 110 and connected to the first inner electrode 121. The second outer electrode 132 may be disposed on the fourth surface 4 of the body 110 and connected to the second inner electrode 122.

[0063] In other words, referencing Figure 3 The first inner electrode 121 can be connected to the first outer electrode 131 but not to the second outer electrode 132, and the second inner electrode 122 can be connected to the second outer electrode 132 but not to the first outer electrode 131. In this case, the first inner electrode 121 and the second inner electrode 122 can be electrically isolated from each other by a dielectric layer 111 disposed between them.

[0064] Alternatively, the main body 110 can be formed by alternately stacking ceramic green sheets printed with conductive paste for the first internal electrode 121 and ceramic green sheets printed with conductive paste for the second internal electrode 122, and then sintering the ceramic green sheets.

[0065] There are no particular limitations on the materials used to form the internal electrodes 121 and 122, and any material with excellent conductivity can be used. For example, the internal electrodes 121 and 122 may include one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof.

[0066] Alternatively, the internal electrodes 121 and 122 can be formed by printing a conductive paste for the internal electrodes, including one or more of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof, onto a ceramic green sheet. Screen printing or gravure printing can be used to print the conductive paste for the internal electrodes, but this disclosure is not limited thereto.

[0067] In addition, the thickness te of the inner electrodes 121 and 122 does not need to be particularly limited.

[0068] However, in order to promote the miniaturization and high capacitance of multilayer electronic components, the thickness of the internal electrodes 121 and 122 can be less than or equal to 0.6 μm, more preferably less than or equal to 0.4 μm.

[0069] Here, the thickness te of the inner electrodes 121 and 122 can refer to the first-direction dimension of the inner electrodes 121 and 122. Furthermore, the thickness te of the inner electrodes 121 and 122 can refer to the average thickness te of the inner electrodes 121 and 122, and can also refer to the average first-direction dimension of the inner electrodes 121 and 122.

[0070] The average size of the inner electrodes 121 and 122 in the first direction can be measured by scanning images obtained using a scanning electron microscope (SEM) at 10,000x magnification of cross sections of the body 110 in the first and second directions. More specifically, the average size of an inner electrode in the first direction can be calculated by averaging the size of an inner electrode in the first direction at five or more equally spaced points in the second direction of the scanning image. Five or more equally spaced points can be specified in the capacitor forming section Ac. Furthermore, the average size of the inner electrodes 121 and 122 in the first direction can be more generalized by extending the average measurement to five or more inner electrodes 121 and 122.

[0071] Additionally, refer to Figure 3 The main body 110 may include cover portions 112 and 113 disposed on two surfaces of the capacitor forming portion Ac in a first direction.

[0072] Specifically, the main body 110 may include a first covering portion disposed on one surface of the capacitor forming portion Ac in the first direction and a second covering portion disposed on another surface of the capacitor forming portion Ac in the first direction. More specifically, the main body 110 may include an upper covering portion 112 disposed above the capacitor forming portion Ac in the first direction and a lower covering portion 113 disposed below the capacitor forming portion Ac in the first direction.

[0073] The upper cover portion 112 and the lower cover portion 113 can be formed by stacking one or two or more dielectric layers on the upper and lower surfaces of the capacitor forming portion Ac in the first direction, respectively, and can fundamentally prevent the inner electrodes 121 and 122 from being damaged due to physical stress and / or chemical stress.

[0074] The upper cover 112 and the lower cover 113 do not include the inner electrodes 121 and 122, and may include the same material as the dielectric layer 111. That is, the upper cover 112 and the lower cover 113 may include ceramic materials, such as barium titanate (BaTiO3) based ceramic materials.

[0075] In addition, the thickness tc of the covering parts 112 and 113 is not specifically limited.

[0076] However, in order to more easily achieve miniaturization and high capacitance of multilayer electronic components, the thickness tc of the covers 112 and 113 can be less than or equal to 100 μm, preferably less than or equal to 30 μm, and more preferably less than or equal to 20 μm for ultra-small products.

[0077] Here, the thickness tc of the covering portions 112 and 113 may refer to the dimensions of the covering portions 112 and 113 in the first direction. Furthermore, the thickness tc of the covering portions 112 and 113 may refer to the average thickness tc of the covering portions 112 and 113, and may also refer to the average dimensions of the covering portions 112 and 113 in the first direction.

[0078] The average dimensions of the covers 112 and 113 in the first direction can be measured by scanning images obtained by scanning the first and second direction sections of the body 110 at 10,000x magnification using a scanning electron microscope (SEM). More specifically, the average dimension can be calculated by measuring the dimensions of a cover at 30 equally spaced points in the second direction in the scanning image.

[0079] Furthermore, the average dimension of the cover portion measured using the aforementioned method in the first direction can be substantially the same as the average dimension of the cover portion in the first direction in the first and third direction sections of the main body 110.

[0080] Additionally, refer to Figure 4 Edge portions 114 and 115 may be provided on two surfaces of the body 110 in the third direction.

[0081] More specifically, edge portions 114 and 115 may include a first edge portion 114 disposed on one surface of the capacitor forming portion Ac in the third-direction orientation and a second edge portion 115 disposed on the other surface of the capacitor forming portion Ac in the third-direction orientation. In other words, edge portions 114 and 115 may be disposed on both surfaces of the capacitor forming portion Ac in the third-direction orientation.

[0082] like Figure 4 As shown, the edges 114 and 115 may refer to the regions between the two ends of the first inner electrode 121 and the second inner electrode 122 in the third direction and the outer surface of the body 110, based on the first direction and the third direction cross section of the body 110.

[0083] Edges 114 and 115 are essentially used to prevent damage to the inner electrodes 121 and 122 due to physical and / or chemical stress.

[0084] Edges 114 and 115 can be formed by applying conductive paste to areas of the ceramic green sheet other than the areas where edges 114 and 115 will be formed to form internal electrodes 121 and 122. To suppress step differences caused by internal electrodes 121 and 122, edges 114 and 115 can be formed as follows: after stacking ceramic green sheets on which internal electrode patterns are formed to form a ceramic stack, the ceramic stack can be cut to expose the internal electrode patterns on the two third-direction surfaces of the capacitor forming portion Ac. Then, a dielectric layer or two or more dielectric layers can be stacked and formed on the two third-direction surfaces of the capacitor forming portion Ac.

[0085] The first edge portion 114 and the second edge portion 115 do not include the inner electrodes 121 and 122, and may include the same material as the dielectric layer 111. That is, the first edge portion 114 and the second edge portion 115 may include a ceramic material, such as a barium titanate (BaTiO3) based ceramic material.

[0086] In addition, the width wm of the first edge portion 114 and the second edge portion 115 is not specifically limited.

[0087] However, in order to promote the miniaturization and high capacitance of the multilayer electronic component 100, the width wm of the first edge portion 114 and the second edge portion 115 can be less than or equal to 100 μm, preferably less than or equal to 30 μm, and more preferably less than or equal to 20 μm for ultra-small products.

[0088] Here, the width wm of edge portions 114 and 115 may refer to the dimension of each of edge portions 114 and 115 in the third direction. Furthermore, the width wm of edge portions 114 and 115 may refer to the average width wm of edge portions 114 and 115, and may refer to the average dimension of edge portions 114 and 115 in the third direction.

[0089] The average dimensions of the edges 114 and 115 in the third direction can be measured by scanning images obtained using a scanning electron microscope (SEM) at 10,000x magnification of the cross-sections of the body 110 in the first and third directions. More specifically, the average dimensions of the edges 114 and 115 in the third direction can be defined as the average value calculated by measuring the third-direction dimensions of an edge at 10 equally spaced points in the first direction in the scanning image.

[0090] In the exemplary embodiments of this disclosure, the multilayer electronic assembly 100 is described as having a structure including two external electrodes 131 and 132. However, the number and shape of the external electrodes 131 and 132 may vary depending on the shape of the internal electrodes 121 and 122 or for other purposes.

[0091] Reference Figure 1External electrodes 131 and 132 can be disposed on the main body 110.

[0092] External electrodes 131 and 132 may be disposed on the main body 110 and connected to internal electrodes 121 and 122.

[0093] More specifically, the external electrodes 131 and 132 may be disposed on the third surface 3 and the fourth surface 4 of the main body 110, respectively, and may include a first external electrode 131 and a second external electrode 132 connected to the first internal electrode 121 and the second internal electrode 122, respectively. That is, the first external electrode 131 may be disposed on the third surface 3 of the main body 110 and connected to the first internal electrode 121, and the second external electrode 132 may be disposed on the fourth surface 4 of the main body 110 and connected to the second internal electrode 122.

[0094] Furthermore, the external electrodes 131 and 132 may be configured to extend to a portion of the first surface 1 and a portion of the second surface 2 of the body 110, and / or may be configured to extend to a portion of the fifth surface 5 and a portion of the sixth surface 6 of the body 110. For example, the first external electrode 131 may be disposed on a portion of the first surface 1, a portion of the second surface 2, a portion of the fifth surface 5 and a portion of the sixth surface 6 of the body 110, as well as on the third surface 3 of the body 110. The second external electrode 132 may be disposed on a portion of the first surface 1, a portion of the second surface 2, a portion of the fifth surface 5 and a portion of the sixth surface 6 of the body 110, as well as on the third surface 3 of the body 110.

[0095] The external electrodes 131 and 132 can be formed from any conductive material, such as metal. The specific material can be determined based on electrical properties, structural stability, and other factors. Furthermore, the external electrodes can have a multilayer structure.

[0096] For example, the external electrodes 131 and 132 may respectively include electrode layers 131a and 132a disposed on the main body 110 and plating layers 131b and 132b disposed on the electrode layers 131a and 132a.

[0097] More specifically, electrode layers 131a and 132a may be sintered electrodes comprising conductive metal and glass or resin-based electrodes comprising conductive metal and resin.

[0098] Furthermore, electrode layers 131a and 132a can be formed in the form of sintered electrodes and resin-based electrodes sequentially formed on the body 110.

[0099] Furthermore, electrode layers 131a and 132a can be formed by transferring a sheet including a conductive metal onto the body 110 or by transferring a sheet including a conductive metal onto a sintered electrode.

[0100] There are no particular limitations on the conductive metals used in electrode layers 131a and 132a, as long as they can be electrically connected to the inner electrodes 121 and 122 to form a capacitor. For example, the conductive metal may include one or more selected from the group consisting of nickel (Ni), copper (Cu), palladium (Pd), silver (Ag), gold (Au), platinum (Pt), tin (Sn), tungsten (W), titanium (Ti), and alloys thereof. Electrode layers 131a and 132a may be formed by coating a conductive paste (prepared by adding glass frit to conductive metal particles) and then sintering the conductive paste.

[0101] Coatings 131b and 132b improve mounting characteristics.

[0102] There are no particular restrictions on the type of plating layers 131b and 132b, and they can be plating layers 131b and 132b, which are both single layers (including one or more of nickel (Ni), tin (Sn), silver (Ag), palladium (Pd) and their alloys), or they can be formed as multiple layers.

[0103] In a specific example, plating layers 131b and 132b can be nickel plating layers or tin plating layers. Nickel plating layers and tin plating layers can be formed sequentially on electrode layers 131a and 132a, or tin plating layers, nickel plating layers, and tin plating layers can be formed sequentially on electrode layers 131a and 132a. Furthermore, plating layers 131b and 132b may include multiple nickel plating layers and / or multiple tin plating layers.

[0104] The dimensions of the multilayer electronic component 100 are not particularly limited.

[0105] However, in order to achieve both miniaturization and high capacitance, the thickness of the dielectric layer and the internal electrode should be reduced to increase the number of layers. Therefore, the effects of this disclosure may be more pronounced in multilayer electronic components 100 with dimensions of 1005 (length × width: 1.0 mm × 0.5 mm, with errors in length and width within ±5%), 0603 (length × width: 0.6 mm × 0.3 mm, with errors in length and width within ±5%), or smaller.

[0106] The present disclosure will be described in more detail below with reference to experimental examples. However, these examples are intended to facilitate a more concrete understanding of the present disclosure and are not intended to limit its scope.

[0107] (Experimental Example) [Table 1] shows a comparison of the capacitance between multilayer electronic component samples based on the frequency of occurrence of bubble domains (BD) with a roundness greater than or equal to 0.85 and less than or equal to 1.00.

[0108] Figure 7A It is an image of the domain region measured using an AFM measuring device when an electric field is applied to the dielectric microstructure, based on test number 1. Figure 7BIt is using image processing software to Figure 7A The image obtained after image visualization Figure 7C This is a graph showing the frequency of occurrence of domains based on roundness in the dielectric microstructure according to test number 1.

[0109] Figure 8A It is an image of the domain region measured using an AFM measuring device when an electric field is applied to the dielectric microstructure, based on test number 2. Figure 8B It is using image processing software to Figure 8A The image obtained after image visualization Figure 8C This is a graph showing the frequency of occurrence of domains based on roundness in the dielectric microstructure according to test number 2.

[0110] The frequency of nanodomain formation was measured using an atomic force microscope (AFM) in DART transverse PFM mode. A driving amplitude of 1V was applied to a 1μm × 1μm region at the center of the capacitor-forming section using an Asyelec.01-R2 cantilever. The capacitor-forming section was a section polished to the third-party direction in the first and second direction cross-sections at the center of the multilayer electronic assembly 100 in the third-party direction. The region with formed nanodomains was measured in transverse PFM mode at a frequency of 650kHz in a direction parallel to the inner electrodes 121 and 122. In PFM mode, amplitude information was used to examine the distribution of domains and domain walls in the sample, and phase information was used to examine the polarization direction. Using an image processing program, the major axis, perimeter, and area of ​​each nanodomain were measured, and the frequency of occurrence of nanodomains LD and BD based on roundness was calculated. The average value for one sample was calculated and presented in [Table 1].

[0111] The effective capacitance of the multilayer electronic components for each test number was calculated from the average capacitance measured at 1 kHz, 1.0 V and 25 °C, and is presented in [Table 1].

[0112] [Table 1]

[0113] The following samples were manufactured.

[0114] First, prepare the ceramic powder used to form the dielectric layer. The ceramic powder used is BaTiO3-based ceramic powder.

[0115] Next, the prepared ceramic powder is dried and ground, then mixed with an organic solvent (such as ethanol) and a dispersant to prepare a slurry, which is then ground for 1 to 30 hours. A binder (such as polyvinyl butyral) is then added to the slurry and ground further for 1 to 15 hours. The prepared slurry is coated onto a carrier film and dried to produce a ceramic green sheet.

[0116] Next, a conductive paste for the internal electrode, including metal powder, binder, organic solvent, etc., is screen-printed onto a ceramic green sheet to a predetermined thickness to form an internal electrode pattern. Then, the ceramic green sheet with the internal electrode pattern printed on it is peeled off from the carrier film, and a predetermined number of ceramic green sheets with the internal electrode pattern printed on them are stacked and pressed together to form a ceramic stack.

[0117] The ceramic stack is then cut into predetermined sheet sizes, and the cut sheets are sintered to form the body. For example, sintering is performed for 2 hours at a temperature of 1000°C to 1400°C in an atmosphere of 1.0% H2 / 99.0% N2 to 3.5% H2 / 96.5% N2 (which may also contain H2O, i.e., H2O / H2 / N2).

[0118] Subsequently, the main body is immersed in a conductive paste for the external electrode, which includes metal powder, glass frit, binder and organic solvent. Then, the conductive paste for the external electrode is sintered at a temperature of 500°C to 900°C to form a sintered electrode layer.

[0119] Subsequently, electroplating is performed to form a coating.

[0120] Individual heat treatments were performed on samples of multilayer electronic components with coatings to adjust the frequency of bubble domain occurrence. Test No. 1 was heat-treated for 1 hour at a temperature of 160°C or less, and Test No. 2 was heat-treated for 1 hour at a temperature of 300°C or greater.

[0121] Referring to Table 1, it can be confirmed that test number 2, with a bubble domain occurrence frequency of 0.24, achieved an effective capacitance of approximately 4.7% higher than that of test number 1, with a bubble domain occurrence frequency of 0.14. In other words, it can be confirmed that the effective capacitance of the multilayer electronic component increases with the increase of the bubble domain occurrence frequency. Furthermore, referring to Table 1 and... Figure 7C and Figure 8C When the frequency of occurrence of multiple nanodomains in the capacitor forming section, based on roundness, reaches a maximum value within a roundness range greater than or equal to 0.85 and less than or equal to 1.00, the capacitance per unit volume of the multilayer electronic component can have a relatively high value (the effective capacitance of test number 1 is 2.33 μF, and the effective capacitance of test number 2 is 2.44 μF). Furthermore, when the frequency of occurrence of bubble domains in the capacitor forming section is greater than or equal to 0.2, the capacitance per unit volume of the multilayer electronic component can have a further improved value (the effective capacitance of test number 2 is 2.44 μF).

[0122] One of the various effects of this disclosure is to increase the capacitance per unit volume of multilayer electronic components.

[0123] One of the various effects of this disclosure is to provide multilayer electronic components comprising dielectric layers with improved dielectric properties by controlling the microstructure of the domain structure of dielectric grains.

[0124] However, the various advantages and effects of this disclosure are not limited to the foregoing, and the various advantages and effects of this disclosure will be more readily understood through the description of specific exemplary embodiments of this disclosure.

[0125] Although exemplary embodiments or experimental examples of this disclosure have been described in detail above, this disclosure is not limited to the above exemplary embodiments and drawings, but is intended to be limited by the appended claims. Therefore, those skilled in the art can make various substitutions, modifications and changes without departing from the technical concept of this disclosure described in the claims, and such changes will also be considered to fall within the scope of this disclosure.

[0126] The expression "example embodiment or example" as used in this disclosure does not refer to the same example, but is provided to highlight the distinct features between the various examples. However, the examples provided in the above description do not preclude the possibility that features of other examples may be associated with and implemented after combination with them. For example, even if something described in a particular example is not described in another example that is different from it, such content may be understood to be related to the other example unless otherwise stated in its description.

[0127] The terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to limit the exemplary embodiments. As used herein, unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well.

Claims

1. A multilayer electronic component, comprising: The main body includes a capacitor forming portion, the capacitor forming portion including a dielectric layer and internal electrodes alternately disposed with the dielectric layer, the dielectric layer including a plurality of dielectric grains; as well as External electrodes are disposed on the main body. Wherein, one or more of the plurality of dielectric grains include a plurality of nanodomains with a major diameter greater than or equal to 1 nm and less than 100 nm, and the plurality of nanodomains include a plurality of bubble domains with a roundness greater than or equal to 0.85 and less than or equal to 1.00, and The frequency of occurrence of the plurality of nanodomains in the capacitor forming section according to roundness has a maximum value in the range of roundness greater than or equal to 0.85 and less than or equal to 1.

00.

2. The multilayer electronic component according to claim 1, wherein, The frequency of occurrence of the bubble domains in the capacitor forming section is greater than or equal to 0.

2.

3. The multilayer electronic component according to claim 1, wherein, The frequency of occurrence of the bubble domains in the capacitor forming section is greater than or equal to 0.

24.

4. The multilayer electronic component according to claim 1, wherein, The bubble domains include BaTiO3-based materials as the main component.

5. The multilayer electronic component according to claim 1, wherein, The dielectric layer comprises BaTiO3-based material as the main component.

6. The multilayer electronic assembly according to claim 1, wherein, The average diameter of the plurality of dielectric grains is greater than or equal to 200 nm and less than or equal to 400 nm.

7. The multilayer electronic assembly according to claim 1, wherein, The average thickness of the dielectric layer is less than or equal to 4 μm.

8. A multilayer electronic component, comprising: The main body includes a capacitor forming portion, the capacitor forming portion including a dielectric layer and internal electrodes alternately disposed with the dielectric layer, the dielectric layer including a plurality of dielectric grains; as well as External electrodes are disposed on the main body. Wherein, one or more of the plurality of dielectric grains include a plurality of nanodomains with a major diameter greater than or equal to 1 nm and less than 100 nm. The plurality of nanodomains includes a plurality of bubble domains with a roundness greater than or equal to 0.85 and less than or equal to 1.00, and The frequency of occurrence of the bubble domains in the capacitor forming section is greater than or equal to 0.

2.

9. The multilayer electronic component according to claim 8, wherein, The frequency of occurrence of the bubble domains in the capacitor forming section is greater than or equal to 0.

24.

10. The multilayer electronic assembly according to claim 8, wherein, The bubble domains include BaTiO3-based materials as the main component.

11. The multilayer electronic assembly according to claim 8, wherein, The dielectric layer comprises BaTiO3-based material as the main component.

12. The multilayer electronic assembly according to claim 8, wherein, The average size of the plurality of dielectric grains is greater than or equal to 200 nm and less than or equal to 400 nm.

13. The multilayer electronic assembly according to claim 8, wherein, The average thickness of the dielectric layer is less than or equal to 4 μm.

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