Thermally tuned laser chip and method of fabrication

Abstract

The present application relates to the field of optical communication technology, provide a kind of thermal tuning laser chip and preparation method, first heat insulation groove and second heat insulation groove are etched on the both sides or same side of ridge waveguide, and hollow heat insulation groove is obtained by etching at the bottom of second heat insulation groove, the optical cavity structure where ridge waveguide is located is separated from other chip structures of chip by first heat insulation groove, second heat insulation groove and hollow heat insulation groove, the heat transfer channel between optical cavity and most other chip structures is cut off, the heat transfer between optical cavity and other chip structures is reduced, the heat insulation effect is guaranteed, the temperature regulation effect for optical cavity is improved, the thermal tuning efficiency of optical cavity is improved;On the other hand, since hollow heat insulation groove is not communicated with first heat insulation groove, while guaranteeing the heat insulation effect, the strength of the support structure of optical cavity itself is guaranteed, material deformation due to insufficient structural strength is avoided, so as to affect the performance of chip.

Description

Technical Field

[0001] This invention belongs to the field of optical communication technology, and more specifically, relates to a thermally tunable laser chip and its fabrication method. Background Technology

[0002] With the rapid development of the internet, the market demand for network bandwidth is increasing, making comprehensive, high-performance, and low-power monolithic integrated chips increasingly important. As coherent transmission networks achieve higher transmission rates, optical networks are evolving towards even higher transmission rates and larger capacities. In increasing the capacity of optical networks, greater emphasis will be placed on their flexibility and scalability to cope with the rapidly changing market environment. Tunable semiconductor lasers play an irreplaceable role in achieving flexible wavelength switching, avoiding congestion, and reducing network maintenance costs. Furthermore, tunable semiconductor lasers are key components in dense wavelength division multiplexing systems and future all-optical networks, and their advantages in improving transmission rates and capacities will become increasingly prominent.

[0003] Currently, tunable laser chips are classified into thermally tunable, current-injection tunable, mechanically tunable, and V-cavity tunable types based on their tuning mechanisms. Thermally tunable laser chips change their refractive index through thermal effects, and have advantages such as good tuning linearity, wide tuning range, and simple fabrication, making them widely used in wavelength division multiplexing (WDM) systems.

[0004] In thermally tunable lasers, the temperature within the optical cavity is primarily adjusted by thermistors to change the refractive index. However, in practical applications, heat from the optical cavity can easily and rapidly transfer to other structures on the chip, resulting in low efficiency in temperature regulation of the optical cavity. Therefore, the effectiveness of thermal insulation between the optical cavity and other parts of the chip directly affects the thermal tuning efficiency. If the optical cavity is directly isolated from other parts of the chip at the structural level, excessively pursuing thermal insulation, it can lead to insufficient cavity support strength, causing deformation of the optical cavity and thin film materials, thus affecting the overall chip performance. Therefore, improving the support strength of the optical cavity while ensuring effective thermal insulation has become the key to improving thermally tunable laser chips.

[0005] Therefore, overcoming the shortcomings of the existing technology is an urgent problem to be solved in this technical field. Summary of the Invention

[0006] The problem this invention aims to solve is how to improve the strength of the optical cavity support structure while ensuring the thermal insulation effect of the optical cavity in a thermally tunable laser chip.

[0007] In a first aspect, a thermally tunable laser chip is provided, comprising: a substrate 1 and a functional layer 2 etched with a ridge waveguide 3, wherein: The functional layer 2 is etched with a first heat-insulating groove 4 and a second heat-insulating groove 5. The first heat-insulating groove 4 and the second heat-insulating groove 5 are distributed on the same side of the ridge waveguide 3 or on both sides of the ridge waveguide 3 respectively. The bottom of the first heat-insulating groove 4 extends to the substrate 1. The first heat insulation groove 4 and the second heat insulation groove 5 both extend parallel to the extension direction of the ridge waveguide 3. A dielectric membrane 41 is provided on the inner wall of the first heat insulation groove 4; The bottom of the second heat insulation groove 5 is provided with a hollow heat insulation groove 6, which extends to the bottom of the ridge waveguide 3. The dielectric film 41 on one side of the first heat insulation groove 4 serves as a corrosion stop layer at one end of the hollow heat insulation groove 6.

[0008] Preferably, the functional layer 2 includes, from bottom to top, a lower cladding layer 21, a lower etch stop layer 22, an InP lower sacrificial layer 23, an InGaAs sacrificial layer 24, an InP upper sacrificial layer 25, an upper etch stop layer 26, a support layer 27, an active layer 28, and a waveguide layer 29.

[0009] Preferably, the bottom of the second heat-insulating groove 5 extends to the InGaAs sacrificial layer 24; At least a portion of the InGaAs sacrificial layer 24 below the second heat insulation groove 5 is corroded away to form the void heat insulation groove 6.

[0010] Preferably, the bottom of the second heat-insulating groove 5 extends to the sacrificial layer 25 on the InP; At least a portion of the InP lower sacrificial layer 23, at least a portion of the InGaAs sacrificial layer 24, and at least a portion of the InP upper sacrificial layer 25 below the second heat insulation groove 5 are corroded away to form the void heat insulation groove 6.

[0011] Preferably, the thermally tuned laser chip includes at least two second heat-insulating grooves 5 spaced apart along the extension direction of the ridge waveguide 3, with a first preset length between adjacent second heat-insulating grooves 5; The first preset length is 2um-20um.

[0012] Preferably, a thin-film heater 7 is also provided on the ridge waveguide 3.

[0013] Preferably, the thickness of the dielectric film 41 is 0.5um-3um.

[0014] Preferably, the width of the first heat insulation groove 4 is 2um-20um.

[0015] Preferably, the depth of the first heat insulation groove 4 is 3-8 μm.

[0016] Secondly, a method for fabricating a thermally tunable laser chip is provided, comprising: The functional layer 2 is grown on the substrate 1, and the ridge waveguide 3 is etched on the functional layer 2; A thin-film heater 7 is sputtered onto the ridge waveguide 3; The first heat-insulating groove 4 is etched on one side of the ridge waveguide 3. The first heat-insulating groove 4 penetrates the functional layer 2 and extends to the substrate 1. The second heat-insulating groove 5 is etched on the same side or the other side of the ridge waveguide 3. The dielectric film 41 is grown on the inner wall of the first heat insulation groove 4; A hollow heat insulation groove 6 is formed by etching at the bottom of the second heat insulation groove 5, and the sidewall of the first heat insulation groove 4 serves as an etching stop layer at one end of the hollow heat insulation groove 6. Unlike existing technologies, this invention has at least the following beneficial effects: The first heat-insulating groove 4 and the second heat-insulating groove 5 are etched on both sides or the same side of the ridge waveguide 3, and a hollow heat-insulating groove 6 is etched at the bottom of the second heat-insulating groove 5. The first heat-insulating groove 4, the second heat-insulating groove 5 and the hollow heat-insulating groove 6 separate the optical cavity 10 structure where the ridge waveguide 3 is located from the other chip structures of the chip, cut off the heat transfer channel between the optical cavity 10 and most other chip structures, reduce the heat transfer between the optical cavity 10 and other chip structures, ensure the heat insulation effect, improve the temperature regulation effect of the optical cavity 10, and improve the thermal tuning efficiency of the optical cavity 10. On the other hand, since the hollow heat-insulating groove 6 is not connected to the first heat-insulating groove 4, while ensuring the heat insulation effect, it also ensures the strength of the support structure of the optical cavity 10 itself, and avoids material deformation due to insufficient structural strength, thereby affecting the chip performance. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments of the present invention will be briefly described below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0018] Figure 1 This is a cross-sectional view of a thermally tunable laser chip provided in an embodiment of the present invention; Figure 2 This is a cross-sectional view of another thermally tunable laser chip provided in an embodiment of the present invention; Figure 3 This is a top view of another thermally tunable laser chip provided in an embodiment of the present invention; Figure 4 This is a cross-sectional view of another thermally tunable laser chip provided in an embodiment of the present invention; Figure 5 This is a cross-sectional view of a thermally tunable laser chip before etching, provided in an embodiment of the present invention. Figure 6 This is a cross-sectional view of a thermally tunable laser chip after etching to obtain a ridge waveguide, provided in an embodiment of the present invention. Figure 7 This is a cross-sectional view of a thermally tunable laser chip before the formation of a cavity heat insulation groove, as provided in an embodiment of the present invention. Figure 8 This is a cross-sectional view of a thermally tunable laser chip after etching to obtain a hollow heat insulation groove, according to an embodiment of the present invention. Figure 9 This is a cross-sectional view of another thermally tunable laser chip before the cavity heat insulation groove is obtained by etching, according to another embodiment of the present invention. Figure 10 This is a cross-sectional view of another thermally tunable laser chip after etching to obtain a hollow heat insulation groove, according to another embodiment of the present invention. Figure 11 This is a cross-sectional view of a thermally tunable laser chip after etching to obtain a hollow heat insulation groove, as provided in another embodiment of the present invention. Figure 12 This is a top view of another thermally tunable laser chip provided in an embodiment of the present invention; Figure 13 This is a flowchart of a method for fabricating a thermally tunable laser chip according to an embodiment of the present invention; The attached figures are numbered as follows: Substrate 1; Functional layer 2; Lower cladding layer 21; Lower etch stop layer 22; InP lower sacrificial layer 23; InGaAs sacrificial layer 24; InP upper sacrificial layer 25; Upper etch stop layer 26; Support layer 27; Active layer 28; Waveguide layer 29; Ridge waveguide 3; First thermal insulation groove 4; Dielectric film 41; Second thermal insulation groove 5; Void thermal insulation groove 6; Thin film heater 7; First electrode 8; Second electrode 9; Optical cavity 10. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0021] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more. Furthermore, for example, the description may use the prefix "A" or "B" to describe the same type of nouns as two independent entities. In this case, the corresponding features defined with "A" and "B" are used only to distinguish between similar entities and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features.

[0022] In the description of this invention, the terms "A and / or B" are used to represent specific features, and the corresponding expressions include the following three combinations: only A, only B, and a combination of A and B.

[0023] As used in this invention, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from a particular value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the particular quantity, i.e., the limitations of the measurement system.

[0024] Furthermore, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0025] Example 1: This embodiment provides a thermally tunable laser chip, such as... Figure 1 and Figure 2As shown, it includes: a substrate 1 and a functional layer 2 etched with a ridge waveguide 3, wherein: a first heat-insulating groove 4 and a second heat-insulating groove 5 are etched on the functional layer 2, the first heat-insulating groove 4 and the second heat-insulating groove 5 are distributed on the same side of the ridge waveguide 3 or respectively distributed on both sides of the ridge waveguide 3, the bottom of the first heat-insulating groove 4 extends to the substrate 1; the first heat-insulating groove 4 and the second heat-insulating groove 5 both extend parallel to the extension direction of the ridge waveguide 3; a dielectric film 41 is provided on the inner wall of the first heat-insulating groove 4; a hollow heat-insulating groove 6 is provided at the bottom of the second heat-insulating groove 5, the hollow heat-insulating groove 6 extends to the bottom of the ridge waveguide 3, and the dielectric film 41 on one side of the first heat-insulating groove 4 serves as an etching stop layer at one end of the hollow heat-insulating groove 6.

[0026] like Figure 1 and Figure 2 As shown, in this embodiment, the surface of the functional layer 2 is etched using a dry etching apparatus, and the etched pattern can be etched using a mixed solution of HCl and H3PO3 to obtain the ridge waveguide 3. The ridge waveguide 3 itself needs to have its temperature adjusted by a thermal resistor to change its refractive index. A thin-film heater 7 is provided on the ridge waveguide 3. The thin-film heater 7 can be sputtered onto the ridge waveguide 3 and heated by the thin-film heater 7 to achieve temperature regulation. Therefore, it is necessary to ensure that the area where the ridge waveguide 3 is located (the description of this area in the following text uses...) is... Figure 2 The heat insulation effect between the optical cavity 10 (described in the illustration) and other layers on the chip reduces the heat exchange efficiency between the optical cavity 10 and other layers on the chip, thereby improving the temperature regulation efficiency of the optical cavity 10 itself. In this embodiment, it is necessary to isolate the optical cavity 10 from other parts on the chip, reduce the connections between the optical cavity 10 and other parts, thereby reducing the heat transfer channels between the optical cavity 10 and other parts on the chip, and improving the temperature regulation effect of the optical cavity 10.

[0027] like Figure 1 and Figure 2As shown, this embodiment provides a feasible solution: the first heat-insulating groove 4 and the second heat-insulating groove 5 are etched on both sides of the ridge waveguide 3 to reduce the connection between the optical cavity 10 and the chip portions on both sides of itself. Dry etching, wet etching, or a combination of both can be used to obtain the first heat-insulating groove 4 and the second heat-insulating groove 5. The first heat-insulating groove 4 is deeper than the second heat-insulating groove 5. Both the first heat-insulating groove 4 and the second heat-insulating groove 5 are strip-shaped structures parallel to the ridge waveguide 3, providing better heat insulation for the optical cavity 10 and preventing the heat generated by the thin-film heater 7 from being transferred through the material layer to the remaining material layers of the chip. The width of the first heat-insulating groove 4 is 2µm-20µm. Specifically, the width of the first heat-insulating groove 4 can be 2µm, 11µm, 20µm, or any value within the aforementioned width range. The depth of the first heat-insulating groove 4 is 3-8 μm. Specifically, the depth of the first heat-insulating groove 4 is 3 μm, 5.5 μm, 8 μm, or any value within the aforementioned depth range. The second heat-insulating groove 5 and the ridge waveguide 3 are spaced at a preset distance. This is to prevent the second heat-insulating groove 5 from being too close to the ridge waveguide 3, thus affecting the heat insulation effect, and also to prevent the second heat-insulating groove 5 from being too far from the ridge waveguide 3. The preset distance is 1 μm-8 μm. Specifically, the preset distance can be 1 μm, 4.5 μm, 8 μm, or any value within the aforementioned distance range.

[0028] The bottom of the second heat insulation groove 5 is also provided with a hollow heat insulation groove 6. The hollow heat insulation groove 6 is formed by etching with an etching solution. The hollow heat insulation groove 6 is used to extend horizontally downwards towards the ridge waveguide 3 inside the chip structure, so that the optical cavity 10 and the chip part below it are separated, reducing the heat transfer efficiency of the optical cavity 10 and the chip part below it, and further improving the heat isolation effect of the optical cavity 10. One end of the hollow heat insulation groove 6 extends to the location of the first heat insulation groove 4, but cannot be directly connected to the first heat insulation groove 4, which would cause the light to be directly connected to the first heat insulation groove 4. The structural support strength around cavity 10 is too weak. Therefore, the dielectric film 41 of the first heat insulation groove 4 is used as the corrosion stop layer of the cavity heat insulation groove 6. That is, when the cavity heat insulation groove 6 is obtained by corrosion, the corrosion of one end of the cavity heat insulation groove 6 stops when it reaches the position of the dielectric film 41. The position of the other end of the cavity heat insulation groove 6 is controlled by controlling the corrosion time of the corrosion liquid, so that one end of the cavity heat insulation groove 6 reaches the dielectric film 41 and is not connected to the first heat insulation groove 4. The dielectric film 41 supports the optical cavity 10 to ensure the basic structural strength.

[0029] In this embodiment, the dielectric membrane 41 provides sufficient structural support and good thermal insulation. The dielectric membrane 41 can be made of a single metal such as Ti, Pt, or Au, or it can be made of two or three metals. The advantage of using a metallic dielectric membrane 41 is its excellent mechanical strength and support strength. Combined with the thicker porous thermal insulation groove 6, it can achieve even better support. The dielectric membrane 41 can also be made of SiO2, Si... X N Y The optical cavity 10 is supported by non-metallic materials such as SiON, and the components are uniformly transitioned during growth to provide a porous structure, offering better thermal insulation while maintaining mechanical strength. The dielectric film 41 reduces the heat exchange efficiency between the optical cavity 10 and the rest of the chip. Simultaneously, its good rigidity provides better support for the optical cavity 10, preventing deformation or material layer breakage due to poor support during subsequent use. In practical applications, a dielectric film 41 that is too thin will have limited support, while a dielectric layer that is too thick can easily form a thermally conductive layer, thus reducing the thermal insulation effect. The thickness of the dielectric film 41 is 0.5µm-5µm. In this embodiment, the thickness of the dielectric film 41 can be 0.5µm, 2.75µm, or 5µm.

[0030] On the other hand, the dielectric film 41 is prepared by multiple growth processes, that is, after growing a thin layer each time, it is taken out and then a thin layer is grown again. The above operation is repeated to eliminate the internal stress of the dielectric film 41, so that the internal stress of the dielectric film 41 is close to 0. Furthermore, the thermal expansion coefficient and other parameters of the dielectric film 41 are close to those of other materials in the chip. This ensures that in practical applications, the chip will not fall off or deform due to the internal stress of the dielectric film 41 during heated operation, thus minimizing the decrease in the support strength of the dielectric film 41.

[0031] To isolate the optical cavity 10 from other parts of the chip, this embodiment provides another feasible solution: etching the first heat-insulating groove 4 and the second heat-insulating groove 5 on the same side of the ridge waveguide 3. The second heat-insulating groove 5 is closer to the ridge waveguide 3. One end of the hollow heat-insulating groove 6 extends to the location of the dielectric film 41 of the first heat-insulating groove 4, and the other end needs to extend under the ridge waveguide 3 to ensure that the optical cavity 10 and the chip part below it are separated, thereby achieving the corresponding heat insulation effect. The first heat-insulating groove 4 and the second heat-insulating groove 5 located on the same side ensure the isolation between the optical cavity 10 and the chip structure on the corresponding side. The process required for etching on the same side is relatively simpler. However, since there is no corresponding isolation groove on the other side of the optical cavity 10, the heat insulation effect of the optical cavity 10 is relatively poor.

[0032] In this embodiment, a first heat-insulating groove 4 and a second heat-insulating groove 5 are etched on both sides or the same side of the ridge waveguide 3, and a hollow heat-insulating groove 6 is etched at the bottom of the second heat-insulating groove 5. The first heat-insulating groove 4, the second heat-insulating groove 5 and the hollow heat-insulating groove 6 separate the optical cavity 10 structure where the ridge waveguide 3 is located from other chip structures, cut off the heat transfer channel between the optical cavity 10 and most other chip structures, reduce the heat transfer between the optical cavity 10 and other chip structures, ensure the heat insulation effect, improve the temperature regulation effect of the optical cavity 10, and improve the thermal tuning efficiency of the optical cavity 10. On the other hand, since the hollow heat-insulating groove 6 is not connected to the first heat-insulating groove 4, while ensuring the heat insulation effect, the strength of the supporting structure of the optical cavity 10 itself is also ensured, avoiding material deformation due to insufficient structural strength, thereby affecting the chip performance.

[0033] To ensure both the heat insulation effect of the optical cavity 10 and the supporting strength of the optical cavity 10, the following design is also involved: such as Figure 3 As shown, a plurality of second heat-insulating grooves 5 are spaced apart along the extension direction of the ridge waveguide 3, with a first preset length between adjacent second heat-insulating grooves 5; the first preset length is 2um-20um, and in this embodiment, the first preset length can be 2um, 11um, or 20um. Figure 2 for Figure 3 A sectional view of the section line position at a-a'. Figure 4 for Figure 3 A sectional view at the position of the line of sight b-b'.

[0034] In this embodiment, since the lower end of the second heat insulation groove 5 is also provided with a hollow heat insulation groove 6, if the second heat insulation groove 5 is set as a continuous groove extending along the ridge waveguide 3, the overall support strength of the chip structure on the side where the second heat insulation groove 5 is located will be weak. Therefore, in order to increase the strength, at least two mutually spaced second heat insulation grooves 5 are provided along the extension direction of the ridge waveguide 3. All the second heat insulation grooves 5 extend in a direction parallel to the extension direction of the ridge waveguide 3. The corresponding functional layer 2 structure is retained between adjacent second heat insulation grooves 5. This part of the structure serves as the support structure of the optical cavity 10, which improves the support strength of the optical cavity 10. However, at the same time, this part of the functional layer 2 structure will serve as a heat transfer channel between the optical cavity 10 and other chip structures. Therefore, the above design improves the support strength but reduces the heat insulation effect. Considering that it is difficult to maintain the support strength of the optical cavity 10 by relying solely on the dielectric film 41, the second heat insulation grooves 5 are spaced apart to improve the support strength of the optical cavity 10, which is a better solution.

[0035] Based on the above design, in order to improve the heat insulation effect, the interval between the two second heat insulation grooves 5 should be as short as possible. In this embodiment, the first preset length is set by those skilled in the art according to the actual situation. The first preset length is 2um-20um, wherein the first preset length can be 2um, the first preset length can be 11um, and the first preset length can be 20um.

[0036] Furthermore, in this embodiment, in order to realize the basic functions of the chip, the functional layer 2 needs to have a conventional hierarchical structure to meet the basic requirements of the chip structure. Therefore, this embodiment also involves the following design: Figures 5-8 As shown, the functional layer 2 includes, from bottom to top, a lower cladding layer 21, a lower etch stop layer 22, an InP lower sacrificial layer 23, an InGaAs sacrificial layer 24, an InP upper sacrificial layer 25, an upper etch stop layer 26, a support layer 27, an active layer 28, and a waveguide layer 29.

[0037] in, Figure 5 This is a structural diagram of the ridge waveguide before etching. Figure 6 The image shows the structure of the ridge waveguide after etching. Figure 7 To obtain the structural diagram before etching the hollow heat insulation groove 6, Figure 8 This is a structural diagram of the cavity insulation groove 6 obtained by etching.

[0038] Furthermore, based on the structure of the aforementioned functional layer 2, the depths of the first heat-insulating groove 4 and the second heat-insulating groove 5 are further defined. Since the lower end of the second heat-insulating groove 5 needs to be etched to obtain a hollow heat-insulating groove 6, the depth of the second heat-insulating groove 5 is less than that of the first heat-insulating groove 4. The first heat-insulating groove 4 penetrates the entire functional layer 2 from top to bottom, up to the substrate 1. The depth of the second heat-insulating groove 5 is determined by the width of the hollow heat-insulating groove 6. The smaller the width of the hollow heat-insulating groove 6, the deeper the second heat-insulating groove 5 can be; the larger the width of the hollow heat-insulating groove 6, the shallower the second heat-insulating groove 5 can be.

[0039] Taking into account both thermal insulation and structural strength, this embodiment provides the following structural design: (e.g.) Figure 7 and Figure 8 As shown, the bottom of the second heat-insulating groove 5 extends to the InGaAs sacrificial layer 24; at least a portion of the InGaAs sacrificial layer 24 below the second heat-insulating groove 5 is corroded away to form the void heat-insulating groove 6.

[0040] like Figure 7 and Figure 8As shown, the InGaAs sacrificial layer 24 is partially etched by an etchant to form a hollow heat insulation groove 6. The etchant used is a mixture of H2SO4, H2O2, and H2O in a certain proportion. The InP upper sacrificial layer 25 and the InP lower sacrificial layer 23 serve as etch stop layers. Since only the InGaAs sacrificial layer 24 is etched, and the InGaAs sacrificial layer 24 is usually thin, the width of the hollow heat insulation groove 6 is relatively small. In this case, the optical cavity 10 and the chip below it are too close, resulting in poor heat insulation. Since the hollow heat insulation groove 6 etches relatively little of the structure, the supporting structure is relatively stronger. Correspondingly, the spacing between the spaced second heat insulation grooves 5 can be set shorter, thereby increasing the total area occupied by all the second heat insulation grooves 5 and thus improving the heat insulation effect. Through the above design, the heat insulation effect and the supporting strength are balanced.

[0041] Based on the above structure, considering that the hollow heat insulation groove 6 is obtained by etching the InGaAs sacrificial layer 24, the width of the hollow heat insulation groove 6 is relatively small when the InGaAs sacrificial layer 24 is relatively thin, resulting in poor heat insulation effect. To solve the above problem, as follows... Figure 9 and Figure 10 As shown, by increasing the thickness of the InGaAs sacrificial layer 24, and correspondingly reducing the thickness of the InP upper sacrificial layer 25 and the InP lower sacrificial layer 23 to keep the overall chip thickness unchanged, the InGaAs sacrificial layer 24 is etched with an etchant, and the InP upper sacrificial layer 25 and the InP lower sacrificial layer 23 are used as etch stop layers, resulting in a relatively wider cavity heat insulation groove 6 to achieve better heat insulation effect. In this embodiment, the width of the cavity heat insulation groove 6 is 0.1um-5um.

[0042] Considering that increasing the width of the hollow heat insulation groove 6 can improve the isolation between the optical cavity 10 and the underlying chip, but reduces the supporting strength of the optical cavity 10, the spacing between adjacent second heat insulation grooves 5 is increased accordingly to compensate for the insufficient supporting strength of the optical cavity 10. The corresponding design is as follows: Figure 11 As shown, the bottom of the second heat-insulating groove 5 extends to the upper InP sacrificial layer 25; at least a portion of the lower InP sacrificial layer 23, at least a portion of the InGaAs sacrificial layer 24, and at least a portion of the upper InP sacrificial layer 25 below the second heat-insulating groove 5 are etched away to form the void heat-insulating groove 6. Specifically, at least a portion of the lower InP sacrificial layer 23 and at least a portion of the upper InP sacrificial layer 25 are etched using a mixture of HCl and H3PO4, and at least a portion of the InGaAs sacrificial layer 24 is etched using a mixture of H2SO4, H2O2, and H2O prepared in a specific ratio.

[0043] like Figure 11As shown, the width of the hollow heat insulation groove 6 is the sum of the thicknesses of the InP lower sacrificial layer 23, the InGaAs sacrificial layer 24, and the InP upper sacrificial layer 25. The thickness of the heat insulation cavity is adjusted according to the thicknesses of the InP lower sacrificial layer 23 and the InP upper sacrificial layer 25. The thicknesses of the InP lower sacrificial layer 23 and the InP upper sacrificial layer 25 range from 0.1 to 3 μm. Compared with the previous scheme, the hollow heat insulation groove 6 of this scheme is wider, so the optical cavity 10 has a better heat insulation effect on the chip portion below it, but the strength of the supporting structure is relatively weaker. To compensate for the above problem, the spacing between the matching second heat insulation grooves 5 needs to be increased, thereby increasing the support structure for the optical cavity 10. Correspondingly, the total area of ​​all the second heat insulation grooves 5 will be reduced, reducing the heat insulation effect of this part of the optical cavity 10. However, since the heat insulation effect of the optical cavity 10 on the chip portion below it is enhanced, this problem is offset.

[0044] In this embodiment, as Figure 12 As shown, the above structure is applied to a thermally tunable laser chip. The thermally tunable laser chip includes a semiconductor optical amplifier (SOA) region, a front grating region, a gain region, a phase region, a rear grating region, and a cleaved optical amplifier (COA) region arranged sequentially along the extension direction of the ridge waveguide 3. The front grating region, the phase region, and the rear grating region are all chip structures provided in this embodiment. In the front grating region, the phase region, and the rear grating region, a first electrode 8 is disposed on the periphery of the chip structure. The thin film heater 7 in the corresponding region is connected to the first electrode 8 in the corresponding region. The SOA region, the gain region, and the COA region are all covered with a second electrode 9.

[0045] Example 2: This embodiment, based on Embodiment 1, provides a method for fabricating a thermally tunable laser chip, used to fabricate the aforementioned thermally tunable laser chip, such as... Figure 13 As shown, the method flow includes: In step 101, the functional layer 2 is grown on the substrate 1, and the ridge waveguide 3 is etched on the functional layer 2.

[0046] In this embodiment, the surface of the functional layer 2 is etched using a dry etching apparatus, and the etched pattern can be further etched using a mixed solution of HCl and H3PO3 to obtain the ridge waveguide 3. The ridge waveguide 3 is located on the axis of the laser beam emission.

[0047] In step 102, a thin-film heater 7 is sputtered onto the ridge waveguide 3.

[0048] In step 103, the first heat insulation groove 4 is etched on one side of the ridge waveguide 3. The first heat insulation groove 4 penetrates the functional layer 2 and extends to the substrate 1. The second heat insulation groove 5 is etched on the same side or the other side of the ridge waveguide 3.

[0049] In this embodiment, the first heat-insulating groove 4 and the second heat-insulating groove 5 are obtained by dry etching, wet etching, or a combination of dry and wet etching. The first heat-insulating groove 4 is deeper than the second heat-insulating groove 5. The depth of the first heat-insulating groove 4 is determined according to the different thicknesses of each functional layer 2, penetrating each functional layer 2 while ensuring smooth sidewalls and meeting verticality requirements. Both the first heat-insulating groove 4 and the second heat-insulating groove 5 are strip-shaped structures parallel to the ridge waveguide 3, providing better heat insulation for the optical cavity 10 and preventing heat generated by the thin-film heater 7 from being transferred through the material layer to the remaining material layers of the chip. The width of the first heat-insulating groove 4 is 2µm-20µm, and the depth is 3-8µm. A preset distance is maintained between the second heat-insulating groove 5 and the ridge waveguide 3. This is to prevent the second heat-insulating groove 5 from being too close to the ridge waveguide 3, affecting the heat insulation effect, and also to prevent the second heat-insulating groove 5 from being too far from the ridge waveguide 3. The preset distance is 1µm-8µm.

[0050] In this embodiment, the second heat-insulating groove 5 is a regular rectangle or a circular ellipse, and there is a certain gap between adjacent second heat-insulating grooves 5, the gap distance being 2-20μm. A dielectric film 41 is grown on the inner wall of the second heat-insulating groove 5 and coated with a layer of photoresist.

[0051] In step 104, the dielectric film 41 is grown on the inner wall of the first heat insulation groove 4.

[0052] In this embodiment, the dielectric film 41 provides sufficient structural support and good thermal insulation. The dielectric film 41 is a non-uniformly grown SiO2, SiXNY, or SiON material, or a metal or its composite metal material, with a low thermal conductivity and a certain rigidity, which can isolate the optical cavity 10 from the heat exchange of the rest of the chip materials. At the same time, the good rigidity can provide a good support effect for the optical cavity 10, preventing deformation of the optical cavity 10 or breakage of the material layer due to poor support during subsequent use. In practical applications, if the dielectric film 41 is too thin, the support effect will be limited, and if the dielectric layer is too thick, it is easy to form a thermally conductive layer, thereby reducing the thermal insulation effect. The thickness of the dielectric film 41 is 0.5um-3um.

[0053] In step 105, a hollow heat insulation groove 6 is obtained by etching at the bottom of the second heat insulation groove 5, and the sidewall of the first heat insulation groove 4 serves as the corrosion stop layer at one end of the hollow heat insulation groove 6.

[0054] In one feasible embodiment, the structure of the second heat insulation groove 5 is as follows: the bottom of the second heat insulation groove 5 extends to the InGaAs sacrificial layer 24; at least a portion of the InGaAs sacrificial layer 24 below the second heat insulation groove 5 is corroded away to form the void heat insulation groove 6.

[0055] The preparation method of the second heat insulation groove 5 of the above structure is as follows: the bottom of the second heat insulation groove 5 is etched, and the InGaAs sacrificial layer 24 is etched with an etchant. The etchant is prepared by H2SO4, H2O2 and H2O in a certain proportion. Since only the InGaAs sacrificial layer 24 is etched, the width of the hollow heat insulation groove 6 is relatively thin. In this case, the optical cavity 10 and the chip part below it are too close, so the heat insulation effect of this structure is poor. Since the structural part etched by the hollow heat insulation groove 6 is relatively small, the supporting structure is relatively stronger. Correspondingly, the spacing between the second heat insulation grooves 5 can be set to be shorter, thereby increasing the total area occupied by all the second heat insulation grooves 5, and thus improving the heat insulation effect. Through the above design, the heat insulation effect and the supporting strength are balanced.

[0056] Furthermore, in another feasible structural scheme, the bottom of the second heat-insulating groove 5 extends to the upper InP sacrificial layer 25; at least a portion of the lower InP sacrificial layer 23, at least a portion of the InGaAs sacrificial layer 24, and at least a portion of the upper InP sacrificial layer 25 below the second heat-insulating groove 5 are etched away to form the void heat-insulating groove 6. Specifically, at least a portion of the lower InP sacrificial layer 23 and at least a portion of the upper InP sacrificial layer 25 are etched using a mixture of HCl and H3PO4, and at least a portion of the InGaAs sacrificial layer 24 is etched using a mixture of H2SO4, H2O2, and H2O in a certain proportion. In the above structural scheme, the width of the void heat-insulating groove 6 is the sum of the thicknesses of the lower InP sacrificial layer 23, the InGaAs sacrificial layer 24, and the upper InP sacrificial layer 25, and the thickness of the heat-insulating cavity is adjusted according to the thicknesses of the lower InP sacrificial layer 23 and the upper InP sacrificial layer 25. The thickness of the InP lower sacrificial layer 23 and the InP upper sacrificial layer 25 ranges from 0.1 to 3 μm. Compared with the previous scheme, the hollow heat insulation groove 6 of this scheme is wider, so the optical cavity 10 has a better heat insulation effect on the chip part below it, but the strength of the supporting structure is relatively worse. In order to make up for the above problems, the spacing between the matching second heat insulation grooves 5 needs to be increased, thereby increasing the support structure for the optical cavity 10. However, the total area of ​​all the second heat insulation grooves 5 will be reduced, which reduces the heat insulation effect of this part of the optical cavity 10. However, since the heat insulation effect of the optical cavity 10 on the chip part below it is enhanced, this problem is offset.

[0057] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A thermally tunable laser chip, characterized in that, include: Substrate (1) and functional layer (2) etched with ridge waveguide (3), wherein: The functional layer (2) is etched with a first heat-insulating groove (4) and a second heat-insulating groove (5). The first heat-insulating groove (4) and the second heat-insulating groove (5) are distributed on the same side of the ridge waveguide (3) or on both sides of the ridge waveguide (3). The bottom of the first heat-insulating groove (4) extends to the substrate (1). The first heat insulation groove (4) and the second heat insulation groove (5) both extend parallel to the extension direction of the ridge waveguide (3); The inner wall of the first heat insulation groove (4) is provided with a medium membrane (41); The bottom of the second heat insulation groove (5) is provided with a hollow heat insulation groove (6), which extends to the bottom of the ridge waveguide (3). The dielectric film (41) on one side of the first heat insulation groove (4) serves as a corrosion stop layer at one end of the hollow heat insulation groove (6).

2. The thermally tunable laser chip according to claim 1, characterized in that, The functional layer (2) includes, from bottom to top, a lower cladding layer (21), a lower etch stop layer (22), an InP lower sacrificial layer (23), an InGaAs sacrificial layer (24), an InP upper sacrificial layer (25), an upper etch stop layer (26), a support layer (27), an active layer (28), and a waveguide layer (29).

3. The thermally tunable laser chip according to claim 2, characterized in that, The bottom of the second heat-insulating groove (5) extends to the InGaAs sacrificial layer (24); At least a portion of the InGaAs sacrificial layer (24) below the second heat insulation groove (5) is corroded away to form the void heat insulation groove (6).

4. The thermally tunable laser chip according to claim 2, characterized in that, The bottom of the second heat-insulating groove (5) extends to the sacrificial layer (25) on the InP; At least a portion of the InP lower sacrificial layer (23), at least a portion of the InGaAs sacrificial layer (24), and at least a portion of the InP upper sacrificial layer (25) below the second heat insulation groove (5) are corroded away to form the void heat insulation groove (6).

5. The thermally tunable laser chip according to claim 1, characterized in that, The thermally tuned laser chip includes at least two second heat-insulating grooves (5) spaced apart along the extension direction of the ridge waveguide (3), with a first preset length between adjacent second heat-insulating grooves (5); The first preset length is 2um-20um.

6. The thermally tunable laser chip according to any one of claims 1-5, characterized in that, A thin-film heater (7) is also provided on the ridge waveguide (3).

7. The thermally tunable laser chip according to any one of claims 1-5, characterized in that, The thickness of the dielectric film (41) is 0.5um-3um.

8. The thermally tunable laser chip according to any one of claims 1-5, characterized in that, The width of the first heat insulation groove (4) is 2um-20um.

9. The thermally tunable laser chip according to any one of claims 1-5, characterized in that, The depth of the first heat insulation groove (4) is 3-8 μm.

10. A method for fabricating a thermally tunable laser chip, used to fabricate a thermally tunable laser chip as described in any one of claims 1-9, characterized in that, include: The functional layer (2) is grown on the substrate (1), and a ridge waveguide (3) is etched on the functional layer (2). A thin-film heater (7) is sputtered onto the ridge waveguide (3); The first heat-insulating groove (4) is etched on one side of the ridge waveguide (3), the first heat-insulating groove (4) penetrates the functional layer (2) and extends to the substrate (1), and the second heat-insulating groove (5) is etched on the same side or the other side of the ridge waveguide (3). The dielectric film (41) is grown on the inner wall of the first heat insulation groove (4); A hollow heat insulation groove (6) is obtained by etching at the bottom of the second heat insulation groove (5), and the side wall of the first heat insulation groove (4) serves as the corrosion stop layer at one end of the hollow heat insulation groove (6).

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