A method for manufacturing a laser chip, a laser chip and an optical module

Abstract

The application discloses a preparation method of a laser chip, the laser chip and an optical module, and relates to the technical field of laser chips. The preparation method comprises the following steps: forming a light-emitting area, an isolation area and a modulation area above a substrate, the isolation area being connected with the light-emitting area and the modulation area; depositing a passivation layer on the surface of the light-emitting area, the isolation area and the modulation area and covering photoresist on the passivation layer; etching the passivation layer by means of reactive ion etching to form a first window, a second window, a third window and a fourth window on the passivation layer, the etching gas containing O2; forming a first positive electrode in the first window, a first negative electrode pad in the second window, a first positive electrode pad on the side of the first negative electrode pad, a second positive electrode in the third window, a second negative electrode pad in the fourth window and a second positive electrode pad on the side of the second negative electrode pad, the first positive electrode pad being electrically connected with the first positive electrode, and the second positive electrode pad being electrically connected with the second positive electrode. The performance of the laser chip is facilitated to be ensured.

Description

Technical Field

[0001] This disclosure relates to the field of optical communication technology, and in particular to a method for fabricating a laser chip, the laser chip, and an optical module. Background Technology

[0002] With the development of new business and application models such as cloud computing, mobile internet, and video, the advancement of optical communication technology has become increasingly important. In optical communication technology, optical modules are the tools for converting between photoelectric signals and signals, and are one of the key components in optical communication equipment. Furthermore, with the evolving needs of optical communication technology, the transmission rate of optical modules is constantly increasing.

[0003] An optical module includes an optical emitting component, which is the main component that transmits optical signals. The laser chip within the optical emitting component is the primary device for generating these signals, and its performance directly affects the overall performance of the optical module. Therefore, a high-quality laser chip is fundamental to ensuring the performance of the optical module. Summary of the Invention

[0004] In some embodiments, a method for fabricating a laser chip, a laser chip, and an optical module are provided to ensure the performance of the optical module.

[0005] In some embodiments, a method for fabricating a laser chip is provided, comprising:

[0006] A light-emitting region, an isolation region, and a modulation region are formed above a substrate, wherein the isolation region connects the light-emitting region and the modulation region; wherein the light-emitting region has a first trench and a second trench, and the modulation region has a third trench and a fourth trench;

[0007] A passivation layer is deposited on the surface of the light-emitting region, the isolation region, and the modulation region, and photoresist is coated on the passivation layer;

[0008] The photoresist is covered by a preset mask and a preset pattern is formed by exposure.

[0009] Based on the preset pattern, the passivation layer is etched by reactive ion etching to open a first window, a second window, a third window, and a fourth window on the passivation layer; wherein the corrosive gas includes O2, the first window is located between the first trench and the second trench, the second window is located on one side of the first trench or the second trench, the third window is located between the third trench and the fourth trench, and the fourth window is located on one side of the third trench or the fourth trench;

[0010] A first positive electrode is formed in the first window, a first negative electrode pad is formed in the second window, a first positive electrode pad is formed on the side of the first negative electrode pad, a second positive electrode is formed in the third window, a second negative electrode pad is formed in the fourth window, and a second positive electrode pad is formed on the side of the second negative electrode pad. The first positive electrode pad is electrically connected to the first positive electrode, and the second positive electrode pad is electrically connected to the second positive electrode.

[0011] One of the above technical solutions has the following advantages or beneficial effects: A light-emitting region, an isolation region, and a modulation region are formed side by side above the substrate. The isolation region is located between the light-emitting region and the modulation region, and it forms a high-resistivity region. The isolation region can block charge carriers, so that the charge carriers in the light-emitting region and the charge carriers in the modulation region do not interfere with each other, which facilitates ensuring the light output quality of the light-emitting region and the modulation signal quality of the modulation region. A passivation layer is covered on top of the light-emitting region, the isolation region, and the modulation region. The passivation layer is waterproof, scratch-resistant, and radiation-resistant, thus protecting the light-emitting region, the isolation region, and the modulation region. Photoresist is covered on the passivation layer. A preset mask is used to cover the photoresist, and a preset pattern is formed by exposure. Based on the preset pattern, the passivation layer is etched by reactive ion etching to open a first window, a second window, a third window, and a fourth window on the passivation layer. The etching gas used in the reactive ion etching process includes oxygen. The first window, the second window, the third window, and the fourth window on the passivation layer are used to form electrodes of the laser chip, so as to facilitate the formation of electrodes on the top of the laser chip. Adding O2 to the corrosive gas allows the polymer generated during the etching process to react with O2, increasing the etching rate of the photoresist and resulting in a faster lateral etching rate. This leads to a smaller sidewall tilt angle during photoresist etching. Furthermore, during the reaction between the polymer and O2, the byproducts of C, F, and Al elements in the polymer react with O2 to form C, F, and Al oxides, reducing polymer adhesion. This allows the etching products to be removed by the reactive ion etching equipment, preventing deposition on the chip surface or sidewalls. This reduces the risk of C, F, and Al byproducts depositing on the chip surface, which could affect subsequent chip processing and chip performance. The first positive pad is used to apply positive current, and the first negative pad is used for grounding, facilitating the application of positive current to the light-emitting area. The second positive pad can apply a first high-frequency signal, and the second negative pad can apply a second high-frequency signal, facilitating the application of differential signals to the modulation area.

[0012] In some embodiments, a preparation method is provided in which the corrosive gas further includes CHF3 and Ar, and the weight ratio of the components of the corrosive gas is CHF3:Ar:O2 = 2:2:1.

[0013] One of the above technical solutions has the following advantages or beneficial effects: the corrosive gas includes CHF3, Ar and O2, and the weight ratio of CHF3, Ar and O2 is 2:2:1, so that the O2 added to the corrosive gas will not seriously reduce the etching rate of the composite film, and can ensure a shorter etching process time, reduce the risk of photoresist denaturation and hardening, and make the photoresist easy to remove.

[0014] In some embodiments, a method for fabricating a laser chip is provided, comprising forming a light-emitting region, an isolation region, and a modulation region above a substrate, including:

[0015] An N-type InP layer is grown on the substrate;

[0016] A first element is implanted in the middle of the N-type InP layer to form a first electrically isolated layer, which divides the N-type InP layer into a first N-type InP layer and a second N-type InP layer.

[0017] A first active layer is grown on top of the first N-type InP layer;

[0018] A conductive layer is grown on the first electrically isolated layer;

[0019] A second active layer is grown on top of the second N-type InP layer; wherein one end of the conductive layer is connected to the first active layer, and the other end of the conductive layer is connected to the second active layer;

[0020] A P-type InP layer is grown, which covers the top of the first active layer, the conductive layer, and the second active layer;

[0021] A first contact layer and a second contact layer are grown on the P-type InP layer. The projection of the first contact layer in the direction of the first active layer covers the first active layer, and the projection of the second contact layer in the direction of the second active layer covers the second active layer.

[0022] The etching process forms the first, second, third, and fourth trenches.

[0023] One of the above technical solutions has the following advantages or beneficial effects: the process of forming a light-emitting region, an isolation region, and a modulation region above a substrate is as follows: first, an N-type InP layer is formed on the substrate; a first element is implanted in the middle of the N-type InP layer to form a first electrically isolated layer, which divides the N-type InP layer into a first N-type InP layer and a second N-type InP layer; a first active layer is formed on the first N-type InP layer, a conductive layer is formed on the first electrically isolated layer, and a second active layer is formed on the second N-type InP layer; a P-type InP layer is formed above the first active layer, the conductive layer, and the second active layer; a first contact layer and a second contact layer are formed above the P-type InP layer, with the first contact layer located above the first active layer and the second contact layer located above the second active layer; and a first trench, a second trench, a third trench, and a fourth trench are formed by etching. Thus, the formed luminescent region facilitates stimulated emission to recombine discrete electron-hole pairs and generate photons, thereby effectively converting electrically injected charge carriers into photons and generating gain light; the formed modulation region is easy to adapt to the increase and decrease of the external electric field and modulate the light; the formed isolation region utilizes the injection of the first element into the N-type InP layer, which can form deep energy level defects, making it easy to ensure the resistivity of the first electrically isolated layer, so that the isolation region has a good carrier isolation effect.

[0024] In some embodiments, a method for fabricating a laser chip is provided, the method further comprising:

[0025] A fifth trench and a sixth trench are etched at the edge of the isolation region, the bottom of the fifth trench and the bottom of the sixth trench extending to the substrate; the inner edge of the fifth trench connects the first trench and the third trench, and the inner edge of the sixth trench connects the second trench and the fourth trench.

[0026] One of the above technical solutions has the following advantages or beneficial effects: a fifth trench is etched on one side of the isolation region, and a sixth trench is etched on the other side of the isolation region. The fifth and sixth trenches can narrow the isolation region, which makes it easier to ensure the carrier isolation effect of the isolation region.

[0027] In some embodiments, a method for fabricating a laser chip is provided, wherein the bottoms of the first trench and the second trench extend to the top of the first active region; and the bottoms of the third trench and the fourth trench extend to the bottom of the second active region.

[0028] One of the above technical solutions has the following advantages or beneficial effects: the bottom of the first trench and the second trench extends above the first active layer, and the bottom of the third trench and the fourth trench extends below the second active layer, so that the light-emitting area generates light and the modulation area modulates to generate light signals.

[0029] In some embodiments, a method for fabricating a laser chip further includes: forming a first electrode connection layer in the second trench and forming a second electrode connection layer in the fourth trench; the first electrode connection layer connects the first positive electrode and the first positive electrode pad, and the second electrode connection layer connects the second positive electrode and the second positive electrode pad.

[0030] One of the above technical solutions has the following advantages or beneficial effects: A first electrode connection layer is formed in the second trench, one end of the first electrode connection layer is connected to the first positive electrode, and the other end of the first electrode connection layer extends to and is electrically connected to the first positive electrode pad, facilitating the electrical connection between the first positive electrode and the first positive electrode pad. A second electrode connection layer is formed in the fourth trench, one end of the second electrode connection layer is connected to the second positive electrode, and the other end of the second electrode connection layer extends to and is electrically connected to the second positive electrode pad, facilitating the electrical connection between the second positive electrode and the second positive electrode pad.

[0031] In some embodiments, a laser chip is provided, comprising:

[0032] Substrate;

[0033] The light-emitting area is located above one end of the substrate; a first trench and a second trench are formed thereon.

[0034] An isolation region is located above the middle of the substrate, with one end connected to the end of the light-emitting region;

[0035] A modulation region is located above the other end of the substrate, with one end connected to the other end of the isolation region; a third trench and a fourth trench are formed thereon.

[0036] The first positive electrode is located at the top between the first trench and the second trench;

[0037] The second positive electrode is located at the top between the third trench and the fourth trench;

[0038] The first negative electrode pad is located on one side of the second trench;

[0039] The second negative electrode pad is located on one side of the fourth trench;

[0040] A passivation layer covers the light-emitting region, the isolation region, and the modulation region outside the first positive electrode and the second positive electrode;

[0041] The first positive electrode pad is located on the side of the first negative electrode pad and is electrically connected to the first positive electrode.

[0042] The second positive electrode pad is located on the side of the second negative electrode pad and is electrically connected to the second positive electrode.

[0043] One of the above technical solutions has the following advantages or beneficial effects: The light-emitting region has a first trench and a second trench. A first positive electrode is disposed at the top between the first and second trenches. A first negative electrode pad and a first positive electrode pad are disposed on one side of the second trench, and the first positive electrode pad is electrically connected to the first positive electrode. The modulation region has a third trench and a fourth trench. A second positive electrode is disposed at the top between the third and fourth trenches. A second negative electrode pad and a second positive electrode pad are disposed on one side of the fourth trench, and the second positive electrode pad is electrically connected to the second positive electrode. The first positive electrode pad is used to apply a positive current, and the first negative electrode pad is used for grounding, causing the light-emitting region to generate light. The second positive electrode pad can apply a first high-frequency signal, and the second negative electrode pad can apply a second high-frequency signal, facilitating coplanar electrode differential driving and reducing power consumption while achieving the same modulation rate. A passivation layer covers the light-emitting region, isolation region, and modulation region outside the first and second positive electrodes, providing protection against water vapor, scratches, and radiation, thus protecting the light-emitting region, isolation region, and modulation region. The isolation region has high resistance, which prevents charge carriers from entering the other region, thus ensuring that the charge carriers in the light-emitting region and the modulation region do not interfere with each other, thereby guaranteeing the light output quality of the light-emitting region and the modulation signal quality of the modulation region.

[0044] In some embodiments, a laser chip is provided in which the isolation region is formed with a fifth trench and a sixth trench; the outer side of the fifth trench extends to the edge of one side of the laser chip, and the inner edge of the fifth trench connects the first trench and the third trench; the outer side of the sixth trench extends to the edge of the other side of the laser chip, and the inner edge of the sixth trench connects the second trench and the fourth trench.

[0045] One of the above technical solutions has the following advantages or beneficial effects: a fifth trench is etched on one side of the isolation region, and a sixth trench is etched on the other side of the isolation region. The fifth and sixth trenches can narrow the isolation region, which makes it easier to ensure the carrier isolation effect of the isolation region.

[0046] In some embodiments, a laser chip is provided, further comprising a first electrode connection layer and a second electrode connection layer; the first electrode connection layer is located in the second trench and extends to connect the first positive electrode and the first positive electrode pad; the second electrode connection layer is located in the fourth trench and extends to connect the second positive electrode and the second positive electrode pad.

[0047] One of the above technical solutions has the following advantages or beneficial effects: the laser chip further includes a first electrode connection layer and a second electrode connection layer; the first electrode connection layer is laid along the surface of the second trench and is electrically connected to the first positive electrode and the first positive electrode pad, which facilitates the electrical connection between the first positive electrode and the first positive electrode pad; the second electrode connection layer is laid along the surface of the fourth trench and is electrically connected to the second positive electrode and the second positive electrode pad, which facilitates the electrical connection between the second positive electrode and the second positive electrode pad.

[0048] In some embodiments, an optical module is provided, comprising:

[0049] Circuit board;

[0050] The light emitting component is electrically connected to the circuit board;

[0051] The light emitting component includes a laser chip, which is a laser chip prepared by the laser chip preparation method provided in the above embodiments or a laser chip provided in the above embodiments.

[0052] One of the above technical solutions has the following advantages or beneficial effects: the laser chip in the optical emitting component uses the laser chip provided in the above embodiments, which facilitates the optical emitting component to generate optical signals, thereby ensuring the performance of the optical module. Attached Figure Description

[0053] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are merely drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. Furthermore, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0054] Figure 1 This is a partial architecture diagram of an optical communication system according to some embodiments;

[0055] Figure 2 This is a partial structural diagram of a host computer according to some embodiments;

[0056] Figure 3 This is a structural diagram of an optical module according to some embodiments;

[0057] Figure 4 An exploded view of an optical module according to some embodiments;

[0058] Figure 5 This is an exploded view of a light emitting component according to some embodiments;

[0059] Figure 6A This is a structural diagram of a laser chip according to some embodiments;

[0060] Figure 6B A cross-section of a laser chip according to some embodiments Figure 1 ;

[0061] Figure 6C A cross-section of a laser chip according to some embodiments Figure 2 ;

[0062] Figure 7 This is a flowchart of a method for fabricating a laser chip according to some embodiments;

[0063] Figure 8A The fabrication process of a laser chip according to some embodiments Figure 1 ;

[0064] Figure 8B The fabrication process of a laser chip according to some embodiments Figure 2 ;

[0065] Figure 9A This is a cross-sectional view of an etched photoresist according to some embodiments;

[0066] Figure 9B This is a cross-sectional view of another etched photoresist according to some embodiments. Detailed Implementation

[0067] The embodiments of this disclosure will now be described clearly and in detail with reference to the accompanying drawings. However, the described embodiments are merely some, and not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0068] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, meaning "including, but not limited to"; the terms "first" and "second" should not be construed as indicating or implying relative importance or indicating an upper limit on the number; the term "multiple" means two or more; the term "connection" should be interpreted broadly, for example, "connection" can be a fixed connection, a detachable connection, or an integral part, and can be a direct connection or an indirect connection through an intermediate medium; the use of the terms "applicable to" or "configured to" implies open and inclusive language, which does not exclude applicability to or configuration to devices performing additional tasks or steps; descriptions such as "parallel," "perpendicular," "identical," "consistent," and "aligned" are not limited to absolute mathematical theoretical relationships, but also include acceptable error ranges arising in practice, and differences based on the same design concept but due to manufacturing reasons.

[0069] In optical communication technology, to establish information transmission between information processing devices, information needs to be loaded onto light, and the propagation of light is used to transmit the information. Here, the light carrying the information is called an optical signal. When optical signals are transmitted in information transmission equipment, optical power loss can be reduced, thus enabling high-speed, long-distance, and low-cost information transmission. Information processing devices can recognize and process electrical signals. Information processing devices typically include optical network units (ONUs), gateways, routers, switches, mobile phones, computers, servers, tablets, televisions, etc., while information transmission equipment typically includes optical fibers and optical waveguides.

[0070] An optical module enables the conversion between optical and electrical signals between information processing and transmission devices. For example, at least one of the optical signal input or output ports of the optical module is connected to an optical fiber, and at least one of the electrical signal input or output ports is connected to an optical network terminal. A first optical signal from the optical fiber is transmitted to the optical module, which converts it into a first electrical signal and transmits it to the optical network terminal. A second electrical signal from the optical network terminal is transmitted to the optical module, which converts it into a second optical signal and transmits it back to the optical fiber. Since multiple information processing devices can transmit information via electrical signals, at least one of the devices needs to be directly connected to the optical module, rather than all devices. Here, the information processing device directly connected to the optical module is referred to as the host computer of the optical module. Furthermore, the optical signal input or output port of the optical module can be referred to as an optical port, and the electrical signal input or output port can be referred to as an electrical port.

[0071] Figure 1 This is a partial structural diagram of an optical communication system according to some embodiments. Figure 1 As shown, the optical communication system mainly includes a remote information processing device 1000, a local information processing device 2000, a host computer 100, an optical module 200, an optical fiber 101, and a network cable 103.

[0072] One end of optical fiber 101 extends toward the remote information processing device 1000, and the other end of optical fiber 101 is connected to optical module 200 through the optical port of optical module 200. The optical signal can undergo total internal reflection in optical fiber 101, and the propagation of the optical signal in the direction of total internal reflection can almost maintain the original optical power. The optical signal undergoes multiple total internal reflections in optical fiber 101 to transmit the optical signal from the remote information processing device 1000 to optical module 200, or to transmit the optical signal from optical module 200 to remote information processing device 1000, thereby realizing long-distance, low-power loss information transmission.

[0073] The optical communication system may include one or more optical fibers 101, and the optical fibers 101 may be detachably or fixedly connected to the optical module 200. The host computer 100 is configured to provide data signals to the optical module 200, receive data signals from the optical module 200, or monitor or control the operating status of the optical module 200.

[0074] The host computer 100 includes a generally rectangular housing and an optical module interface 102 disposed on the housing. The optical module interface 102 is configured to connect to the optical module 200 so that the host computer 100 and the optical module 200 can establish a one-way or two-way electrical signal connection.

[0075] The host computer 100 also includes an external power interface that can connect to an electrical signal network. For example, this external power interface includes a Universal Serial Bus (USB) interface or a network cable interface 104, which is configured to connect a network cable 103 to establish a unidirectional or bidirectional electrical signal connection between the host computer 100 and the network cable 103. One end of the network cable 103 is connected to the local information processing device 2000, and the other end of the network cable 103 is connected to the host computer 100, thereby establishing an electrical signal connection between the local information processing device 2000 and the host computer 100 via the network cable 103. For example, a third electrical signal emitted by the local information processing device 2000 is transmitted to the host computer 100 via the network cable 103. The host computer 100 generates a second electrical signal based on the third electrical signal. This second electrical signal from the host computer 100 is transmitted to the optical module 200, which converts the second electrical signal into a second optical signal and transmits it to the optical fiber 101. The second optical signal is then transmitted in the optical fiber 101 to the remote information processing device 1000. Alternatively, a first optical signal from the remote information processing device 1000 propagates through the optical fiber 101 and is transmitted to the optical module 200. The optical module 200 converts the first optical signal into a first electrical signal and transmits it to the host computer 100. The host computer 100 generates a fourth electrical signal based on the first electrical signal and transmits the fourth electrical signal to the local information processing device 2000. It should be noted that an optical module is a tool for converting optical signals to electrical signals. During the conversion process, the information itself does not change, but the encoding and decoding methods can change.

[0076] In addition to optical network terminals, the host computer 100 also includes optical line terminals (OLTs), optical network equipment (ONTs), or data center servers.

[0077] Figure 2 This is a partial structural diagram of a host computer according to some embodiments. To clearly show the connection relationship between the optical module 200 and the host computer 100, Figure 2 Only the structure of the host computer 100 related to the optical module 200 is shown. For example... Figure 2 As shown, the host computer 100 also includes a PCB circuit board 105 disposed within the housing, a cage 106 disposed on the surface of the PCB circuit board 105, a heat sink 107 disposed on the cage 106, and an electrical connector disposed inside the cage 106. The electrical connector is configured to connect to the electrical port of the optical module 200; the heat sink 107 has fins and other protruding structures to increase the heat dissipation area.

[0078] The optical module 200 is inserted into the cage 106 of the host computer 100, where it is secured. Heat generated by the optical module 200 is conducted to the cage 106 and then dissipated through the heat sink 107. After insertion into the cage 106, the optical module 200's electrical port connects to an electrical connector inside the cage 106, establishing a bidirectional electrical signal connection between the optical module 200 and the host computer 100. Furthermore, the optical port of the optical module 200 connects to the optical fiber 101, establishing a bidirectional optical signal connection between the optical module 200 and the optical fiber 101.

[0079] Figure 3 This is a structural diagram of an optical module according to some embodiments. Figure 4 This is an exploded view of an optical module according to some embodiments. Figure 3 and Figure 4 As shown, the optical module 200 includes a shell, a circuit board 300 disposed within the shell, a light emitting component 400, and a light receiving component 500. However, this disclosure is not limited thereto; in some embodiments, the optical module 200 includes one of the light emitting component 400 and the light receiving component 500.

[0080] The housing includes an upper housing 201 and a lower housing 202, with the upper housing 201 covering the lower housing 202 to form the aforementioned housing having two openings 203 and 204; the outer contour of the housing is generally square.

[0081] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011, which covers the two lower side plates 2022 of the lower housing 202 to form the aforementioned housing.

[0082] In some embodiments, the lower housing 202 includes a base plate 2021 and two lower side plates 2022 located on both sides of the base plate 2021 and perpendicular to the base plate 2021; the upper housing 201 includes a cover plate 2011 and two upper side plates located on both sides of the cover plate 2011 and perpendicular to the cover plate 2011. The two upper side plates and the two lower side plates 2022 are combined to realize that the upper housing 201 covers the lower housing 202.

[0083] The direction of the line connecting the two openings 203 and 204 can be consistent with or inconsistent with the length direction of the optical module 200. For example, opening 203 is located at the end of the optical module 200. Figure 3 The opening 204 is located at the end of the optical module 200 (left end). Figure 3(The right end). Alternatively, opening 203 is located at the end of optical module 200, while opening 204 is located on the side of optical module 200. Opening 203 is an electrical port, from which the end of circuit board 300 extends and is inserted into the electrical connector of host computer 100; opening 204 is an optical port, configured to connect to external optical fiber 101 so that optical fiber 101 connects optical emitting component 400 and optical receiving component 500 in optical module 200.

[0084] The assembly method using an upper housing 201 and a lower housing 202 facilitates the installation of the circuit board 300, the light emitting component 400, the light receiving component 500, etc., into the aforementioned housings. The upper housing 201 and the lower housing 202 can encapsulate and protect these devices. Furthermore, the assembly of the circuit board 300, the light emitting component 400, and the light receiving component 500 facilitates the deployment of positioning components, heat dissipation components, and electromagnetic shielding components for these devices, which is beneficial for automated production.

[0085] In some embodiments, the upper housing 201 and the lower housing 202 are made of metal materials, which facilitates electromagnetic shielding and heat dissipation.

[0086] In some embodiments, the optical module 200 further includes an unlocking component 600 located outside its housing. The unlocking component 600 is configured to establish a fixed connection between the optical module 200 and the host computer, or to release the fixed connection between the optical module 200 and the host computer.

[0087] For example, the unlocking component 600 is located on the outside of the two lower side plates 2022 of the lower housing 202, and includes a locking component that matches the cage 106 of the host computer 100. When the optical module 200 is inserted into the cage 106, the locking component of the unlocking component 600 fixes the optical module 200 in the cage 106; when the unlocking component 600 is pulled, the locking component of the unlocking component 600 moves accordingly, thereby changing the connection relationship between the locking component and the host computer, so as to release the fixation between the optical module 200 and the host computer, thereby allowing the optical module 200 to be pulled out of the cage 106.

[0088] Circuit board 300 includes circuit traces, electronic components, and chips. The circuit traces connect the electronic components and chips according to the circuit design to achieve functions such as power supply, electrical signal transmission, and grounding. Electronic components may include, for example, capacitors, resistors, transistors, and metal-oxide-semiconductor field-effect transistors (MOSFETs). Chips may include, for example, microcontroller units (MCUs), laser driver chips, transimpedance amplifiers (TIAs), limiting amplifiers (LAs), clock and data recovery chips (CDRs), power management chips, and digital signal processing (DSP) chips.

[0089] Circuit board 300 is generally a rigid circuit board. Due to its relatively hard material, the rigid circuit board can also perform a load-bearing function. For example, the rigid circuit board can stably support the aforementioned electronic components and chips. The rigid circuit board can also be inserted into the electrical connector in the cage 106 of the host computer 100.

[0090] The circuit board 300 also includes gold fingers formed on its end surfaces, each gold finger consisting of a plurality of independent pins. The circuit board 300 is inserted into a cage 106 and is electrically connected to an electrical connector within the cage 106 by the gold fingers. The gold fingers may be located only on one side of the surface of the circuit board 300 (e.g., ...). Figure 4 The upper surface shown can also be positioned on the upper and lower surfaces of the circuit board 300 to provide a greater number of pins, thus adapting to applications with high pin count requirements. The gold fingers are configured to establish an electrical connection with the host computer to achieve power supply, grounding, two-wire synchronous serial (Inter-Integrated Circuit, I2C) signal transmission, and data signal transmission. Of course, flexible circuit boards are also used in some optical modules. Flexible circuit boards are generally used in conjunction with rigid circuit boards as a supplement to rigid circuit boards.

[0091] At least one of the light emitting component 400 or the light receiving component 500 is located on the side of the circuit board 300 away from the gold fingers.

[0092] In some embodiments, the light emitting component 400 and the light receiving component 500 are physically separated from the circuit board 300, and then electrically connected to the circuit board 300 through corresponding flexible circuit boards or electrical connectors.

[0093] In some embodiments, at least one of the light emitting component 400 or the light receiving component 500 may be directly disposed on the circuit board 300. For example, at least one of the light emitting component 400 or the light receiving component 500 may be disposed on the surface of the circuit board 300 or the side of the circuit board 300.

[0094] In some embodiments, the light emitting component 400 may include a cavity, in which an electrical device for generating emitted light signals and an optical device for transmitting emitted light signals are disposed; wherein the electrical device includes a laser, etc., and the optical device includes a collimating lens, etc.

[0095] In some embodiments, the light receiving component 500 may include a cavity, in which an optical device for transmitting received light signals and an electrical device for converting received light signals are disposed; wherein the optical device includes a converging lens, etc., and the electrical device includes a photodetector, etc.

[0096] In some embodiments, the light emitting component 400 and the light receiving component 500 may share a cavity, such as a double-layer cavity, with one layer for the light emitting component 400 and the other layer for the light receiving component 500.

[0097] In some embodiments, the light emitting component 400 and the light receiving component 500 may not share a cavity, and the light emitting component 400 and the light receiving component 500 may be independent of each other and may be disposed on the same side of the circuit board 300. Of course, in this embodiment of the present disclosure, the light emitting component 400 and the light receiving component 500 may also be disposed on different sides of the circuit board 300.

[0098] In some embodiments, the light emitting component 400 can generate light signals of multiple wavelengths. For example, the light emitting component 400 can generate a beam of light signal including four wavelengths.

[0099] Figure 5 This is an exploded view of a light emitting component according to some embodiments. Figure 5 A structure for a light-emitting component that generates four light signals is shown. For example... Figure 5 As shown, in some embodiments, the light emitting component 400 includes four laser components 400a arranged in an array; wherein, each laser component 400a includes a substrate and a laser chip, and the laser chip generates a light signal of a certain wavelength, and the laser chip is disposed on the substrate.

[0100] In some embodiments, a ceramic substrate is used as the substrate, and the laser chip is eutectic bonded to the ceramic substrate. Four laser components 400a are arranged in an array, and a preset spacing must be maintained between adjacent laser components 400a, which places high demands on the assembly of the laser components 400a.

[0101] In some embodiments, to ensure the coupling efficiency of the optical signal generated by the laser component 400a, a lens is provided in the output optical path of the laser component 400a, and the assembly accuracy of the lens is required to be high. To ensure the assembly accuracy of the lens, the lens is usually placed in the output optical path of the corresponding laser component 400a by active coupling.

[0102] In some embodiments, the light emitting component 400 includes a cavity 401, in which a laser assembly 400a is disposed. Exemplarily, an opening is provided on one side wall of the cavity 401 for insertion of a circuit board 300; the circuit board 300 extending into the cavity is electrically connected to the laser assembly 400a.

[0103] In some embodiments, the light emitting component 400 includes a cover plate 402 that covers the connecting cavity 401.

[0104] In some embodiments, the laser component 400a includes a laser chip and a substrate. A circuit pattern is formed on the surface of the substrate. For example, transmission lines, pads, etc., are provided on the top surface of the substrate. The laser chip is disposed on the substrate, and the laser chip is connected to a corresponding circuit pattern on the substrate to supply power or input high-frequency signals, etc., to the laser chip through the substrate.

[0105] Figure 6A This is a structural diagram of a laser chip according to some embodiments. Figure 6B A cross-section of a laser chip according to some embodiments Figure 1 , Figure 6C A cross-section of a laser chip according to some embodiments Figure 2 ;in, Figure 6B It shows Figure 6A Cross-sectional structure in the x-direction, Figure 6C It shows Figure 6A Cross-sectional structure in the y-direction. For example... Figures 6A-6C As shown, in some embodiments, the laser chip 400b includes a substrate 410. The substrate 410 may be a substrate such as Si or SiO2.

[0106] In some embodiments, a light-emitting region, a modulation region, and an electrically isolated region located between the light-emitting region and the modulation region are formed on the substrate 410. The electrically isolated region is used to increase the impedance between the light-emitting region and the modulation region. Both the light-emitting region and the modulation region have electrodes on their tops. When the laser chip 400b is working, the light-emitting region reflects light based on the applied positive current and transmits it to the modulation region; the light entering the modulation region is modulated by an AC signal to obtain an optical signal with a data signal. Due to the high impedance of the isolation region, when the light-emitting region and the modulation region are simultaneously energized, charge carriers will not be able to enter each other's regions through the isolation region, so that the charge carriers of the light-emitting region and the modulation region do not interfere with each other, thereby ensuring the light output quality of the light-emitting region and the modulation signal quality of the modulation region.

[0107] In some embodiments, the light-emitting region includes a first N-type InP layer 421. A substrate 410 supports and connects to the first N-type InP layer 421. The first N-type InP layer 421 is an N-type doped semiconductor, such as doped Si or S.

[0108] In some embodiments, a first active layer 431 is disposed above the first N-type InP layer 421, and the first active layer 431 can be used to generate light of a specific wavelength.

[0109] In some embodiments, the first active layer 431 may include a first quantum well layer. The first quantum well layer may be disposed above the first N-type InP layer 421 and be in surface contact with the first N-type InP layer 421. The first quantum well layer may include InGaAsP or InAlGaAs multilayer quantum well material.

[0110] In some embodiments, the first active layer 431 may include a grating layer. The grating layer may be disposed above and contacted with the first quantum well layer. The grating layer is used to select light of a specific wavelength from the light emitted from the first quantum well layer. The grating layer may be a Bragg grating. By changing the current injected into the grating layer, the effective refractive index of the grating layer can be changed, thereby changing the resonant lasing wavelength of the grating layer, thus achieving the selection of a specific wavelength.

[0111] In some embodiments, a first P-type InP layer 441 is disposed above the first active layer 431. The first P-type InP layer 441 is a P-type doped semiconductor, such as a doped divalent element.

[0112] In some embodiments, a first contact layer 451 is disposed above the first P-type InP layer 441. The first contact layer 451 is used to facilitate the transmission of received electrical signals to the first P-type InP layer 441. The first contact layer 451 may be a highly doped P-type InGaAs material to achieve good ohmic contact with the electrode metal.

[0113] In some embodiments, a first trench 461a and a second trench 462a are formed on the light-emitting area. The bottom of the first trench 461a and the bottom of the second trench 462a extend above the first active layer 431.

[0114] In some embodiments, the first N-type InP layer 421 and the first P-type InP layer 441 form a PN junction. The concentration difference of charge carriers causes diffusion, resulting in the first P-type InP layer 441 containing holes and negative ions, and the first N-type InP layer 421 containing electrons and positive ions. Based on the principle of charge, holes are driven downward into the first quantum well layer, and electrons are driven upward into the first quantum well layer. Within the first quantum well layer, stimulated emission causes discrete electron-hole pairs to recombine and generate photons, thereby effectively converting electrically injected charge carriers into photons and generating gain light. The photons generated by recombination within the first quantum well layer are reflected by the resonant cavity or distributed feedback grating to form positive feedback, thereby generating lasing light.

[0115] In some embodiments, the modulation region includes a second N-type InP layer 422. The substrate 410 supports and connects to the second N-type InP layer 422. The second N-type InP layer 422 is an N-type doped semiconductor, such as doped Si or S.

[0116] In some embodiments, a second active layer 432 is disposed above the second N-type InP layer 422. The second active layer 432 can absorb light to modulate the output optical signal.

[0117] In some embodiments, the second active layer 432 may include a second quantum well layer. The second quantum well layer may be disposed above the second N-type InP layer 422 and contacted with the top surface of the second N-type InP layer. The second quantum well layer is generally made of InGaAsP or InAlGaAs multilayer quantum well material to absorb light and achieve light modulation. A quantum well is formed in a normal semiconductor material by inserting a narrow bandgap material between two wide bandgap materials to increase band gaps, thereby restricting the movement of electrons and holes.

[0118] In some embodiments, a second P-type InP layer 442 is disposed above the second active layer 432. The second P-type InP layer 442 is a P-type doped semiconductor, such as a doped with a divalent element.

[0119] In some embodiments, a second contact layer 452 is disposed above the second P-type InP layer 442. The second contact layer 452 is used to facilitate the transmission of received electrical signals to the second P-type InP layer 442. The second contact layer 452 may be a highly doped P-type InGaAs material to achieve good ohmic contact with the electrode metal.

[0120] In some embodiments, a third trench 461b and a fourth trench 462b are formed on the modulation region. The bottom of the third trench 461b and the bottom of the fourth trench 462b extend below the second active layer 432.

[0121] In some embodiments, the first groove 461a is flush with the third groove 461b, and the second groove 462a is flush with the fourth groove 462b.

[0122] In some embodiments, the second N-type InP layer 422 and the second P-type InP layer 442 form a PN junction. When light reaches the second quantum well layer, a photovoltaic effect occurs, generating electron-hole pairs. When there is no external electric field, the band gap is greater than the photon's energy, so photons cannot be absorbed and pass through with low loss. However, when the external electric field increases, the band structure tilts, the energy difference between the conduction and valence bands decreases, becoming less than the photon's energy. Light then absorbs photons and generates electron-hole pairs, thereby changing the light intensity, i.e., modulating the light. Conversely, when the external electric field decreases or becomes zero, the band structure recovers, the band gap increases, and light can pass through the material with low loss, reducing absorption.

[0123] In some embodiments, the isolation region includes a first electrical isolation layer 471. The first electrical isolation layer 471 is an N-type InP layer doped with a first element. The first element in the first electrical isolation layer 471 can form deep-level defects, causing charge carriers to recombine in the first electrical isolation layer 471, thereby increasing the resistivity of the first electrical isolation layer 471. This prevents charge carriers from passing through the first electrical isolation layer 471 to enter the first N-type InP layer 421 or from passing through the first electrical isolation layer 471 to enter the second N-type InP layer 422. The first element can be boron, helium, or iron, etc. The first electrical isolation layer 471 can be formed by ion implantation of an N-type InP layer.

[0124] In some embodiments, a conductive layer 472 is disposed above the first electrical isolation layer 471, and the first electrical isolation layer 471 supports and connects to the conductive layer 472. One end of the conductive layer 472 is connected to the first active layer 431, and the other end of the conductive layer 472 is connected to the second active layer 432. The conductive layer 472 may be formed of InGaAsP and is used to transmit the light generated by the first active layer 431 to the second active layer 432.

[0125] In some embodiments, a second electrical isolation layer 473 is disposed above the conductive layer 472, and the conductive layer 472 supports and connects to the second electrical isolation layer 473. Exemplarily, one end of the second electrical isolation layer 473 is connected to a first P-type InP layer 441, and the other end of the second electrical isolation layer 473 is connected to a second N-type InP layer 422. The second electrical isolation layer 473 may be a P-type InP layer doped with a first element.

[0126] In some embodiments, a fifth trench 474 and a sixth trench 475 are formed on the isolation region. The fifth trench 474 is located at the edge of one side of the isolation region, and the sixth trench 475 is located at the edge of the other side of the isolation region. The bottom of the fifth trench 474 and the bottom of the sixth trench 475 extend to the substrate. The fifth trench 474 isolates the light-emitting region and the modulation region on one side of the laser chip, and the inner edge of the fifth trench 474 connects the first trench 461a and the third trench 461b. The sixth trench 475 isolates the light-emitting region and the modulation region on the other side of the laser chip, and the inner edge of the sixth trench 475 connects the second trench 462a and the fourth trench 462b. Exemplarily, the inner edge of the fifth trench 474 is flush with the side of the first trench 461a near the second trench 462a, and the inner edge of the sixth trench 475 is flush with the side of the second trench 462a near the first trench 461a.

[0127] In some embodiments, a first positive electrode 491 is formed on a first contact layer 451 between the first trench 461a and the second trench 462a. A first positive pad 492 and a first negative pad 493 are formed above the first contact layer 451 on the side of the first trench 461a away from the second trench 462a or the side of the second trench 462a away from the first trench 461a. The first positive pad 492 is electrically connected to the first positive electrode 491, and the first negative pad 493 is insulated from the first positive pad 492. The first positive pad 492 is used to apply a positive current, and the first negative pad 493 is used to ground. The positive current sequentially passes through the first positive pad 492, the first positive electrode 491, and the first contact layer 451 into the first P-type InP layer 441.

[0128] In some embodiments, a second positive electrode 494 is formed on the second contact layer 452 between the third trench 461b and the fourth trench 462b. A second positive electrode pad 495 and a second negative electrode pad 496 are formed above the second contact layer 452 on the side of the third trench 461b away from the fourth trench 462b or the side of the fourth trench 462b away from the third trench 461b. The second positive electrode pad 495 is electrically connected to the second positive electrode 494, and the second negative electrode pad 496 is insulated from the second positive electrode pad 495. A first high-frequency signal can be applied to the second positive electrode pad 495, and a second high-frequency signal can be applied to the second negative electrode pad 496. The first high-frequency signal can sequentially pass through the second positive electrode pad 495, the second positive electrode 494, and the second contact layer 452 to enter the second P-type InP layer 442, and the second high-frequency signal can sequentially pass through the second negative electrode pad 496 and the second negative electrode to enter the second P-type InP layer 442, realizing coplanar electrode differential driving, which facilitates reducing power consumption while achieving the same modulation rate.

[0129] In some embodiments, the laser chip 400b may include a passivation layer 480, which covers the surfaces of the first trench 461a, the second trench 462a, the isolation region, the third trench 461b, and the fourth trench 462b. Exemplarily, the passivation layer 480 of the light-emitting region covers the first contact layer 451 on the sides of the first trench 461a and the second trench 462a; the passivation layer 480 of the modulation region covers the second contact layer 452 on the sides of the third trench 461b and the fourth trench 462b. The passivation layer 480 is waterproof, scratch-resistant, and radiation-resistant, thus protecting the light-emitting region, the isolation region, and the modulation region.

[0130] In some embodiments, a first positive electrode pad 492 is disposed on a passivation layer 480, such that the first positive electrode pad 492 does not contact the first contact layer 451; a first negative electrode pad 493 contacts and connects to the first contact layer 451. Exemplarily, the first contact layer 451 supports and connects to the first negative electrode pad 493, and the passivation layer 480 surrounds the side of the first negative electrode pad 493.

[0131] In some embodiments, a first electrode connection layer 497 may be disposed on the passivation layer 480. One end of the first electrode connection layer 497 is connected to the first positive electrode 491, and the other end of the first electrode connection layer 497 is connected to the first positive electrode pad 492. The first electrode connection layer 497 extends from the trench of the first trench 461a or the second trench 462a toward the first positive electrode pad 492. Of course, in some embodiments, the first electrode connection layer 497 may extend across the top of the first trench 461a or the second trench 462a toward the first positive electrode pad 492.

[0132] In some embodiments, a second positive electrode pad 495 is disposed on a passivation layer 480, such that the second positive electrode pad 495 does not contact the second contact layer 452; a second negative electrode pad 496 contacts and connects to the second contact layer 452. Exemplarily, the second contact layer 452 supports and connects to the second negative electrode pad 496, and the passivation layer 480 surrounds the side of the second negative electrode pad 496.

[0133] In some embodiments, a second electrode connection layer 498 may be disposed on the passivation layer 480. One end of the second electrode connection layer 498 is connected to the second positive electrode 494, and the other end of the second electrode connection layer 498 is connected to the second positive electrode pad 495. The second electrode connection layer 498 extends from the trench of the third trench 461b or the fourth trench 462b toward the second positive electrode pad 495. Of course, in some embodiments, the second electrode connection layer 498 may extend across the top of the third trench 461b or the fourth trench 462b toward the second positive electrode pad 495.

[0134] Figure 7 This is a flowchart illustrating a method for fabricating a laser chip according to some embodiments. Figure 7As shown, in some embodiments, the method for fabricating the laser chip includes:

[0135] S100: A light-emitting region, an isolation region, and a modulation region are formed above a substrate, wherein the isolation region connects the light-emitting region and the modulation region; wherein: the light-emitting region has a first trench and a second trench, and the modulation region has a third trench and a fourth trench.

[0136] In some embodiments, a light-emitting region is formed above one end of the substrate 410, an isolation region is formed above the middle of the substrate 410, and a modulation region is formed above the other end of the substrate 410. One end of the isolation region is connected to the light-emitting region, and the other end of the isolation region is connected to the modulation region.

[0137] Figure 8A The fabrication process of a laser chip according to some embodiments Figure 1 , Figure 8B The fabrication process of a laser chip according to some embodiments Figure 2 .like Figure 8A and Figure 8B As shown, in some embodiments, an N-type InP layer 420 is grown on substrate 410 by metal-organic chemical vapor deposition (MOCVD). Substrate 410 may be a SiO2 substrate.

[0138] In some embodiments, a first element is implanted in the middle of the N-type InP layer 420 to form a first electrical isolation layer 471. The first electrical isolation layer 471 divides the N-type InP layer 420 into a first N-type InP layer 421 and a second N-type InP layer 422. The first N-type InP layer 421 is located at one end of the first electrical isolation layer 471, and the second N-type InP layer 422 is located at the other end of the first electrical isolation layer 471. The first electrical isolation layer 471 connects the first N-type InP layer 421 and the second N-type InP layer 422. The first element may be boron, helium, or iron, etc.

[0139] In some embodiments, a first active layer 431 is grown and formed above the first N-type InP layer 421. Exemplarily, a first quantum well layer is formed above the first N-type InP layer 421, and a grating layer is formed on the first quantum well layer. The first active layer 431 can emit light of a specific wavelength, enabling the laser chip to emit light of that specific wavelength.

[0140] In some embodiments, the first quantum well layer may include InGaAsP or InAlGaAs multilayer quantum well material. A protective layer is coated on the first quantum well layer, a grating pattern is fabricated on the protective layer by holographic exposure, and the grating pattern on the protective layer is transferred to the grating layer using wet etching or dry etching processes. The protective layer on the surface of the substrate wafer is then removed to form a grating layer with the grating pattern.

[0141] In some embodiments, a second active layer 432 is grown above the second N-type InP layer 422. The second active layer 432 may include a second quantum well layer, which may be disposed above the second N-type InP layer 422 and contacted with the top surface of the second N-type InP layer. The second quantum well layer is generally made of InGaAsP or InAlGaAs multilayer quantum well material to absorb light and achieve light modulation.

[0142] In some embodiments, a conductive layer 472 is grown and formed above the first electrical isolation layer 471. The conductive layer 472 may be formed using InGaAsP. One end of the conductive layer 472 is connected to the first active layer 431, and the other end of the conductive layer 472 is connected to the second active layer 432. Light generated by the first active layer 431 is transmitted to the second active layer 432 through the conductive layer 472.

[0143] In some embodiments, a P-type InP layer 440 is formed over the first active layer 431, the first electrical isolation layer 471, and the second active layer 432. The P-type InP layer 440 covers the top of the first active layer 431, the top of the first electrical isolation layer 471, and the top of the second active layer 432.

[0144] In some embodiments, a first contact layer 451 and a second contact layer 452 are grown and formed above a p-type InP layer 440. The projection of the first contact layer 451 in the direction of the first active layer 431 covers the first active layer 431, such that the first contact layer 451 is directly above the first active layer 431; the projection of the second contact layer 452 in the direction of the second active layer 432 covers the second active layer 432, such that the second contact layer 452 is directly above the second active layer 432. The first contact layer 451 and the second contact layer 452 may be formed using a p-type InGaAs material with a high doping concentration.

[0145] In some embodiments, a contact layer 450 is grown and formed over a P-type InP layer 440, covering the P-type InP layer 440. The contact layer 450 above the conductive layer 472 is removed to divide the contact layer 450 into a first contact layer 451 and a second contact layer 452. The first contact layer 451 is located directly above the first active layer 431, and the second contact layer 452 is located directly above the second active layer 432.

[0146] In some embodiments, a first trench 461a and a second trench 462a are etched onto the first contact layer 451. Exemplarily, the bottom of the first trench 461a extends over the first active layer 431, and the bottom of the second trench 462a extends over the first active layer 431. The first trench 461a and the second trench 462a extend in a direction from the first contact layer 451 to the second contact layer 452. A gap is provided between the first trench 461a and the second trench 462a to form a waveguide structure between the first trench 461a and the second trench 462a.

[0147] In some embodiments, a third trench 461b and a fourth trench 462b are etched onto the second contact layer 452. Exemplarily, the bottom of the third trench 461b extends below the second active layer 432, and the bottom of the fourth trench 462b extends below the second active layer 432. The third trench 461b and the fourth trench 462b extend along the direction from the second contact layer 452 to the first contact layer 451. A gap is provided between the third trench 461b and the fourth trench 462b to form a waveguide structure between them.

[0148] In some embodiments, a fifth trench 474 and a sixth trench 475 are etched between the first contact layer 451 and the second contact layer 452, and the fifth trench 474 and the sixth trench 475 are not connected. The bottom of the fifth trench 474 extends over the substrate 410, and the outer edge of the fifth trench 474 extends to the edge of one side of the substrate 410; the bottom of the sixth trench 475 extends over the substrate 410, and the outer edge of the sixth trench 475 extends to the edge of the other side of the substrate 410. Exemplarily, the fifth trench 474 may connect to the first trench 461a and the third trench 461b, and the sixth trench 475 may connect to the second trench 462a and the fourth trench 462b. The fifth trench 474 and the sixth trench 475 may narrow the isolation area.

[0149] In some embodiments, the two ends of the inner edge of the fifth groove 474 extend to the first groove 461a and the third groove 461b, and the two ends of the inner edge of the sixth groove 475 extend to the second groove 462a and the fourth groove 462b.

[0150] S200: A passivation layer is deposited on the surface of the light-emitting region, the isolation region and the modulation region, and photoresist is covered on the passivation layer.

[0151] A passivation layer 480 is deposited on the surface of the light-emitting region, the isolation region, and the modulation region, and photoresist 490 is covered on the passivation layer 480. The passivation layer 480 and the photoresist 490 cover the top surface of the first contact layer 451, the surface of the first trench 461a, the surface of the second trench 462a, the top surface of the second contact layer 452, the surface of the third trench 461b, the surface of the fourth trench 462b, the surface of the fifth trench 474, and the surface of the sixth trench 475, etc.

[0152] S300: Use a preset mask to cover the photoresist and form a preset pattern through exposure.

[0153] A preset mask is used to cover the photoresist 490, and exposure is performed to create a preset pattern on the photoresist. This preset pattern is used to assist in creating a window on the passivation layer.

[0154] S400: Based on the preset pattern, the passivation layer is etched by reactive ion etching to open a first window, a second window, a third window, and a fourth window on the passivation layer; wherein, the first window is located between the first trench and the second trench, the second window is located on one side of the first trench or the second trench, the third window is located between the third trench and the fourth trench, and the fourth window is located on one side of the third trench or the fourth trench.

[0155] Based on the preset pattern on the photoresist, windows are created on the passivation layer 480 using reactive ion etching (RIE) to complete the passivation protection layer pattern fabrication.

[0156] In some embodiments, a first window 481 and a second window 482 are formed on a passivation layer above the light-emitting region, and a third window 483 and a fourth window 484 are formed on a passivation layer above the modulation region, based on a preset pattern on the photoresist. The first window 481 is located between a first trench 461a and a second trench 462a, with its bottom extending to the top of the first contact layer 451. The third window 483 is located between a third trench 461b and a fourth trench 462b, with its bottom extending to the top of the second contact layer 452. The second window 482 is located on the side of either the first trench 461a or the second trench 462a, with its bottom extending to the top of the first contact layer 451. The fourth window 484 is located on the side of either the third trench 461b or the fourth trench 462b, with its bottom extending to the top of the second contact layer 452. For example, the second window 482 is located on the side of the second groove 462a, and the fourth window 484 is located on the side of the fourth groove 462b.

[0157] In some embodiments, the reactive ion etching apparatus may use a mixture of Ar and the corrosive gases CHF3, CF4, or SF6. During the etching of the passivation layer, the etching product contains a large amount of polymer, which in turn contains a significant amount of C, F, and Al elemental byproducts. These C, F, and Al byproducts adhere to the surfaces of the photoresist, windows created in the passivation layer, etc. The adhesion of these C, F, and Al byproducts to the photoresist causes excessive deposition at the contact points between the photoresist and the chip surface, making the photoresist difficult to remove. This ultimately results in filamentous photoresist residue on the chip surface, affecting the performance of the laser chip. The deposition of C, F, and Al byproducts on the chip surface will affect subsequent chip processing and chip performance.

[0158] In some embodiments, the reactive ion etching apparatus may use a mixture of Ar and O2 in the etching gas CHF3, CF4, or SF6. Exemplarily, the etching gas includes CHF3, Ar, and O2, or SF6, Ar, and O2, or CHF3, CF4, Ar, and O2, etc. Adding O2 to the etching gas allows the polymer generated during the etching process to react with O2, increasing the etching rate of the photoresist and resulting in a faster rate of lateral etching. This leads to a smaller sidewall tilt angle of the photoresist during etching. Furthermore, during the reaction between the polymer and O2, the byproducts of C, F, and Al elements in the polymer react with O2 to form C, F, and Al oxides, which reduces polymer adhesion. This allows the etching products to be removed by the reactive ion etching apparatus, preventing deposition on the chip surface or sidewalls.

[0159] In some embodiments, the weight percentage of O2 in the corrosive gas is less than or equal to 20%. Adding O2 to the corrosive gas does not significantly reduce the etching rate of the composite film, ensuring a shorter etching process time while reducing the risk of photoresist denaturation and hardening, making the photoresist easier to remove. For example, the weight ratio of the corrosive gas components CHF3:Ar:O2 = 2:2:1.

[0160] Figure 9A This is a cross-sectional view of an etched photoresist according to some embodiments. Figure 9B This is a cross-sectional view of another etched photoresist according to some embodiments; wherein, Figure 9A The cross-section shown represents the structure produced when no O2 was added to the corrosive gas. Figure 9B The cross-section shown represents the structure produced when O2 is added to a corrosive gas. For example... Figure 9A and Figure 9B As shown, in some embodiments, adding O2 to the corrosive gas used in the reactive ion etching apparatus can accelerate the rate of lateral etching of the photoresist and reduce the sidewall tilt angle of the photoresist.

[0161] S500: A first positive electrode is formed in the first window, a first negative electrode pad is formed in the second window, a first positive electrode pad is formed on the side of the first negative electrode pad, a second positive electrode is formed in the third window, a second negative electrode pad is formed in the fourth window, and a second positive electrode pad is formed on the side of the second negative electrode pad. The first positive electrode pad is electrically connected to the first positive electrode, and the second positive electrode pad is electrically connected to the second positive electrode.

[0162] The photoresist on the passivation layer 480 is removed, and a first positive electrode 491 is formed in the first window 481, a first negative electrode pad 493 is formed in the second window 482, a second positive electrode 494 is formed in the third window 483, and a second negative electrode pad 496 is formed in the fourth window 484. The first positive electrode pad 492 is formed on the passivation layer 480 on one side of the second trench 462a, and the second positive electrode pad 495 is formed on the passivation layer 480 on one side of the fourth trench 462b. The first positive electrode 491 is electrically connected to the first positive electrode pad 492, and the second positive electrode 494 is electrically connected to the second positive electrode pad 495. Exemplarily, the first positive electrode pad 492 is located next to the first negative electrode pad 493, and the second positive electrode pad 495 is located next to the second negative electrode pad 496.

[0163] In some embodiments, a first electrode connection layer 497 is formed in the second trench 462a. One end of the first electrode connection layer 497 is connected to the first positive electrode 491, and the other end of the first electrode connection layer 497 extends to the side of the first positive electrode pad 492. The other end of the first electrode connection layer 497 is electrically connected to the first positive electrode pad 492.

[0164] In some embodiments, a second electrode connection layer 498 is formed in the fourth trench 462b. One end of the second electrode connection layer 498 is connected to the second positive electrode 494, and the other end of the second electrode connection layer 498 extends to the side of the second positive electrode pad 495. The other end of the second electrode connection layer 498 is electrically connected to the second positive electrode pad 495.

[0165] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a laser chip, characterized in that, include: A light-emitting region, an isolation region, and a modulation region are formed above a substrate, wherein the isolation region connects the light-emitting region and the modulation region; wherein the light-emitting region has a first trench and a second trench, and the modulation region has a third trench and a fourth trench; A passivation layer is deposited on the surface of the light-emitting region, the isolation region, and the modulation region, and photoresist is coated on the passivation layer; The photoresist is covered by a preset mask and a preset pattern is formed by exposure. Based on the preset pattern, the passivation layer is etched by reactive ion etching to open a first window, a second window, a third window, and a fourth window on the passivation layer; wherein the corrosive gas includes O2, the first window is located between the first trench and the second trench, the second window is located on one side of the first trench or the second trench, the third window is located between the third trench and the fourth trench, and the fourth window is located on one side of the third trench or the fourth trench; A first positive electrode is formed in the first window, a first negative electrode pad is formed in the second window, a first positive electrode pad is formed on the side of the first negative electrode pad, a second positive electrode is formed in the third window, a second negative electrode pad is formed in the fourth window, and a second positive electrode pad is formed on the side of the second negative electrode pad. The first positive electrode pad is electrically connected to the first positive electrode, and the second positive electrode pad is electrically connected to the second positive electrode.

2. The preparation method according to claim 1, characterized in that, The corrosive gas also includes CHF3 and Ar, and the weight ratio of the components of the corrosive gas is CHF3:Ar:O2 = 2:2:

1.

3. The preparation method according to claim 1, characterized in that, A light-emitting region, an isolation region, and a modulation region are formed above the substrate, including: An N-type InP layer is grown on the substrate; A first element is implanted in the middle of the N-type InP layer to form a first electrically isolated layer, which divides the N-type InP layer into a first N-type InP layer and a second N-type InP layer. A first active layer is grown on top of the first N-type InP layer; A conductive layer is grown on the first electrically isolated layer; A second active layer is grown on top of the second N-type InP layer; wherein one end of the conductive layer is connected to the first active layer, and the other end of the conductive layer is connected to the second active layer; A P-type InP layer is grown, which covers the top of the first active layer, the conductive layer, and the second active layer; A first contact layer and a second contact layer are grown on the P-type InP layer. The projection of the first contact layer in the direction of the first active layer covers the first active layer, and the projection of the second contact layer in the direction of the second active layer covers the second active layer. The etching process forms the first, second, third, and fourth trenches.

4. The preparation method according to claim 3, characterized in that, The method further includes: A fifth trench and a sixth trench are etched at the edge of the isolation region, the bottom of the fifth trench and the bottom of the sixth trench extending to the substrate; the inner edge of the fifth trench connects the first trench and the third trench, and the inner edge of the sixth trench connects the second trench and the fourth trench.

5. The preparation method according to claim 3, characterized in that, The bottoms of the first trench and the second trench extend to the top of the first active region; the bottoms of the third trench and the fourth trench extend to the bottom of the second active region.

6. The preparation method according to claim 3, characterized in that, Also includes: A first electrode connection layer is formed in the second trench and a second electrode connection layer is formed in the fourth trench; The first electrode connection layer connects the first positive electrode and the first positive electrode pad, and the second electrode connection layer connects the second positive electrode and the second positive electrode pad.

7. A laser chip, characterized in that, include: Substrate; The light-emitting area is located above one end of the substrate; a first trench and a second trench are formed thereon. An isolation region is located above the middle of the substrate, with one end connected to the end of the light-emitting region; The modulation region is located above the other end of the substrate, with one end connected to the other end of the isolation region; It forms a third and a fourth groove; The first positive electrode is located at the top between the first trench and the second trench; The second positive electrode is located at the top between the third trench and the fourth trench; The first negative electrode pad is located on one side of the second trench; The second negative electrode pad is located on one side of the fourth trench; A passivation layer covers the light-emitting region, the isolation region, and the modulation region outside the first positive electrode and the second positive electrode; The first positive electrode pad is located on the side of the first negative electrode pad and is electrically connected to the first positive electrode. The second positive electrode pad is located on the side of the second negative electrode pad and is electrically connected to the second positive electrode.

8. The laser chip according to claim 7, characterized in that, The isolation area is formed with a fifth trench and a sixth trench; the outer side of the fifth trench extends to the edge of one side of the laser chip, and the inner edge of the fifth trench connects the first trench and the third trench; the outer side of the sixth trench extends to the edge of the other side of the laser chip, and the inner edge of the sixth trench connects the second trench and the fourth trench.

9. The laser chip according to claim 7, characterized in that, It also includes a first electrode connection layer and a second electrode connection layer; the first electrode connection layer is located in the second trench and extends to connect the first positive electrode and the first positive electrode pad; the second electrode connection layer is located in the fourth trench and extends to connect the second positive electrode and the second positive electrode pad.

10. An optical module, characterized in that, include: Circuit board; The light emitting component is electrically connected to the circuit board; The light emitting component includes a laser chip, which is a laser chip prepared by the method of any one of claims 1-6 or a laser chip according to any one of claims 7-9.

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