A small-capacitance high-speed laser

Abstract

This invention proposes a high-speed laser with small capacitance, belonging to the field of semiconductor optoelectronic device manufacturing technology. It addresses the core problem of excessive parasitic capacitance in high-speed lasers, which leads to insufficient modulation bandwidth and degraded high-frequency performance. The laser comprises, from bottom to top, a bottom electrode, a substrate, an epitaxial layer, and a top electrode. The epitaxial layer integrates a quantum well active region, a Bragg grating, and a ridge waveguide. An insulating dielectric layer with an injection window is located at the top. The top electrode includes a ridge-mounted injection electrode and a bonding pad. The ridge-mounted injection electrode makes direct ohmic contact with the contact layer through the injection window. The key feature is the separate 4-8 μm thick dielectric isolation layer between the insulating dielectric layer and the epitaxial layer below the bonding pad. The material is selected from one or more of SiO2, PI, and SiN, providing five dielectric isolation layer schemes: single-layer SiO2, multi-layer SiO2, SiO2 pillar + PI, multi-layer PI stack, and SiO2 / SiN / PI multi-layer intercalation. By introducing a low-dielectric-constant, thick dielectric layer below the high-speed laser electrode, the distance between the electrode and the substrate is significantly increased, reducing parasitic capacitance. This invention does not require changes to the active region structure and core process of the EML / DML chip. It only optimizes the dielectric layer preparation and patterning process to reduce the parasitic capacitance to below 50fF, thus meeting the application requirements of 10G / 50G / 100G / 200G high-speed optical communication.

Description

Technical Field

[0001] This invention belongs to the technical field of semiconductor optoelectronic devices, specifically relating to an InP-based small-capacitance ridge waveguide laser for high-speed optical communication, suitable for high-speed light source devices such as EML electro-absorption modulated lasers and DML direct modulated lasers. Background Technology

[0002] In recent years, the explosive growth of cloud computing, big data, and AI big data models has driven a continuous surge in global data traffic, pushing the transmission capacity and speed of optical communication systems to new heights. Among these, high-speed electro-absorption modulated lasers (EMLs) and direct-modulated lasers (DMLs), with their advantages of high modulation rates, low power consumption, and small size, have become core light sources for 5G / 6G communications, data center interconnects, and fiber optic access networks. Currently, single-channel optical communication rates are rapidly evolving from 25G / 50G to 100G / 200G and even 400G, placing higher demands on the modulation bandwidth, high-frequency response, and signal integrity of lasers.

[0003] For high-speed lasers, modulation bandwidth is the core indicator determining their maximum transmission rate. Besides intrinsic factors such as carrier recombination time, parasitic parameters are the main bottleneck restricting the improvement of modulation bandwidth, with parasitic capacitance being the most influential factor. Parasitic capacitance mainly includes three categories: electrode-semiconductor interface capacitance, PN junction capacitance, and pad parasitic capacitance, with pad parasitic capacitance being the primary component.

[0004] Currently, conventional InP-based high-speed lasers in the industry generally use 300-500nm thick SiO2 as a passivation insulating layer. Due to the thin dielectric layer and the small distance between the electrode and the semiconductor substrate, the parasitic capacitance of the device is generally between 100-150fF. Excessive parasitic capacitance will form RC delay with the electrode resistance, severely slowing down the modulation speed. This manifests as high-frequency response roll-off, slower signal edges, insufficient eye diagram opening, and increased bit error rate, which cannot meet the application requirements of high-speed systems.

[0005] To address this issue, the industry has explored various solutions to reduce parasitic capacitance, but all have significant limitations. For example, reducing the size of the pads and implanted electrodes can decrease the capacitor plate area, but excessively small electrode areas lead to a sharp increase in electrode resistance and uneven current distribution, resulting in a series of problems such as increased threshold current, decreased output power, and increased thermal resistance. Simultaneously, excessively small pads significantly increase the difficulty of gold wire bonding, leading to a substantial decrease in mass production yield. Alternatively, materials such as polyimide (PI) and BCB can be used to replace SiO2, but single organic dielectrics have poor thermal stability and mechanical strength, and poor adhesion to InP substrates, making them prone to film cracking and peeling during long-term operation, compromising device reliability.

[0006] In summary, existing technologies cannot effectively solve the problem of excessive parasitic capacitance in high-speed lasers without altering the active region structure, sacrificing device performance, or reducing mass production yield. Therefore, there is an urgent need to develop a simple, cost-effective small-capacitor laser structure that is compatible with existing processes to meet the performance requirements of high-speed optical communication systems for core light sources. Summary of the Invention

[0007] To address the technical problem of excessive parasitic capacitance limiting modulation bandwidth in high-speed lasers, this invention proposes a low-capacitance high-speed laser. By introducing a thick dielectric isolation layer with low dielectric constant below the electrodes, the parasitic capacitance is significantly reduced, improving the high-frequency performance of EML / DML. At the same time, it ensures simple process, high yield, and strong compatibility, making it suitable for various types of high-speed laser applications.

[0008] To achieve the above objectives, the technical solution of the present invention is implemented as follows:

[0009] A high-speed laser with small capacitance comprises, from bottom to top, a bottom electrode, a substrate, an epitaxial layer, and a top electrode. The bottom electrode covers the entire lower surface of the substrate; the substrate is preferably an InP single-crystal substrate; the epitaxial layer is grown on the upper surface of the substrate and, from bottom to top, consists of a buffer layer, a lower cladding layer, a quantum well active region, a grating layer, an upper cladding layer, and a top heavily doped P-type contact layer, which is etched to form a ridge waveguide structure; a thin insulating dielectric layer of 50-200 nm thickness is covered on top of the epitaxial layer, with continuous injection windows only at the corresponding positions on the top of the ridge waveguide, and the remaining area is completely covered, for surface insulation protection and to prevent leakage; the top electrode consists of an integrally connected ridge injection electrode and a bonding pad, with the ridge injection electrode forming a low-resistance ohmic contact directly with the P-type contact layer on top of the ridge waveguide through the injection window, for vertically injecting current into the quantum well active region; the bonding pad extends outward from one or both ends of the ridge injection electrode for gold wire bonding in the subsequent packaging process, introducing external electrical signals.

[0010] Between the thin insulating dielectric layer and the epitaxial layer below the bonding pad area, a separate dielectric isolation layer of 4-8μm thickness is provided. The material of the dielectric isolation layer is selected from one or a combination of two or more of SiO2, PI (polyimide) and SiN (silicon nitride). The planar dimensions of the dielectric isolation layer are completely matched with or slightly larger than the planar dimensions of the bonding pad.

[0011] The design principle of this invention is based on the parallel plate capacitance formula:

[0012]

[0013] in, The vacuum permittivity, The relative permittivity of the dielectric layer, For electrode area, The distance between the electrode and the substrate.

[0014] As can be seen from the formula, there are two core approaches to reducing parasitic capacitance: one is to increase the distance d between the electrode and the substrate, and the other is to reduce the relative permittivity of the dielectric layer. This invention is based on these two principles. By adding a thick dielectric isolation layer under the pads, the spacing d is increased from the traditional 300-500nm to 4-8μm. At the same time, by selecting low dielectric constant materials such as PI or composite dielectric structures, the equivalent dielectric density is reduced. This significantly reduces parasitic capacitance.

[0015] Unlike traditional full-chip thick dielectric solutions, this invention employs a localized design because: the pad area is large and does not participate in current injection or light emission; placing a thick dielectric beneath it will not affect the core optoelectronic performance of the device. Conversely, covering the active area with a thick dielectric would obstruct current injection and worsen heat dissipation, ultimately reducing device performance. This invention, by strictly confining the thick dielectric to the pad area, balances capacitance reduction with core device performance.

[0016] This invention provides five specific implementation schemes for dielectric isolation layers, which can be flexibly selected according to different performance requirements and process conditions:

[0017] Option 1: Single-layer 6μm SiO2 dielectric isolation scheme

[0018] This method achieves small capacitors by fabricating a thick SiO2 dielectric isolation layer in the area where the bonding pads are located, significantly increasing the distance between the bonding pads and the substrate. The process steps are as follows:

[0019] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0020] (2) A 6μm thick SiO2 dielectric isolation layer was grown on the entire surface of the wafer using PECVD process;

[0021] (3) Perform the first photolithography, retaining only the photoresist pattern in the area where the bonding pads are located on the photomask, and exposing and developing the remaining areas;

[0022] (4) Using the BOE wet etching process, SiO2 in the non-bonded pad area is removed, leaving only a 6μm thick dielectric isolation layer below the bonded pad. By using lateral etching, a gentle slope is formed between the top of SiO2 and InP, which is conducive to metal growth and electroplating. There are no abrupt changes, which is more conducive to high-frequency signal transmission.

[0023] (5) Remove the photoresist and grow a thin insulating dielectric layer on the entire surface of the wafer using PECVD process. Then, perform window electrode preparation, electroplating to thicken gold and bottom electrode processes.

[0024] This solution features the simplest process, low cost, good adhesion between SiO2 and InP substrates, high thermal stability and mechanical strength, a wide process window, and high yield, making it suitable for large-scale mass production.

[0025] Option 2: Multiple growth of 2μm thick SiO2 dielectric isolation scheme

[0026] This method forms a thick dielectric isolation layer by growing thin SiO2 layers in multiple stages and stacking them. The process steps are as follows:

[0027] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0028] (2) A 2μm thick SiO2 dielectric isolation layer was grown on the entire surface of the wafer in three stages using PECVD process, for a total thickness of 6μm;

[0029] (3) Perform the first photolithography, retaining only the photoresist pattern in the area where the bonding pads are located on the photomask, and exposing and developing the remaining areas;

[0030] (4) Using the BOE wet etching process, SiO2 in the non-bonded pad area is removed, leaving only a 6μm thick dielectric isolation layer below the bonded pad. By using lateral etching, a gentle slope is formed between the top of SiO2 and InP, which is conducive to metal growth and electroplating. There are no abrupt changes, which is more conducive to high-frequency signal transmission.

[0031] (5) Remove the photoresist and grow a thin insulating dielectric layer on the entire surface of the wafer using PECVD process. Then, perform window electrode preparation, electroplating to thicken gold and bottom electrode processes.

[0032] Option 3: SiO2 column + PI reinforced composite dielectric isolation solution

[0033] This method uses SiO2 pillars to provide mechanical support, and PI to fill the voids and reduce the dielectric constant. The process steps are as follows:

[0034] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0035] (2) Perform the first photolithography to develop the photoresist pattern in the area where the bonding pads are located;

[0036] (3) A 4μm thick SiO2 dielectric isolation layer was grown using PECVD process;

[0037] (4) The SiO2 in the non-bonded pad area is removed by stripping process, and only a 4μm thick dielectric isolation layer is retained in the area where the bonded pad is located;

[0038] (5) Perform a second photolithography to etch multiple uniformly distributed columnar vias on the SiO2 dielectric isolation layer in the area where the bonding pads are located, forming an array of SiO2 support pillars;

[0039] (6) Perform the third photolithography, coat the entire wafer with PI adhesive, fill the gaps between SiO2 pillars and cover the entire area where the bonding pads are located, and expose and develop the remaining areas.

[0040] (7) Perform the PI curing process;

[0041] (8) A thin insulating dielectric layer is grown on the entire surface of the wafer using PECVD process, followed by window electrode preparation, electroplating for thickened gold, and bottom electrode process.

[0042] Option 4: Multilayer PI Stacked Dielectric Isolation Solution

[0043] This method employs multilayer PI stacking to fabricate a thick, low-dielectric-constant dielectric isolation layer, which is a simple process. The process steps are as follows:

[0044] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0045] (2) A 1 μm thick SiO2 buffer layer was grown using PECVD process;

[0046] (3) Perform the first PI photolithography: spin-coat the first layer of PI, photolithographically develop the PI pattern of the area where the bonding pads are located, and then perform the PI curing process;

[0047] (4) Perform the second PI photolithography: spin-coat the second layer of PI, and develop the PI pattern in the area where the bonding pads are completely overlapped with the first layer by photolithography, and cure under the same conditions;

[0048] (5) Perform the third PI photolithography: spin-coat the third PI layer, photolithographically develop the PI pattern in the area where the bonding pads are completely overlapped with the first two layers, cure under the same conditions to form a three-layer PI stacked dielectric isolation layer with a total thickness of about 6μm.

[0049] (6) A thin insulating dielectric layer is grown on the entire surface of the wafer using PECVD process, followed by window electrode preparation, electroplating for thickened gold, and bottom electrode process.

[0050] Option 5: SiO2 / SiN / PI multilayer inclusion dielectric isolation scheme

[0051] This method utilizes alternating stacking of inorganic and organic dielectrics to achieve a balance between low dielectric constant, high mechanical strength, and good hermeticity. The process steps are as follows:

[0052] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0053] (2) Perform the first photolithography to develop the photoresist pattern in the area where the bonding pads are located;

[0054] (3) A first SiO2 dielectric isolation layer with a thickness of 1 μm was grown using PECVD process;

[0055] (4) Use a stripping process to remove SiO2 from the non-bonded pad area, leaving only a 1μm thick dielectric isolation layer in the area where the bonded pad is located;

[0056] (5) Perform the first PI photolithography: spin-coat PI, photolithographically develop the PI pattern in the area where the bonding pads are located, and then perform the PI curing process to form a second PI dielectric isolation layer with a thickness of 2μm.

[0057] (6) Repeat the peeling process of steps 2-4 to prepare a 1μm thick third SiN dielectric isolation layer;

[0058] (7) Perform the second PI photolithography: spin-coat PI, photolithography develop the PI pattern in the area where the bonding pads are completely overlapped with the first layer, cure under the same conditions to form a 2μm thick fourth PI dielectric isolation layer.

[0059] (8) Repeat the peeling process of steps 2-4 to prepare a fifth SiO2 dielectric isolation layer with a thickness of 1 μm, forming a SiO2 / PI / SiN / PI / SiO2 multilayer mixed dielectric isolation layer with a total thickness of about 7 μm.

[0060] (9) A thin insulating dielectric layer is grown on the entire surface of the wafer using PECVD process, followed by window electrode preparation, electroplating for thickened gold, and bottom electrode process.

[0061] All of the above solutions do not require modification to the core processes of the high-speed laser, such as the active region structure, grating fabrication, and waveguide etching. They only require the addition of a thick dielectric isolation layer deposition and patterning process before the conventional thin insulating dielectric layer fabrication process, and can be directly integrated into existing high-speed laser mass production lines. The small-capacitor high-speed laser described in this invention is preferably an InP-based ridge waveguide DFB laser, but it is also applicable to other types of high-speed optical communication lasers such as EML and DML.

[0062] The beneficial effects of this invention are:

[0063] (1) By separately setting a 4-8μm thick dielectric isolation layer under the bonding pads, the vertical distance between the pad electrodes and the semiconductor epitaxial layer is increased, thereby reducing the total parasitic capacitance of the device to below 50fF, which is more than 50% lower than the traditional 300~500nm thin SiO2 process. The reduction of RC delay directly improves the high-frequency response and modulation bandwidth of the laser, which is fully compatible with the requirements of optical communication systems with 50G / 100G / 200G and higher single-channel rates.

[0064] (2) No changes are required to the core processes of the active region structure, grating and waveguide fabrication of the high-speed laser. Only a thick dielectric layer deposition and patterning step is added before the conventional passivation layer process. All steps use mature semiconductor processing technology, which can be directly connected to existing mass production lines without the need for new special equipment. The modification cost is low and it is easy to quickly industrialize.

[0065] (3) All five dielectric isolation layer schemes are based on mature PECVD deposition and wet etching processes, with large process tolerance and stable yield. Among them, the composite dielectric and multilayer stacking schemes can also improve the adhesion between the dielectric layer and the InP substrate, improve mechanical and thermal stability, avoid problems such as dielectric layer peeling and cracking, and ensure long-term reliable operation of the device.

[0066] (4) It provides a variety of dielectric isolation layer solutions, such as single-layer SiO2, multi-layer SiO2, multi-layer PI, SiO2-PI composite, and SiO2 skeleton-filled PI. These solutions can be used individually or in combination according to different speeds and performance requirements. It covers the needs of high-speed EML / DML lasers from 50G to 200G, leaving ample room for product differentiation design. Attached Figure Description

[0067] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 This is a schematic diagram of the device structure at each step of the fabrication process of the high-speed capacitive laser described in Example 1.

[0069] Figure 2 This is a schematic diagram of the device structure at each step of the fabrication process of the high-speed capacitive laser described in Example 2.

[0070] Figure 3 This is a schematic diagram of the device structure at each step of the fabrication process of the high-speed capacitive laser described in Example 3.

[0071] Figure 4 This is a schematic diagram of the device structure at each step of the fabrication process of the high-speed capacitive laser described in Example 4.

[0072] Figure 5 This is a schematic diagram of the device structure at each step of the fabrication process of the high-speed capacitive laser described in Example 5. Detailed Implementation

[0073] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0074] Example 1

[0075] A high-speed laser with small capacitance is disclosed, comprising, from bottom to top, a bottom electrode, an InP substrate, an epitaxial layer, and a top electrode. The epitaxial layer, from bottom to top, consists of a buffer layer, a lower cladding layer, a quantum well active region, a grating layer, an upper cladding layer, and a top heavily doped P-type contact layer, which is etched to form a ridge-type optical waveguide structure. A thin insulating dielectric layer covers the top of the epitaxial layer, and this thin insulating dielectric layer has continuous injection windows only at the corresponding positions on the top of the ridge-type optical waveguide.

[0076] The top electrode consists of an integrally connected ridge-mounted injection electrode and a bonding pad. The ridge-mounted injection electrode directly forms a low-resistance ohmic contact with the P-type contact layer at the top of the ridge-type optical waveguide through the injection window. A separate 6μm thick SiO2 dielectric isolation layer is provided between the thin insulating dielectric layer and the epitaxial layer below the area where the bonding pad is located. The sidewalls are formed by wet lateral etching to create a gentle slope. The bonding pad metal continuously covers the top surface and slope surface of the dielectric isolation layer.

[0077] Preparation process such as Figure 1 Specifically, it includes the following steps:

[0078] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0079] (2) Using PECVD process, under 150℃ and 13.56MHz RF conditions, a 2μm thick SiO2 dielectric isolation layer was grown in 3 stages, for a total thickness of 6μm, with a deposition rate of about 200nm / min.

[0080] (3) Spin-coat positive photoresist, pre-bake, expose and develop, retaining only the photoresist in the area where the bonding pads are located;

[0081] (4) Use BOE etching solution to etch SiO2 at a rate of about 100 nm / min for about 60 minutes to remove SiO2 from the non-bonded pad area;

[0082] (5) Remove the photoresist and grow a thin insulating dielectric layer using PECVD;

[0083] (6) The window is etched by photolithography, the metal electrode is deposited by vapor deposition, and after stripping, the window electrode is prepared, the thickened gold is electroplated and the bottom electrode is processed.

[0084] Example 2

[0085] A high-speed laser with small capacitance is disclosed. The overall structure of the laser is basically the same as that of Embodiment 1, except that the dielectric isolation layer is composed of three SiO2 layers, each with a thickness of 2μm.

[0086] Preparation process such as Figure 2 Specifically, it includes the following steps:

[0087] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0088] (2) Using PECVD process, a 6μm thick SiO2 dielectric isolation layer was grown in one step at 150℃ and 13.56MHz RF conditions, with a deposition rate of about 200nm / min;

[0089] (3) Spin-coat positive photoresist, pre-bake, expose and develop, retaining only the photoresist in the area where the bonding pads are located;

[0090] (4) Use BOE etching solution to etch SiO2 at a rate of about 100 nm / min for about 60 minutes to remove SiO2 from the non-bonded pad area;

[0091] (5) Remove the photoresist and grow a thin insulating dielectric layer using PECVD;

[0092] (6) The window is etched by photolithography, the metal electrode is deposited by vapor deposition, and after stripping, the window electrode is prepared, the thickened gold is electroplated and the bottom electrode is processed.

[0093] Example 3

[0094] A high-speed laser with small capacitance is described. The overall structure of the laser is basically the same as that of Embodiment 1, except that the dielectric isolation layer is a composite structure: the substrate is a 4μm thick SiO2 layer, in which an 8×8 array of columnar through holes (column diameter 5μm, spacing 10μm) is etched to form a SiO2 support column array, and the through holes are filled with PI material, with a total thickness of 6μm.

[0095] Preparation process such as Figure 3 Specifically, it includes the following steps:

[0096] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0097] (2) Spin-coat positive photoresist, pre-bake and then expose, and develop the pattern of the area where the bonding pads are located;

[0098] (3) PECVD grows 4μm thick SiO2, and 400T stripping process is used to retain SiO2 blocks only in the area where the bonding pads are located;

[0099] (4) Photolithography and development: 8×8 array of columnar through holes are etched on the SiO2 block. The column diameter is 5μm and the spacing is 10μm to form SiO2 support columns.

[0100] (5) Spin-coat PI to a thickness of 6μm to fill the gaps in the support columns, and then perform PI curing at 350℃ for 1 hour;

[0101] (6) A thin insulating dielectric layer is grown on the entire surface of the wafer using PECVD process;

[0102] (7) The window is etched by photolithography, the metal electrode is deposited by vapor deposition, and after stripping, the window electrode is prepared, the thickened gold is electroplated and the bottom electrode is processed.

[0103] Example 4

[0104] A small capacitor high-speed laser, the overall structure of which is basically the same as that of Embodiment 1, the only difference being that the dielectric isolation layer is composed of three PI layers with a thickness of 2μm stacked together, with a total thickness of 6μm, and a 1μm thick SiO2 buffer layer is provided between the PI layer and the epitaxial layer.

[0105] Preparation process such as Figure 4 Specifically, it includes the following steps:

[0106] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0107] (2) A 1μm thick SiO2 buffer layer was grown using PECVD process to improve the adhesion between PI and InP substrate;

[0108] (3) Spin-coat the first layer of PI with a thickness of 2μm, photolithographically develop the pattern of the area where the bonding pads are located, and then perform PI curing process at 350℃ for 1 hour;

[0109] (4) Spin-coat the second PI layer with a thickness of 2μm, and develop the area of ​​the bonding pads that completely overlaps with the first layer by photolithography, and cure under the same conditions;

[0110] (5) Spin-coat the third PI layer with a thickness of 2μm, and develop the area of ​​the bonding pads that completely overlaps with the first two layers by photolithography. Then cure under the same conditions to form a three-layer PI stacked dielectric isolation layer with a total thickness of about 6μm.

[0111] (6) A thin insulating dielectric layer is grown on the entire surface of the wafer using PECVD process;

[0112] (7) The window is etched by photolithography, the metal electrode is deposited by vapor deposition, and after stripping, the window electrode is prepared, the thickened gold is electroplated and the bottom electrode is processed.

[0113] Example 5

[0114] A high-speed laser with small capacitance is disclosed. The overall structure of the laser is basically the same as that of Embodiment 1, except that the dielectric isolation layer is a multilayer hybrid structure of SiO2 / PI / SiN / PI / SiO2, consisting of a 1μm thick SiO2 layer, a 2μm thick PI layer, a 1μm thick SiN layer, a 2μm thick PI layer, and a 1μm thick SiO2 layer from bottom to top, with a total thickness of 7μm.

[0115] Preparation process such as Figure 5 Specifically, it includes the following steps:

[0116] (1) Complete the assembly, grating, waveguide, isolation, and deep trench fabrication of high-speed laser wafers;

[0117] (2) Spin-coat positive photoresist, pre-bake and then expose, and develop the pattern of the area where the bonding pads are located;

[0118] (3) A first SiO2 dielectric isolation layer with a thickness of 1 μm was grown by PECVD and a 400T stripping process was used to retain SiO2 blocks only in the area where the bonding pads are located.

[0119] (4) Spin-coat PI with a thickness of 2μm, photolithography to develop the pattern of the bonding pad area, and then perform PI curing process at 350℃ for 1 hour to form the second PI dielectric isolation layer.

[0120] (5) Repeat the peeling process of steps (2)-(3) to prepare a 1μm thick third SiN dielectric isolation layer;

[0121] (6) Spin-coat PI with a thickness of 2μm, and develop the area of ​​the bonding pads that completely overlap with the first layer by photolithography. Then cure under the same conditions to form the fourth PI dielectric isolation layer.

[0122] (7) Repeat the peeling process of steps (2)-(3) to prepare a fifth SiO2 dielectric isolation layer with a thickness of 1 μm, forming a multilayer mixed dielectric isolation layer with a total thickness of about 7 μm;

[0123] (8) A thin insulating dielectric layer is grown on the entire surface of the wafer using PECVD process;

[0124] (9) The window is etched by photolithography, the metal electrode is deposited by vapor deposition, and after stripping, the window electrode is prepared, the thickened gold is electroplated and the bottom electrode is processed.

[0125] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A small-capacitor high-speed laser, comprising, from bottom to top, a bottom electrode, a substrate, an epitaxial layer, and a top electrode, wherein the epitaxial layer includes a quantum well active region, a Bragg grating, and a ridge waveguide, an insulating dielectric layer is disposed on the top of the epitaxial layer, and an injection window is provided on the insulating dielectric layer at a corresponding position on the top of the ridge waveguide; the top electrode includes a ridge-mounted injection electrode disposed corresponding to the ridge waveguide and an outwardly extending bonding pad; characterized in that, A dielectric isolation layer is provided between the insulating dielectric layer and the epitaxial layer below the area where the bonding pad is located. The thickness of the dielectric isolation layer is 4-8 μm, and the material is one or more of SiO2, PI and SiN.

2. The small-capacitor high-speed laser according to claim 1, characterized in that, The dielectric isolation layer is a SiO2 layer with a thickness of 4-8 μm.

3. The high-speed laser with small capacitance according to claim 1, characterized in that, The dielectric isolation layer has a multi-layer structure, including 3-5 single-layer isolation layers, wherein the single-layer isolation layer is a SiO2, PI or SiN layer with a thickness of 1-3 μm.

4. The small-capacitor high-speed laser according to claim 3, characterized in that, The dielectric isolation layer consists of three SiO2 layers, each with a thickness of 2 μm.

5. The small-capacitor high-speed laser according to claim 3, characterized in that, The dielectric isolation layer consists of three PI layers, each with a thickness of 2 μm.

6. The high-speed laser with small capacitance according to claim 5, characterized in that, A 1μm thick SiO2 buffer layer is also provided between the PI layer and the epitaxial layer.

7. The small-capacitor high-speed laser according to claim 3, characterized in that, The dielectric isolation layer comprises, from bottom to top, a SiO2 layer, a PI layer, a SiN layer, a PI layer, and a SiO2 layer.

8. The high-speed laser with small capacitance according to claim 7, characterized in that, The thickness of the SiO2 layer is 1 μm, the thickness of the PI layer is 2 μm, and the thickness of each SiN layer is 1 μm.

9. The high-speed laser with small capacitance according to claim 1, characterized in that, The dielectric isolation layer is a SiO2 layer with a thickness of 4-8 μm, and the SiO2 layer has a columnar through-hole array filled with PI.

10. The high-speed laser with small capacitance according to any one of claims 1-9, characterized in that, The laser is an InP-based ridge waveguide DFB laser, an EML electro-absorption modulated laser, or a DML direct modulated laser.

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