A short circuit protection circuit for a silicon carbide power device

Abstract

The present application belongs to the field of power electronics, and in particular to a silicon carbide power device short-circuit protection circuit; the inverter main circuit is used to carry silicon carbide power tubes and output driving power; the high-voltage side current sampling comparison unit is electrically connected to the lower bridge arm of the inverter main circuit, real-time collects the bridge arm current and compares it with the preset overcurrent threshold at high speed, and outputs an isolated fault signal to the low-voltage side in case of failure; the low-voltage side fault latching and wave control unit receives the high-voltage side isolated fault signal, hardware latches the fault state and directly locks the PWM driving signal output, and at the same time reports the fault identification to the main control MCU; the silicon carbide power device short-circuit protection circuit adopts a hardware direct-through wave locking architecture, and can complete SiC device short-circuit protection within 1.2 microseconds without the participation of the MCU, has very fast short-circuit protection capability, can complete protection within the short-circuit tolerance time of the silicon carbide power device, effectively prevents device thermal breakdown; at the same time, the detection blind area is eliminated, the anti-noise interference capability is improved, and the system operation is stable and reliable.

Description

Technical Field

[0001] This invention relates to the field of power electronics technology, specifically to a short-circuit protection circuit for silicon carbide power devices. Background Technology

[0002] As new energy vehicles rapidly evolve towards 800V high-voltage platforms and high power densities, silicon carbide power devices, with their low conduction losses, high switching frequencies, and excellent high-temperature characteristics, are gradually becoming core components of electric drive inverters, on-board DC / DC converters, and chargers. This technological path plays a crucial role in improving system energy efficiency, reducing equipment size, and achieving lightweighting. However, in actual operation, the operating conditions of new energy vehicles are complex and variable. Motor winding insulation failure, sudden load changes, or abnormal control signals can all lead to bridge arm shoot-through or phase-to-phase short-circuit faults. Under such faults, silicon carbide MOSFETs exhibit two prominent defects: their short-circuit withstand time is extremely short, typically only lasting 2 to 3 microseconds, far lower than the response window of silicon-based IGBT devices; simultaneously, their voltage change rate during switching is extremely high, with dv / dt reaching 50 to 100 kV per microsecond, causing traditional current detection schemes to be severely interfered with by parasitic inductance noise, easily resulting in false triggering or missed alarms.

[0003] Existing protection technologies have significant limitations. Desaturation detection methods require long blanking times, creating a blind zone that cannot detect short circuits. Gate charge detection schemes, due to their complex circuit structures and numerous components, are unable to meet the stringent long-term reliability requirements of automotive-grade applications. These shortcomings mean that protection circuits cannot promptly block energy accumulation during short-circuit faults, potentially leading to thermal breakdown damage to power devices and even power interruption during vehicle operation, posing a significant threat to driving safety and system lifespan.

[0004] Therefore, we propose a short-circuit protection circuit for silicon carbide power devices to solve the above problems. Summary of the Invention

[0005] (a) Technical problems to be solved To address the shortcomings of existing technologies, this invention provides a short-circuit protection circuit for silicon carbide power devices, which features extremely fast short-circuit protection capability with a response time of no more than 1.2 microseconds. It can complete protection within the short-circuit tolerance time of silicon carbide power devices, effectively preventing thermal breakdown of the devices. At the same time, it eliminates detection blind zones, improves noise interference immunity, and ensures stable and reliable system operation, thus solving the problems mentioned in the background technology.

[0006] (II) Technical Solution

[0007] To achieve the above objectives, the present invention specifically adopts the following technical solution: A short-circuit protection circuit for silicon carbide power devices includes an inverter main circuit, a high-voltage side current sampling and comparison unit, and a low-voltage side fault latching and blocking control unit. The inverter main circuit is used to carry silicon carbide power transistors and output driving power; the high-voltage side current sampling and comparison unit is electrically connected to the lower bridge arm of the inverter main circuit, collects the bridge arm current in real time and compares it with a preset overcurrent threshold at high speed, and outputs an isolation fault signal to the low-voltage side when a fault occurs; the low-voltage side fault latching and blocking control unit receives the high-voltage side isolation fault signal, hardware latches the fault state and directly blocks the PWM drive signal output, and reports the fault mark to the main control MCU. The short-circuit protection circuit for the silicon carbide power device adopts a hardware pass-through blocking architecture.

[0008] Furthermore, the inverter main circuit includes a three-phase inverter power transistor group, a lower bridge shunt sampling resistor group, and a bus filter capacitor; The three-phase inverter power transistor group includes phase A upper transistor U1, phase A lower transistor U6, phase B upper transistor U2, phase B lower transistor U7, phase C upper transistor U3, and phase C lower transistor U8. All power transistors are silicon carbide MOSFET devices. The lower bridge shunt sampling resistor group includes phase A shunt resistor R8, phase B shunt resistor R9, and phase C shunt resistor R10; the emitters of each phase silicon carbide lower transistor are connected in series with the corresponding shunt resistors and then grounded. The voltage across the shunt resistors is proportional to the phase current of the corresponding bridge arm and serves as the high-voltage side current sampling input signal. The bus filter capacitor C25 is connected in parallel across the DC high voltage bus.

[0009] Furthermore, the high-voltage side current sampling and comparison unit includes three high-speed isolation comparison branches with completely identical structures, corresponding to the A / B / C three-phase inverter bridge arms respectively. Each high-speed isolation comparison branch includes a high-speed isolation comparator, a high-voltage side power supply RC filter circuit, a current sampling RC filter circuit, and a reference voltage generation circuit.

[0010] Furthermore, the low-voltage side fault latching and blocking control unit includes an isolation comparator low-voltage power supply filtering branch, a three-phase independent fault latching branch, a diode logic AND gate circuit, a three-state buffer drive signal conversion circuit, and a buffer enable blocking control circuit.

[0011] Furthermore, the low-voltage side fault latching and blocking control unit is also equipped with impedance matching resistors R16, R26, and R27; R16 is connected in series between the OUT pin of U12 and the anode of D1, R26 is connected in series between the OUT pin of U13 and the anode of D2, and R27 is connected in series between the OUT pin of U14 and the anode of D3.

[0012] Furthermore, the overall fault protection process of the circuit is as follows: short circuit of inverter bridge arm → the lower bridge shunt resistor generates an over-threshold sampling voltage → the sampling voltage of the high-voltage side isolation comparator is compared with Vref and then the level flips → the fault signal is transmitted to the low-voltage side by opto-isolation → the corresponding latching transistor is turned on to lock the fault state → the diode AND gate pulls the Fault signal low → the wave blocking control transistor is turned on to turn off the tri-state buffer is enabled → all PWM drive signals are hardware blocked, and the entire hardware path is completed.

[0013] Furthermore, the high-speed isolation comparator simultaneously achieves electrical isolation between the high-voltage sampling circuit and the low-voltage control circuit, blocking the common-mode high-voltage noise crosstalk generated by the 50-100kV / μs high-speed switching of the SiC device to the low-voltage control domain of the MCU.

[0014] Furthermore, the circuit adopts a direct sampling architecture using the lower bridge emitter shunt resistor, avoiding the blanking and turn-on blind zone of more than 4μs in traditional SiC desaturation detection, and monitors the bridge arm current in real time throughout the entire switching cycle without any detection blind zone.

[0015] Furthermore, the Fault signal is output in two channels simultaneously: one channel is connected to the blocking control circuit to realize hardware instantaneous blocking protection; the other channel is connected to the fault detection IO port of the main control MCU. After the MCU detects the Fault low level, it performs fault recording, power reduction, reports short circuit alarm to the host computer, and performs secondary protection actions of fault shutdown.

[0016] Furthermore, the protection circuit is adapted to the 800V high-voltage electric drive platform of new energy vehicles. Taking into account the short-circuit withstand time of only 2-3μs for SiC MOSFETs, it relies on a pure hardware high-speed protection link to cut off the drive signal before the device thermally breaks down, thus preventing the continuous accumulation of short-circuit energy. Moreover, the fault latching mechanism avoids the interruption of vehicle driving power caused by instantaneous noise false blocking waves, thus balancing the protection response speed and system operation stability.

[0017] (III) Beneficial Effects

[0018] Compared with the prior art, the present invention provides a short-circuit protection circuit for silicon carbide power devices, which has the following beneficial effects: This invention includes an inverter main circuit, a high-voltage side current sampling and comparison unit, and a low-voltage side fault latching and blocking control unit. The inverter main circuit is used to carry silicon carbide power transistors and output drive power. The high-voltage side current sampling and comparison unit is electrically connected to the lower bridge arm of the inverter main circuit, collects the bridge arm current in real time, and compares it with a preset overcurrent threshold at high speed. In case of a fault, it outputs an isolation fault signal to the low-voltage side. The low-voltage side fault latching and blocking control unit receives the high-voltage side isolation fault signal, hardware latches the fault state, directly blocks the PWM drive signal output, and reports the fault identifier to the main control MCU. The short-circuit protection circuit of the silicon carbide power device adopts a hardware pass-through blocking architecture. Short-circuit protection for SiC devices can be completed within 1.2μs without MCU intervention. It is suitable for short-circuit protection of silicon carbide power modules in 800V high-voltage new energy vehicle electric drive inverters, vehicle DC / DC converters, vehicle chargers, and industrial frequency converters. Through a hardware pass-through waveform blocking architecture, it realizes real-time high-speed comparison of bridge arm current and pass-through processing of fault signals, cutting off the drive signal before the device thermally breaks down. It has extremely fast short-circuit protection capability with a response time of no more than 1.2 microseconds. It can complete protection within the short-circuit tolerance time of silicon carbide power devices, effectively preventing device thermal breakdown. At the same time, it eliminates detection blind spots, improves noise interference resistance, and ensures stable and reliable system operation. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of the short-circuit protection circuit for the silicon carbide power device of the present invention. Figure 2 This is a block diagram of the overall system architecture of the present invention. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Example

[0021] When traditional electric drive systems for new energy vehicles use silicon carbide power devices, the short-circuit withstand time of these devices is extremely short (usually only 2-3μs) and the switching speed is extremely high (dv / dt can reach 50-100kV / μs). This makes traditional current detection schemes susceptible to parasitic inductance noise interference, resulting in false triggering or missed alarms. At the same time, existing desaturation detection schemes have turn-on blind zones, and the gate charge detection circuits are complex and lack reliability, making it difficult to meet automotive-grade functional safety requirements.

[0022] In this regard, such as Figure 1-2As shown, this application proposes a short-circuit protection circuit for silicon carbide power devices, including an inverter main circuit, a high-voltage side current sampling and comparison unit, and a low-voltage side fault latching and blocking control unit; The inverter main circuit is used to carry silicon carbide power transistors and output drive power; the high-voltage side current sampling and comparison unit is electrically connected to the lower bridge arm of the inverter main circuit, collects the bridge arm current in real time and compares it with the preset overcurrent threshold at high speed, and outputs an isolation fault signal to the low-voltage side when a fault occurs; the low-voltage side fault latching and blocking control unit receives the high-voltage side isolation fault signal, hardware latches the fault state and directly blocks the PWM drive signal output, and reports the fault mark to the main control MCU. This silicon carbide power device short-circuit protection circuit adopts a hardware pass-through blocking architecture, which can complete the short-circuit protection of SiC devices within 1.2μs without the participation of an MCU. It is suitable for short-circuit protection of silicon carbide power modules in 800V high-voltage new energy vehicle electric drive inverters, vehicle DC / DC converters, vehicle chargers and industrial frequency converters.

[0023] This application provides a short-circuit protection circuit for silicon carbide power devices, which mainly consists of an inverter main circuit, a high-voltage side current sampling and comparison unit, and a low-voltage side fault latching and blocking control unit. The inverter main circuit, as the core of energy conversion, can be composed of multiple power switching devices.

[0024] The high-voltage side current sampling and comparison unit is responsible for monitoring the operating status of the inverter main circuit in real time. This unit can implement current sampling in various ways.

[0025] The low-voltage side fault latching and blocking control unit receives the isolation fault signal from the high-voltage side. This unit can use a hardware latch (such as a D flip-flop or SR latch) to maintain the fault state and prevent the loss of fault information due to transient interference. Once the fault state is latched, the unit will directly block the PWM drive signal.

[0026] The short-circuit protection circuit for this silicon carbide power device adopts a hardware pass-through blocking architecture. This means that the entire process from fault detection to drive signal blocking is mainly implemented through hardware circuitry, without the need for software intervention from the main control MCU.

[0027] The short-circuit protection circuit for silicon carbide power devices disclosed in this application achieves extremely fast response to short-circuit faults in silicon carbide power devices by adopting a hardware pass-through blocking architecture. This effectively solves the problems of long response time, susceptibility to noise interference, and detection blind spots in traditional solutions. This circuit can complete short-circuit protection of SiC devices within 1.2μs, significantly improving the operational reliability and safety of silicon carbide power modules in 800V high-voltage new energy vehicle electric drive systems, on-board DC / DC converters, on-board chargers, and industrial frequency converters, and avoiding the risks of device thermal breakdown and system power interruption.

[0028] To address this issue, this application proposes a short-circuit protection circuit for silicon carbide power devices, comprising an inverter main circuit, a high-voltage side current sampling and comparison unit, and a low-voltage side fault latching and blocking control unit. The inverter main circuit carries silicon carbide power transistors and outputs drive power. The high-voltage side current sampling and comparison unit is electrically connected to the lower bridge arm of the inverter main circuit, real-time sampling of the bridge arm current and high-speed comparison with a preset overcurrent threshold. In case of a fault, it outputs an isolation fault signal to the low-voltage side. The low-voltage side fault latching and blocking control unit receives the high-voltage side isolation fault signal, hardware latches the fault state, directly blocks the PWM drive signal output, and simultaneously reports a fault identifier to the main control MCU. This silicon carbide power device short-circuit protection circuit adopts a hardware direct-through blocking architecture, enabling short-circuit protection of SiC devices within 1.2μs without MCU intervention. It is suitable for short-circuit protection of silicon carbide power modules in 800V high-voltage new energy vehicle electric drive inverters, on-board DC / DC converters, on-board chargers, and industrial frequency converters. However, to ensure the stable, efficient, and accurate operation of this short-circuit protection circuit, especially considering the high-speed switching characteristics of silicon carbide power devices and the high requirements for current sampling accuracy, the specific structure of the inverter main circuit and the synergistic effect of its internal components are crucial. Improper structural design of the inverter main circuit may lead to distortion of the current sampling signal and poor power supply stability, thereby affecting the judgment accuracy of the high-voltage side current sampling comparison unit and the response speed of the entire protection system.

[0029] In some of the embodiments described above in this application, in order to solve the above problems, this application further proposes that the inverter main circuit includes a three-phase inverter power transistor group, a lower bridge shunt sampling resistor group, and a bus filter capacitor.

[0030] Specifically, the three-phase inverter power transistor group is the core component of the inverter main circuit, responsible for efficiently converting DC power into AC power to drive the load. This power transistor group includes phase A upper transistor U1 and phase A lower transistor U6, phase B upper transistor U2 and phase B lower transistor U7, and phase C upper transistor U3 and phase C lower transistor U8. All of these power transistors are silicon carbide MOSFET devices. Silicon carbide MOSFET devices are particularly suitable for high-voltage, high-power power electronic conversion applications due to their excellent high-frequency switching capability, low conduction loss, high voltage withstand characteristics, and excellent heat dissipation performance.

[0031] The lower bridge shunt sampling resistor group is used to monitor the current flowing through the lower bridge arm of the inverter main circuit in real time. This resistor group consists of phase A shunt resistor R8, phase B shunt resistor R9, and phase C shunt resistor R10. In the circuit connection, the emitters of each phase silicon carbide transistor are connected in series with their corresponding shunt resistors and then grounded. When current flows through these shunt resistors, according to Ohm's law, a voltage drop proportional to the current flowing through the resistors is generated across them. This voltage drop is used as the high-voltage side current sampling input signal for subsequent fault diagnosis by the high-voltage side current sampling comparison unit. This direct shunt sampling method provides accurate and real-time bridge arm current information, which is a key input for the rapid activation of the short-circuit protection mechanism.

[0032] The bus filter capacitor C25 is connected in parallel across the DC high-voltage bus. Its main function is to stabilize the DC high-voltage bus voltage of the inverter main circuit, absorb voltage fluctuations on the DC bus, and effectively suppress potential spike noise during high-speed switching of the power transistors. This is crucial for ensuring the stable operation of the inverter main circuit and also provides a clean power supply environment for the high-voltage side current sampling and comparison unit, thereby avoiding false triggering caused by power supply noise and improving the reliability of the entire protection circuit.

[0033] This application further proposes that the high-voltage side current sampling and comparison unit includes three high-speed isolated comparison branches with completely identical structures, corresponding to the A / B / C three-phase inverter bridge arms respectively. This multi-path parallel design ensures comprehensive monitoring of the three-phase inverter bridge arm currents and improves the system's response capability to multi-phase faults. Specifically, each high-speed isolated comparison branch includes a high-speed isolation comparator, a high-voltage side power supply RC filter circuit, a current sampling RC filter circuit, and a reference voltage generation circuit.

[0034] The high-speed isolated comparators are U12, U13, and U14. These comparator chips have a built-in 100μA constant current source to generate a precise reference voltage. Their opto-isolated output channels achieve electrical isolation between the high-voltage side sampling circuit and the low-voltage side control circuit, effectively blocking common-mode noise interference on the high-voltage side and ensuring the reliability and safety of signal transmission. Simultaneously, their hardware latch pin can lock the fault state when a fault is detected, preventing false triggering or loss of fault signals caused by transient noise. The high-speed isolated comparators acquire analog current signals on the high-voltage side and output digital fault levels on the low-voltage side, realizing signal conversion and isolation between the high and low voltage domains.

[0035] The high-voltage side power supply RC filter circuit consists of resistor R11, capacitors C5 and C6; resistor R17, capacitors C11 and C12; and resistor R21, capacitors C17 and C18. These RC filter circuits are connected in parallel to the high-voltage power supply pins of the high-speed isolation comparators U12, U13, and U14. Their function is to filter out dv / dt coupling interference generated during high-voltage side switching, providing a stable and clean power supply to the comparators, thereby ensuring their normal operation and comparison accuracy under high-voltage conditions.

[0036] The current sampling RC filter circuits are composed of resistor R13 and capacitor C4; resistor R18 and capacitor C10; and resistor R22 and capacitor C16, respectively. One end of each filter circuit is connected to the sampling output terminal of the corresponding shunt resistor, and the other end is connected to the analog input pin of the isolation comparator. They perform high-frequency filtering of the current sampling signal through an RC network, effectively suppressing parasitic inductance noise generated during the high-speed switching process of SiC, ensuring the accuracy of the current sampling signal sent to the comparator, and avoiding misjudgments caused by noise.

[0037] The reference voltage generation circuit consists of reference resistor R14 and bypass capacitor C3; reference resistor R19 and bypass capacitor C9; and reference resistor R23 and bypass capacitor C15. A 100μA constant current source built into the REF reference pin of the isolation comparator flows through the reference resistor, generating a precise and stable threshold reference voltage Vref. The bypass capacitor performs high-frequency filtering on Vref, further improving the stability of the reference voltage. When the shunt resistor sampling voltage is greater than Vref, the OUT output level on the low-voltage side of the isolation comparator flips to a low-level fault signal, indicating that an overcurrent fault has been detected.

[0038] This application further proposes a low-voltage side fault latching and blocking control unit, which includes an isolation comparator low-voltage power supply filter branch, a three-phase independent fault latching branch, a diode logic AND gate circuit, a three-state buffer drive signal conversion circuit, and a buffer enable blocking control circuit.

[0039] The low-voltage power supply filter branch for the isolation comparators aims to provide a stable operating environment for the 5V low-voltage side power supply of isolation comparators U12, U13, and U14. This branch, by configuring bypass capacitors C7, C8; C14, C18; C19, and C20 connected in parallel across the power supply, effectively filters out high-frequency noise and transient voltage fluctuations in the power supply, ensuring the purity and stability of the low-voltage side power supply voltage of the isolation comparators, thereby providing a reliable power foundation for subsequent fault signal processing.

[0040] The three-phase independent fault latch branch receives fault signals from the low-voltage side OUT pins of isolation comparators U12, U13, and U14, and implements hardware latching of the fault status. This branch consists of transistor Q2 and resistor R15; transistor Q3 and resistor R20; and transistor Q4 and resistor R24, respectively. Specifically, the base of each transistor is connected to the low-voltage side OUT pin of the corresponding isolation comparator U12, U13, or U14, while its collector is connected to the LATCH latch pin of the isolation comparator U12, U13, or U14. When the OUT pin of any isolation comparator U12, U13, or U14 outputs a low-level fault signal, the corresponding transistor Q2, Q3, or Q4 will conduct, thereby pulling up the LATCH pin level of the isolation comparator U12, U13, or U14 and activating its built-in hardware latching function. Once the hardware latching function is enabled, the OUT pins of isolation comparators U12, U13, and U14 will remain locked in a low-level fault state, and the fault state will remain unchanged even if the transient condition causing the fault disappears. This latching mechanism effectively prevents malfunctions or incomplete protection caused by transient noise or brief faults, significantly improving the safety and reliability of the system. The fault state can only be cleared by powering the entire system back on.

[0041] The diode-based AND gate circuit is responsible for logically aggregating the three independent fault signals into a unified Fault signal network. This circuit includes diodes D1, D2, and D3, whose anodes are connected to the OUT outputs of isolation comparators U12, U13, and U14, respectively. The cathodes of the three diodes are connected together to form the Fault signal network. With this configuration, whenever any one of the isolation comparators U12, U13, or U14 outputs a low level (indicating a fault), the corresponding diode D1, D2, or D3 will conduct in the forward direction, pulling the entire Fault signal network low. This achieves rapid hardware OR logic aggregation of the three-phase fault signals, ensuring that a short-circuit fault in any one phase immediately triggers the overall protection action.

[0042] The tri-state buffer drive signal conversion circuit receives six raw PWM drive signals (DSP_UH, DSP_UL, DSP_VH, DSP_VL, DSP_WH, and DSP_WL) output from the main control MCU and converts them into standard 5V drive levels (UH, UL, VH, VL, WH, WL) suitable for driving optocouplers of SiC power transistors. This circuit includes a tri-state buffer chip U10 and a bypass filter capacitor C1. The input of the tri-state buffer chip U10 receives the raw PWM signal from the MCU, and its output converts it into a standard drive level, which is then connected to the input of the corresponding three-phase SiC power transistor drive optocoupler. The bypass filter capacitor C1 is connected in parallel to the power supply pin of the tri-state buffer chip U10 to filter the power supply and ensure stable chip operation.

[0043] The buffer enable blocking control circuit controls the operating mode of the tri-state buffer chip U10 based on the state of the fault signal network, thereby achieving hardware blocking of the PWM drive signal. This circuit includes a transistor Q1 and a pull-down resistor R12. The base of transistor Q1 is connected to the fault signal network, and its collector is connected in series with the resistor R12 to the low-active enable pin 2OE# of the tri-state buffer chip U10. In the fault-free state, the fault signal network is high, transistor Q1 is off, and the enable pin 2OE# of the tri-state buffer chip U10 is pulled low through the pull-down resistor R12, allowing the tri-state buffer chip U10 to operate normally and output a PWM signal. When a short-circuit fault occurs, the fault signal network is pulled low, transistor Q1 turns on, pulling the enable pin 2OE# of the tri-state buffer chip U10 high, thus putting the tri-state buffer chip U10 into a high-impedance state, directly blocking the output of all PWM drive signals in hardware.

[0044] This application further proposes incorporating impedance matching resistors R16, R26, and R27 in the low-voltage side fault latching and blocking control unit. Specifically, impedance matching resistor R16 is connected in series between the OUT pin of U12 and the anode of D1, impedance matching resistor R26 is connected in series between the OUT pin of U13 and the anode of D2, and impedance matching resistor R27 is connected in series between the OUT pin of U14 and the anode of D3. Each impedance matching resistor aims to suppress signal ringing and reflection interference during high-speed fault signal transmission and improve the circuit's immunity to dv / dt noise.

[0045] Impedance matching resistors are commonly used in high-speed signal transmission paths. By adjusting the impedance of the transmission line to match the impedance of the signal source or load, they minimize signal reflection during transmission. When the signal source impedance does not match the transmission line impedance, the signal will reflect at the impedance discontinuity, causing waveform distortion and ringing. By connecting impedance matching resistors in series, reflected energy can be effectively absorbed, improving signal integrity. In this embodiment, impedance matching resistors R16, R26, and R27 are connected in series between the OUT pins of isolation comparators U12, U13, and U14 and the anodes of diodes D1, D2, and D3, respectively. Their function is to match the output impedance of the isolation comparators with the input impedance of the subsequent diode logic AND gate circuits, thereby ensuring that fault signals output from the isolation comparators can be transmitted to the diode logic AND gate circuits with a smoother and clearer waveform, avoiding signal reflection and ringing caused by impedance mismatch. Signal ringing and reflection interference are common signal integrity problems in high-speed digital circuits. They cause signal levels to cross logic thresholds multiple times, potentially leading to misinterpretations as multiple signal transitions or prolonged signal settling times. Introducing impedance matching resistors can effectively suppress these phenomena, resulting in steeper rising and falling edges of fault signals without overshoot, thus improving signal determination accuracy. Furthermore, a clearer signal waveform also means enhanced immunity to external noise (including dv / dt noise generated by high-speed switching in SiC devices), as noise is less likely to cause signal levels to cross clear logic thresholds, reducing the risk of false triggering.

[0046] This application further proposes the following overall fault protection process for the circuit: inverter bridge arm short circuit → lower bridge shunt resistor generates over-threshold sampling voltage → high-voltage side isolation comparator compares the sampling voltage with Vref and then flips the level → opto-isolation transmits the fault signal to the low-voltage side → corresponding latching transistor turns on to lock the fault state → diode AND gate pulls the Fault signal low → wave blocking control transistor turns on to turn off the tri-state buffer → all PWM drive signals are hardware blocked, the entire hardware path is completed, and the total response time is ≤1.2μs.

[0047] The fault signal is safely and quickly transmitted from the high-voltage side to the low-voltage side control circuit through the built-in opto-isolation channel of the isolation comparator. Opto-isolation effectively blocks the interference of common-mode high-voltage noise generated by the high-voltage side switch on the low-voltage control domain. On the low-voltage side, upon receiving the fault signal, the corresponding latching transistors, such as transistors Q2, Q3, and Q4, will immediately conduct after their bases receive the low-level output signal from the isolation comparator. This conduction pulls up the level of the LATCH latch pin of the isolation comparator, thus enabling the hardware latching function of the isolation comparator. Once the fault state is hardware latched, even if the fault disappears momentarily, the output level will remain locked at a low level, ensuring reliable retention of the fault information until the entire system is powered on again.

[0048] Next, the low-level fault output signal of the isolation comparator is fed into a diode AND gate circuit, which includes diodes D1, D2, and D3. When any one phase isolation comparator outputs a low level, the corresponding diode conducts forward, pulling the common fault signal network low. This achieves hardware OR logic aggregation of the three-phase fault signals, ensuring that a short-circuit fault in any one phase can trigger a unified system-level fault signal.

[0049] The pulled-down Fault signal is then sent to the buffer enable blocking control circuit. Specifically, the Fault signal is connected to the base of the blocking control transistor Q1. When the Fault signal is low, transistor Q1 is turned on. The collector of transistor Q1 is connected in series with resistor R12 to the low-active enable pin 2OE# of the tri-state buffer chip U10. When Q1 is turned on, it pulls the level of pin 2OE# high. When the enable pin 2OE# of the tri-state buffer chip U10 is pulled high, U10 immediately enters a high-impedance state. In the high-impedance state, the tri-state buffer U10 cannot output the received original MCU PWM drive signal, thus achieving hardware blocking of all PWM drive signals and immediately cutting off the drive of the silicon carbide power transistor.

[0050] This application further proposes that the high-speed isolation comparator simultaneously achieves electrical isolation between the high-voltage sampling circuit and the low-voltage control circuit, blocking common-mode high-voltage noise crosstalk generated by the 50-100kV / μs high-speed switching of SiC devices to the low-voltage control domain of the MCU, and eliminating the noise-induced triggering defects of traditional sampling schemes. Specifically, electrical isolation refers to the complete electrical separation of two or more circuit parts in a circuit through a non-conductive medium to prevent direct transmission of current or voltage between them. In this application, the high-speed isolation comparator achieves electrical isolation between the high-voltage side current sampling circuit and the low-voltage side control circuit through a built-in opto-isolation channel or by using other isolation technologies (such as magnetic isolation, capacitive isolation). This isolation mechanism ensures that transient high voltage or noise on the high-voltage side will not be directly coupled to the sensitive control circuit on the low-voltage side, thereby protecting the MCU and other control components on the low-voltage side from high-voltage surges and interference. Silicon carbide (SiC) power devices, due to their excellent switching characteristics, can achieve extremely high switching speeds, with dv / dt (voltage change rate) reaching 50-100kV / μs. High-speed switching generates significant common-mode high-voltage noise, which, through parasitic capacitance and inductance coupling, can easily crosstalk into the low-voltage control domain, especially the main control MCU. The high-speed isolation comparator, through its electrical isolation function, physically isolates the common-mode noise path between the high-voltage and low-voltage sides, effectively suppressing the propagation of this high-frequency, high-amplitude common-mode noise into the MCU's low-voltage control domain, thus avoiding the impact of noise on the normal operation of the MCU. In traditional current sampling schemes without effective isolation measures, the common-mode high-voltage noise generated by the high-speed switching of SiC devices is directly superimposed on the sampling signal, causing the instantaneous value of the sampling signal to exceed the preset overcurrent threshold, thereby triggering misjudgments and false triggers in the protection circuit. Such false triggers can cause the system to perform protection actions in a non-fault state, such as blocking the PWM drive signal, resulting in system shutdown or performance degradation. By using a high-speed isolation comparator to electrically isolate the high-voltage and low-voltage sides and effectively block the crosstalk of common-mode high-voltage noise, this application can ensure the purity and accuracy of the sampling signal, fundamentally eliminating the false trigger defects caused by noise, and improving the reliability of the protection circuit and the operational stability of the system.

[0051] This application further proposes that the circuit adopts a direct sampling architecture with the lower bridge emitter shunt resistor, which avoids the blanking and turn-on blind zone of more than 4μs in the traditional SiC desaturation detection, monitors the bridge arm current in real time throughout the entire switching cycle, and has no detection blind zone. At the same time, compared with the gate charge detection scheme, it simplifies the peripheral circuit and improves the long-term operational reliability of automotive-grade systems.

[0052] Specifically, the lower bridge emitter shunt resistor direct sampling architecture directly measures the current flowing through the power transistor by connecting a low-resistance resistor in series with the emitter (or source of the MOSFET) of the lower bridge arm power transistor in the inverter main circuit. When the power transistor is turned on, the current flows through the shunt resistor, generating a voltage signal proportional to the current across it. This voltage signal can be used as the input for current sampling, directly reflecting the magnitude of the bridge arm current. This direct sampling method features fast response speed and high measurement accuracy, enabling real-time capture of current changes. Traditional desaturation detection methods determine short-circuit faults by monitoring the drain-source voltage (Vds) of the power transistor. However, to avoid false triggering caused by device turn-on transients, a relatively long blanking time is usually required, during which short-circuit detection is not possible. For silicon carbide power devices, their short-circuit withstand time is extremely short (typically only 2-3 μs). If there is a blanking blind zone of more than 4 μs, the short-circuit fault may cause permanent damage to the device before it is detected. Direct sampling using the lower-bridge emitter shunt resistor eliminates the need for a blanking time, effectively avoiding this detection blind spot, as it is independent of Vds stability. Given the characteristics of this architecture, the current signal can be continuously and in real-time monitored as long as the lower-bridge power transistor is on. This means that the current is constantly monitored throughout the entire conduction cycle, from the moment the power transistor turns on to its turn-off, eliminating any detection blind spots. This is particularly important for rapidly changing short-circuit currents, ensuring timely detection of any short-circuit fault. Gate charge detection schemes typically require complex circuitry to accurately measure and analyze the gate charge or gate voltage / current waveform of the power transistor to indirectly infer the current state. Such schemes often have complex peripheral circuitry, including numerous active components and precise timing control, increasing system design complexity and potential failure points. In contrast, the lower-bridge emitter shunt resistor direct sampling scheme primarily relies on resistors and simple signal conditioning circuitry, resulting in a simpler peripheral circuit structure with fewer components, thus reducing system cost and design complexity. The simplification of the circuit directly improves the long-term operational reliability of the system, which is crucial for automotive-grade applications with extremely high reliability requirements.

[0053] This application further proposes that the Fault signal be output simultaneously in two channels: one channel is connected to the blocking control circuit to realize hardware instantaneous blocking protection; the other channel is connected to the fault detection IO port of the main control MCU. After the MCU detects the Fault low level, it performs fault recording, power reduction, reports short circuit alarm to the host computer, and fault shutdown secondary protection actions.

[0054] Specifically, the Fault signal is an indication signal generated by the short-circuit protection circuit of the silicon carbide power device after detecting a short-circuit fault. It is designed with two simultaneous outputs to achieve layered and parallel fault handling. One output triggers a rapid hardware-level response, ensuring the drive signal is cut off in a very short time to prevent device damage. This Fault signal is directly connected to the blocking control circuit. The blocking control circuit typically consists of hardware components such as high-speed logic gates and tri-state buffers. Its function is to immediately place the PWM drive signal to a high impedance state or a low level upon receiving the Fault signal, thereby quickly shutting off the drive of the silicon carbide power transistor. This purely hardware-implemented instantaneous blocking protection has an extremely fast response speed, completing the protection action within the short-circuit tolerance time of the silicon carbide device, effectively preventing thermal breakdown of the device.

[0055] The other fault signal is provided to the main MCU, enabling it to participate in higher-level fault management and system recovery processes. This fault signal is led out and connected to a dedicated fault detection I / O port of the main MCU (Microcontroller Unit). This I / O port is configured in input mode to monitor the status of the fault signal in real time. When the fault signal goes low (usually indicating a fault has occurred), the MCU can detect this change through interrupts or polling, thereby triggering the corresponding fault handling procedure. This connection method allows the MCU to promptly detect hardware-level fault events.

[0056] When the main control MCU detects a low-level Fault signal through the fault detection I / O port, it immediately initiates a series of preset fault handling procedures. First, it logs the fault, storing key information such as the time and type of the fault in non-volatile memory for subsequent analysis and diagnosis. Second, based on the severity of the fault and the system's operating status, it performs power reduction operations, such as reducing the inverter's output power, to alleviate system stress and buy time for further processing. Simultaneously, it reports a short-circuit alarm to the host computer (such as a vehicle controller or monitoring system), notifying operators or higher-level control systems. Finally, it executes secondary fault shutdown protection actions, such as safely shutting down the entire system to ensure the safety of personnel and equipment. These actions collectively constitute the MCU-level advanced fault management strategy, complementing the hardware-based instantaneous signal blocking.

[0057] To address this issue, this application proposes a short-circuit protection circuit for silicon carbide power devices, employing a hardware pass-through blocking architecture capable of completing short-circuit protection for SiC devices within 1.2μs. However, in application scenarios such as 800V high-voltage new energy vehicle electric drive platforms, the short-circuit withstand time of silicon carbide MOSFET devices is extremely short, typically only 2-3μs. Within this stringent time window, it is crucial not only to ensure extremely rapid protection action to prevent thermal breakdown of the device but also to avoid false blocking caused by transient noise, thereby ensuring the continuity of power and the stability of system operation during vehicle operation. This places higher demands on the design of the protection circuit.

[0058] The protection circuit of this application is adapted to the 800V high-voltage electric drive platform of new energy vehicles. Taking into account the short-circuit withstand time of only 2-3μs of SiC MOSFET, it relies on a pure hardware high-speed protection link to cut off the drive signal before the device thermally breaks down, thus blocking the continuous accumulation of short-circuit energy. In addition, the fault latching mechanism avoids the interruption of vehicle driving power caused by instantaneous noise false blocking waves, thus balancing the protection response speed and system operation stability.

[0059] Specifically, the protection circuit is adapted to the 800V high-voltage electric drive platform of new energy vehicles, meaning that the protection circuit is designed to operate stably and reliably in the 800V high-voltage electric drive system of new energy vehicles. This requires that the selection of components, layout and wiring, insulation and isolation in the circuit all meet the requirements of high voltage, high current, high power density and stringent electromagnetic compatibility.

[0060] Due to the short-circuit withstand time of only 2-3 μs for SiC MOSFETs, and the excellent switching characteristics of silicon carbide MOSFETs, the internal junction temperature rises rapidly when a short-circuit fault occurs, resulting in a very narrow thermal breakdown time window, typically only 2-3 microseconds. This characteristic requires short-circuit protection circuits to have extremely high response speeds, far exceeding the protection time requirements of traditional silicon-based IGBT devices. Therefore, the design of the protection circuit must aim for a nanosecond (ns) response speed to ensure that the drive signal can be cut off in time before the device reaches the thermal breakdown critical point.

[0061] Relying on a purely hardware-based high-speed protection link, the drive signal is cut off before the device thermally breaks down, preventing the continuous accumulation of short-circuit energy. This means that the protection function is implemented entirely by discrete hardware circuits, without relying on software judgment and processing by a microcontroller (MCU). This architecture avoids the time overhead caused by software execution, interrupt handling, and communication delays, thus achieving an ultra-fast response at the nanosecond level. Its core lies in directly detecting the overcurrent signal through a high-speed comparator and immediately triggering the blocking of the drive signal. This ensures that the drive signal is quickly cut off within the short-circuit withstand time window of the SiC MOSFET, effectively preventing the short-circuit current from continuously flowing inside the device, thereby avoiding permanent damage to the device due to overheating.

[0062] Furthermore, the fault latching mechanism prevents transient noise from falsely blocking the vehicle's power supply. This means that once a short-circuit fault is detected, the fault state is locked by the hardware circuitry. Even if the transient noise disappears, the fault signal will continue to be output until the system is manually reset or powered on again. This mechanism can effectively distinguish between genuine short-circuit faults and transient noise caused by electromagnetic interference, transient spikes, etc. In new energy vehicle applications, transient noise may cause protection circuits to malfunction, unnecessarily blocking the drive signal, causing a power interruption, affecting driving experience and safety. Fault latching ensures that only persistent, genuine faults trigger protection, thereby improving the system's anti-interference capability and operational stability.

[0063] Balancing protection response speed and system operational stability refers to the trade-off between these two factors. Protection response speed refers to the time required from the occurrence of a short-circuit fault to the interruption of the drive signal, while system operational stability refers to the system's ability to operate normally or without unnecessary shutdowns due to transient disturbances. In SiC power device protection, these two aspects often present a contradiction: an excessively fast response may be overly sensitive to noise, leading to false triggering; while an excessively slow response may fail to protect the device in time. This implementation method ensures an extremely fast response speed through a purely hardware-based high-speed protection link, while simultaneously combining a fault latching mechanism to effectively filter out transient noise and avoid false blocking, thus meeting the stringent protection time requirements of SiC devices while ensuring the long-term stable operation of the electric drive system for new energy vehicles.

[0064] The following example will provide a more detailed explanation of the above technical solution: In an 800V high-voltage electric drive inverter for new energy vehicles, a short-circuit protection circuit for silicon carbide power devices is used to protect the silicon carbide power transistors in the inverter. The main inverter circuit carries these silicon carbide power transistors and outputs drive power. When the electric drive system is in operation, for example, if a short circuit occurs in one phase arm of the main inverter circuit due to insulation failure in the motor windings, this protection circuit will activate.

[0065] Specifically, the inverter main circuit includes a three-phase inverter power transistor group, a lower bridge shunt sampling resistor group, and a bus filter capacitor C25. The three-phase inverter power transistor group consists of phase A upper transistor U1, phase A lower transistor U6, phase B upper transistor U2, phase B lower transistor U7, phase C upper transistor U3, and phase C lower transistor U8. These power transistors are all silicon carbide MOSFET devices. The lower bridge shunt sampling resistor group includes phase A shunt resistor R8, phase B shunt resistor R9, and phase C shunt resistor R10. In the event of a short-circuit fault, such as a short circuit in phase A bridge arm, an over-threshold voltage proportional to the phase current of the bridge arm will be generated across the phase A shunt resistor R8 connected in series with the emitter of phase A silicon carbide lower transistor U6. This voltage serves as the high-voltage side current sampling input signal. The bus filter capacitor C25 is connected in parallel across the DC high-voltage bus to filter the high-voltage bus voltage and suppress switching spike noise.

[0066] The high-voltage side current sampling and comparison unit is electrically connected to the lower bridge arm of the inverter main circuit, acquiring the bridge arm current in real time and comparing it at high speed with a preset overcurrent threshold. This unit contains three high-speed isolated comparison branches with identical structures, corresponding to the A / B / C three-phase inverter bridge arms respectively. Taking phase A as an example, its high-speed isolated comparison branch includes a high-speed isolation comparator U12, a high-voltage side power supply RC filter circuit, a current sampling RC filter circuit, and a reference voltage generation circuit. The high-voltage side power supply RC filter circuit consists of resistor R11, capacitor C5, and capacitor C6, used to filter out dv / dt coupling interference from the high-voltage side switch on the high-voltage power supply pin of U12. The current sampling RC filter circuit consists of resistor R13 and capacitor C4, one end connected to the sampling output terminal of the phase A shunt resistor R8, and the other end connected to the analog input pin of the isolation comparator U12, used to filter out parasitic inductance noise generated by the silicon carbide high-speed switch. Unlike traditional current detection schemes that are susceptible to parasitic inductance noise interference in existing technologies, this scheme effectively improves the anti-interference capability through RC filtering. The reference voltage generation circuit consists of a reference resistor R14 and a bypass capacitor C3. The REF reference pin of the isolation comparator U12 has a built-in 100μA constant current source, which flows through the reference resistor R14 to generate a precision threshold reference voltage Vref. The bypass capacitor C3 performs high-frequency filtering on Vref. When the sampling voltage of the A-phase shunt resistor R8 is greater than Vref, the low-voltage side OUT output level of the isolation comparator U12 immediately flips to a low-level fault signal. The high-speed isolation comparator U12 simultaneously achieves electrical isolation between the high-voltage sampling circuit and the low-voltage control circuit, effectively blocking the common-mode high-voltage noise crosstalk generated by the 50-100kV / μs high-speed switching of the silicon carbide device to the low-voltage control domain of the main control MCU, avoiding the noise-induced false triggering defects of traditional sampling schemes.

[0067] The fault signal is transmitted to the low-voltage side fault latching and blocking control unit via opto-isolation. Upon receiving the high-voltage side isolation fault signal, this unit will hardware-latch the fault state and directly block the PWM drive signal output, while simultaneously reporting the fault identifier to the main control MCU. The low-voltage side fault latching and blocking control unit includes an isolation comparator low-voltage power supply filter branch, a three-phase independent fault latching branch, a diode logic AND gate circuit, a three-state buffer drive signal conversion circuit, and a buffer enable blocking control circuit. The isolation comparator low-voltage power supply filter branch is equipped with bypass capacitors C7 and C8, connected in parallel across the 5V low-voltage side power supply of U12 to stabilize the low-voltage control side power supply voltage.

[0068] When the OUT output of U12 is low-level fault signal, the transistor Q2 (composed of transistor Q2 and resistor R15) in the corresponding three-phase independent fault latch branch is turned on, pulling the LATCH latch pin of U12 high and enabling the hardware latch function to continuously lock the low-level fault state of OUT. This fault state can only be cleared by powering on the entire unit, avoiding the interruption of vehicle driving power caused by transient noise false blocking waves, thus balancing protection response speed and system operation stability.

[0069] Meanwhile, the anodes of diode D1 (including diodes D1, D2, and D3) in the diode logic AND gate are connected to the OUT output terminal of U12. When U12 outputs a low level, diode D1 is forward-biased, pulling the entire Fault signal network low, thus achieving hardware or logic aggregation of the three-phase fault signals. An impedance matching resistor R16 is connected in series between the OUT pin of U12 and the anode of D1 to suppress signal ringing and reflection interference during high-speed fault signal transmission, improving the circuit's immunity to dv / dt noise.

[0070] The fault signal is output simultaneously in two paths: one path connects to the buffer enable and blocking control circuit, and the other path connects to the fault detection I / O port of the main control MCU. In the buffer enable and blocking control circuit, the base of transistor Q1 is connected to the fault signal network, and the collector of Q1 is connected in series with pull-down resistor R12 and then to the low-active enable pin 2OE# of the tri-state buffer chip U10. When there is no fault, Fault is high, transistor Q1 is off, 2OE# is pulled down to low by R12, and U10 outputs the PWM signal normally. When there is a short-circuit fault, Fault is low, transistor Q1 is on, pulling the 2OE# pin high, U10 enters a high-impedance state, and the hardware directly blocks all PWM drive outputs. The tri-state buffer chip U10 in the tri-state buffer drive signal conversion circuit receives six raw PWM drive signals (DSP_UH, DSP_UL, DSP_VH, DSP_VL, DSP_WH, DSP_WL) from the MCU at its input. The U10 output converts these signals to generate standard 5V drive levels (UH, UL, VH, VL, WH, WL). These six output signals are then connected to the input terminals of the corresponding optocouplers for the three-phase silicon carbide power transistors. Capacitor C1 is connected in parallel to the power supply pin of U10 for power filtering.

[0071] After the main control MCU detects a low level of Fault, it performs the following secondary protection actions: fault recording, power reduction, reporting a short circuit alarm to the host computer, and fault shutdown.

[0072] The fault protection process of the entire circuit is as follows: inverter bridge arm short circuit → lower bridge shunt resistor generates over-threshold sampling voltage → high-voltage side isolation comparator compares the sampled voltage with Vref and then flips the level → opto-isolation transmits the fault signal to the low-voltage side → corresponding latching transistor Q2 turns on to lock the fault state → diode AND gate pulls the Fault signal low → wave blocking control transistor Q1 turns on to turn off the tri-state buffer U10 to enable → all PWM drive signals are hardware blocked. This circuit adopts a hardware pass-through wave blocking architecture, which can complete the short circuit protection of silicon carbide devices within 1.2μs without the participation of MCU. Compared with the short circuit withstand time characteristic of silicon carbide MOSFETs of only 2-3μs, this pure hardware ultra-fast protection link can cut off the drive signal before the device thermally breaks down, preventing the continuous accumulation of short circuit energy. Meanwhile, the circuit adopts a direct sampling architecture with the lower bridge emitter shunt resistor, which avoids the blanking and turn-on blind zone of more than 4μs in traditional silicon carbide desaturation detection. It realizes real-time monitoring of bridge arm current throughout the entire switching cycle without detection blind zone. Compared with the gate charge detection scheme, it simplifies the peripheral circuit and improves the long-term operational reliability of automotive-grade systems.

[0073] In use, this application provides a short-circuit protection circuit for silicon carbide power devices to solve the bridge arm shoot-through protection problem in new energy vehicle drives and industrial frequency converters. To achieve the above objective, the technical solution adopted by this invention is as follows: the circuit is a protection circuit that combines lower bridge emitter current sampling, high-speed isolation comparator output latch-up, and buffer enable. The core uses a high-speed isolation comparator to collect the high-voltage side bridge arm current signal and compare it with a preset reference voltage of the high-speed isolation comparator. The comparison value is output to the low-voltage control side via internal optocoupler. A fault overcurrent low-level latch signal is output after a diode AND gate to disable the buffer and notify the MCU. This circuit prioritizes disabling the buffer enable signal to block the PWM output. Subsequently, the MCU performs a protection action and issues a warning message to the host computer. Within a 1.2µs time period, the hardware action fully protects the silicon carbide power device. This overcurrent protection circuit is as follows: Figure 1 As shown, the high-voltage side consists of capacitor C25, power transistors U1 / U2 / U3 / U6 / U7 / U8, and shunts R8 / R9 / R10 forming the inverter main circuit. Shunts R3 / R4 / R5 form the output current sampling circuit. The high-speed isolation comparators U12 / U13 / U14 and their peripheral components have the same function. R8 / R9 / R10 are shunts for detecting bridge arm current. According to Ohm's law U=IR, the voltage across these shunts corresponds to the current flowing through the lower bridge. Therefore, the high-speed isolation comparators U12 / U13 / U14 determine whether the bridge arm is overcurrent based on the shunt voltage. R11 / C6 / C5, R17 / C12 / C11, and R21 / C17 / C18 form the high-voltage side chip power supply RC filter circuit for U12 / U13 / U14. R13 / C4, R18 / C... 10. R22 / C16 form RC filters for the high-voltage side bridge arm current detection circuit of U12 / U13 / U14 respectively; the REF pin of U12 / U13 / U14 is the preset voltage reference pin, which integrates a 100uA constant current source. The constant current source provides a precision reference voltage Vref for U12 / U13 / U14 through R14 / R19 / R23 respectively. The bypass capacitors C3 / C9 / C15 perform high-frequency filtering on the precision reference voltage Vref. When the external sampling voltage is higher than Vref, the isolation comparator will activate, causing the OUT output level to flip to low.

[0074] The low-voltage side circuit consists of chips U10, U12, U13, and U14, along with peripheral circuitry. Bypass capacitors C7 / C8, C14 / C18, and C19 / C20 filter the 5V input power to the low-voltage side of U12 / U13 / U14. Q2 / Q3 / Q4 and resistors R15 / R20 / R24, along with the low-voltage side OUT error output pin and LATCH latch pin of U12 / U13 / U14, form an error latch circuit. When any chip's OUT pin outputs a low level, the connected transistors (Q2 / Q3 / Q4) turn on, and the corresponding LATCH latch pin flips from low to high, enabling the LATCH latch function. At this time, the low-level state of the OUT pin is latched. Diodes D1, D2, and D3 form an AND gate; when the cathode of any diode is low, the Fault network level will be pulled low. Resistors R16, R26, and R27 serve as impedance matching to prevent ringing during signal transmission. U10 is a tri-state buffer (input and output logic are the same); The DSP_UH / DSP_UL / DSP_VH / DSP_VL / DSP_WH / DSP_WL drive signals input from the MCU are converted into 5V level output signals UH / UL / VH / VL / WH / WL. These signals are then connected to the optocouplers driving power transistors U1, U6, U2, U7, U3, and U8, respectively. C1 is the bypass filter capacitor for U10. Q1 and R12 form the control circuit for the U10 output enable pin 2OE#, which is in a low-level enable state by default. When the fault signal pin is low, transistor Q1 turns on, allowing current to flow through R12, and the U10 enable pin 2OE# goes high, turning off the PWM signal output to the drive optocouplers.

[0075] 1. Normal operating state of the inverter circuit When the inverter circuit is operating normally, the voltage generated by the current flowing through R8 / R9 / R10 in each phase does not exceed the reference voltage value Vref of the optocoupler comparator, and the isolation comparator remains inactive. The OUT pin remains high, and D1, D2, and D3 cannot conduct forward, causing the Fault signal to remain high. Transistor Q1 cannot conduct, causing the 2OE# enable signal to be continuously pulled low by R12. The MCU input PWM drive signal is always converted into a 5V PWM drive signal through buffer U10.

[0076] 2. Operating status of the inverter circuit when a short circuit fault occurs When a short-circuit fault occurs in any phase of the inverter circuit, the corresponding shunt in shunts R8 / R9 / R10 will generate a large voltage drop. When this voltage drop exceeds the reference voltage Vref of the optocoupler comparator, the isolation comparator will flip its state. The OUT pin outputs a low level, and the corresponding diodes (D1, D2, D3) will conduct. At the same time, the transistors (Q2, Q3, Q4) will also conduct. The current through the resistors (R15, R20, R24) increases the voltage across the resistors, enabling the LATCH latch pin, and OUT remains low. Subsequently, the Fault pin remains low, which turns on transistor Q1. The current flowing through resistor R12 after transistor Q1 is turned on increases its own voltage. At this time, the voltage of the buffer enable pin 2OE# flips, and the buffer cannot output the PWM drive signal (UH / UL / VH / VL / WH / WL) normally, instead exhibiting a high impedance state. The entire inverter circuit needs to be cleared of short circuit faults and powered on again before it can operate normally.

[0077] As described above, this circuit protects silicon carbide power devices through a process of sampling by the lower bridge arm shunt of the inverter circuit → voltage comparison by the isolation comparator → opto-isolation → state flip-flopping latch → enable flip-flopping → output blocking. The core principle is to compare the sampled current values ​​of each inverter bridge circuit with the preset threshold voltage of the isolation comparator, and then condition the signal to directly control the enable output of the buffer. Because the high-speed isolation comparator has the characteristics of preset threshold, short response time, high protection accuracy, and strong common-mode interference resistance, it can perform PWM blocking processing before the MCU in case of a fault, completing the protection of the silicon carbide power devices within 1.2µs, avoiding the risk of damage to the power devices due to an excessively long response loop.

[0078] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A short-circuit protection circuit for silicon carbide power devices, characterized in that: It includes the inverter main circuit, the high-voltage side current sampling and comparison unit, and the low-voltage side fault latching and blocking control unit; The inverter main circuit is used to carry silicon carbide power transistors and output driving power; the high-voltage side current sampling and comparison unit is electrically connected to the lower bridge arm of the inverter main circuit, collects the bridge arm current in real time and compares it with a preset overcurrent threshold at high speed, and outputs an isolation fault signal to the low-voltage side when a fault occurs; the low-voltage side fault latching and blocking control unit receives the high-voltage side isolation fault signal, hardware latches the fault state and directly blocks the PWM drive signal output, and reports the fault mark to the main control MCU. The short-circuit protection circuit for the silicon carbide power device adopts a hardware pass-through blocking architecture.

2. The short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The inverter main circuit includes a three-phase inverter power transistor group, a lower bridge shunt sampling resistor group, and a bus filter capacitor; The three-phase inverter power transistor group includes phase A upper transistor U1, phase A lower transistor U6, phase B upper transistor U2, phase B lower transistor U7, phase C upper transistor U3, and phase C lower transistor U8. All power transistors are silicon carbide MOSFET devices. The lower bridge shunt sampling resistor group includes phase A shunt resistor R8, phase B shunt resistor R9, and phase C shunt resistor R10; the emitters of each phase silicon carbide lower transistor are connected in series with the corresponding shunt resistors and then grounded. The voltage across the shunt resistors is proportional to the phase current of the corresponding bridge arm and serves as the high-voltage side current sampling input signal. The bus filter capacitor C25 is connected in parallel across the DC high voltage bus.

3. The short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The high-voltage side current sampling and comparison unit includes three high-speed isolation comparison branches with completely identical structures, corresponding to the A / B / C three-phase inverter bridge arms respectively. Each high-speed isolation comparison branch includes a high-speed isolation comparator, a high-voltage side power supply RC filter circuit, a current sampling RC filter circuit, and a reference voltage generation circuit.

4. The short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The low-voltage side fault latching and blocking control unit includes an isolation comparator low-voltage power supply filtering branch, a three-phase independent fault latching branch, a diode logic AND gate circuit, a three-state buffer drive signal conversion circuit, and a buffer enable blocking control circuit.

5. A short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The low-voltage side fault latching and blocking control unit is also equipped with impedance matching resistors R16, R26, and R27; R16 is connected in series between the OUT pin of U12 and the anode of D1, R26 is connected in series between the OUT pin of U13 and the anode of D2, and R27 is connected in series between the OUT pin of U14 and the anode of D3.

6. The short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The overall fault protection process of the circuit is as follows: short circuit of inverter bridge arm → the shunt resistor of the lower bridge generates an over-threshold sampling voltage → the sampling voltage of the high-voltage side isolation comparator is compared with Vref and then the level flips → the fault signal is transmitted to the low-voltage side by opto-isolation → the corresponding latching transistor is turned on to lock the fault state → the diode AND gate pulls the fault signal low → the wave blocking control transistor is turned on to turn off the tri-state buffer is enabled → all PWM drive signals are hardware blocked, and the entire hardware path is completed.

7. The short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The high-speed isolation comparator simultaneously achieves electrical isolation between the high-voltage sampling circuit and the low-voltage control circuit, blocking common-mode high-voltage noise crosstalk generated by the 50-100kV / μs high-speed switching of SiC devices to the low-voltage control domain of the MCU.

8. A short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The circuit adopts a direct sampling architecture with the lower bridge emitter shunt resistor, avoiding the blanking and turn-on blind zone of more than 4μs in traditional SiC desaturation detection, and monitors the bridge arm current in real time throughout the entire switching cycle without detection blind zone.

9. A short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The Fault signal is output in two channels simultaneously: one channel is connected to the blocking control circuit to realize hardware instantaneous blocking protection; the other channel is connected to the fault detection IO port of the main control MCU. After the MCU detects the Fault low level, it performs fault recording, power reduction, reports short circuit alarm to the host computer, and performs secondary protection actions of fault shutdown.

10. A short-circuit protection circuit for a silicon carbide power device according to claim 1, characterized in that: The protection circuit is adapted to the 800V high-voltage electric drive platform of new energy vehicles. Taking into account the short-circuit withstand time of only 2-3μs for SiC MOSFETs, it relies on a pure hardware high-speed protection link to cut off the drive signal before the device thermally breaks down, thus preventing the continuous accumulation of short-circuit energy. In addition, the fault latching mechanism avoids the interruption of vehicle driving power caused by instantaneous noise false blocking waves, thus balancing the protection response speed and system operation stability.

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