ESD clamping circuit and ESD protection module

Abstract

The present disclosure provides an ESD clamp circuit and an ESD protection module, and relates to the technical field of integrated circuits. The circuit comprises an ESD trigger circuit, a first end of which is electrically connected with a first power supply, and a second end of which is electrically connected with a first node; the ESD trigger circuit raises the voltage of the first node in response to the first power supply being subjected to an ESD impact; a false trigger prevention circuit, a first end of which is electrically connected with the first node, a second end of which is electrically connected with a second node, and a third end of which is electrically connected with a third node; a voltage holding circuit, a first end of which is electrically connected with the second node, and a second end of which is electrically connected with a voltage clamp circuit through the third node; the voltage holding circuit raises the voltage of the third node to the voltage of the first power supply to make the voltage clamp circuit conductive in response to being triggered by the false trigger prevention circuit. The circuit of the present disclosure has a small area and effectively prevents false triggering.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to an ESD clamping circuit and an ESD protection module. Background Technology

[0002] Throughout the lifecycle of an integrated circuit, it may be affected by electrostatic discharge (ESD), which can cause damage to the internal circuitry of the chip and prevent the chip from functioning properly.

[0003] In related technologies, clamping circuits based on RC delayed triggering circuits and ESD clamping circuits based on changing the number of diodes are commonly used to ensure the performance and reliability of integrated circuits. However, ESD clamping circuits based on RC delayed triggering circuits consume a large area, which is not conducive to further miniaturization of integrated circuits. Severe leakage current leads to increased power consumption and is prone to false triggering. ESD clamping circuits based on changing the number of diodes have the problems of large leakage current and high static power consumption. Summary of the Invention

[0004] This disclosure provides an ESD clamping circuit and an ESD protection module, which at least to some extent overcomes the problems of false triggering, large leakage current, and high power consumption in related ESD clamping circuits.

[0005] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0006] According to one aspect of this disclosure, an ESD clamping circuit is provided, comprising an ESD triggering circuit, an anti-false triggering circuit, a voltage holding circuit, and a voltage clamping circuit, wherein:

[0007] The first terminal of the ESD trigger circuit is electrically connected to the first power supply, and the second terminal of the ESD trigger circuit is electrically connected to the first node. The ESD trigger circuit is used to increase the voltage of the first node in response to the first power supply being subjected to an ESD impact.

[0008] The first terminal of the anti-false triggering circuit is electrically connected to the first node, the second terminal of the anti-false triggering circuit is electrically connected to the second node, and the third terminal of the anti-false triggering circuit is electrically connected to the third node. It is used to respond to the first power supply being subjected to an ESD impact and the voltage change rate of the first power supply being greater than the voltage change rate of the first node, so that the anti-false triggering circuit is turned on, the voltage of the third node is increased, and the voltage holding circuit is triggered.

[0009] The first terminal of the voltage holding circuit is electrically connected to the second node, and the second terminal of the voltage holding circuit is electrically connected to the voltage clamping circuit through the third node. It is used to pull down the voltage of the second node in response to being triggered by the anti-false triggering circuit, so as to turn off the pull-down unit in the anti-false triggering circuit.

[0010] The voltage clamping circuit is electrically connected between the first power supply and the second power supply, and the controlled terminal of the voltage clamping circuit is electrically connected to the third node.

[0011] In one embodiment of this disclosure, the anti-false triggering circuit includes a first diode, a first PMOS transistor, and a first NMOS transistor, wherein the anode of the first diode is electrically connected to the first power supply, the cathode of the first diode is electrically connected to the source of the first PMOS transistor, the gate of the first PMOS transistor is electrically connected to the first node, and the drain of the first PMOS transistor is electrically connected to the third node.

[0012] The drain of the first NMOS transistor is electrically connected to the third node, the gate of the first NMOS transistor is electrically connected to the second node, and the source of the first NMOS transistor is electrically connected to the second power supply.

[0013] In one embodiment of this disclosure, the first diode includes a plurality of diodes connected in series.

[0014] In one embodiment of this disclosure, the voltage holding circuit includes a second PMOS transistor and a second NMOS transistor, the source of the second PMOS transistor is electrically connected to the first power supply, the gate of the second PMOS transistor is electrically connected to the third node, and the drain of the second PMOS transistor is electrically connected to the second node.

[0015] The gate of the second NMOS transistor is electrically connected to the third node, the source of the second NMOS transistor is electrically connected to the second power supply, and the drain of the second NMOS transistor is electrically connected to the second node.

[0016] In one embodiment of this disclosure, the ESD trigger circuit includes a first resistor unit and a protection unit. One end of the first resistor unit is electrically connected to the first power supply, and the other end of the first resistor unit is electrically connected to the first node. One end of the protection unit is electrically connected to the first node, and the other end of the protection unit is electrically connected to a second power supply.

[0017] In one embodiment of this disclosure, the protection unit includes at least one of a capacitor, a second diode, and a varistor.

[0018] In one embodiment of this disclosure, when the protection unit includes a capacitor, the ESD clamping circuit further includes a leakage protection circuit, which is electrically connected between the other end of the capacitor and the second power supply, and the controlled end of the leakage protection circuit is electrically connected to the third node.

[0019] In one embodiment of this disclosure, the leakage prevention circuit includes a third NMOS transistor, the drain of which is electrically connected to the other end of a capacitor, the source of which is electrically connected to the second power supply, and the gate of which is electrically connected to the third node as a controlled terminal.

[0020] In one embodiment of this disclosure, the voltage clamping circuit includes a clamping NMOS transistor, the gate of which is electrically connected to the third node, the drain of which is electrically connected to the first power supply, and the source of which is electrically connected to the second power supply.

[0021] In one embodiment of this disclosure, the ESD clamping circuit further includes a second resistor unit, one end of which is electrically connected to the third node, and the other end of which is electrically connected to a second power supply.

[0022] According to another aspect of this disclosure, an ESD protection module is provided, including the ESD clamping circuit provided in the above embodiments.

[0023] In embodiments of this disclosure, the ESD clamping circuit includes an ESD triggering circuit, whose first terminal is electrically connected to a first power supply and whose second terminal is electrically connected to a first node. The ESD triggering circuit increases the voltage of the first node in response to an ESD surge to the first power supply. An anti-false triggering circuit is also included, whose first terminal is electrically connected to the first node, whose second terminal is electrically connected to a second node, and whose third terminal is electrically connected to a third node. In response to an surge to the first power supply and a voltage change rate greater than that of the first node, the anti-false triggering circuit is activated, pulling up the voltage of the third node and triggering a voltage holding circuit. A voltage holding circuit is further included, whose first terminal is electrically connected to the second node and whose second terminal is electrically connected to the voltage clamping circuit via the third node. In response to being triggered by the anti-false triggering circuit, it pulls down the voltage of the second node to turn off the pull-down unit in the anti-false triggering circuit. The voltage clamping circuit is electrically connected between the first and second power supplies, and its controlled terminal is electrically connected to the third node. This disclosure utilizes the gate leakage of the voltage clamping circuit to shut itself off, which can ensure sufficient discharge time. Combined with the anti-false triggering circuit, it eliminates the need for large capacitors, reduces the capacitor area occupied, and effectively prevents false triggering and reduces subthreshold current.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0025] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0026] Figure 1 This diagram illustrates the structure of an ESD clamping circuit provided in an embodiment of the present disclosure.

[0027] Figure 2 This diagram illustrates a circuit diagram of an ESD clamping circuit provided in an embodiment of the present disclosure.

[0028] Figure 3 A circuit diagram of another ESD clamping circuit provided in an embodiment of this disclosure is shown.

[0029] Figure 4 This diagram illustrates the structure of another ESD clamping circuit provided in an embodiment of the present disclosure.

[0030] Figure 5 A circuit diagram of yet another ESD clamping circuit provided in an embodiment of this disclosure is shown.

[0031] Figure 6 A circuit diagram of another ESD clamping circuit provided in an embodiment of this disclosure is shown.

[0032] Figure 7 This diagram illustrates the discharge current of the ESD clamping circuit provided in this embodiment when subjected to an ESD event.

[0033] Figure 8 This diagram illustrates the structure of an ESD protection module provided in an embodiment of the present disclosure.

[0034] The reference numerals in the attached figures are explained as follows:

[0035] 100. ESD clamping circuit; 110. ESD triggering circuit; 120. Anti-false triggering circuit; 130. Voltage holding circuit; 140. Voltage clamping circuit; 150. Leakage prevention circuit; 800. ESD protection module. Detailed Implementation

[0036] Preferred embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0037] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly stated.

[0038] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0039] The following disclosure provides many different implementations or examples for carrying out different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0040] The lifecycle of an integrated circuit typically includes the manufacturing, transportation, system integration, and user application stages. Electrostatic discharge (ESD) can occur at the pins of the integrated circuit during each of these stages. ESD can generate instantaneous high-voltage electrostatic pulses that flow through the chip's internal circuitry, causing damage and rendering the chip malfunction. As the integration level of microelectronic devices increases and the linewidth of processes narrows, the inherent resistance of integrated circuits to ESD events decreases, making it imperative to reduce the damage caused by ESD to integrated circuits.

[0041] In related technologies, ESD clamping circuits are commonly used to improve the performance and reliability of integrated circuits. ESD clamping circuits can be implemented using RC delay triggering circuits, or they can be implemented using voltage-triggered circuits that adjust the trigger voltage by changing the number of diodes to avoid false triggering.

[0042] For ESD clamping circuits based on RC delayed trigger circuits, when an ESD event occurs, the RC delayed trigger circuit can keep the gate voltage of the clamping transistor high for a period of time and release the ESD current. To ensure that the circuit can recognize the ESD event and has a sufficiently long power-on time, the RC time constant of the battery cell is 200ns. However, a 200ns RC time constant requires a large-value sensing capacitor, which occupies 30% to 40% of the layout area of ​​the entire ESD clamping circuit, resulting in significant area consumption, which is not conducive to reducing the size of the integrated circuit. Furthermore, a large-value sensing capacitor will also have significant leakage current, leading to increased power consumption of the ESD clamping circuit. In addition, ESD clamping circuits based on RC delayed trigger circuits are prone to false triggering during rapid power-on operations, resulting in poor reliability of the ESD clamping circuit.

[0043] For ESD clamping circuits based on varying the number of diodes, the issue of false triggering is not a concern. When the threshold voltage of the diode string is set higher than the supply voltage VDD, it ensures that the clamping transistor is turned off during rapid power-up operations. However, the diode string still suffers from high leakage current, especially at high temperatures, resulting in high static power consumption for the ESD clamping circuit.

[0044] To address at least some of the aforementioned technical problems, this disclosure provides an ESD clamping circuit 100, including an ESD trigger circuit 110, whose first terminal is electrically connected to a first power supply VDD and whose second terminal is electrically connected to a first node N1. The ESD trigger circuit 110 increases the voltage of the first node N1 in response to an ESD surge to the first power supply VDD. An anti-false triggering circuit 120 is also provided, whose first terminal is electrically connected to the first node N1, whose second terminal is electrically connected to a second node N2, and whose third terminal is electrically connected to a third node N3. This circuit increases the voltage of the first power supply VDD in response to an ESD surge to the first power supply VDD and the rate of change of the first power supply VDD is greater than a certain value. The voltage change rate of the first node N1 activates the anti-false triggering circuit 120, pulling up the voltage of the third node N3 and triggering the voltage holding circuit 130. The voltage holding circuit 130 has its first terminal electrically connected to the second node N2, and its second terminal electrically connected to the voltage clamping circuit 140 through the third node N3. In response to being triggered by the anti-false triggering circuit 120, it pulls down the voltage of the second node N2, thus turning off the pull-down unit in the anti-false triggering circuit 120. The voltage clamping circuit 140 is electrically connected between the first power supply VDD and the second power supply VSS, and its controlled terminal is electrically connected to the third node N3. This disclosure utilizes the gate leakage current of the voltage clamping circuit 140 to shut itself down, ensuring sufficient discharge time. Combined with the anti-false triggering circuit 120, it eliminates the need for a large capacitor, reducing the capacitor's footprint and effectively preventing false triggering and reducing subthreshold current.

[0045] The specific implementation of the ESD clamping circuit of this disclosure is described below with reference to the accompanying drawings.

[0046] Figure 1 This diagram illustrates the structure of an ESD clamping circuit 100 provided in an embodiment of this disclosure. Figure 1 As shown, in one embodiment, the ESD clamping circuit 100 of this disclosure includes an ESD triggering circuit 110, an anti-false triggering circuit 120, a voltage holding circuit 130, and a voltage clamping circuit 140, wherein:

[0047] The first terminal of the ESD trigger circuit 110 is electrically connected to the first power supply VDD, and the second terminal of the ESD trigger circuit 110 is electrically connected to the first node N1. The ESD trigger circuit 110 is used to increase the voltage of the first node N1 in response to the first power supply VDD being subjected to an ESD impact.

[0048] The first terminal of the anti-false triggering circuit 120 is electrically connected to the first node N1, the second terminal of the anti-false triggering circuit 120 is electrically connected to the second node N2, and the third terminal of the anti-false triggering circuit 120 is electrically connected to the third node N3. In response to the first power supply VDD being subjected to an ESD impact and the voltage change rate of the first power supply VDD being greater than the voltage change rate of the first node N1, the anti-false triggering circuit 120 is turned on, increasing the voltage of the third node N3 and triggering the voltage holding circuit 130.

[0049] The first terminal of the voltage holding circuit 130 is electrically connected to the second node N2, and the second terminal of the voltage holding circuit 130 is electrically connected to the voltage clamping circuit 140 through the third node N3. It is used to pull down the voltage of the second node N2 in response to being triggered by the anti-false triggering circuit 120, so that the pull-down unit in the anti-false triggering circuit 120 is turned off.

[0050] The voltage clamping circuit 140 is electrically connected between the first power supply VDD and the second power supply VSS, and the controlled terminal of the voltage clamping circuit 140 is electrically connected to the third node N3.

[0051] The first power supply VDD and the second power supply VSS can provide drive signals for the operating voltage of the clamping device in the voltage clamping circuit 140, so as to ensure that the ESD clamping circuit 100 can respond quickly and protect the internal circuit when an ESD event occurs.

[0052] The voltage value of the first power supply VDD can be determined according to the chip design and ESD protection strategy, and this disclosure does not impose specific limitations on it.

[0053] The voltage of the second power supply VSS is less than the voltage of the first power supply VDD. The second power supply VSS can be ground voltage GND or a negative power supply voltage.

[0054] In one embodiment, the anti-accidental triggering circuit 120 may include an anti-accidental triggering unit, a pull-up unit, and a pull-down unit, which are connected in series between the first power supply VDD and the second power supply VSS.

[0055] When the first voltage VDD is subjected to an ESD event, the anti-accidental touch unit is turned on. Since the voltage change rate of the first node N1 is less than the voltage change rate of the first power supply VDD, the voltage of the first node N1 cannot keep up with the change of the first power supply VDD, causing the pull-up unit to be turned on, thereby pulling up the voltage of the third node N3 to a high level, and thus turning on the voltage clamping circuit 140.

[0056] Furthermore, when the voltage of the third node N3 increases, the voltage holding circuit 130 is triggered. Under the control of the high level of the third node N3, the voltage holding circuit 130 pulls down the second node N2 to a low level, thereby controlling the pull-down unit of the anti-false triggering circuit to turn off, so that the potential of the third node N3 cannot be pulled down, ensuring that the voltage clamping circuit 140 has a sufficiently long turn-on time to fully discharge the electrostatic charge.

[0057] In this embodiment, the ESD clamping circuit 100 includes an ESD triggering circuit 110, whose first terminal is electrically connected to the first power supply VDD and whose second terminal is electrically connected to the first node N1. The ESD triggering circuit 110 increases the voltage of the first node N1 in response to an ESD surge to the first power supply VDD. An anti-false triggering circuit 120 has its first terminal electrically connected to the first node N1, its second terminal electrically connected to the second node N2, and its third terminal electrically connected to the third node N3. It increases the voltage of the first power supply VDD in response to an ESD surge to the first power supply VDD and the rate of change of the first power supply VDD being greater than that of the first node N1. The voltage change rate triggers the anti-false triggering circuit 120 to conduct, pulling up the voltage of the third node N3 and triggering the voltage holding circuit 130. The voltage holding circuit 130 has its first terminal electrically connected to the second node N2, and its second terminal electrically connected to the voltage clamping circuit 140 through the third node N3. In response to being triggered by the anti-false triggering circuit 120, it pulls down the voltage of the second node N2, thus turning off the pull-down unit in the anti-false triggering circuit 120. The voltage clamping circuit 140 is electrically connected between the first power supply VDD and the second power supply VSS, and its controlled terminal is electrically connected to the third node N3. This disclosure utilizes the gate leakage current of the voltage clamping circuit 140 to shut itself down, ensuring sufficient discharge time. Combined with the anti-false triggering circuit 120, it eliminates the need for a large capacitor, reducing the capacitor's footprint and effectively preventing false triggering and reducing subthreshold current.

[0058] Figure 2 This diagram illustrates a circuit diagram of an ESD clamping circuit provided in an embodiment of this disclosure. Figure 2 As shown, in one embodiment, the anti-false triggering circuit 120 includes a first diode D1, a first PMOS transistor MP0, and a first NMOS transistor MN0, wherein the anode of the first diode D1 is electrically connected to the first power supply VDD, the cathode of the first diode D1 is electrically connected to the source of the first PMOS transistor MP0, the gate of the first PMOS transistor MP0 is electrically connected to the first node N1, and the drain of the first PMOS transistor MP0 is electrically connected to the third node N3.

[0059] The drain of the first NMOS transistor MN0 is electrically connected to the third node N3, the gate of the first NMOS transistor MN0 is electrically connected to the second node N2, and the source of the first NMOS transistor MN0 is electrically connected to the second power supply VSS.

[0060] It should be noted that when the voltage of the first power supply VDD is greater than or equal to the forward voltage drop of the first diode D1, the first diode D1 is turned on; when the voltage of the first power supply VDD is less than the forward voltage drop of the first diode D1, the first diode D1 is turned off.

[0061] When the first diode D1 is turned on, the voltage change rate of the first node N1 and the voltage change rate of the first power supply VDD are tracked through the first PMOS transistor MP0 and the first NMOS transistor MN0.

[0062] When the first diode D1 is turned on and the first power supply VDD is slowly powered on, the first power supply VDD can charge the first node N1 in time because the time constant of the ESD trigger circuit is less than the rise time of the first power supply VDD. This makes the first node N1 and the first power supply VDD maintain the same level. At this time, the gate-source voltage of the first PMOS transistor MP0 is less than the turn-on threshold, so the first PMOS transistor MP0 is turned off. The drain-source voltage of the first PMOS transistor MP0 is significantly different, which keeps the third node N3 at a low level and prevents the voltage holding circuit 140 from being turned on.

[0063] When the first diode D1 is turned on and the first power supply VDD is rapidly powered on, the first power supply VDD cannot charge the first node N1 in time because the ESD trigger circuit duration is longer than the rise time of the first power supply VDD. This results in a voltage difference between the first node N1 and the first power supply VDD. During normal power-on, this voltage difference is usually small and insufficient to turn on the first PMOS transistor MP0. At this time, the drain-source voltage difference of the first PMOS transistor MP0 is large, causing the third node N2 to remain at a low level and preventing the voltage holding circuit 140 from being activated.

[0064] When the first power supply VDD is subjected to an ESD impact, the first diode D1 is turned on. At this time, the voltage change rate of the first node N1 cannot keep up with the voltage change rate of the first power supply VDD, causing the gate voltage of the first PMOS transistor MP0 (the voltage of the first node N1) to be lower than the source voltage (the voltage of the first power supply VDD), which turns on the first PMOS transistor MP0, pulls the third node to a high level, and then turns on the voltage holding circuit 140, providing a low-impedance path from the first power supply VDD to the second power supply VSS, dissipating electrostatic charge and protecting the internal circuit of the chip from electrostatic damage.

[0065] In this embodiment of the disclosure, by setting the first diode D1 in the anti-false triggering circuit 120, it can be ensured that the potential of the third node N3 will not rise during normal operation, effectively preventing false triggering and subthreshold conduction of the voltage clamping circuit 140, thereby improving the effectiveness and reliability of the ESD clamping circuit.

[0066] In one embodiment, the first diode D1 includes a plurality of diodes connected in series. The number of diodes can be determined according to actual needs, and this disclosure does not specifically limit it.

[0067] In adjacent diodes, the anode of one diode is connected to the cathode of another diode. The anode of multiple diodes connected in series is electrically connected to the first power supply VDD, and the cathode is electrically connected to the source of the first PMOS transistor MP0. This adjusts the potential of the third node N3, adjusts the start-up voltage of the ESD clamping circuit, and further prevents false triggering and subthreshold conduction of the voltage clamping circuit 140.

[0068] Continue to refer to Figure 2 In one embodiment, the voltage holding circuit 130 includes a second PMOS transistor MP1 and a second NMOS transistor MN1. The source of the second PMOS transistor MP1 is electrically connected to the first power supply VDD, the gate of the second PMOS transistor MP1 is electrically connected to the third node N3, and the drain of the second PMOS transistor MP1 is electrically connected to the second node N2.

[0069] The gate of the second NMOS transistor MN1 is electrically connected to the third node N3, the source of the second NMOS transistor MN1 is electrically connected to the second power supply VSS, and the drain of the second NMOS transistor MN1 is electrically connected to the second node N2.

[0070] It should be noted that when the first power supply VDD is subjected to an ESD event, the first PMOS transistor MP0 turns on, pulling the voltage of the third node N3 to a high level. On the one hand, the third node N3 controls the voltage clamping circuit 140 to turn on; on the other hand, with the third node N3 at a high level, the voltage of the second power supply VSS is less than the voltage of the third node N3, controlling the second NMOS transistor MN1 to turn on. The source-drain voltage of the second NMOS transistor MN1 is relatively small, pulling the second node N2 down to a low level. When the second node N2 is at a low level, the gate-source voltage of the first NMOS transistor MN0 is less than the corresponding threshold voltage. At this time, the first NMOS transistor MN0 cannot turn on and cannot pull the voltage of the third node N3 down to a low level, thus giving the voltage clamping circuit 140 a longer turn-on time to fully discharge the electrostatic current.

[0071] refer to Figure 2 and Figure 3In one embodiment, the ESD trigger circuit 110 includes a first resistor unit R1 and a protection unit. One end of the first resistor unit R1 is electrically connected to the first power supply VDD, and the other end of the first resistor unit R1 is electrically connected to the first node N1. One end of the protection unit is electrically connected to the first node N1, and the other end of the protection unit is electrically connected to the second power supply VSS, thereby achieving effective protection of the ESD clamping circuit 100.

[0072] In one embodiment, the protection unit includes at least one of a capacitor C1, a second diode D2, and a varistor.

[0073] like Figure 2 As shown, capacitor C1 is connected in series between the first node N1 and the second power supply VSS. When the second power supply VDD is subjected to an ESD event, capacitor C1 can store the electrical energy generated by the ESD event. During the charging process, capacitor C1 stores charge, forms an electric field, and removes high-frequency noise through its filtering characteristics, thereby protecting the internal circuitry of the chip from damage.

[0074] It should be noted that the ESD clamping circuit disclosed herein does not rely on increasing the capacitor area for discharge time, but rather shuts off through the leakage current of the voltage clamping circuit itself, thereby ensuring a sufficiently long discharge time. This effectively resolves the contradiction between discharge time and capacitor layout area, enabling rapid power-on, avoiding false triggering, and ensuring subthreshold conduction of the voltage clamping circuit 140 under normal operation, thus improving the effectiveness and reliability of the ESD clamping circuit.

[0075] like Figure 3 As shown, the protection unit may include multiple second diodes D2 connected in series. These multiple second diodes D2 are electrically connected between the first node N1 and the second power supply VSS. When the voltage of the first power supply VDD is lower than the forward voltage of the multiple second diodes D2, the multiple second diodes D2 are in the off state, and no current flows through them. When the first power supply VDD is subjected to an ESD event, the multiple second diodes D2 can respond quickly, and when the voltage of the first power supply VDD exceeds the forward voltage of the multiple second diodes D2, the second diodes D2 turn on, allowing current to flow. This clamps the voltage of the first node N3 to a relatively safe level, preventing excessive voltage.

[0076] In addition, the protection unit can also be a varistor, which is electrically connected between the first power supply VDD and the second power supply VSS. Under normal operating conditions, the resistance of the varistor is very high, equivalent to a resistor with infinite resistance or an open switch. When the first power supply VDD is subjected to an ESD event, the resistance of the varistor drops sharply as the voltage of the first power supply VDD increases, and it quickly conducts, clamping the voltage at the first node N1 to a relatively safe level and preventing excessive voltage.

[0077] like Figure 4 As shown, in one embodiment, when the protection unit includes capacitor C1, the ESD clamping circuit 100 further includes a leakage prevention circuit 150. The leakage prevention circuit 150 is electrically connected between the other end of capacitor C1 and the second power supply VSS. The controlled end of the leakage prevention circuit 150 is electrically connected to the third node N3, thereby preventing leakage of capacitor C1.

[0078] like Figure 5 As shown, in one embodiment, the anti-leakage circuit 150 includes a third NMOS transistor MN2, the drain of the third NMOS transistor MN2 is electrically connected to the other end of the capacitor C1, the source of the third NMOS transistor MN2 is electrically connected to the second power supply VSS, and the gate of the third NMOS transistor MN2 is electrically connected to the third node N3 as a controlled terminal.

[0079] During normal operation of the first power supply VDD, the potential of the third node N3 is very low, so the third NMOS transistor MN2 cannot be turned on. Therefore, the voltage difference across capacitor C1 is close to 0, thereby reducing the leakage current of capacitor C1.

[0080] When the first power supply VDD is subjected to an ESD event, the potential of the third node N2 is sufficient to turn on the third NMOS transistor MN2. After the third NMOS transistor MN2 is turned on, the capacitor C1 can discharge the charge to the second power supply VSS through the third NMOS transistor MN2.

[0081] In this embodiment of the disclosure, the leakage current of capacitor C1 can be effectively reduced and the reliability of the ESD clamping circuit can be improved by adding a third NMOS transistor MN2.

[0082] It should be noted that, in addition to using the third NMOS transistor MN2 to achieve the leakage prevention function, insulated gate bipolar transistors (IGBTs), NPN transistors, etc. can also be used, and this disclosure does not make specific limitations on this.

[0083] like Figures 5-6 As shown, in one embodiment, the voltage clamping circuit 140 includes a clamping NMOS transistor Mesd. The gate of the clamping NMOS transistor Mesd is electrically connected to a third node N3, the drain of the clamping NMOS transistor Mesd is electrically connected to a first power supply VDD, and the source of the clamping NMOS transistor Mesd is electrically connected to a second power supply VSS. When the third node N3 is high, the clamping NMOS transistor Mesd is turned on, realizing the function of discharging charge and effectively protecting the internal circuitry of the chip.

[0084] It should be noted that, in addition to using NMOS transistors, voltage clamping circuit 140 can also be IGBT or NPN transistor; this disclosure does not make any specific limitations on this.

[0085] Continue to refer to Figure 6 In one embodiment, the ESD clamping circuit 100 further includes a second resistor unit R2, one end of which is electrically connected to the third node N3, and the other end of which is electrically connected to the second power supply VSS. Specifically, one end of the second power supply unit R2 is electrically connected to the gate of the clamping NMOS transistor Mesd, thereby effectively suppressing the influence of noise from the second power supply VSS on the gate voltage of the clamping NMOS transistor.

[0086] It should be noted that the first resistor unit R1 and the second resistor unit R2 can be obtained by connecting resistors in series and / or in parallel, or by connecting self-biased transistors in series and / or in parallel, or by combining resistors and self-biased transistors. The number of resistors or self-biased transistors can be determined according to actual needs, and this disclosure does not make specific limitations in this regard.

[0087] like Figure 7 As shown, when the first power supply VDD is subjected to an ESD event, the first diode D1 conducts, and the rate of change of the voltage at the first node N1 is less than the rate of change of the first power supply VDD, thereby turning on the first PMOS transistor, pulling the third node N3 to a high level, and then turning on the discharge NMOS transistor Mesd, providing a low-impedance path from the first power supply VDD to the second power supply VSS to discharge electrostatic charge. On the other hand, the high level of the third node N3 controls the second NMOS transistor MN1 to conduct, pulling the second node N2 to a low level, thereby preventing the first NMOS transistor MN0 from conducting, so that the third node N3 cannot be pulled down, and the discharge NMOS transistor Mesd has a sufficiently long turn-on time to fully discharge electrostatic charge.

[0088] The gate oxide layer of the clamped NMOS transistor Mesd is relatively thick, and the leakage current is negligible. However, due to the channel leakage current Ich and gate junction leakage current Ijun of the first NMOS transistor, and the leakage current of the second resistor unit R2, the gate potential of the clamped NMOS transistor Mesd will not always be high. That is, the potential of the third node N3 cannot always be high. Therefore, the gate leakage of the clamped NMOS transistor Mesd is used to shut itself off, so as to ensure sufficient discharge time, which is not as good as using a large capacitor.

[0089] Figure 8 This diagram illustrates the structure of an ESD protection module 800 provided in an embodiment of this disclosure. Figure 8As shown, in one embodiment, the ESD protection module 800 of this disclosure includes the ESD clamping circuit 100 of the above embodiment. The ESD clamping circuit 100 is electrically connected to the first power supply VDD.

[0090] For example, the ESD protection module 800 can be a memory, which may include a power supply module, powered by a first power supply VDD. Within the memory, the power supply module may include control logic circuits, sensitive amplifiers, decoding circuits, ECC modules, data paths, address paths, and other supporting circuit modules to support the normal operation of the memory and protect the semiconductor devices within the memory from ESD damage.

[0091] By combining the ESD clamping circuit 100 described above, the integrated circuit can be protected from failure caused by ESD, thereby improving the performance and reliability of the integrated circuit.

[0092] In the embodiments of this application, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term "multiple" refers to two or more unless otherwise expressly defined. The terms "install," "connect," "link," and "fix" should be interpreted broadly. For example, "connect" can be a fixed connection, a detachable connection, or an integral connection; "link" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application based on the specific circumstances.

[0093] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the embodiments of the application and simplifying the description, and do not indicate or imply that the device or unit referred to must have a specific orientation or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the application.

[0094] In the description of this specification, the terms "one embodiment," "some embodiments," "specific embodiment," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of the claims. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0095] The above are merely preferred embodiments of the application examples and are not intended to limit the application examples. For those skilled in the art, the application examples can have various modifications and variations. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the application examples should be included within the protection scope of the application examples.

Claims

1. An electrostatic discharge (ESD) clamping circuit, characterized in that, It includes an ESD trigger circuit, an anti-false trigger circuit, a voltage holding circuit, and a voltage clamping circuit, among which: The first terminal of the ESD trigger circuit is electrically connected to the first power supply, and the second terminal of the ESD trigger circuit is electrically connected to the first node. The ESD trigger circuit is used to increase the voltage of the first node in response to the first power supply being subjected to an ESD impact. The first terminal of the anti-false triggering circuit is electrically connected to the first node, the second terminal of the anti-false triggering circuit is electrically connected to the second node, and the third terminal of the anti-false triggering circuit is electrically connected to the third node. It is used to respond to the first power supply being subjected to an ESD impact and the voltage change rate of the first power supply being greater than the voltage change rate of the first node, so that the anti-false triggering circuit is turned on, the voltage of the third node is increased, and the voltage holding circuit is triggered. The first terminal of the voltage holding circuit is electrically connected to the second node, and the second terminal of the voltage holding circuit is electrically connected to the voltage clamping circuit through the third node. It is used to pull down the voltage of the second node in response to being triggered by the anti-false triggering circuit, so as to turn off the pull-down unit in the anti-false triggering circuit. The voltage clamping circuit is electrically connected between the first power supply and the second power supply, and the controlled terminal of the voltage clamping circuit is electrically connected to the third node.

2. The ESD clamping circuit according to claim 1, characterized in that, The anti-false triggering circuit includes a first diode, a first PMOS transistor, and a first NMOS transistor, wherein the anode of the first diode is electrically connected to the first power supply, the cathode of the first diode is electrically connected to the source of the first PMOS transistor, the gate of the first PMOS transistor is electrically connected to the first node, and the drain of the first PMOS transistor is electrically connected to the third node. The drain of the first NMOS transistor is electrically connected to the third node, the gate of the first NMOS transistor is electrically connected to the second node, and the source of the first NMOS transistor is electrically connected to the second power supply.

3. The ESD clamping circuit according to claim 2, characterized in that, The first diode includes a plurality of diodes connected in series.

4. The ESD clamping circuit according to claim 1, characterized in that, The voltage holding circuit includes a second PMOS transistor and a second NMOS transistor. The source of the second PMOS transistor is electrically connected to the first power supply, the gate of the second PMOS transistor is electrically connected to the third node, and the drain of the second PMOS transistor is electrically connected to the second node. The gate of the second NMOS transistor is electrically connected to the third node, the source of the second NMOS transistor is electrically connected to the second power supply, and the drain of the second NMOS transistor is electrically connected to the second node.

5. The ESD clamping circuit according to claim 1, characterized in that, The ESD trigger circuit includes a first resistor unit and a protection unit. One end of the first resistor unit is electrically connected to the first power supply, and the other end of the first resistor unit is electrically connected to the first node. One end of the protection unit is electrically connected to the first node, and the other end of the protection unit is electrically connected to the second power supply.

6. The ESD clamping circuit according to claim 5, characterized in that, The protection unit includes at least one of a capacitor, a second diode, and a varistor.

7. The ESD clamping circuit according to claim 5, characterized in that, When the protection unit includes a capacitor, the ESD clamping circuit also includes a leakage protection circuit, which is electrically connected between the other end of the capacitor and the second power supply, and the controlled end of the leakage protection circuit is electrically connected to the third node.

8. The ESD clamping circuit according to claim 7, characterized in that, The leakage prevention circuit includes a third NMOS transistor, the drain of which is electrically connected to the other end of a capacitor, the source of which is electrically connected to the second power supply, and the gate of which is electrically connected to the third node as a controlled terminal.

9. The ESD clamping circuit according to claim 1, characterized in that, The voltage clamping circuit includes a clamping NMOS transistor, the gate of which is electrically connected to the third node, the drain of which is electrically connected to the first power supply, and the source of which is electrically connected to the second power supply.

10. The ESD clamping circuit according to any one of claims 1-9, characterized in that, The ESD clamping circuit further includes a second resistor unit, one end of which is electrically connected to the third node, and the other end of which is electrically connected to the second power supply.

11. An ESD protection module, characterized in that, Includes the ESD clamping circuit as described in any one of claims 1-10.

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