A protection circuit for inhibiting surge mis-triggering and a distribution box

Abstract

This invention provides a protection circuit and distribution box for suppressing surge false triggering. The protection circuit includes an input terminal, an output terminal, and a suppression circuit. The input terminal is connected to the live wire, neutral wire, and ground wire; the output terminal is connected to the protected device; and the suppression circuit is located between the two terminals and consists of a hybrid clamping unit, a choke module, and a leading-edge shaping array. The hybrid clamping unit includes two sets of bidirectional TVS arrays, respectively connected to the live wire and neutral wire and sharing a common center node. A bidirectional thyristor shunt unit is connected to the center node and ground wire, with polysilicon thin-film resistors connected in parallel between the array diodes. The choke module includes a magnetically saturated inductor connected in series with the live wire and neutral wire, and a π-type low-pass filter network located on the input side of the magnetically saturated inductor. The leading-edge shaping array is connected in parallel to the input terminal of the hybrid clamping unit and includes a main energy absorption branch and a delayed triggering branch. The magnetically controlled resistor is magnetically correlated with the magnetically saturated inductor, and its resistance value changes according to the surge flux to achieve bidirectional thyristor trigger delay adjustment.

Description

Technical Field

[0001] This application belongs to the field of circuits, and in particular relates to a protection circuit and distribution box for suppressing surge false triggering. Background Technology

[0002] In actual power grid operation, lightning strikes on transmission lines, large load switching within the grid, and various electromagnetic interferences can all induce transient high voltages and large currents, i.e., surges, in the power supply network. These transient surges are characterized by their suddenness, short duration, concentrated energy, and steep rise edges. If they intrude into downstream electrical equipment through distribution boxes, they can easily break down the insulation layer and damage core components, leading to economic losses and data loss. Existing surge protection schemes typically rely on components such as varistors, discharge tubes, or transient voltage suppressor diodes for overvoltage clamping and energy dissipation, forming a low-impedance discharge path when a surge occurs, diverting dangerous energy to the ground wire, thereby protecting subsequent circuits. However, traditional protection modes struggle to balance rapid response and high energy absorption capabilities. When faced with surges with steep rise edges, protection devices may fail to suppress the leading-edge transient high voltage in time due to response lag; when faced with high-energy surges, device overload may cause thermal breakdown, reducing overall protection reliability. Existing protection circuits lack the ability to distribute surge energy, smooth and shape waveforms, and perform multi-level coordinated processing during surge suppression. They also struggle to adjust impedance and control trigger delays based on the instantaneous characteristics of the surge. This static protection mechanism not only easily leads to excessively high residual output voltage but may also allow residual high-frequency interference to affect the normal operation of sensitive equipment. Therefore, there is an urgent need for a surge protection circuit for distribution boxes that can suppress false surge triggering. This circuit should coordinate the relationship between large energy discharge, rapid clamping, and waveform leading-edge shaping in its overall architecture, achieving adaptive and comprehensive surge suppression and improving the protection level of the power distribution system. Summary of the Invention

[0003] To achieve surge adaptation and comprehensive suppression, and improve the protection level of the power distribution system, this invention proposes a protection circuit for suppressing surge false triggering, comprising: The device includes an input terminal, an output terminal, and a suppression circuit. The input terminal is connected to the live wire, neutral wire, and ground wire. The output terminal is connected to the protected device. The suppression circuit is disposed between the input terminal and the output terminal. The suppression circuit includes a hybrid clamping unit, a choke module, and a leading edge shaping array. The hybrid clamping unit includes a first bidirectional transient voltage suppressor diode array and a second bidirectional transient voltage suppressor diode array. One end of the first bidirectional transient voltage suppressor diode array is connected to the live wire, and one end of the second bidirectional transient voltage suppressor diode array is connected to the neutral wire. The other ends of both are connected to the center node. A bidirectional thyristor shunt unit is connected between the center node and the ground wire. Each of the bidirectional transient voltage suppressor diode arrays is provided with a polysilicon thin film resistor. The choke module includes a pair of magnetic saturation inductors connected in series with the live wire and the neutral wire and a π-type low-pass filter network located on the input side of the magnetic saturation inductors. The leading edge shaping array is connected in parallel to the input of the hybrid clamping unit. The leading edge shaping array includes a main energy absorption branch and a delayed triggering branch connected in parallel. The main energy absorption branch includes a series varistor and a bidirectional transient voltage suppressor diode. The delayed triggering branch includes a series magnetoresistive resistor, a capacitor, and a bidirectional avalanche diode, and is connected to the gate of the bidirectional thyristor shunt unit via a gate current limiting resistor. The magnetoresistive resistor is magnetically correlated with the magnetic saturation inductor. The trigger delay time is adjusted by modulating the resistance value of the magnetoresistive resistor using the magnetic flux generated by the surge current in the magnetic saturation inductor.

[0004] Furthermore, the present invention also relates to a distribution box, comprising: Box; And a protection circuit for suppressing surge false triggering as described in any of the above, the protection circuit being installed inside the enclosure.

[0005] The surge protection circuit of this invention improves the overall protection capability of the power distribution system against transient overvoltages through the coordinated operation of a hybrid clamping unit, a choke module, and a leading-edge shaping array. By connecting polysilicon thin-film resistors in parallel between adjacent nodes of the bidirectional transient voltage suppression diode array, the voltage balance characteristics within the array are improved, reducing the risk of local devices experiencing excessive voltage stress. The choke module, formed by a magnetically saturated inductor and a π-type low-pass filter network, filters out high-frequency electromagnetic interference and softens the steep rise of the surge current, mitigating the transient impact on subsequent clamping devices. By setting the physical magnetic correlation between the magnetically controlled resistor and the magnetically saturated inductor, the resistance value of the magnetically controlled resistor is adjusted using the magnetic flux generated by the surge current itself, thereby changing the trigger delay time of the bidirectional thyristor shunt unit. This structure enables the main energy absorption branch and the shunt discharge channel to coordinate in sequence, achieving timely discharge of large energy surges while reducing the probability of false triggering of the bidirectional thyristor shunt unit under normal operating conditions. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a hybrid clamping unit; Figure 2 This is a schematic diagram of a π-type low-pass filter and a saturation choke. Detailed Implementation

[0007] To make the purpose, features, and advantages of this application more apparent and understandable, specific embodiments and accompanying drawings will be used to clearly and completely describe the technical solution protected by this application. Obviously, the embodiments described below are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0008] In this application, a protection circuit for suppressing surge false triggering includes: The device includes an input terminal, an output terminal, and a suppression circuit. The input terminal is connected to the live wire, neutral wire, and ground wire. The output terminal is connected to the protected device. The suppression circuit is located between the input terminal and the output terminal. The suppression circuit includes a hybrid clamping unit, a choke module, and a leading edge shaping array.

[0009] During the hardware implementation and circuit board layout phase, the electrical connections of the input, output, and suppression circuits are established. The live, neutral, and ground wires of the mains power are physically connected to the circuit system via terminal blocks. The output is connected to the main circuit of the switching power supply or the protected device of the servo drive using copper busbars. To reduce the parasitic effects of the suppression circuit during high-frequency, high-current switching between the input and output, a three-dimensional electromagnetic field simulation algorithm based on finite element analysis is used to extract the parasitic inductance and capacitance parameters of the traces. For the connection status detection of the input, output, or ground terminals, a low-voltage isolated sampling signal is first generated through resistor voltage division, optocoupler isolation, isolation sampling amplifier, or voltage transformer. This low-voltage isolated sampling signal is then connected to the microcontroller's general-purpose input / output port or analog-to-digital converter port. The microcontroller's underlying driver configures an initialization program for the general-purpose input / output port to read the isolated voltage connection status, instead of directly connecting the mains high-voltage signal to the microcontroller port. The hybrid clamping unit, choke module, and leading-edge shaping array are ensured to be stably connected at both the physical and electrical levels to jointly intercept surge voltages.

[0010] The hybrid clamping unit includes a first bidirectional transient voltage suppressor diode array and a second bidirectional transient voltage suppressor diode array. One end of the first bidirectional transient voltage suppressor diode array is connected to the live wire, and one end of the second bidirectional transient voltage suppressor diode array is connected to the neutral wire. The other ends of both are connected to the center node. A bidirectional thyristor shunt unit is connected between the center node and the ground wire. Each of the bidirectional transient voltage suppressor diode arrays is provided with a polysilicon thin film resistor. The choke module includes a pair of magnetically saturated inductors connected in series with the live wire and the neutral wire, and a π-type low-pass filter network located on the input side of the magnetically saturated inductors.

[0011] In the specific construction of the hybrid clamping unit, multiple silicon avalanche diodes with ultrafast response speeds are selected and connected in series and parallel to form a first bidirectional transient voltage suppressor (VTPS) diode array and a second bidirectional VTPS diode array. The input terminal of the first bidirectional VTPS diode array is directly soldered to the live wire, and the input terminal of the second bidirectional VTPS diode array is soldered to the neutral wire. The output terminals of both arrays are connected to the center node on the copper-clad laminate. The hybrid clamping unit circuit topology is as follows: Figure 1 As shown.

[0012] A bidirectional thyristor device with high surge current carrying capacity is connected between the central node and the ground wire to form a bidirectional thyristor shunt unit. To reduce the differences in volt-ampere characteristics caused by the manufacturing processes of each diode and to achieve uniform internal voltage recovery after a surge, a polycrystalline silicon thin-film resistor is connected in parallel between adjacent diode nodes. This polycrystalline silicon thin-film resistor can be fabricated on a substrate using a thin-film deposition process or soldered between adjacent nodes using surface-mount thin-film resistors. The initial resistance value of this resistor can be determined by matching the diode's withstand voltage rating, junction capacitance difference, and discharge time requirements. In the implementation of the choke module, a pair of magnetically saturated inductors are wound using an iron-based nanocrystalline alloy core and connected in series in the transmission paths of the live and neutral wires, respectively. Simultaneously, a symmetrical π-type low-pass filter network is constructed at the input front end of the magnetically saturated inductors using a thin-film capacitor and a high-frequency inductor. The choke module circuit topology is as follows: Figure 2 As shown, the parameter determination process for each component in the filter network uses the Chebyshev filter synthesis algorithm, and the frequency domain response curve is simulated and corrected to achieve the blocking of common-mode and differential-mode high-frequency noise signals.

[0013] In some embodiments, the polycrystalline silicon thin-film resistor includes: A resistor with a resistance of 470 kΩ and a rated power dissipation of 1 watt is connected across the leads of two adjacent bidirectional transient voltage suppressor diodes with a spacing of 3 mm to discharge and balance transient charges.

[0014] In the PCB layout of the hybrid clamping unit, the center-to-center spacing between the pins of two adjacent bidirectional transient voltage suppressor diodes is set to 3mm to shorten the high-frequency transient current path and reduce parasitic inductance. The polysilicon thin-film resistor uses a surface mount process; for example, an SMD2512 package is selected to meet the rated power dissipation of 1 watt. The pads at both ends are connected in parallel with the pin pads of the adjacent bidirectional transient voltage suppressor diodes using copper plating. During actual surge impacts, slight manufacturing differences in the internal PN junction capacitance of each diode, such as a junction capacitance fluctuation range between 100pF and 150pF, can lead to uneven transient response speed and residual voltage distribution. At this time, the 470 kΩ polysilicon thin-film resistor serves as a discharge channel for static charge and residual charge during the surge dissipation phase. Within the time after the surge subsides, for example, calculated using the RC time constant, approximately 50 to 100 microseconds, the residual charge accumulated on the diode junction capacitance completes its main decay and continues to be released to a stable state in the subsequent time.

[0015] Furthermore, when multiple diodes are cascaded and subjected to surge overvoltages as high as, for example, 4000 volts, this parallel resistor network reduces the voltage stress deviation between diodes through static voltage equalization and charge balancing mechanisms after surge subsidence. This reduces the risk of local diodes being subjected to excessively high residual voltages for a long time, thereby reducing avalanche cascade failure caused by overvoltage breakdown of a single diode and improving overall voltage equalization reliability.

[0016] In some embodiments, the π-type low-pass filter network includes: A first capacitor, a two-wire inductor, and a second capacitor, both having a capacitance of 0.47 microfarads, and the two-wire inductor having an inductance of 5 microhenries, are connected across the live wire and the neutral wire, respectively. The two-wire inductor is connected in series with both the live wire and the neutral wire.

[0017] The implementation of the π-type low-pass filter network on the circuit board involves a coordinated suppression structure layout for differential-mode and common-mode noise. The first and second capacitors are selected from metallized polypropylene film capacitors with a voltage rating of X2 safety level, such as a nominal voltage rating of 275VAC and a tolerance range controlled within ±10%. Utilizing their low equivalent series resistance (ERT) characteristics, for example, ERT less than 20 milliohms, they are connected in parallel between the live and neutral copper foil networks at the input and output terminals of the choke module, respectively, to bypass high-frequency differential-mode surge energy. The dual-wire parallel-wound inductor uses a high-permeability ferrite core, such as manganese-zinc ferrite with an initial permeability of about 5000. It is wound with polyurethane enameled wire with a diameter of 1.2mm using a dual-wire parallel-wound process, so that the number of turns of the coil for the live wire and the neutral wire are consistent and connected in the direction of common-mode choke. This allows the magnetic flux generated by the common-mode current to be superimposed in the core, while the magnetic flux generated by the normal differential-mode load current tends to cancel each other out. At the same time, the leakage inductance of the winding or the additional differential-mode inductance is used to form a differential-mode equivalent inductance of about 5 microhenries, thereby taking into account both differential-mode high-frequency attenuation and common-mode impedance improvement.

[0018] For high-frequency surge ringing interference in the 100kHz to 30MHz frequency range, the first capacitor and the leakage inductance of the two-wire parallel-wound inductor form a primary low-pass filter, blocking high-frequency harmonics at the transient leading edge. The remaining high-frequency energy is absorbed by the secondary bypass filter of the second capacitor, and the resonance peak can be suppressed by combining the capacitor's equivalent series resistance, core loss, winding copper loss, and optional damping resistor. This π-type structure can generate insertion loss in the target high-frequency band, reducing the surge waveform voltage change rate dv / dt entering the subsequent hybrid clamping unit, and alleviating the transient power burden on the subsequent protection circuit; the specific insertion loss value can be determined based on device loss parameters, wiring parasitic parameters, and frequency domain simulation results.

[0019] The leading edge shaping array is connected in parallel to the input of the hybrid clamping unit. The leading edge shaping array includes a main energy absorption branch and a delayed triggering branch connected in parallel. The main energy absorption branch includes a series varistor and a bidirectional transient voltage suppressor diode. The delayed triggering branch includes a series magnetoresistive resistor, a capacitor, and a bidirectional avalanche diode, and is connected to the gate of the bidirectional thyristor shunt unit via a gate current limiting resistor. The magnetoresistive resistor is magnetically correlated with the magnetic saturation inductor. The trigger delay time is adjusted by modulating the resistance value of the magnetoresistive resistor using the magnetic flux generated by the surge current in the magnetic saturation inductor.

[0020] The circuit traces of the leading edge shaping array are soldered in parallel to the live and neutral input terminals of the hybrid clamping unit. When constructing the main energy absorption branch, a high-energy zinc oxide varistor and a bidirectional transient voltage suppressor diode are connected in series using silver paste soldering to absorb most of the energy at the leading edge of the surge voltage. In the implementation of the delayed trigger branch, an equivalent magnetoresistive resistor composed of a negative magnetoresistive material, a magnetically sensitive semiconductor material, or a magnetically sensitive element and a bypass resistor network is selected as the magnetoresistive resistor. This is then connected in series with a ceramic dielectric capacitor and a bidirectional avalanche diode to obtain a RC delay network. One end of the delayed trigger branch is connected to the surge sampling terminal of the leading edge shaping array. The surge sampling terminal can be taken from the live input terminal, the neutral input terminal, or the voltage divider sampling node between the live and neutral lines. The other end of the delayed trigger branch is connected to the gate of the bidirectional thyristor shunt unit via a trigger node and a gate current-limiting resistor, forming a gate trigger circuit with the ground reference terminal of the bidirectional thyristor shunt unit. In this configuration, the first terminal of the bidirectional avalanche diode is connected to the trigger node after the capacitor, and the second terminal of the bidirectional avalanche diode is connected to the control gate of the bidirectional thyristor shunt unit via a gate current-limiting resistor and a copper-clad wire. The reference terminal of the bidirectional thyristor shunt unit is connected to ground or a ground reference terminal, allowing the capacitor release current to form a complete gate trigger current loop through the bidirectional avalanche diode, the gate current-limiting resistor, and the control gate. Therefore, both the main energy absorption branch and the delayed trigger branch are connected to the input side of the hybrid clamping unit, but they respectively undertake the functions of energy absorption between the live and neutral lines and gate trigger sampling.

[0021] During the physical assembly stage, the magnetron resistor is tightly bonded and fixed to the air gap of the magnetic circuit of the magnetically saturated inductor using insulating and thermally conductive adhesive, resulting in a stable magnetic correlation structure. When an external lightning strike or surge current flows through the magnetically saturated inductor, the transient magnetic flux generated is estimated. This leakage magnetic field acts on the magnetron resistor, causing it to produce a magnetoresistive effect, thereby changing its resistance value. During the prototype calibration or factory testing stage, the rate of change of the input surge current can be collected using an isolation current transformer, Rogowski coil, or Hall current sensor, and the sampled data can be observed to verify the matching relationship between the time constant of the RC network and the surge current amplitude. In actual operation, the time constant of the delayed trigger branch is jointly determined by the resistance and capacitance value of the magnetron resistor after magnetic flux modulation. The microcontroller does not directly intervene in the triggering process of the passive RC network, thereby enabling the gate trigger delay time to adaptively shorten according to the increase of the surge current amplitude, and enabling the thyristor shunt unit to establish a residual surge energy discharge channel after meeting the triggering conditions, achieving rapid and safe discharge of residual high-voltage surge energy.

[0022] In some embodiments, the main energy absorption branch includes: A varistor and a bidirectional transient voltage suppressor diode are connected in series. The varistor has a varistor voltage of 500 volts, and the bidirectional transient voltage suppressor diode has a breakdown voltage of 450 volts. One end of the varistor is connected to the live wire, and the other end is connected to one end of the bidirectional transient voltage suppressor diode. The other end of the bidirectional transient voltage suppressor diode is connected to the neutral wire.

[0023] The hardware assembly and parameter matching of the main energy absorption branch follow the principle of voltage gradient matching. During assembly, the input pin of a metal oxide varistor with a nominal voltage of 500 volts, a tolerance of ±10%, and a leakage current of less than 20 microamps is connected to the live wire at the input of the distribution box through a wide, flat copper foil, for example, at least 5 mm wide and 2 ounces thick, to withstand kiloamp-level pulse currents. The output pin is connected in series to one end of a bidirectional transient voltage suppressor diode with a breakdown voltage of 450 volts and a pulse current carrying capacity matched to the target surge level. The other end of this diode is extensively copper-plated and connected to the neutral wire.

[0024] When a differential-mode surge occurs, such as an 8 / 20 microsecond waveform entering the input terminal of the distribution box, the working mechanism of this series combination exhibits a composite nonlinear clamping response. The surge current flowing through this branch is limited to the rated pulse current carrying capacity of the components by the pre-stage choke, parallel absorption path, and component selection. When the transient overvoltage at both ends of the branch rapidly rises to the composite action range, the bidirectional transient voltage suppression diode and the varistor form a voltage divider coordination based on their respective leakage current characteristics, junction capacitance characteristics, and dynamic impedance, and jointly enter a nonlinear conduction state.

[0025] A bidirectional transient voltage suppressor diode is used to limit transient voltage spikes, while a varistor is used to absorb the main pulse energy. Both are selected based on the pulse current of the same branch, thereby controlling the residual voltage between the live and neutral wires within a preset range. This surge pulse is mainly shared by the main energy absorption branch and the input-side filter choke structure. The bidirectional thyristor shunt unit is used to discharge the residual common-mode energy at the center node after the triggering conditions are met, rather than solely carrying the entire kiloampere-level differential-mode surge current.

[0026] In some embodiments, the delayed triggering branch includes: A copper-clad wiring is connected to the gate of the bidirectional thyristor shunt unit, and a gate current-limiting resistor is connected in series between the copper-clad wiring and the gate. The trigger current threshold of the bidirectional thyristor shunt unit is 8mA, the continuous on-state current capability is 15A, and it has a non-repetitive surge current capability that matches the residual common-mode discharge current under surge pulse conditions, which is used to conduct the discharge circuit from the center node to the ground after triggering.

[0027] The physical connection and control drive design between the delayed trigger branch and the thyristor shunt unit adopts a low-impedance routing strategy. This copper-clad trace is designed as a dedicated trigger signal trace on the printed circuit board, with a trace width set between 1.5mm and 2mm. In order to reduce parasitic inductance and reduce spatial correlation interference of high-frequency surge signals, the trace length is controlled within 15mm, and it is kept as far away as possible from the strong electromagnetic interference area of ​​the main power circuit.

[0028] The core component of the thyristor shunt unit is a sensitive bidirectional thyristor with a gate trigger current threshold set at 8mA to ensure stable conduction upon detecting a trigger signal regulated by the delayed trigger branch. Once the gate receives a trigger current exceeding 8mA, the thyristor shunt unit enters a low-impedance conduction state, utilizing its 15 amp steady-state load current capability and withstanding a surge peak current of no less than 100 amps under non-repetitive surge pulse conditions, thus establishing a low-impedance residual surge discharge loop between the center node and ground.

[0029] This action discharges the residual common-mode surge energy originally applied to the subsequent hybrid clamping unit into the ground, thereby reducing the common-mode potential of the central node, ensuring the insulation safety of the protected equipment, and preventing leakage or arcing. For lightning surges with peak currents reaching the kiloampere level, the main energy absorption branch, the input-side filter choke structure, and the external grounding channel should share the load. The thyristor shunt unit should be selected according to the residual common-mode discharge current, and if necessary, a thyristor device with a higher non-repetitive surge current carrying capacity or a parallel shunt structure can be selected.

[0030] In some embodiments, the delayed triggering branch includes: A magnetron resistor, a capacitor, a bidirectional avalanche diode, and a gate current-limiting resistor are connected in series. The magnetron resistor has a rated power of 0.5 watts, the capacitor has a capacitance of 3 nanofarads, and the bidirectional avalanche diode has a breakdown voltage of 10 volts. The bidirectional avalanche diode is connected to the gate of the bidirectional thyristor shunt unit via the gate current-limiting resistor. The reference terminal of the bidirectional thyristor shunt unit is connected to ground.

[0031] The signal conditioning link of the delayed trigger branch is implemented in hardware using a cascaded structure of an RC network and a threshold switching element. In circuit board assembly, a 0.5W magnetoresistive resistor (equivalent to a magnetoresistive resistor composed of a negative magnetoresistive material, a magnetically sensitive semiconductor material, or a magnetically sensitive element and a bypass resistor network), a 3NF nominal capacitance capacitor (using a high-frequency ceramic capacitor to ensure capacitance stability over a wide temperature range with an error controlled within ±5%), and a 10V breakdown voltage bidirectional avalanche diode are sequentially connected in series. One end of the bidirectional avalanche diode is connected to the trigger node after the capacitor, and the other end is connected to the gate of the bidirectional thyristor shunt unit via a gate current-limiting resistor and copper wiring. The reference terminal of the bidirectional thyristor shunt unit is connected to ground or a ground reference terminal, thus forming an integral trigger circuit consisting of the input surge signal, magnetoresistive resistor, capacitor, bidirectional avalanche diode, gate current-limiting resistor, bidirectional thyristor gate, and ground reference terminal.

[0032] In actual operation, this branch constitutes an integral delay circuit with adaptive adjustment characteristics. When a surge voltage pulse enters, the signal shunt into this branch begins to charge the 3 nanofarad capacitor, and the charging rate is determined by the real-time resistance value of the magnetron. As the voltage across the capacitor rises exponentially, once the potential difference reaches the 10-volt avalanche breakdown threshold, the bidirectional avalanche diode conducts, and the capacitor discharge current is injected into the gate of the bidirectional thyristor shunt unit through the bidirectional avalanche diode, the gate current-limiting resistor, and the copper-clad wiring.

[0033] This high-frequency integration mechanism, based on a 10-volt reference and a 3-nanofa capacity, results in a trigger pulse with a steep edge, such as a rise time of less than 50 nanoseconds, preventing thermal damage from the slow conduction of subsequent switching elements.

[0034] In some embodiments, the magnetically controlled resistor is magnetically associated with the magnetically saturated inductor, and the trigger delay time is adjusted by modulating the magnetic flux generated by the surge current in the magnetically saturated inductor to modulate the resistance value of the magnetically controlled resistor. This includes: An insulating sleeve with a spacing of 1mm is provided between the magnetically controlled resistor and the magnetically saturated inductor. When the surge current flowing through the magnetically saturated inductor reaches a preset surge trigger threshold, the generated magnetic flux reduces the resistance of the magnetically controlled resistor from the normal 500 ohms to below 125 ohms, thereby adjusting the trigger delay time of the delayed trigger branch to a delay range that matches the requirements for residual surge energy discharge.

[0035] The magnetic correlation structure between the magnetoresistive resistor and the magnetically saturated inductor depends on the physical spatial layout and insulation process. During assembly, the magnetoresistive resistor is attached to the outside of the leakage magnetic flux concentration area of ​​the toroidal core of the magnetically saturated inductor. The two are mechanically fixed and electrically isolated by an injection-molded insulating sleeve, such as flame-retardant silicone rubber. The thickness of this insulating sleeve is controlled at 1 mm, which can withstand an isolation withstand voltage of at least 2000 volts to prevent primary-side surge high voltage breakdown to the control circuit, while also ensuring that the magnetoresistive resistor is within the effective magnetic field linear correlation range of the magnetically saturated inductor.

[0036] When the system encounters a leading-edge surge, and the surge current flowing through the main circuit of the magnetically saturated inductor rises above the 100-ampere threshold, the magnetic core approaches saturation and simultaneously generates an alternating leakage flux. The magnetic field penetrating the 1mm insulating sleeve acts on the charge carriers inside the magnetically controlled resistor, inducing a magnetoresistance modulation effect. This causes the resistance of the equivalent magnetically controlled resistor to decrease from the normal 500 ohms to below 125 ohms under the influence of the transient magnetic flux.

[0037] The decrease in resistance reduces the integral time constant of the delayed trigger branch, compressing the trigger delay time of this branch to no more than 0.8 microseconds, thereby enabling the thyristor to conduct earlier and accelerate the discharge of residual energy when a large surge occurs.

[0038] In this application, a distribution box includes: Box; And a protection circuit for suppressing surge false triggering as described in any of the above, the protection circuit being installed inside the enclosure.

[0039] In some embodiments, the enclosure is provided with mounting rails and a grounding busbar; The protection circuit is integrated into one or more surge protection modules, which are snapped onto the mounting rail, and the ground wire in the protection circuit is connected to the grounding busbar via a physical wire.

[0040] In some embodiments, the surge protection module includes an insulating housing, and the components of the protection circuit are soldered onto a circuit board and installed inside the insulating housing; The insulating shell is filled with thermally conductive and flame-retardant potting compound. The magnetically controlled resistor, the magnetically saturated inductor, and the insulating sleeve between them in the suppression circuit are all covered by the thermally conductive and flame-retardant potting compound and fixed inside the insulating shell.

[0041] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A protection circuit for suppressing surge false triggering, characterized in that, include: The device includes an input terminal, an output terminal, and a suppression circuit. The input terminal is connected to the live wire, neutral wire, and ground wire. The output terminal is connected to the protected device. The suppression circuit is disposed between the input terminal and the output terminal. The suppression circuit includes a hybrid clamping unit, a choke module, and a leading edge shaping array. The hybrid clamping unit includes a first bidirectional transient voltage suppressor diode array and a second bidirectional transient voltage suppressor diode array. One end of the first bidirectional transient voltage suppressor diode array is connected to the live wire, and one end of the second bidirectional transient voltage suppressor diode array is connected to the neutral wire. The other ends of both are connected to the center node. A bidirectional thyristor shunt unit is connected between the center node and the ground wire. Each of the bidirectional transient voltage suppressor diode arrays is provided with a polysilicon thin film resistor. The choke module includes a pair of magnetic saturation inductors connected in series with the live wire and the neutral wire and a π-type low-pass filter network located on the input side of the magnetic saturation inductors. The leading edge shaping array is connected in parallel to the input of the hybrid clamping unit. The leading edge shaping array includes a main energy absorption branch and a delayed triggering branch connected in parallel. The main energy absorption branch includes a series varistor and a bidirectional transient voltage suppressor diode. The delayed triggering branch includes a series magnetoresistive resistor, a capacitor, and a bidirectional avalanche diode, and is connected to the gate of the bidirectional thyristor shunt unit via a gate current limiting resistor. The magnetoresistive resistor is magnetically correlated with the magnetic saturation inductor. The trigger delay time is adjusted by modulating the resistance value of the magnetoresistive resistor using the magnetic flux generated by the surge current in the magnetic saturation inductor.

2. The protection circuit for suppressing surge false triggering according to claim 1, characterized in that, The polycrystalline silicon thin-film resistor includes: A resistor with a resistance of 470 kΩ and a rated power dissipation of 1 watt is connected across the leads of two adjacent bidirectional transient voltage suppressor diodes with a spacing of 3 mm to discharge and balance transient charges.

3. The protection circuit for suppressing surge false triggering according to claim 2, characterized in that, The π-type low-pass filter network includes: A first capacitor, a two-wire inductor, and a second capacitor, both having a capacitance of 0.47 microfarads, and the two-wire inductor having an inductance of 5 microhenries, are connected across the live wire and the neutral wire, respectively. The two-wire inductor is connected in series with both the live wire and the neutral wire.

4. The protection circuit for suppressing surge false triggering according to claim 1, characterized in that, The main energy absorption branch includes: A varistor and a bidirectional transient voltage suppressor diode are connected in series. The varistor has a varistor voltage of 500 volts, and the bidirectional transient voltage suppressor diode has a breakdown voltage of 450 volts. One end of the varistor is connected to the live wire, and the other end is connected to one end of the bidirectional transient voltage suppressor diode. The other end of the bidirectional transient voltage suppressor diode is connected to the neutral wire.

5. The protection circuit for suppressing surge false triggering according to claim 1 or 4, characterized in that, The delayed trigger branch includes: A copper-clad wiring is connected to the gate of the bidirectional thyristor shunt unit, and a gate current-limiting resistor is connected in series between the copper-clad wiring and the gate. The trigger current threshold of the bidirectional thyristor shunt unit is 8mA, the continuous on-state current capability is 15A, and it has a non-repetitive surge current capability that matches the residual common-mode discharge current under surge pulse conditions, which is used to conduct the discharge circuit from the center node to the ground after triggering.

6. The protection circuit for suppressing surge false triggering according to claim 1, characterized in that, The delayed trigger branch includes: A magnetron resistor, a capacitor, a bidirectional avalanche diode, and a gate current-limiting resistor are connected in series. The magnetron resistor has a rated power of 0.5 watts, the capacitor has a capacitance of 3 nanofarads, and the bidirectional avalanche diode has a breakdown voltage of 10 volts. The bidirectional avalanche diode is connected to the gate of the bidirectional thyristor shunt unit via the gate current-limiting resistor. The reference terminal of the bidirectional thyristor shunt unit is connected to ground.

7. The protection circuit for suppressing surge false triggering according to claim 1, characterized in that, The magnetically controlled resistor is magnetically correlated with the magnetically saturated inductor. The trigger delay time is adjusted by modulating the magnetic flux generated by the surge current in the magnetically saturated inductor to control the resistance value of the magnetically controlled resistor, including: An insulating sleeve with a spacing of 1mm is provided between the magnetically controlled resistor and the magnetically saturated inductor. When the surge current flowing through the magnetically saturated inductor reaches a preset surge trigger threshold, the generated magnetic flux reduces the resistance of the magnetically controlled resistor from the normal 500 ohms to below 125 ohms, thereby adjusting the trigger delay time of the delayed trigger branch to a delay range that matches the requirements for residual surge energy discharge.

8. A distribution box, characterized in that, include: Box; And a protection circuit for suppressing surge false triggering as described in any one of claims 1 to 7, the protection circuit being installed inside the enclosure.

9. The distribution box according to claim 8, characterized in that, The enclosure is equipped with mounting rails and a grounding busbar. The protection circuit is integrated into one or more surge protection modules, which are snapped onto the mounting rail, and the ground wire in the protection circuit is connected to the grounding busbar via a physical wire.

10. The distribution box according to claim 9, characterized in that, The surge protection module includes an insulating housing, and the components of the protection circuit are soldered onto a circuit board and installed inside the insulating housing; The insulating shell is filled with thermally conductive and flame-retardant potting compound. The magnetically controlled resistor, the magnetically saturated inductor, and the insulating sleeve between them in the suppression circuit are all covered by the thermally conductive and flame-retardant potting compound and fixed inside the insulating shell.

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