A virtual synchronous machine stability evaluation and hierarchical current limiting method

Abstract

The present disclosure relates to a virtual synchronous machine stability evaluation and hierarchical current limiting method. The method includes: dividing the grid operating state by real-time monitoring of the common coupling point voltage and the output current, triggering the hierarchical current limiting mechanism when a fault or overcurrent is detected; calculating the active current allowable upper limit based on the circular current limiting constraint and adaptively adjusting the power reference value to suppress the acceleration area during the fault and maintain the reactive support; dynamically injecting a transient virtual impedance according to the current overrun degree, calculating the dynamic resistance and inductance pressure drop through proportional gain and configurable X / R ratio to reshape the output characteristics; when the current exceeds the hard current limiting threshold, the dq axis current components are normalized, and the current vector amplitude is limited within the safety boundary. The present application adopts a dual-state machine framework to coordinate the three levels of power limitation, transient virtual impedance soft current limiting and inner loop hard current limiting, effectively improving the transient stability and fault ride-through capability of the virtual synchronous machine in off-grid and grid-connected modes.

Description

Technical Field

[0001] This disclosure relates to the field of virtual synchronizer stability assessment, and more specifically, to a method and apparatus for virtual synchronizer stability assessment and hierarchical current limiting. Background Technology

[0002] With the large-scale integration of renewable energy sources such as photovoltaics and wind power into the power system, the stability and reliability of the power grid are facing unprecedented challenges. The intermittency and volatility of renewable energy make the frequency and voltage stability of the power grid more difficult to predict. To address this challenge, VSG-based PCS has become one of the key devices supporting power grids with a high proportion of renewable energy. VSG can provide necessary grid support services such as frequency regulation and voltage stabilization, and is an effective solution for achieving a 100% power electronic power system.

[0003] While VSGs provide essential support for microgrid and grid stability, their overcurrent characteristics differ significantly from those of traditional SGs. Traditional synchronous generators can provide short-circuit currents several times their rated value for a short period during faults. However, when disturbances such as short-circuit faults, phase angle jumps, frequency jumps, overloads, motor starting, or black starts occur in the microgrid or grid, VSGs may be forced into an overcurrent state. Furthermore, constrained by software design and inherent limitations of power semiconductor devices, their overcurrent capacity is typically only slightly above the rated value. Therefore, designing effective current-limiting strategies to ensure stable operation of VSGs during faults or overloads and to prevent equipment shutdown due to overcurrent has become a core research issue.

[0004] The design of current limiting strategies not only protects the hardware but also determines the dynamic performance of the system under non-rated grid disturbances. Current limiter design needs to consider the following aspects: device-level stability, system transient stability, and power system protection and fault recovery. Currently, research on current limiting control strategies for grid-connected (GFM) inverters can be broadly categorized into four types: direct software current limiting, direct hardware current limiting, indirect current limiting, and composite current limiting.

[0005] Software and hardware direct current limiting are the two most direct methods for implementing overcurrent protection. Software direct current limiting strategies directly limit fault current through software methods such as current loop saturation. By limiting the current reference value in the inner loop, overcurrent caused by the fault can be constrained. This strategy is also commonly found in DC / DC power supplies and V / F controlled inverters. Hardware direct current limiting typically employs a cycle-by-cycle (CBC) current limiting strategy. Its operation involves detecting overcurrent in each control interrupt cycle and applying a clamping signal to the PWM once an overcurrent is detected. However, it can be seen that direct current limiting strategies struggle to maintain the VSG network characteristics during faults. Although a complete theoretical evaluation of this phenomenon is currently lacking, during the fault recovery phase, if there is no anti-integral saturation PI (AWPI) controller in the inner current loop, fault recovery is likely to cause saturation of the outer voltage loop, thereby triggering VSG instability.

[0006] Indirect current limiting employs an alternative approach: real-time adjustment of the PCS port voltage to match the fault voltage at the point of common coupling (PCC), thereby reducing the fault current. This method maintains the original VSG modulation wave unchanged but superimposes the difference between the PCC voltage and the reference voltage, forming a voltage feedforward strategy. This control strategy has the advantage of fast response speed. If the grid voltage Vg drops to 0 V, the modulation wave must be reduced to maintain current limiting. When Vg-Vn is negative, this strategy reduces the modulation wave amplitude and takes effect. Under steady-state conditions, Vg and Vn are approximately equal. In practice, current limiting using VI or TVI has a similar idea, except that in these strategies, Δe is calculated by multiplying the overcurrent and impedance.

[0007] A composite current limiting strategy has been proposed, combining software current limiting, hardware current limiting, and indirect current limiting. The synergy of different types of current limiters leverages their respective advantages to improve current limiting capability and enhance control over the current-limited current. Existing technologies include combining direct software current limiting with indirect current limiting to achieve better current limiting performance and stability. Furthermore, by integrating both grid-based and network-connected modes into the PCS, current limiting is relatively easier to implement in grid-based mode, and there are no network stability issues. Existing technologies include achieving current limiting through seamless mode switching during faults. Existing technologies also include rapidly switching to a voltage hysteresis comparator during faults, maintaining voltage source characteristics while achieving current limiting.

[0008] Although the above methods have proposed corresponding current limiting strategies, there are still two main problems: (1) VSG stability analysis under large disturbances is still challenging and lacks a quantitative evaluation framework; (2) Some existing verification experiments are not comprehensive enough and fail to cover the performance under different scenarios and operating conditions.

[0009] Therefore, one or more methods are needed to solve the above problems.

[0010] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0011] The purpose of this disclosure is to provide a method and apparatus for evaluating the stability of a virtual synchronizer and for hierarchical current limiting, thereby overcoming, to at least some extent, one or more problems caused by the limitations and defects of related technologies.

[0012] According to one aspect of this disclosure, a method for evaluating the stability of a virtual synchronizer and for hierarchical current limiting is provided, comprising: Real-time monitoring of common coupling point voltage and output current; classification of grid operation status based on voltage amplitude; and triggering of graded current limiting mechanism when fault or overcurrent is detected. Based on circular current limiting constraints, the upper limit of active current is calculated according to the real-time reactive current component, and the active power reference value and reactive power reference value are adaptively adjusted to suppress the acceleration area during the fault and maintain reactive power support. Based on the degree of current overshoot, a transient virtual impedance is dynamically injected, and the dynamic resistance and inductor voltage drop are calculated through proportional gain and configurable X / R ratio to reshape the output characteristics to soften current surges. When the current exceeds the hard current limiting threshold, the dq axis current component is normalized to directly limit the current vector amplitude within the safe boundary, thereby achieving progressive current suppression and fault ride-through.

[0013] In one exemplary embodiment of this disclosure, the method further includes: A transient stability assessment model is established based on the equal area criterion, according to... Calculate the critical clearing angle δ RM and based on , The acceleration area A a With deceleration area A d Determine the maximum work angle δ based on the iso-area stability condition. m To assess the transient stability margin of the system; in, δ RM The critical rotor angle, δ m For the maximum angle of attack, δ 0 represents the initial power angle, t represents the fault duration, and a = ωn / H represents the angular acceleration. P ref For active power reference, i CLmax The current limiting threshold for the CL phase. EV represents the internal electromotive force of the VSG, k represents the voltage drop depth across the grid (k=1 for normal conditions, k=0 for zero-voltage crossing), and V represents the voltage drop depth across the grid. g This is the effective value of the grid voltage. δ For rotor angle, The angle formed by the active and reactive currents during the fault period. E X represents the internal electromotive force of the VSG, and X represents the internal electromotive force E of the virtual synchronous machine and the line inductance parameter at the grid connection point.

[0014] In one exemplary embodiment of this disclosure, the method further includes: The power output under the current limiting strategy is based on

[0015] Approximate representation, where the phase angle of the current reference vector is given by It is determined that the acceleration area and the deceleration area are:

[0016]

[0017] Where P is the active power transmitted under current limiting and amplitude limiting, and X... g The electromotive force E within the virtual synchronous machine and the line inductance parameters at the grid connection point are given. i s Let P be the current amplitude in the dq coordinate system. max To theoretically transmit the active power limit, This serves as a reference for reactive current during a fault. This serves as a reference for active current during a fault. A a To accelerate the area, A d This represents the deceleration area.

[0018] In one exemplary embodiment of this disclosure, the method further includes: The maximum power angle δ m By solving

[0019] The transcendental equations are obtained, where parameters A and B are derived from... The normalized equation is defined as follows: As shown; Among them, I max The maximum allowable current limit set for the software.

[0020] In one exemplary embodiment of this disclosure, the method further includes: The quasi-steady-state fault current of the transient virtual impedance strategy is The time constant τ of the transient process of the fault current is determined by the ratio of the equivalent inductance to the equivalent resistance. in, To determine the quasi-steady-state fault current under virtual impedance current limiting, This represents the voltage difference before and after the fault. These are the electromotive force E within the virtual synchronous machine and the line resistance parameters at the grid connection point. The electromotive force E within the virtual synchronous machine and the line inductance parameters at the grid connection point are given. It represents the virtual part.

[0021] In one exemplary embodiment of this disclosure, the method further includes: The power output under different current conditions under the transient virtual impedance strategy is as follows: , The corresponding acceleration and deceleration areas are as follows:

[0022]

[0023] And according to The semi-analytical expression is used to solve for the maximum work angle δ. m ; in, For grid impedance, This is the impedance value switched when using transient virtual impedance.

[0024] In one exemplary embodiment of this disclosure, the method further includes: The upper limit of the active current is based on The calculation shows that this formula reflects the geometric relationship of the dq current distribution under amplitude constraints, ensuring that the current vector always lies within the specified safety boundary. Among them, i dmax i represents the upper limit of the d-axis current of the current-limiting circle. Pmax For current amplitude limits, i oq This represents the real-time q-axis current.

[0025] In one exemplary embodiment of this disclosure, the method further includes: The normalization process is based on The process scales the dq-axis current components proportionally to keep the magnitude of the synthesized current vector below the hardware protection threshold.

[0026] In one exemplary embodiment of this disclosure, the method further includes: The graded current limiting mechanism adopts a dual-state machine framework to coordinate three levels: power limiting, transient virtual impedance soft current limiting, and inner-loop hard current limiting. Based on the degree of current exceeding the limit, the overcurrent points OC1, OC2, and OC3 are activated in sequence to achieve priority injection of reactive current and adaptive recovery of active current.

[0027] In one aspect of this disclosure, a virtual synchronizer stability assessment and hierarchical current limiting device is provided, comprising: The fault detection and status classification module is used to monitor the voltage and output current of the common coupling point in real time, classify the grid operation status according to the voltage amplitude, and trigger a graded current limiting mechanism when a fault or overcurrent is detected. The adaptive power reference adjustment module is used to calculate the upper limit of active current based on the real-time reactive current component according to the circular current limiting constraint, and adaptively adjust the active power reference value and reactive power reference value to suppress the acceleration area during the fault and maintain reactive power support. The transient virtual impedance injection module is used to dynamically inject transient virtual impedance according to the degree of current overrun. It calculates dynamic resistance and inductor voltage drop through proportional gain and configurable X / R ratio to reshape output characteristics to soften current surges. The direct current limiting protection module is used to normalize the dq axis current components when the current exceeds the hard current limiting threshold, directly limiting the current vector amplitude within the safe boundary, thereby achieving progressive current suppression and fault ride-through.

[0028] An exemplary embodiment of this disclosure discloses a method for stability assessment and hierarchical current limiting of a virtual synchronous machine. The method includes: classifying the grid operating state by real-time monitoring of the common coupling point voltage and output current; triggering a hierarchical current limiting mechanism when a fault or overcurrent is detected; calculating the upper limit of the active current based on circular current limiting constraints and adaptively adjusting the power reference value to suppress the acceleration area during faults and maintain reactive power support; dynamically injecting transient virtual impedance according to the degree of current exceeding limits, and calculating dynamic resistance and inductor voltage drop through proportional gain and a configurable X / R ratio to reshape the output characteristics; and normalizing the dq-axis current component when the current exceeds the hard current limiting threshold to limit the current vector amplitude within a safe boundary. This invention employs a dual-state machine framework to coordinate three levels: power limiting, transient virtual impedance soft current limiting, and inner-loop hard current limiting, effectively improving the transient stability and fault ride-through capability of the virtual synchronous machine in both off-grid and grid-connected modes.

[0029] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0030] The above and other features and advantages of this disclosure will become more apparent from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0031] Figure 1 A flowchart of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure is shown; Figure 2 A structural analogy diagram of SG and VSG for a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure is shown. Figure 3 The diagram illustrates the EAC principle under an unstable scenario of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure. Figure 4 A schematic diagram showing the relationship between inertia H, fault clearing time t, and critical clearing angle δRM of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure is shown. Figure 5 A schematic diagram of VSG operation mode switching under CL control is shown in an exemplary embodiment of the present disclosure of a virtual synchronizer stability assessment and hierarchical current limiting method. Figure 6 The diagram shows the power angle trajectory under CL control of a virtual synchronous machine stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure; Figure 7 The diagram shows the contour lines and sensitivity-dominant region on the (r,b) plane of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure; Figure 8 This diagram illustrates the VSG operation mode switching under TVI control of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure. Figure 9 The diagram illustrates Aa and Ad under different TVI parameters of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure; Figure 10 A schematic diagram illustrating the effect of transient virtual impedance increment on the maximum power angle and sensitivity dominance region of a virtual synchronous machine stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure is shown. Figure 11 This diagram illustrates a multi-level current limiting threshold in the dq coordinate system of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure. Figure 12 A current limiting strategy diagram of a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure is shown; Figure 13A schematic diagram illustrating the fault ride-through voltage region classification of a virtual synchronous machine stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure is shown. Figure 14 The active power limiting logic diagram at overcurrent point 1 (OC1) of a virtual synchronous machine stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure is shown. Figure 15 A recalculated power reference during the FRT (Functional Time Reference) is shown in an exemplary embodiment of the present disclosure for a virtual synchronizer stability assessment and hierarchical current limiting method. Figure 16 This illustration shows a dynamic diagram of the power angle under a multi-stage current limiting strategy for a virtual synchronizer stability assessment and hierarchical current limiting method according to an exemplary embodiment of the present disclosure. Figure 17 A schematic block diagram of a virtual synchronizer stability assessment and hierarchical current limiting device according to an exemplary embodiment of the present disclosure is shown.

[0032] Symbol explanation: Detailed Implementation

[0033] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0034] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of the specific details described, or other methods, components, materials, apparatuses, steps, etc., can be employed. In other instances, well-known structures, methods, apparatuses, implementations, materials, or operations are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0035] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, or in one or more software-hardened modules, or in different network and / or processor devices and / or microcontroller devices.

[0036] In this example embodiment, a method for evaluating the stability of a virtual synchronizer and for hierarchical current limiting is first provided; refer to Figure 1 As shown, the virtual synchronizer stability assessment and hierarchical current limiting method may include the following steps: Step S110: Monitor the voltage and output current at the common coupling point in real time, classify the grid operation status according to the voltage amplitude, and trigger the graded current limiting mechanism when a fault or overcurrent is detected; Step S120: Based on the circular current limiting constraint, calculate the upper limit of the active current according to the real-time reactive current component, and adaptively adjust the active power reference value and reactive power reference value to suppress the acceleration area during the fault and maintain reactive power support. Step S130: Dynamically inject transient virtual impedance according to the degree of current overrun, calculate dynamic resistance and inductor voltage drop through proportional gain and configurable X / R ratio, and reshape output characteristics to soften current surges. Step S140: When the current exceeds the hard current limiting threshold, the dq axis current component is normalized to directly limit the current vector amplitude within the safe boundary, thereby achieving progressive current suppression and fault ride-through.

[0037] An exemplary embodiment of this disclosure discloses a method for stability assessment and hierarchical current limiting of a virtual synchronous machine. The method includes: classifying the grid operating state by real-time monitoring of the common coupling point voltage and output current; triggering a hierarchical current limiting mechanism when a fault or overcurrent is detected; calculating the upper limit of the active current based on circular current limiting constraints and adaptively adjusting the power reference value to suppress the acceleration area during faults and maintain reactive power support; dynamically injecting transient virtual impedance according to the degree of current exceeding limits, and calculating dynamic resistance and inductor voltage drop through proportional gain and a configurable X / R ratio to reshape the output characteristics; and normalizing the dq-axis current component when the current exceeds the hard current limiting threshold to limit the current vector amplitude within a safe boundary. This invention employs a dual-state machine framework to coordinate three levels: power limiting, transient virtual impedance soft current limiting, and inner-loop hard current limiting, effectively improving the transient stability and fault ride-through capability of the virtual synchronous machine in both off-grid and grid-connected modes.

[0038] The following will further explain a method for evaluating the stability of a virtual synchronizer and for hierarchical current limiting in this example embodiment.

[0039] Example 1: In step S110, the voltage and output current of the common coupling point can be monitored in real time, the grid operation status can be divided according to the voltage amplitude, and a graded current limiting mechanism can be triggered when a fault or overcurrent is detected.

[0040] In this example embodiment, the method further includes: A transient stability assessment model is established based on the equal area criterion, according to... Calculate the critical clearing angle δ RM and based on , The acceleration area A a With deceleration area A d Determine the maximum work angle δ based on the iso-area stability condition. m To assess the transient stability margin of the system; in, δ RM The critical rotor angle, δ m For the maximum angle of attack, δ 0 represents the initial power angle, t represents the fault duration, and a = ωn / H represents the angular acceleration. P ref For active power reference, i CLmax The current limiting threshold for the CL phase. E V represents the internal electromotive force of the VSG, k represents the voltage drop depth across the grid (k=1 for normal conditions, k=0 for zero-voltage crossing), and V represents the voltage drop depth across the grid. g This is the effective value of the grid voltage. δ For rotor angle, The angle formed by the active and reactive currents during the fault period. E X represents the internal electromotive force of the VSG, and X represents the internal electromotive force E of the virtual synchronous machine and the line inductance parameter at the grid connection point.

[0041] In this example embodiment, the method further includes: The power output under the current limiting strategy is based on

[0042] Approximate representation, where the phase angle of the current reference vector is given by It is determined that the acceleration area and the deceleration area are:

[0043]

[0044] Where P is the active power transmitted under current limiting and amplitude limiting, and X... g The electromotive force E within the virtual synchronous machine and the line inductance parameters at the grid connection point are given. i s Let P be the current amplitude in the dq coordinate system. max To theoretically transmit the active power limit, This serves as a reference for reactive current during a fault. This serves as a reference for active current during a fault. A a To accelerate the area, Ad This represents the deceleration area.

[0045] In step S120, based on the circular current limiting constraint, the upper limit of the active current can be calculated according to the real-time reactive current component, and the active power reference value and reactive power reference value can be adaptively adjusted to suppress the acceleration area during the fault and maintain reactive power support.

[0046] In this example embodiment, the method further includes: The maximum power angle δ m By solving

[0047] The transcendental equations are obtained, where parameters A and B are derived from... The normalized equation is defined as follows: As shown; Among them, I max The maximum allowable current limit set for the software.

[0048] In this example embodiment, the method further includes: The quasi-steady-state fault current of the transient virtual impedance strategy is The time constant τ of the transient process of the fault current is determined by the ratio of the equivalent inductance to the equivalent resistance. in, To determine the quasi-steady-state fault current under virtual impedance current limiting, This represents the voltage difference before and after the fault. These are the electromotive force E within the virtual synchronous machine and the line resistance parameters at the grid connection point. The electromotive force E within the virtual synchronous machine and the line inductance parameters at the grid connection point are given. It represents the virtual part.

[0049] In step S130, a transient virtual impedance can be dynamically injected according to the degree of current overshoot. The dynamic resistance and inductor voltage drop are calculated through proportional gain and configurable X / R ratio to reshape the output characteristics to soften the current surge.

[0050] In this example embodiment, the method further includes: The power output under different current conditions under the transient virtual impedance strategy is as follows: , The corresponding acceleration and deceleration areas are as follows:

[0051]

[0052] And according to The semi-analytical expression is used to solve for the maximum work angle δ. m ; in, For grid impedance, This is the impedance value switched when using transient virtual impedance.

[0053] In this example embodiment, the method further includes: The upper limit of the active current is based on The calculation shows that this formula reflects the geometric relationship of the dq current distribution under amplitude constraints, ensuring that the current vector always lies within the specified safety boundary. Among them, i dmax i represents the upper limit of the d-axis current of the current-limiting circle. Pmax For current amplitude limits, i oq This represents the real-time q-axis current.

[0054] In step S140, when the current exceeds the hard current limiting threshold, the dq axis current component can be normalized to directly limit the current vector amplitude within the safe boundary, thereby achieving progressive current suppression and fault ride-through.

[0055] In this example embodiment, the method further includes: The normalization process is based on The process scales the dq-axis current components proportionally to keep the magnitude of the synthesized current vector below the hardware protection threshold.

[0056] In this example embodiment, the method further includes: The graded current limiting mechanism adopts a dual-state machine framework to coordinate three levels: power limiting, transient virtual impedance soft current limiting, and inner-loop hard current limiting. Based on the degree of current exceeding the limit, the overcurrent points OC1, OC2, and OC3 are activated in sequence to achieve priority injection of reactive current and adaptive recovery of active current.

[0057] Example 2: In this example embodiment, the present invention proposes a multi-level current limiting control strategy combining CL and TVI, aiming to improve the stability and fault ride-through capability of VSG under different fault conditions. To quantitatively evaluate the performance of different current limiting methods under fault conditions, especially their impact on the maximum power angle δm, the present invention uses EAC to calculate the fault clearing angle δRM based on the fault clearing time and determines the maximum power angle δm to evaluate the stability of the grid-type PCS. Based on this analysis, the proposed strategy dynamically switches the current limiting state through adaptive power reference and impedance adjustment, effectively suppressing fault current without affecting the grid synchronization capability. Experiments cover various situations including resistive loads, overloads, motor starting, and typical grid faults (single-phase, two-phase, and three-phase), verifying that the proposed strategy can effectively suppress overcurrent and maintain system stability. The innovations of this invention include: 1. A stability assessment method based on EAC is proposed to quantify the impact of different current limiting strategies on fault clearing time and maximum power angle, and to evaluate the transient stability and system recovery capability of VSG; 2. Design and implement a dual-state machine framework to achieve dynamic switching of current limiting strategies, ensuring rapid suppression of overcurrent and maintenance of voltage stability during fault periods; 3. The effectiveness of the proposed strategy is verified through experiments under different fault and load conditions, demonstrating its superior performance under high current disturbances.

[0058] In this example embodiment, the comparison between VSG and SG based on the energy storage VSG and the equal area criterion includes: Energy storage VSGs reconstruct inertia and damping characteristics through rotor rocking equations, thereby simulating the behavior of SGs. For example... Figure 2 As shown, the battery in the system functions similarly to the prime mover in the SG, providing kinetic energy support. The mechanical power output Pm of the SG turbine corresponds to the active power reference Pref in the VSG, and the electrical output Pe of the SG corresponds to the output Po of the VSG.

[0059] The inertia of a VSG system is determined by its energy storage system and is simulated using a virtual inertia constant J or a time constant H, thereby providing frequency support under dynamic conditions.

[0060] In this example embodiment, the application of the equal area criterion includes: In SG, when the mechanical torque Tm is greater than the electromagnetic torque Te, the accelerating torque Ta = Tm will occur. Te causes the rotor angle δ to increase. Neglecting friction and iron loss, the oscillation equation describing this dynamic process is: (1) in, Let be the inertia constant. o is the rated angular frequency. The relationship between the moment of inertia J and the moment of inertia J is as follows: (2) If the rotor angle oscillates near the equilibrium point, the system has transient stability; otherwise, a continuous increase in δ indicates system instability. Figure 3 As shown, EAC graphically assesses transient stability by ensuring that the acceleration area Aa (the kinetic energy gained) during the disturbance is equal to the deceleration area Ad (the energy dissipated).

[0061] In this example embodiment, the relationship between VSG inertia response time and critical clearing angle includes: Unlike SGs, the critical clearance time (CCT) of energy storage VSGs is typically specified by standards. For example, under severe faults such as three-phase short circuits, standards may require fault ride-through durations of 0.15 s, 0.625 s, or 2 s. The inertia time constant H of VSGs is typically designed between 3 and 12 s.

[0062] Assuming the rotor angle starts from δ0, the acceleration caused by the disturbance will lead to the critical rotor angle δRM, which is calculated as follows: (3) Where a = ωn / H is the angular acceleration. For example... Figure 4 As shown, this expression reveals the dependence of δRM on purge time t and inertia H.

[0063] It is generally believed that δRM≈π / 2 represents the transient stability boundary, while δRM>π represents the complete instability of the system, at which point the system transitions from the generating state to the motoring state.

[0064] Therefore, calculating δRM given δ0 and H is the theoretical basis for analyzing the maximum allowable angle δm in subsequent current limiting strategies.

[0065] In this example embodiment, the transient stability assessment under two energy storage VSG current limiting strategies includes: Various current limiting strategies have been proposed for VSG control. This invention focuses on two representative methods, CL and TVI, and uses the equal area criterion to evaluate their transient stability in order to analyze their dynamic response under fault disturbances.

[0066] The transient stability assessment under CL control includes: Figure 5 The dynamic switching behavior of the VSG under the CL strategy is demonstrated. When the output current exceeds a preset threshold due to a fault or disturbance, the system switches to constant current mode to protect the power converter and energy storage components. When the current falls below the limit, the system reverts to voltage source mode.

[0067] During transient processes, the CL mechanism controls the current by adjusting the voltage magnitude and phase, thereby affecting the energy exchange path. This alters the effective P-δ trajectory and influences the acceleration and deceleration areas defined by EAC. Therefore, dynamic stability assessments must consider both power angle evolution and current threshold.

[0068] The power output under CL control can be approximated as: (4) in, k This is the voltage attenuation factor during the fault period. Let the phase angle be the current reference vector, and its expression is: (5) Since the outer (Pf) loop remains active during the flow-limiting phase, EAC analysis can still be used for transient evolution under strong disturbances. For example... Figure 6 As shown, the current-limiting action alters the power angle trajectory, thereby changing the acceleration and deceleration areas defined by EAC. The dynamic process is as follows: a → b: Fault triggers CL, VSG runs as a constant current source.

[0069] b → c: Accelerate continuously until the critical angle δRM is reached.

[0070] c → d → e: Fault clearing or control exiting CL mode, the system switches back to voltage source control and tends to stabilize.

[0071] Energy area is defined as: (6) (7) The stability condition based on EAC is: (8) According to the equal area criterion, δm is defined as the maximum power angle of the first swing after a disturbance, that is, the angle corresponding to when the acceleration area equals the deceleration area and the virtual rotor speed deviation ω returns to zero. Since δm reflects the maximum phase angle shift after a disturbance, a larger δm indicates a larger first swing amplitude and higher synchronization stress, requiring stronger electrical deceleration to dissipate the equivalent kinetic energy accumulated during the fault. Therefore, this invention uses δm as a unified index to evaluate the transient swing amplitude and synchronization risk under different parameters and current limiting strategies.

[0072] It should be noted that under the influence of current limiting and control actions, the power angle relationship may be reshaped, and the strictly stable boundary is no longer exactly the same as that of a traditional synchronous generator. Therefore, this invention focuses on comparing the dynamic performance of the system through the variation trend of δm. In the numerical solution, the search range of δm is limited to (δRM, π); if no solution exists within this interval, the operating condition is marked as an invalid point.

[0073] Finally, the equal area condition in equation (8) yields an equation where δm appears in both trigonometric and linear terms, resulting in multiple unknowns. For ease of solution, we define: (9) Therefore, the integral result can be equivalently rewritten as the following transcendental equation in terms of δm: (10) Divide both sides by achievable (11) in (12) Figure 7 The contour map of the maximum work angle δm on the (r,b) plane and the corresponding normalized sensitivity assessment are given. The blank area indicates that within the specified first pendulum search interval, the transcendental equation has no feasible solution under this parameter combination, i.e., the equal area condition cannot be satisfied.

[0074] like Figure 7 The upper part of the diagram is shown in the figure. When δ0=10 δRM=30 and φ=20 Under these conditions, the maximum power angle exhibits a significant nonlinear dependence on the dimensionless parameters r and b. As r increases, the deceleration capability after fault clearance gradually weakens. To compensate for the equivalent acceleration energy accumulated within the fault / current limiting interval, the system must evolve to a larger power angle to obtain a sufficient deceleration area Ad. Therefore, δm increases and approaches the critical region. Conversely, when r is smaller, the deceleration capability remains sufficient, δm is smaller, the first swing is suppressed, and the stability margin is larger. Furthermore, changes in b significantly reshape the δm contour lines in certain regions of the (r,b) plane, indicating that the current limiting value Imax, line reactance X, and voltage drop severity k affect the maximum power angle by altering the acceleration area during the fault / current limiting phase.

[0075] Figure 7The lower half of the diagram illustrates the relative sensitivity distribution with respect to r. The colored bars represent log10(Sr / Sb): positive values ​​indicate that δm is more sensitive to r, while negative values ​​indicate that δm is more dependent on b. The black dashed line represents the Sr=Sb boundary, where δm has the same sensitivity to both parameters. It can be observed that the sensitivity-dominant region exhibits clear partitioning on the (r,b) plane, and in most cases, the influence of r is dominant.

[0076] Based on the above analysis, improving transient stability under fault conditions should primarily focus on suppressing the acceleration area before the current limiter activates. In practice, this means that the active power reference should be appropriately reduced in the early stages of a fault, thereby reducing the acceleration area, increasing the deceleration margin, and improving overall stability while maintaining effective current limiting.

[0077] In this example embodiment, the transient stability assessment under TVI control includes: To further reveal the evolution of VSG fault current and transient stability characteristics under the TVI strategy, its fault ride-through performance is studied from both time and energy perspectives.

[0078] In this example embodiment, the time-domain analysis of TVI includes: In this invention, the VI function is preserved during fault traversal, while a TVI strategy is introduced, such as... Figure 8 As shown.

[0079] During a grid fault, it is assumed that the magnitude and phase of the internal electromotive force of the VSG remain constant: (13) The voltage difference caused by the fault is: (14) Wherein, Vf(t) Vf(t+) and Vf(t+) are the voltages at the fault location before and during the fault, respectively.

[0080] The dynamic behavior of VSG voltage and current during a fault satisfies the basic circuit equations (assuming the current controller is not saturated): (15) Solving for the fault current, we obtain the following expression: (16) Where τ = Leq / Req is the time constant of the transient process of the fault current. Increasing Req or Xeq helps to dampen the current surge more quickly. Ignoring the exponential term, the quasi-steady-state fault current can be simplified to: (17) A larger Req / Leq ratio will cause the fault current to decay more quickly. Increasing both resistance and reactance can help limit the current peak during a fault.

[0081] In this example embodiment, the stability analysis based on EAC under TVI includes: The TVI controller reduces the reference voltage applied to the voltage loop, thereby limiting the output current while maintaining the VSG network characteristics. The power expressions under different current conditions are: (18) Figure 9 (ad) While keeping the fault clearing angle δRM constant, the acceleration area and deceleration area under different TVI parameters were compared.

[0082] Figure 9 (a): When there is no TVI and the inertia is low, the rotor accelerates faster and has poor stability.

[0083] Figure 9 (b): Increasing the moment of inertia can improve the deceleration capability and extend the maximum power angle δm.

[0084] Figure 9 (c): Activating TVI at the onset of a fault increases the output impedance, mitigates angle evolution, and improves Ad.

[0085] Figure 9 (d): Another approach is to directly move the reference power angle, thereby reducing Aa and enhancing stability.

[0086] The energy expression based on EAC under TVI is: (19) (20) Let Aa = Ad, then we get: (twenty one) The semi-analytical expression for δm can be rearranged as follows: (twenty two) In equation (22), Pref, δ0, δRM, E, Vg, Zg, and k can be considered as known constants. All angle-related variables in the expression are expressed in radians, and the remaining quantities are expressed in per-unit values. Therefore, the limiting power angle δm under different TVI parameter settings can be numerically solved. The resulting contour maps and sensitivity distributions are as follows: Figure 10 As shown.

[0087] like Figure 10As shown in the upper part of the schematic diagram, δm typically decreases with increasing transient virtual impedance increment. Especially in the low impedance increment region, the contour lines are denser, indicating that δm is more sensitive to TVI changes in this range. This result demonstrates that increasing the equivalent impedance through TVI can effectively improve transient stability.

[0088] Figure 10 The lower half of the schematic diagram shows the dominant sensitivity distribution, where the black curve represents the dominant boundary. This distribution exhibits an approximately linear variation over the selected parameter range, with the dominant boundary approaching a straight line. These results indicate that the sensitivity of δm to the transient virtual impedance is mainly determined by… Rv and The relative size of Lv determines this. When When Rv's contribution is dominant, δm's contribution to Rv is more sensitive; otherwise, δm is more sensitive. Lv is more sensitive. In other words, the influence of the two components on δm can be approximately understood as a competitive relationship with near-linear superposition characteristics, where the larger component has a stronger influence.

[0089] In this example embodiment, the proposed rate limiting strategy is designed as follows: This invention combines transient virtual impedance (TVI) control with a current limiting mechanism to propose a multi-level current limiting strategy, the overall structure of which is as follows: Figure 11 The proposed grid-type current limiting control system adopts a hierarchical coordination scheme, which can accurately suppress fault current while protecting system stability and maintaining grid synchronization capability.

[0090] The proposed structure is achieved through the coordinated action of three current-limiting modules: an adaptive power reference module, which dynamically estimates the available current margin / power boundary in real time during the current-limiting process and reconstructs the active and reactive power references to ensure reasonable power allocation and stable power angle response; an adaptive TVI parameter tuning module, which adjusts the virtual impedance parameters online according to the system response (such as the degree of current over-limit and the severity of voltage drop) to achieve a dynamic trade-off between current-limiting strength and stability margin; and a circular current limiter module, which acts as the final protection layer to precisely constrain the current vector amplitude and prevent over-limit transients and hardware protection triggering.

[0091] Figure 12 Multi-stage circular current thresholds in the dq coordinate system are presented. As is increases, power limiting (OC1), TVI-based soft current limiting (OC2), and inner-loop hard current limiting (OC3) are activated sequentially. Through rapid response and adaptive multi-stage coordination, the proposed strategy achieves progressive current suppression and smooth recovery under fault conditions, thereby improving overload capacity, fault ride-through performance, and grid adaptability.

[0092] A. Power grid fault detection logic Figure 13 A curve of voltage amplitude vs over time is provided, which is divided into: Normal zone (vs>0.95 p.u.): the grid conditions are normal, and no action is required.

[0093] Buffer zone (0.9<vs ≤ 0.95 p.u.): there is slight voltage fluctuation, and the controller delays the fault determination to avoid false triggering.

[0094] Fault zone (vs ≤ 0.9 p.u.): it is confirmed that a fault has occurred, and LVRT (Low Voltage Ride Through) control is activated.

[0095] During the fault ride-through process, all possible voltage trajectories are as shown in Figure 13 curves ① to ⑤ therein.

[0096] Curves ① and ② remain in the normal zone and the buffer zone respectively, so they are not determined as faults.

[0097] Curve ③ drops below 0.9 p.u. at moment A, so it is identified as a fault ride-through event.

[0098] Curve ④ enters the fault zone at moment B and is marked as a fault. Even if the voltage recovers to the buffer zone at moment C, the fault state remains.

[0099] Curve ⑤ undergoes fault ride-through at moment D, then returns to the normal zone at moment E, completing the fault clearing process.

[0100] In the embodiment of this example, the adaptive power reference includes: When overcurrent point 1 (OC1) is triggered, the active power reference regulation logic is as shown in Figure 14 . This logic takes the PCC voltage amplitude as the fault detection index, and based on the circular current limiting constraint, calculates the allowable maximum d-axis current in real time in the dq coordinate system. Subsequently, differentiated power regulation actions are taken for different overcurrent mechanisms to achieve the control objective of "current safety priority, while maintaining power continuity as much as possible".

[0101] (1) Fault identification (grid fault and non-fault) First, the d-axis voltage amplitude at the converter port is used to identify the grid state. When , a voltage sag fault is determined and the OC1 current limiting function is activated; otherwise, the event is regarded as a non-fault disturbance or power overload condition. 0.9p.u. is selected as the threshold to achieve rapid detection of voltage sag: this level is usually sufficient to distinguish between normal load changes and significant grid disturbances, and is consistent with the commonly used empirical LVRT triggering range, thereby avoiding frequent entry into the current limiting mode under slight voltage fluctuations.

[0102] (2) Calculation of the upper limit of d-axis current based on the current limiting circle: Once OC1 is triggered, the maximum available d-axis current is calculated based on the current amplitude limit iPmax and the real-time q-axis current: (twenty three) This equation reflects the geometric relationship of the dq current distribution under amplitude constraints: when ioq occupies part of the current margin, the remaining margin is allocated to the d-axis component, thereby ensuring that the current vector is always within the specified safety boundary.

[0103] (3) Overcurrent mechanism identification and power limitation (power overload and grid fault) Subsequently, the calculated idmax is compared with the rated current amplitude to distinguish between the "sustainable power overload" region and the fault scenario that requires rapid unloading.

[0104] From an energy / EAC perspective, the correction of Pref based on OC1 during voltage dips essentially suppresses the equivalent acceleration power and energy accumulation within the fault range, thereby preventing the power angle from continuously shifting forward. In particular, when the active current exceeds the allowable range, timely resetting of the reference power effectively reduces the acceleration area, avoids control performance degradation caused by current saturation, and suppresses rapid power angle accumulation. Therefore, the proposed logic, while satisfying current safety constraints, maintains active power continuity as much as possible, providing a practical trade-off between fault ride-through stability and power retention capability.

[0105] The active-reactive power limiting logic of the VSG in Fault Ride-through (FRT) mode is as follows: Figure 15 As shown, the power grid fault determination logic first uses the fault triggering flag and then constructs an estimated reactive current demand based on the terminal voltage deviation, where K represents the voltage support gain. This form can be modified according to the requirements of different national power grid specifications regarding reactive current injection during FRT.

[0106] Subsequently, the reactive power reference is determined based on the terminal voltage amplitude. To avoid insufficient reactive power support due to extremely low voltage (thus underestimating the reactive power command), a lower limit is directly applied to Qref. Finally, the reactive power reference is selected from multiple candidate values, reflecting a "fault support priority" strategy.

[0107] Following the principle of "current safety first," once the current margin occupied by reactive power injection is determined, the controller further calculates the available upper limit of the d-axis current using the current-limiting circle. A coefficient of 0.9 is introduced to reserve a safety margin to resist measurement noise, transient spikes, and dq transformation errors, thereby avoiding current saturation and frequent mode switching. Subsequently, the upper limit of active power implied by the current constraint is obtained and compared with other active power constraints (such as the active power limit imposed by OC1 and the outer loop power command), and the minimum value among them is finally adopted.

[0108] Therefore, during the FRT, the proposed logic achieves reactive power priority and adaptive active power derating under total current constraints: on the one hand, it ensures the reactive power support required during voltage dips to meet grid specifications and promote voltage recovery; on the other hand, it automatically compresses active power under current constraints to suppress the accumulation of equivalent acceleration energy within the fault interval. This reduces the risk of power angle sway and loss of synchronism, and improves the stability and repeatability of VSG fault ride-through performance.

[0109] In this example embodiment, the internal rate limiting strategy includes: The proposed current control scheme integrates TVI and direct current limiting. To ensure coordination among these mechanisms, a dedicated state machine is designed to enable or disable the control mode in real time based on the current system state.

[0110] While virtual impedance is widely used for power distribution in microgrid scenarios and grid impedance adaptation in grid-connected scenarios, its role in current limiting is not always fully utilized. This invention employs a transient virtual impedance scheme only when the apparent output current exceeds a given threshold, ensuring that the conventional impedance function remains effective during grid-connected or off-grid operation.

[0111] Figure 12 The TVI controller architecture is presented, which consists of three key modules: (1) Overcurrent detection module (OC2): The instantaneous current is is compared with the threshold iTVImax (1.2 pu).

[0112] Hysteresis comparators with a range of ±0.01 pu prevent frequent mode switching and ensure stability.

[0113] (2) Virtual impedance calculation: Calculate the dynamic resistance Rvi and inductance Xvi using the proportional gain kp, Rvi and the configurable X / R ratio.

[0114] (3) Voltage drop calculation: Calculate the voltage drop vectors Δed and Δeq using Rvi and Xvi, and inject them into the voltage loop to reduce the output voltage and limit the current.

[0115] In this example embodiment, direct current limiting includes: This strategy does not directly clamp the current reference generated by the voltage loop, but rather normalizes the dq-axis current components to keep their vector magnitude within specified limits. The current limiting equation is: (twenty four) This normalization method ensures that the final output current vector is within the hardware safety margin, effectively limiting the current without compromising the control structure.

[0116] In this example embodiment, the graphical explanation of the transient stability under the proposed hierarchical hybrid current limiting strategy includes: Because the current limiting scheme employed consists of power limiting, transient virtual impedance, and inner-loop current saturation, it is a layered hybrid strategy. Its operation is inherently nonlinear and piecewise: different current limiting layers dominate at different overcurrent levels and time periods, while the current limiting threshold, switching logic, and control saturation jointly reshape the effective output voltage and power transfer characteristics. Therefore, unlike single current limiting methods (such as pure current saturation or pure TVI current limiting), it is difficult to derive a unified closed-form expression for acceleration / deceleration areas. To address this, this invention employs a graphical explanation to qualitatively analyze the power angle dynamics caused by faults under the proposed strategy, thereby clarifying the transient stability mechanism and the impact of key parameters.

[0117] Taking a three-phase ground fault as an example, this fault is usually considered the most serious power grid fault.

[0118] exist Figure 16 In (a), the system operates under normal conditions with the active power setpoint Pref and steady-state power angle δ0. Once a fault occurs, the PCC voltage drops sharply, and the reactive power support demand increases rapidly, causing the reactive current command to rise quickly. The power limiting layer is activated first: because the current margin is occupied by the reactive component, the calculated active power command is compressed to near zero, thus achieving the rule of prioritizing reactive power support and preserving active power as much as possible. However, under severe faults, simply reducing the active power reference is usually insufficient to constrain the actual output current, and the controller further enters the current limiting phase. For mild overcurrent situations, the TVI can maintain the current near the threshold, and the trajectory can be determined by… Figure 16 (b) directly evolved to Figure 16 (d). In more severe cases, inner loop current saturation is forced to intervene. Figure 16 (c)] At this point, the voltage source characteristics of the converter are weakened or even destroyed. Therefore, the effective power angle characteristic of the VSG changes from an approximately sinusoidal relationship to a cosine-like / constrained curve, and the power angle operating point jumps from δ0 to δm. During this stage, the system mainly obtains deceleration area and has almost no acceleration area, thereby reducing the risk of instability during the fault entry stage.

[0119] It is important to emphasize that the TVI remains active throughout the inner-loop saturation phase. Since the TVI activation threshold is typically lower than the inner-loop saturation threshold, the TVI can "soften" the output characteristics when the current first begins to increase abnormally, and continue to work in conjunction with hard current limiting at deeper current-limiting levels to gradually alleviate the severity of the overcurrent. Once the current decays below the inner-loop saturation exit condition, the converter gradually resumes its voltage source behavior, and the power angle curve shifts towards... Figure 16(d) Transition, the power angle evolves from δm to δv. If the fault is permanent, the system can stabilize at a new equilibrium point under constrained power transfer characteristics and continue operating. If the fault is non-permanent, during the recovery period after the fault, TVI is first released. Figure 16 (e)], restoring the power transfer curve to its rated shape. At this point, since the power limiting layer has not yet fully released, additional deceleration area is still available to suppress power angle bounce and enhance recovery stability. As the power limiting gradually exits, the active power command returns to the original Pref, and the system eventually returns to its pre-fault operating state.

[0120] Depend on Figure 16 (c) and Figure 16 (d) The key parameter design implications of the layered hybrid current limiting strategy can be summarized, which is consistent with the power angle analysis above. First, under the premise of meeting device safety and power grid specification constraints, the hard current limiting value should be appropriately increased to expand the achievable deceleration area and improve fault ride-through margin. Second, the TVI amplitude should not be too large; excessively large virtual impedance will significantly compress the power angle curve amplitude and reduce... Figure 16 (d) The available deceleration area may lead to instability during the fault entry phase due to insufficient deceleration. Overall, the system is more likely to maintain a continuous deceleration area during the fault exit phase, thus ensuring greater stability. By properly tuning the power limiting logic and TVI parameters, the grid-type energy storage VSG can operate primarily in a "deceleration area" manner throughout the entire FRT process. This differs from a single current limiting strategy, which inevitably introduces an acceleration area at certain stages and may trigger instability. By coordinating current distribution in the power loop, TVI-based soft current limiting, and inner loop hard saturation, the proposed hierarchical hybrid strategy can achieve priority injection of reactive current during faults and smooth recovery of active current after faults, thereby significantly improving the stability and controllability of the FRT.

[0121] It should be noted that although the steps of the method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple steps.

[0122] Furthermore, this example embodiment also provides a virtual synchronizer stability assessment and hierarchical current limiting device. (Refer to...) Figure 17 As shown, the virtual synchronous machine stability assessment and hierarchical current limiting device 200 may include: a fault detection and state division module 210, an adaptive power reference adjustment module 220, a transient virtual impedance injection module 230, and a direct current limiting protection module 240. Wherein: The fault detection and state classification module 210 is used to monitor the voltage and output current of the common coupling point in real time, classify the grid operation state according to the voltage amplitude, and trigger a graded current limiting mechanism when a fault or overcurrent is detected. The adaptive power reference adjustment module 220 is used to calculate the upper limit of active current based on the real-time reactive current component according to the circular current limiting constraint, and adaptively adjust the active power reference value and reactive power reference value to suppress the acceleration area during the fault and maintain reactive power support. The transient virtual impedance injection module 230 is used to dynamically inject transient virtual impedance according to the degree of current over-limit. It calculates dynamic resistance and inductor voltage drop through proportional gain and configurable X / R ratio to reshape output characteristics to soften current surges. The direct current limiting protection module 240 is used to normalize the dq axis current component when the current exceeds the hard current limiting threshold, and directly limit the current vector amplitude within the safe boundary to achieve progressive current suppression and fault ride-through.

[0123] The specific details of each of the above-mentioned virtual synchronizer stability assessment and hierarchical current limiting device modules have been described in detail in the corresponding virtual synchronizer stability assessment and hierarchical current limiting method, so they will not be repeated here.

[0124] It should be noted that although several modules or units of a virtual synchronizer stability assessment and hierarchical current limiting device 200 have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0125] Furthermore, the above figures are merely illustrative of the processes included in the method according to exemplary embodiments of the present invention, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0126] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0127] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A method for stability evaluation and hierarchical current limiting of a virtual synchronizer, characterized in that, The method includes: Real-time monitoring of common coupling point voltage and output current; classification of grid operation status based on voltage amplitude; and triggering of graded current limiting mechanism when fault or overcurrent is detected. Based on circular current limiting constraints, the upper limit of active current is calculated according to the real-time reactive current component, and the active power reference value and reactive power reference value are adaptively adjusted to suppress the acceleration area during the fault and maintain reactive power support. Based on the degree of current overshoot, a transient virtual impedance is dynamically injected, and the dynamic resistance and inductor voltage drop are calculated through proportional gain and configurable X / R ratio to reshape the output characteristics to soften current surges. When the current exceeds the hard current limiting threshold, the dq axis current component is normalized to directly limit the current vector amplitude within the safe boundary, thereby achieving progressive current suppression and fault ride-through.

2. The method as described in claim 1, characterized in that, The method also includes: A transient stability assessment model is established based on the equal area criterion, according to... Calculate the critical clearing angle δ RM and based on , The acceleration area A a With deceleration area A d Determine the maximum work angle δ based on the iso-area stability condition. m To assess the transient stability margin of the system; in, δ RM The critical rotor angle, δ m For the maximum angle of attack, δ 0 represents the initial power angle, t represents the fault duration, and a = ωn / H represents the angular acceleration. P ref For active power reference, i CLmax The current limiting threshold for the CL phase. E V represents the internal electromotive force of the VSG, k represents the voltage drop depth across the grid (k=1 for normal conditions, k=0 for zero-voltage crossing), and V represents the voltage drop depth across the grid. g This is the effective value of the grid voltage. δ For rotor angle, The angle formed by the active and reactive currents during the fault period. E X represents the internal electromotive force of the VSG, and X represents the internal electromotive force E of the virtual synchronous machine and the line inductance parameter at the grid connection point.

3. The method as described in claim 1, characterized in that, The method further includes: The power output under the current limiting strategy is based on An approximate representation, where the phase angle of the current reference vector is given by... It is determined that the acceleration area and the deceleration area are: Where P is the active power transmitted under current limiting and amplitude limiting, and X... g The electromotive force E within the virtual synchronous machine and the line inductance parameters at the grid connection point are given. i s Let P be the current amplitude in the dq coordinate system. max To theoretically transmit the active power limit, This serves as a reference for reactive current during a fault. This serves as a reference for active current during a fault period. A a To accelerate the area, A d This represents the deceleration area.

4. The method as described in claim 1, characterized in that, The method further includes: The maximum power angle δ m By solving The transcendental equations are obtained, where parameters A and B are derived from... The normalized equation is defined as follows: As shown; Among them, I max The maximum allowable current limit set for the software.

5. The method as described in claim 1, characterized in that, The method further includes: The quasi-steady-state fault current of the transient virtual impedance strategy is The time constant τ of the transient process of the fault current is determined by the ratio of the equivalent inductance to the equivalent resistance. in, To determine the quasi-steady-state fault current under virtual impedance current limiting, This represents the voltage difference before and after the fault. These are the electromotive force E within the virtual synchronous machine and the line resistance parameters at the grid connection point. The electromotive force E within the virtual synchronous machine and the line inductance parameters at the grid connection point are given. It represents the virtual part.

6. The method as described in claim 1, characterized in that, The method further includes: The power output under different current conditions under the transient virtual impedance strategy is as follows: ， The corresponding acceleration and deceleration areas are as follows: And according to The semi-analytical expression is used to solve for the maximum work angle δ. m ; in, For grid impedance, This is the impedance value switched when using transient virtual impedance.

7. The method as described in claim 1, characterized in that, The method further includes: The upper limit of the active current is based on The calculation shows that this formula reflects the geometric relationship of the dq current distribution under amplitude constraints, ensuring that the current vector always lies within the specified safety boundary. Among them, i dmax i represents the upper limit of the d-axis current of the current-limiting circle. Pmax For current amplitude limits, i oq This represents the real-time q-axis current.

8. The method as described in claim 1, characterized in that, The method further includes: The normalization process is based on The process scales the dq-axis current components proportionally to keep the magnitude of the synthesized current vector below the hardware protection threshold.

9. The method as described in claim 1, characterized in that, The method further includes: The graded current limiting mechanism adopts a dual-state machine framework to coordinate three levels: power limiting, transient virtual impedance soft current limiting, and inner-loop hard current limiting. Based on the degree of current exceeding the limit, the overcurrent points OC1, OC2, and OC3 are activated in sequence to achieve priority injection of reactive current and adaptive recovery of active current.

10. A virtual synchronizer stability assessment and hierarchical current limiting device, characterized in that, The device includes: The fault detection and status classification module is used to monitor the voltage and output current of the common coupling point in real time, classify the grid operation status according to the voltage amplitude, and trigger a graded current limiting mechanism when a fault or overcurrent is detected. The adaptive power reference adjustment module is used to calculate the upper limit of active current based on the real-time reactive current component according to the circular current limiting constraint, and adaptively adjust the active power reference value and reactive power reference value to suppress the acceleration area during the fault and maintain reactive power support. The transient virtual impedance injection module is used to dynamically inject transient virtual impedance according to the degree of current overrun. It calculates dynamic resistance and inductor voltage drop through proportional gain and configurable X / R ratio to reshape output characteristics to soften current surges. The direct current limiting protection module is used to normalize the dq axis current components when the current exceeds the hard current limiting threshold, directly limiting the current vector amplitude within the safe boundary, thereby achieving progressive current suppression and fault ride-through.

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