Method and circuit for improving the slope of the voltage waveform of a capacitor charge and discharge

Abstract

The application discloses a method and circuit for improving the voltage waveform slope of capacitor charging and discharging, and relates to the technical field of analog integrated circuit design and power management. A steady-state voltage dividing network with a first equivalent impedance is used to establish and maintain a stable DC voltage across the target capacitor. In response to a charging start event, a separate timing capacitor is reset to a preset initial level, triggering a hysteresis comparison module to output a first logic signal to turn on an auxiliary charging path. After the reset is removed, the timing capacitor charges at a preset time constant, and the hysteresis comparison module only collects the voltage for threshold monitoring, maintaining the signal before it rises to the positive flip threshold. The auxiliary charging path charges the target capacitor at a second equivalent impedance much smaller than the first equivalent impedance, and the auxiliary path is turned off after the threshold is reached, and the steady-state voltage dividing network is connected to maintain it. The application decouples the steady-state power consumption and the charging and discharging speed, realizes fast voltage establishment under micro-power steady-state, and improves the charging timing consistency.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit design and power management technology, specifically to a method and circuit for improving the slope of capacitor charging and discharging voltage waveform. Background Technology

[0002] As electronic devices place increasingly stringent requirements on power timing control and signal setup time, resistor divider networks combined with target capacitors to form low-pass filters or energy storage circuits have become a core infrastructure in power management, voltage divider sampling, and other applications. The current mainstream approach involves directly charging and discharging the target capacitor using the equivalent impedance formed by the voltage divider resistors. This architecture, with its simple structure and low cost, is widely used in various electronic systems, especially in battery-powered or low-power scenarios where steady-state power consumption is critical. In these cases, the resistance values ​​of the voltage divider resistors are typically selected in the hundreds of kiloohms to megaohms range to reduce continuous current consumption.

[0003] However, in this architecture, the voltage divider resistors simultaneously perform the functions of steady-state voltage division and limiting the charge / discharge rate, leading to inherent physical constraints during long-term operation: while high resistance reduces steady-state power consumption, it also increases the charge / discharge time constant, extending the settling time of the target capacitor voltage to several seconds or even tens of seconds; conversely, reducing the resistance to increase speed will proportionally increase steady-state power consumption. This physical binding between power consumption and speed limits the performance of existing solutions in applications requiring frequent power-on / off cycles or with strict settling time requirements.

[0004] Further analysis reveals that in low-power applications, the real constraint on system performance is often not the absolute value of steady-state power consumption, but rather its secondary effects: the high-impedance charging and discharging network leads to excessively long voltage settling time, becoming a bottleneck for the entire system's response speed. Taking a typical battery-powered device as an example, using megaohm-level voltage divider resistors to control the steady-state current to a few microamps results in a charging time constant for the target capacitor reaching hundreds of milliseconds to several seconds, consequently extending the voltage settling time to the second level. If the steady-state maintenance function and transient charging function can be separated, with the high-impedance network independently handling the steady-state voltage division, and a low-impedance path completing rapid charging during a brief conduction period, then the steady-state power consumption is still determined by the high-impedance network, while the voltage settling time is determined by the low-impedance path, and the two no longer mutually constrain each other. Although the control circuit introduced in this way increases the static current by several to tens of microamps, the overall system power consumption remains in the microamp range, and the voltage settling time is shortened from the second level to the millisecond level.

[0005] Furthermore, under continuous power-on and power-off conditions, the residual voltage of the target capacitor in the existing solution leads to inconsistent initial states for each charge and discharge, resulting in fluctuations in the settling time. To ensure consistent initial states for each charge, it is necessary to wait for the capacitor to discharge naturally through a high-impedance voltage divider network. This waiting time is on the order of seconds, similar to the charging time, further extending the total time from triggering charging to voltage readiness.

[0006] Therefore, there is a need in the art for a method and circuit that can functionally decouple steady-state power consumption from charge / discharge speed while ensuring settling time consistency and system reliability, thereby improving the slope of the capacitor charge / discharge voltage waveform. Summary of the Invention

[0007] The main objective of this invention is to provide a method and circuit for improving the slope of the capacitor charging and discharging voltage waveform, aiming to resolve the contradiction between steady-state power consumption and charging / discharging speed in existing voltage divider networks, achieve rapid setup under low power consumption steady state, and improve the consistency of setup time and system reliability.

[0008] To overcome the shortcomings of existing technologies and achieve the above objectives, a method for improving the slope of a capacitor charging and discharging voltage waveform is provided, comprising: S1: A stable DC voltage is established and maintained across the target capacitor through a steady-state voltage divider network with a first equivalent impedance; S2: Under the condition that the steady-state voltage divider network maintains the DC voltage, in response to the charging start event, the energy storage state is reset for the timing capacitor set independently of the target capacitor, triggering the hysteresis comparison module to output the first logic signal; wherein, before the charging start event is triggered, the target capacitor is in a preset initial voltage state; S3: During the first logic signal output period, the reset constraint on the timing capacitor is released, so that the timing capacitor is continuously charged based on the preset time constant of the timing network, and the target capacitor is fast charged through an auxiliary charging path with a second equivalent impedance, wherein the second equivalent impedance is not greater than one-tenth of the first equivalent impedance. S4: During the fast charging process of the target capacitor, the voltage of the timing capacitor is monitored for a threshold. Before the voltage of the timing capacitor rises to the positive flip threshold, the first logic signal is maintained to keep the auxiliary charging path on, and the timing control is decoupled from the charging power link of the target capacitor. S5: When the voltage of the waiting capacitor rises to the positive flip threshold, the hysteresis comparison module outputs a second logic signal to turn off the auxiliary charging path, and the steady-state voltage divider network continues to maintain the steady-state voltage of the target capacitor; wherein, the conduction time of the auxiliary charging path is configured such that, when the initial voltage of the target capacitor is lower than the steady-state voltage, the voltage of the target capacitor is not higher than the steady-state voltage when it is turned off.

[0009] Further, in step S2, resetting the energy storage state of the timing capacitor specifically includes: S21: In response to the charging start event, generate a reset pulse of a preset width; S22: Based on the reset pulse, control the low-impedance discharge path to be turned on, connect the non-grounded terminal of the timing capacitor to ground potential, eliminate the residual charge of the previous working cycle, and keep the initial level of the timing capacitor consistent before each charging start.

[0010] Furthermore, in step S22, the discharge time constant of the low-impedance discharge path in the conducting state is not greater than one-tenth of the charging time constant of the timing network, and the width of the reset pulse ensures that the voltage across the timing capacitor is completely discharged to the preset initial level.

[0011] Further, in step S4, the threshold monitoring of the voltage of the timing capacitor specifically includes: S41: A reference voltage is generated by a voltage divider network connected between the power supply and ground, and the reference voltage is proportional to the power supply voltage. S42: Couple the voltage of the timing capacitor to the first input terminal of the hysteresis comparator module, and couple the reference voltage to the second input terminal of the hysteresis comparator module; S43: The output of the hysteresis comparator module is coupled to the first input terminal through a positive feedback impedance network to form a Schmitt trigger structure, so that the hysteresis comparator module has different positive and negative flip thresholds, and the flip thresholds change proportionally with the reference voltage.

[0012] Furthermore, the input terminal of the hysteresis comparison module is only coupled to the voltage of the timing capacitor and the reference voltage, and there is no feedback loop between it and the target capacitor. This allows the conduction duration of the auxiliary charging path to be independently determined by the charging process of the timing network, and is not affected by the charging state of the target capacitor.

[0013] Furthermore, the absolute values ​​of the positive flip threshold, negative flip threshold, and hysteresis window are all proportional to the power supply voltage, so that the conduction time of the auxiliary charging path remains stable when the power supply voltage fluctuates, and the relative level of hysteresis immunity remains consistent across the entire power supply voltage range.

[0014] Further, in step S5, the voltage of the target capacitor during the turn-off is not higher than the steady-state voltage. This is achieved by matching the second equivalent impedance of the auxiliary charging path with the preset time constant of the timing network and the positive flip threshold of the hysteresis comparison module. The conduction duration of the auxiliary charging path is determined by the preset time constant and the positive flip threshold. The second equivalent impedance is determined based on the conduction duration, the capacitance of the target capacitor, and the steady-state voltage, so that the target capacitor is charged to a level not higher than the steady-state voltage within the conduction duration.

[0015] Furthermore, it also includes: S6: In response to a discharge trigger signal independent of the charging start event, conduct an auxiliary discharge path connected in parallel with the target capacitor, wherein the equivalent impedance of the auxiliary discharge path is not greater than one-tenth of the equivalent impedance of the steady-state voltage divider network.

[0016] Furthermore, in step S6, the conduction and cutoff of the auxiliary discharge path are directly controlled by an independent discharge trigger signal. Its control link is electrically and logically independent from the control link of the auxiliary charging path, so that the charging and discharging operations can be triggered independently in any order without interference between the timing sequences. The charging start event and the discharge trigger signal are both kept at an invalid level under normal conditions, and are only briefly switched to an effective level when fast charging or fast discharging is required. This ensures that during steady-state maintenance, both the auxiliary charging path and the auxiliary discharge path are in a turned-off state, and the voltage of the target capacitor is independently maintained by the steady-state voltage divider network.

[0017] A circuit for increasing the slope of the capacitor charging and discharging voltage waveform is also provided to implement the above method, comprising: Target capacitance; A steady-state voltage divider network is connected between the power supply and ground, with its intermediate node connected to the first end of the target capacitor and having a first equivalent impedance; An auxiliary charging path is connected between the power supply and the first terminal of the target capacitor, and its equivalent impedance is no more than one-tenth of the equivalent impedance of the steady-state voltage divider network. An auxiliary discharge path is connected in parallel with the target capacitor. Its equivalent impedance is no more than one-tenth of the equivalent impedance of the steady-state voltage divider network. Its conduction and cutoff are controlled by a discharge trigger signal independent of the charging start event. A timing network includes a timing resistor and a timing capacitor connected in series. One end of the timing resistor is connected to a power supply, and one end of the timing capacitor is grounded. The connection node of the two outputs a timing voltage. A forced reset module, connected in parallel with the timing capacitor, has a control input terminal for receiving a reset signal, and is used to reset the voltage of the timing capacitor to a preset initial level in response to the reset signal; A reference voltage divider network, connected between the power supply and ground, is used to provide a reference voltage that is in a fixed proportion to the power supply voltage. The hysteresis comparison module includes a comparator, an input resistor, and a positive feedback resistor. The non-inverting input of the comparator is coupled to the timing voltage via the input resistor, the inverting input receives the reference voltage, and the output is coupled to the non-inverting input via the positive feedback resistor to form a Schmitt trigger structure. The auxiliary charging path has a control terminal, which is coupled to the output terminal of the hysteresis comparison module, so that the conduction and cutoff of the auxiliary charging path are controlled by the output terminal of the hysteresis comparison module. The input of the hysteresis comparator module is coupled only to the timing voltage and the reference voltage, and does not sample the voltage of the target capacitor. There is no feedback loop between the hysteresis comparator module and the target capacitor. The equivalent impedance of the auxiliary charging path is configured to match the preset time constant of the timing network and the positive flip threshold of the hysteresis comparator module. The conduction duration of the auxiliary charging path is determined by the preset time constant and the positive flip threshold. The equivalent impedance of the auxiliary charging path is determined based on the conduction duration, the capacitance of the target capacitor, and the steady-state voltage maintained across the target capacitor by the steady-state voltage divider network, so that the target capacitor is charged to a level not higher than the steady-state voltage within the conduction duration.

[0018] The beneficial effects of the present invention are: 1. By constructing a steady-state voltage divider network with a first equivalent impedance and an auxiliary charging path with a second equivalent impedance much smaller than the first equivalent impedance, the steady-state voltage maintenance and fast charging and discharging functions are separated, solving the problem of power consumption and speed constraints caused by the voltage divider resistor simultaneously undertaking two functions in the prior art, and realizing fast voltage establishment under low power consumption steady-state operation.

[0019] 2. By configuring a hysteresis comparison module that only collects the timing capacitor voltage and not the target capacitor voltage, the timing control link and the charging power link are completely decoupled, solving the loop stability problem that may exist in closed-loop feedback control and realizing open-loop precise timing control.

[0020] 3. By resetting the energy storage state of the timing capacitor before each charging start, the voltage of the timing capacitor is reset to the preset initial level, eliminating the uncertainty of the timing circuit itself and ensuring the high consistency of the fast charging conduction time. Thus, under the premise that the initial voltage of the target capacitor is consistent, the repeatability accuracy of the charging sequence under continuous power-on and power-off conditions is improved. Attached Figure Description

[0021] Figure 1 This is a schematic diagram illustrating the steps of the method for increasing the slope of the capacitor charging and discharging voltage waveform according to an embodiment of the present invention; Figure 2This is a schematic diagram of the circuit architecture for improving the slope of the capacitor charging and discharging voltage waveform according to an embodiment of the present invention. Figure 3 This is a schematic diagram of a specific structure of the circuit for improving the slope of the capacitor charging and discharging voltage waveform according to an embodiment of the present invention.

[0022] Figure Labels R1 - First resistor, R2 - Second resistor, R3 - Third resistor, R4 - Fourth resistor, R5 - Fifth resistor, R6 - Sixth resistor, R7 - Seventh resistor, R8 - Eighth resistor, R9 - Ninth resistor, R10 - Tenth resistor, Rin - Eleventh resistor, C1 - First capacitor, C2 - Second capacitor, Q1 - First switching transistor, Q2 - Second switching transistor, Q3 - Third switching transistor, U1 - Comparator, DZ - Clamp transistor, CTRL1 - First control signal line, CTRL2 - Second control signal line. Detailed Implementation

[0023] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described content is only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0024] like Figure 1 As shown, a method for increasing the slope of a capacitor charging and discharging voltage waveform includes: S1: A stable DC voltage is established and maintained across the target capacitor through a steady-state voltage divider network with a first equivalent impedance; S2: Under the condition that the steady-state voltage divider network maintains the DC voltage, in response to the charging start event, the energy storage state is reset for the timing capacitor set independently of the target capacitor, triggering the hysteresis comparison module to output the first logic signal; wherein, before the charging start event is triggered, the target capacitor is in a preset initial voltage state; S3: During the first logic signal output period, the reset constraint on the timing capacitor is released, so that the timing capacitor is continuously charged based on the preset time constant of the timing network, and the target capacitor is fast charged through an auxiliary charging path with a second equivalent impedance, wherein the second equivalent impedance is not greater than one-tenth of the first equivalent impedance. S4: During the fast charging process of the target capacitor, the voltage of the timing capacitor is monitored for a threshold. Before the voltage of the timing capacitor rises to the positive flip threshold, the first logic signal is maintained to keep the auxiliary charging path on, and the timing control is decoupled from the charging power link of the target capacitor. S5: When the voltage of the waiting capacitor rises to the positive flip threshold, the hysteresis comparison module outputs a second logic signal to turn off the auxiliary charging path, and the steady-state voltage divider network continues to maintain the steady-state voltage of the target capacitor; wherein, the conduction time of the auxiliary charging path is configured such that, when the initial voltage of the target capacitor is lower than the steady-state voltage, the voltage of the target capacitor is not higher than the steady-state voltage when it is turned off.

[0025] In this embodiment, the steady-state voltage divider network refers to a voltage divider circuit network composed of impedance elements that can establish and maintain a stable DC voltage across the target capacitor for a long time. Its core feature is that it has a relatively large equivalent impedance to limit the steady-state operating current. The first equivalent impedance refers to the equivalent resistance of the steady-state voltage divider network to the outside at the node where the target capacitor is located. Its value is the parallel equivalent value of each impedance element constituting the steady-state voltage divider network at that node. The timing capacitor refers to a capacitor element set independently of the target capacitor and specifically used to generate timing control signals. Its capacitance value and operating state do not directly affect the voltage of the target capacitor. The energy storage state reset refers to forcibly restoring the voltage across the timing capacitor to a preset initial level through a low-impedance discharge path to eliminate the influence of residual charge from the previous operation on the subsequent timing accuracy. For example, this reset operation can be achieved by conducting a low-impedance discharge path connected in parallel with the timing capacitor. The charging start event refers to the control signal or state change issued by the system controller to start a fast charging process. The hysteresis comparison module refers to a voltage comparison function unit with Schmitt trigger characteristics. The relationship between its input voltage and output voltage exhibits a hysteresis loop characteristic. The first and second logic signals refer to two different level states output by the hysteresis comparator module, corresponding to the on and off states of the auxiliary charging path, respectively. The auxiliary charging path is a low-impedance path that is turned on during the fast charging phase to inject charging current into the target capacitor. The second equivalent impedance refers to the equivalent resistance of the auxiliary charging path in the on state. The second equivalent impedance is no greater than one-tenth of the first equivalent impedance (i.e., the ratio of the two differs by at least one order of magnitude), ensuring that the charging current when the auxiliary charging path is on is significantly greater than the current provided solely by the steady-state voltage divider network. The timing network refers to an RC series charging circuit composed of a timing resistor and a timing capacitor. The preset time constant refers to the RC time constant determined by the product of the parameters of the resistive and capacitive elements in the timing network. The preset initial voltage state refers to the voltage across the target capacitor being placed at a known fixed level before the charging start event is triggered; for example, the zero-voltage state naturally present when the system is first powered on, or the ground potential pre-discharged through the auxiliary discharge path. The flip threshold refers to the critical voltage value that the input terminal needs to reach when the output of the hysteresis comparator module flips. The positive flip threshold refers to the critical voltage at which the output flips from the first logic signal to the second logic signal, and the negative flip threshold refers to the critical voltage at which the output flips from the second logic signal to the first logic signal.

[0026] In this embodiment, the overall timing of the method is as follows: In the steady-state maintenance state, only the steady-state voltage divider network operates, the auxiliary charging path is off, and the target capacitor voltage is determined by the voltage division ratio of the steady-state voltage divider network. When the system controller issues a charging start event, while the steady-state voltage divider network continues to maintain the DC voltage, the target capacitor is already in a preset initial voltage state. The energy storage state is reset for the timing capacitor, which is set independently of the target capacitor, triggering the hysteresis comparison module to output a first logic signal. During the first logic signal output, the reset constraint on the timing capacitor is released, and the timing capacitor begins charging according to a preset time constant. Simultaneously, the auxiliary charging path is turned on, performing fast charging of the target capacitor through a low-impedance path. During the fast charging of the target capacitor, the hysteresis comparison module continuously monitors the voltage of the timing capacitor for threshold values. It maintains the output of the first logic signal until the timing capacitor voltage rises to the positive flip threshold, keeping the auxiliary charging path on. Because the hysteresis comparison module only collects the voltage of the timing capacitor and not the voltage of the target capacitor, it achieves decoupling between the timing control link and the target capacitor charging power link. The two are electrically and signal-wise independent, and there is no feedback loop. When the voltage of the waiting capacitor rises to the positive flip threshold, the hysteresis comparator outputs the second logic signal, the auxiliary charging path is turned off, and the target capacitor is then maintained by the steady-state voltage divider network. When turned off, the voltage of the target capacitor is not higher than the steady-state voltage.

[0027] It should be noted that the initial power-on process of the system can be considered a specific charging start event. At this time, the timing capacitor voltage is naturally at the preset initial level, so the energy storage state reset is equivalent to completing the reset without executing a reset pulse. In the scenario of the system's first power-on or when the target capacitor voltage has not yet reached the steady-state voltage, the steady-state maintenance state has not yet been established, the initial voltage of the timing capacitor is zero, which is lower than the negative flip threshold of the hysteresis comparator module. The hysteresis comparator module outputs the first logic signal, the auxiliary charging path is automatically turned on, and the fast charging process is directly executed. The target capacitor is quickly charged to near the steady-state voltage through the auxiliary charging path, and then the steady-state voltage divider network continues to maintain it, entering the steady-state maintenance state. After the initial power-on fast charging is completed, the timing capacitor has been charged to the power supply voltage, and the auxiliary charging path is turned off. If fast charging is required again thereafter, the system controller must actively issue a charging start event.

[0028] This embodiment assigns the steady-state voltage maintenance function and the fast charging function to two paths with different equivalent impedances and separates their control in time. This eliminates the constraint of charging speed on steady-state power consumption, instead allowing the charging speed to be determined by the low-impedance auxiliary path, thus removing the physical binding relationship between the two in traditional solutions. Simultaneously, by decoupling the timing control link from the target capacitor's charging power link, loop stability issues that might be introduced by closed-loop feedback are avoided, simplifying the control architecture. Furthermore, by resetting the energy storage state of the timing capacitor before each charging start, the fast charging conduction duration is highly consistent, improving the repeatability accuracy of the charging sequence while maintaining a consistent initial voltage of the target capacitor.

[0029] In one feasible implementation, step S2, resetting the energy storage state of the timing capacitor, specifically includes: S21: In response to the charging start event, generate a reset pulse of a preset width; S22: Based on the reset pulse, control the low-impedance discharge path to be turned on, connect the non-grounded terminal of the timing capacitor to ground potential, eliminate the residual charge of the previous working cycle, and keep the initial level of the timing capacitor consistent before each charging start.

[0030] In step S22, the discharge time constant of the low-impedance discharge path in the conducting state is not greater than one-tenth of the charging time constant of the timing network, and the width of the reset pulse ensures that the voltage across the timing capacitor is completely discharged to the preset initial level.

[0031] In this embodiment, the reset pulse refers to a control pulse signal with a preset duration generated by the system controller in response to a charging start event. The low-impedance discharge path refers to a switching element connected in parallel with the timing capacitor that is turned on during the effective period of the reset pulse, exhibiting extremely low on-resistance in the on-state. The preset initial level is ground potential. In other embodiments, the preset initial level can also be set to other fixed reference levels, as long as this level is ensured to be lower than the negative flip threshold of the hysteresis comparator module, ensuring that the timing capacitor starts charging from the same predetermined state. The discharge time constant refers to the product of the on-resistance of the low-impedance discharge path and the timing capacitor. This time constant is much smaller than the charging time constant of the timing network, ensuring that the discharge speed is much faster than the charging speed.

[0032] In this embodiment, the low-impedance discharge path is implemented using an N-channel MOSFET. Its gate is controlled by the reset pulse, its drain is connected to the ungrounded terminal of the timing capacitor, and its source is grounded. When the reset pulse is active, the MOSFET is turned on, forcing the ungrounded terminal of the timing capacitor to ground potential, eliminating its residual charge. For example, the width of the reset pulse can be set to 1µs to 5µs. When the on-resistance of the MOSFET is less than 50mΩ and the timing capacitor is 0.2µF, the discharge time constant is less than 10ns, and the reset operation can be completed in a very short time. The width of the reset pulse must be selected to ensure that the conduction time of the low-impedance discharge path is sufficient to completely discharge the voltage across the timing capacitor to the preset initial level. After the reset pulse returns to an inactive level, the MOSFET is turned off, and the timing capacitor begins charging through the timing network. During the process of resetting the timing capacitor to ground potential, because the timing capacitor voltage drops below the negative flip threshold, the output of the hysteresis comparator module flips to the first logic signal, and the auxiliary charging path is activated during the reset phase. The fast charging action starts synchronously with the timing capacitor reset. Subsequently, the hysteresis comparator module continues to output the first logic signal, and the auxiliary charging path remains on until the timing capacitor voltage rises to the positive flip threshold.

[0033] This embodiment generates a reset pulse before each charge start to control the low-impedance discharge path, forcibly resetting the timing capacitor voltage to a consistent initial level. This eliminates the influence of residual charge from the previous working cycle on the timing of the current cycle, ensuring a completely uniform timing start point for each charge. Simultaneously, by limiting the discharge time constant to be much smaller than the charging time constant and by using a wide pulse width to ensure complete discharge, the thoroughness and speed of the reset operation are guaranteed, thereby improving the repeatability accuracy of the charging conduction time under continuous charge-discharge conditions.

[0034] In one feasible implementation, step S4, specifically the threshold monitoring of the voltage of the timing capacitor, includes: S41: A reference voltage is generated by a voltage divider network connected between the power supply and ground, and the reference voltage is proportional to the power supply voltage. S42: Couple the voltage of the timing capacitor to the first input terminal of the hysteresis comparator module, and couple the reference voltage to the second input terminal of the hysteresis comparator module; S43: The output of the hysteresis comparator module is coupled to the first input terminal through a positive feedback impedance network to form a Schmitt trigger structure, so that the hysteresis comparator module has different positive and negative flip thresholds, and the flip thresholds change proportionally with the reference voltage.

[0035] In step S4, the input terminal of the hysteresis comparison module is only coupled to the voltage of the timing capacitor and the reference voltage, and there is no feedback loop between it and the target capacitor. This allows the conduction duration of the auxiliary charging path to be independently determined by the charging process of the timing network and is not affected by the charging state of the target capacitor.

[0036] In step S4, the absolute values ​​of the positive flip threshold, the negative flip threshold, and the hysteresis window are all proportional to the power supply voltage, so that the conduction time of the auxiliary charging path remains stable when the power supply voltage fluctuates, and the relative level of hysteresis immunity remains consistent within the normal operating power supply voltage range of the hysteresis comparison module and the reference voltage divider network.

[0037] In this embodiment, the reference voltage refers to the reference voltage generated by a voltage divider network connected between the power supply and ground, used for comparison with the timing capacitor voltage. The positive feedback impedance network refers to the impedance element connected between the output terminal of the hysteresis comparator module and the first input terminal; its width, together with the input impedance coupling the timing capacitor voltage to the first input terminal, determines the hysteresis window width. The hysteresis window refers to the voltage difference between the positive and negative flip thresholds, and its function is to suppress noise oscillations of the comparator near the flip thresholds. The relative level of hysteresis immunity refers to the ratio of the absolute value of the hysteresis window to the power supply voltage. When this ratio remains constant as the power supply voltage changes, it means that the hysteresis comparator module has a suppression capability for noise and interference of different amplitudes that is proportional to the power supply voltage.

[0038] In this embodiment, the reference voltage is generated by connecting two resistors in series between the power supply and ground, with the intermediate node providing the reference voltage. For example, the two resistors have equal resistance values, and the reference voltage is half the power supply voltage. The timing capacitor voltage is coupled to the first input terminal of the hysteresis comparator module via the input impedance, the reference voltage is coupled to the second input terminal, and the output terminal is coupled to the first input terminal via a positive feedback impedance network, forming a Schmitt trigger structure. Since the reference voltage is generated by a voltage divider network connected between the power supply and ground and has a fixed proportional relationship with the power supply voltage, and the flip threshold of the Schmitt trigger structure is proportional to the reference voltage, both the positive and negative flip thresholds maintain the same proportional relationship with the power supply voltage. For example, when the input impedance is 100kΩ, the positive feedback impedance network is 2MΩ, the power supply voltage is 12V, and the reference voltage is 6V, the positive flip threshold is approximately 6.3V, the negative flip threshold is approximately 5.7V, and the hysteresis window width is approximately 0.6V. When the power supply voltage changes from 10V to 14V, the hysteresis window changes accordingly from 0.5V to 0.7V, always maintaining 5% of the power supply voltage. The input of the hysteresis comparator module is only coupled to the timing capacitor voltage and the reference voltage, and there is no electrical connection or signal feedback path between it and the target capacitor. The conduction time is entirely determined by the RC charging process and the switching threshold of the timing network, and is not affected by the load characteristics, initial voltage, or voltage changes during the charging process of the target capacitor. It remains stable when the power supply voltage fluctuates, meaning that within the typical fluctuation range of the power supply voltage, the rate of change of the conduction time of the auxiliary charging path is much smaller than the rate of change of the power supply voltage, so that the conduction time is basically unaffected by the power supply voltage fluctuation.

[0039] This embodiment constructs a reference voltage with a fixed proportional relationship to the power supply voltage. Combined with the proportional characteristics of the Schmitt trigger structure, this allows the flip-flop threshold and hysteresis window to automatically follow changes in the power supply voltage, maintaining stable conduction time even during power supply voltage fluctuations, while simultaneously maintaining a consistent level of disturbance rejection capability. By coupling the input of the hysteresis comparator module only to the timing capacitor voltage and the reference voltage, the feedback loop with the target capacitor is severed, making timing control completely independent of the power link. This eliminates loop stability issues that may be introduced by closed-loop feedback, achieving precise open-loop timing control.

[0040] In one feasible implementation, in step S5, the voltage of the target capacitor during the turn-off is not higher than the steady-state voltage. This is achieved by matching the second equivalent impedance of the auxiliary charging path with the preset time constant of the timing network and the positive flip threshold of the hysteresis comparison module. The conduction duration of the auxiliary charging path is determined by the preset time constant and the positive flip threshold. The second equivalent impedance is determined based on the conduction duration, the capacitance of the target capacitor, and the steady-state voltage, so that the target capacitor is charged to a level not higher than the steady-state voltage within the conduction duration.

[0041] In this embodiment, the conduction duration refers to the time elapsed from the auxiliary charging path being turned on to the output flipping of the hysteresis comparator module and the auxiliary charging path being turned off. This duration is jointly determined by the preset time constant of the timing network and the forward flipping threshold. The second equivalent impedance matching refers to, based on the determined conduction duration, the capacitance value of the target capacitor, and the steady-state voltage value, deriving the upper limit of the equivalent impedance that allows the target capacitor to charge from the initial voltage to no more than the steady-state voltage within the conduction duration, and selecting or designing the equivalent impedance of the auxiliary charging path accordingly.

[0042] In this embodiment, the specific configuration method is as follows: the conduction duration is calculated based on the preset time constant and forward flip threshold of the timing network, and then the value of the second equivalent impedance is determined based on the capacitance and steady-state voltage of the target capacitor. Specifically, the conduction duration ton of the auxiliary charging path is determined by the preset time constant of the timing network. and forward flip threshold Sure: ,in This is the power supply voltage. During the conduction duration... Inside, the target capacitor passes through the second equivalent impedance. Charging, its voltage ,in This is the capacitance value of the target capacitor. The goal is to ensure that VC does not exceed the steady-state voltage during turn-off. , The value of should satisfy Preferably, The minimum value satisfying the above inequality is selected to obtain the fastest charging speed without exceeding the voltage limit. For example, when the initial voltage of the target capacitor is 0V, the time constant of the timing network is 20ms, the forward flip threshold is 52.5% of the supply voltage, the target capacitor is 10µF, and the steady-state voltage is 50% of the supply voltage, the conduction time is approximately 14.9ms. The equivalent resistance of the auxiliary charging path is configured to be approximately 2.2kΩ, so that the target capacitor voltage is slightly lower than the steady-state value when turned off, and is subsequently supplemented to the steady-state value by the steady-state voltage divider network. In other embodiments, the charging resistor in the auxiliary charging path can be an adjustable resistor to calibrate the charging termination voltage during production or debugging, overcoming the influence of component parameter dispersion.

[0043] It should be noted that the aforementioned effect of ensuring the target capacitor voltage is not higher than the steady-state voltage during shutdown is achieved under normal operating conditions where the target capacitor voltage is lower than the steady-state voltage when the charging start event is triggered. If the charging start event is mistakenly triggered when the target capacitor voltage is close to or has reached the steady-state voltage, the target capacitor voltage will exceed the steady-state value because the conduction duration of the auxiliary charging path is fixed by the timing network. In practical applications, the system controller should only issue a charging start event when the target capacitor voltage is lower than a set threshold.

[0044] This embodiment matches the second equivalent impedance of the auxiliary charging path with the preset time constant of the timing network and the positive flip threshold of the hysteresis comparison module. Based on the conduction time and the target capacitor parameters, the second equivalent impedance is determined so that the fast charging phase is precisely terminated when the target capacitor voltage is close to but does not exceed the steady-state value. This avoids voltage overshoot caused by excessively long fast charging conduction time under normal operating conditions. The final precise establishment is completed by the steady-state voltage divider network, achieving a balance between fast charging speed and voltage accuracy.

[0045] In one feasible implementation, it further includes: S6: In response to a discharge trigger signal independent of the charging start event, conduct an auxiliary discharge path connected in parallel with the target capacitor, wherein the equivalent impedance of the auxiliary discharge path is not greater than one-tenth of the equivalent impedance of the steady-state voltage divider network.

[0046] In step S6, the conduction and cutoff of the auxiliary discharge path are directly controlled by an independent discharge trigger signal. Its control link is electrically and logically independent from the control link of the auxiliary charging path, so that the charging and discharging operations can be triggered independently in any order without interference between the timing. The charging start event and the discharge trigger signal are both kept at an invalid level under normal conditions, and are only briefly switched to an effective level when fast charging or fast discharging is required. This ensures that during steady-state maintenance, both the auxiliary charging path and the auxiliary discharge path are in a turned-off state, and the voltage of the target capacitor is independently maintained by the steady-state voltage divider network.

[0047] In this embodiment, the discharge trigger signal refers to a control signal issued by the system controller to initiate rapid discharge, independent of the charging start event. The auxiliary discharge path refers to a low-impedance path connected in parallel with the target capacitor and conducted during the discharge phase; its equivalent impedance is much smaller than the equivalent impedance of the steady-state voltage divider network. The control links are electrically and logically independent, meaning that the on / off control signal chains of the auxiliary charging path and the auxiliary discharge path do not have signal multiplexing or interlocking relationships in physical wiring or control logic. An invalid level refers to a control signal level state that does not trigger the corresponding action, while an effective level refers to a control signal level state that triggers the corresponding action. Normal state refers to the time period during which the system is in a steady-state maintenance state and does not perform charging or discharging operations. Brief switching means that the control signal maintains an effective level only for the limited time required to perform charging or discharging, and returns to an invalid level for the rest of the time.

[0048] In this embodiment, the charging start event is transmitted to the forced reset module via the first control signal line, and the discharge trigger signal is transmitted to the switching element of the auxiliary discharge path via the second control signal line. The two signal lines are physically independent, and their respective control logic is independent within the controller. The system controller can independently determine the timing of the charging start event and the discharge trigger signal; the timing relationship between them is flexibly configured by the controller according to application requirements and is not limited by the circuit structure. The effective level of the charging start event is a high-level pulse with a pulse width of at least 1µs, used to trigger the forced reset module to complete the energy storage state reset of the timing capacitor. It then returns to a low level, and the timing network and hysteresis comparison module automatically complete the subsequent timing and fast charging control. The duration of the discharge trigger signal is determined by the time required for the target capacitor to discharge from the current voltage to the desired low level, which is determined by the product of the equivalent impedance of the auxiliary discharge path and the target capacitor. For example, when the equivalent resistance of the auxiliary discharge path is 2.2kΩ and the target capacitor is 10µF, the time required to discharge from 6V to 0.6V is approximately 50.6ms. The controller can maintain the effective level of the discharge trigger signal for approximately 55ms to ensure sufficient discharge. After discharge is complete, the discharge trigger signal returns to an invalid level, and the auxiliary discharge path is turned off. In the steady-state maintenance state, both the charging start event and the discharge trigger signal remain at a low level. The switching elements in the auxiliary charging path are in the off state, and the switching elements in the auxiliary discharge path are also in the off state. The voltage of the target capacitor is maintained only by the steady-state voltage divider network, without introducing any additional power consumption path.

[0049] This embodiment achieves rapid discharge by configuring an auxiliary discharge path independent of the charging path, thus freeing the target capacitor's discharge speed from the high-impedance steady-state voltage divider network. By completely decoupling the discharge control link from the charging control link electrically and logically, charging and discharging operations can be triggered independently in any order without interference. By designing the control signal as a pulse-triggered mode that is normally inactive and transiently active, it ensures that the auxiliary charging and discharging paths only operate briefly when needed and completely deactivate in steady state, with the steady-state voltage divider network independently maintaining the target capacitor voltage. This achieves a function separation strategy of on-demand wake-up, minimizing the additional impact on steady-state power consumption and voltage accuracy.

[0050] In one feasible implementation, the method further includes: configuring a voltage clamping mechanism across the target capacitor, wherein the conduction threshold of the voltage clamping mechanism is higher than the steady-state voltage, and a discharge path is provided only when the voltage of the target capacitor exceeds the conduction threshold to limit the voltage peak. During steady-state operation, the mechanism is in a non-conducting state and does not increase the steady-state power consumption.

[0051] In this embodiment, the voltage clamping mechanism refers to a protection circuit connected in parallel across the target capacitor that conducts when the voltage exceeds a preset threshold to limit the voltage amplitude. The conduction threshold is the critical voltage value at which the voltage clamping mechanism begins to conduct; its set value is higher than the steady-state voltage of the target capacitor to ensure that the voltage clamping mechanism is in a non-conducting state during normal steady-state operation.

[0052] In this embodiment, the voltage clamping mechanism is implemented using a Zener diode. The cathode of the Zener diode is connected to the upper end of the target capacitor, and the anode is grounded. The breakdown voltage of the Zener diode is selected to be slightly higher than the steady-state voltage. For example, when the steady-state voltage is 6V, a Zener diode with a breakdown voltage of 7.5V is selected. When the voltage of the target capacitor exceeds 7.5V due to power-on instantaneously or abnormal circuit fluctuations, the Zener diode breaks down and conducts, discharging the excess charge to ground and limiting further increases in the voltage of the target capacitor. During steady-state operation, the voltage of the target capacitor remains at 6V, which is lower than the breakdown voltage of the Zener diode. The Zener diode is in reverse cutoff mode, and the leakage current is in the nanoamp level, without adding extra steady-state power consumption.

[0053] This embodiment provides overvoltage protection for subsequent circuits without affecting normal steady-state operation by configuring a voltage clamping mechanism with a conduction threshold higher than the steady-state voltage across the target capacitor, thereby improving the reliability of the system.

[0054] like Figure 2 As shown, in one feasible embodiment, a circuit is provided to improve the slope of the capacitor charging and discharging voltage waveform to implement the above method, comprising: Target capacitance; A steady-state voltage divider network is connected between the power supply and ground, with its intermediate node connected to the first end of the target capacitor and having a first equivalent impedance; An auxiliary charging path is connected between the power supply and the first terminal of the target capacitor, and its equivalent impedance is no more than one-tenth of the equivalent impedance of the steady-state voltage divider network. An auxiliary discharge path is connected in parallel with the target capacitor. Its equivalent impedance is no more than one-tenth of the equivalent impedance of the steady-state voltage divider network. Its conduction and cutoff are controlled by a discharge trigger signal independent of the charging start event. A timing network includes a timing resistor and a timing capacitor connected in series. One end of the timing resistor is connected to a power supply, and one end of the timing capacitor is grounded. The connection node of the two outputs a timing voltage. A forced reset module, connected in parallel with the timing capacitor, has a control input terminal for receiving a reset signal, and is used to reset the voltage of the timing capacitor to a preset initial level in response to the reset signal; A reference voltage divider network, connected between the power supply and ground, is used to provide a reference voltage that is in a fixed proportion to the power supply voltage. The hysteresis comparison module includes a comparator, an input resistor, and a positive feedback resistor. The non-inverting input of the comparator is coupled to the timing voltage via the input resistor, the inverting input receives the reference voltage, and the output is coupled to the non-inverting input via the positive feedback resistor to form a Schmitt trigger structure. The auxiliary charging path has a control terminal, which is coupled to the output terminal of the hysteresis comparison module, so that the conduction and cutoff of the auxiliary charging path are controlled by the output terminal of the hysteresis comparison module. The input of the hysteresis comparator module is coupled only to the timing voltage and the reference voltage, and does not sample the voltage of the target capacitor. There is no feedback loop between the hysteresis comparator module and the target capacitor. The equivalent impedance of the auxiliary charging path is configured to match the preset time constant of the timing network and the positive flip threshold of the hysteresis comparator module. The conduction duration of the auxiliary charging path is determined by the preset time constant and the positive flip threshold. The equivalent impedance of the auxiliary charging path is determined based on the conduction duration, the capacitance of the target capacitor, and the steady-state voltage maintained across the target capacitor by the steady-state voltage divider network, so that the target capacitor is charged to a level not higher than the steady-state voltage within the conduction duration.

[0055] In this embodiment, the steady-state voltage divider network refers to a circuit network consisting of at least two impedance elements connected in series between the power supply and ground, outputting a voltage divider from an intermediate node. The equivalent resistance at that node is the first equivalent impedance. The auxiliary charging path refers to a circuit branch that, when in the on-state, can provide a low-impedance charging path from the power supply to the target capacitor. The timing network refers to an RC series charging circuit composed of a timing resistor and a timing capacitor. One end of the timing resistor is connected to the power supply, and one end of the timing capacitor is grounded. The voltage at the connection node increases exponentially. The forced reset module refers to a controlled switch circuit connected in parallel with the timing capacitor. When a reset signal is received, it turns on, shorting the two ends of the timing capacitor to ground to achieve voltage reset. The reference voltage divider network refers to a voltage divider circuit that generates a DC reference voltage that maintains a fixed proportional relationship with the power supply voltage. The hysteresis comparison module refers to a voltage comparison function unit with two different flip thresholds, whose output signal is used to control the on / off state of the auxiliary charging path.

[0056] In this embodiment, the overall operation of the circuit is as follows: During the steady-state maintenance phase, the auxiliary charging path is off, and the voltage of the target capacitor is determined by the voltage division ratio of the steady-state voltage divider network. When fast charging is required, the system controller sends a reset signal, forcing the reset module to turn on and resetting the voltage across the timing capacitor to ground potential. After the reset, the timing capacitor voltage is lower than the negative flip threshold of the hysteresis comparator module. The hysteresis comparator module outputs a first logic signal to control the auxiliary charging path to turn on, and the power supply injects a large current into the target capacitor through the low-impedance auxiliary charging path to achieve fast charging. After the reset signal is removed, the timing capacitor begins to charge through the timing resistor, and the timing voltage rises from zero. The hysteresis comparator module maintains the output of the first logic signal, and the auxiliary charging path remains on. When the timing voltage rises to the positive flip threshold, the hysteresis comparator module outputs a flip signal to the second logic signal, controlling the auxiliary charging path to turn off. The target capacitor is then maintained at a steady-state voltage by the steady-state voltage divider network. Throughout the entire process, the hysteresis comparator module only collects the timing voltage and reference voltage, and there is no feedback loop between it and the target capacitor.

[0057] It should be noted that upon initial power-up, the timing capacitor's initial voltage is zero, and the voltage at the non-inverting input of the hysteresis comparator module is lower than the reference voltage. The comparator outputs the first logic signal, automatically activating the auxiliary charging path and initiating rapid charging of the target capacitor. This automatic fast charging behavior upon power-up allows the target capacitor to quickly build up to near-steady-state voltage after power-up, without waiting for the controller to issue a charging start event, thus shortening the system's initial readiness time. After the initial fast charging is complete, the timing capacitor has charged to the power supply voltage, and the auxiliary charging path is turned off. Subsequent fast charging requires a reset signal from the controller to trigger it.

[0058] This embodiment constructs a circuit with a functional separation architecture, which physically and temporally separates the control of the high-impedance steady-state voltage divider network and the low-impedance auxiliary charging path. At the same time, it uses a timing network and hysteresis comparison module independent of the target capacitor to achieve precise open-loop timing shutdown, which solves the contradiction between steady-state power consumption and charging speed in traditional voltage divider circuits and realizes rapid voltage establishment under low-power steady-state operation.

[0059] like Figure 3As shown, in one feasible implementation, a specific implementation structure of the above circuit is provided. The upper end of the first resistor R1 is connected to the power supply, the lower end of the first resistor R1 and the upper end of the second resistor R2 are connected to the first node, the lower end of the second resistor R2 is grounded, the first node is connected to the upper end of the first capacitor C1, and the lower end of the first capacitor C1 is grounded. The upper end of the third resistor R3 is connected to the power supply, the lower end of the third resistor R3 and the upper end of the second capacitor C2 are connected to the second node, the lower end of the second capacitor C2 is grounded, and the second node outputs a timing voltage. The drain of the first switching transistor Q1 is connected to the second node, the source of the first switching transistor Q1 is grounded, and the gate of the first switching transistor Q1 is connected to the first control signal line CTRL1. The upper end of the fourth resistor R4 is connected to the power supply, the lower end of the fourth resistor R4 and the upper end of the fifth resistor R5 are connected to the third node, the lower end of the fifth resistor R5 is grounded, and the third node provides a reference voltage. The non-inverting input of comparator U1 is connected to the second node via the eleventh resistor Rin, and the inverting input is connected to the third node. The output of comparator U1 is connected to the non-inverting input via the tenth resistor R10, and the output is also connected to the power supply via the sixth resistor R6. The output of comparator U1 is connected to the base of the second switching transistor Q2 via the seventh resistor R7. The emitter of the second switching transistor Q2 is connected to the power supply, and the collector of the second switching transistor Q2 is connected to the first node via the eighth resistor R8. The drain of the third switching transistor Q3 is connected to the first node via the ninth resistor R9, the source of the third switching transistor Q3 is grounded, and the gate of the third switching transistor Q3 is connected to the second control signal line CTRL2. The cathode of the clamping transistor DZ is connected to the first node, and the anode of the clamping transistor DZ is grounded. The above circuit integrates functions such as fast charging, fast discharging, and voltage clamping. The auxiliary discharge path and voltage clamping mechanism are optional configurations, and their connection or disconnection does not affect the realization of the basic charging function of the circuit.

[0060] In this embodiment, the first resistor R1 is a pull-up resistor, and the second resistor R2 is a pull-down resistor. Together, they form a steady-state voltage divider network, with an exemplary resistance of 1MΩ, providing half of the power supply voltage to the first node in a steady-state voltage division, resulting in a steady-state current of approximately 6µA. The third resistor R3 is a timing resistor, with an exemplary resistance of 100kΩ, and the second capacitor C2 is a timing capacitor, with an exemplary capacitance of 0.2µF. Together, they form a timing network with a time constant of approximately 20ms. The first switch Q1 is an N-channel MOSFET, serving as the execution element of the forced reset module. In its on-state, it directly shorts the second node to ground, with an on-resistance of less than 50mΩ. An exemplary model is AO3400. The fourth resistor R4 and the fifth resistor R5 form a reference voltage divider network, providing half of the power supply voltage as a reference voltage. For example, when both are 100kΩ, the steady-state current of this branch is approximately 60µA; to further reduce the total steady-state power consumption to match the low-power design goal, it is preferable to use 1MΩ for both, at which point the steady-state current of this branch can be reduced to approximately 6µA. Comparator U1 is an open-drain output comparator, exemplarily an LMC7221, with a supply range of 2.7V to 15V and a typical quiescent current of 10µA. The eleventh resistor, Rin, is the input resistor, exemplarily 100kΩ, and the tenth resistor, R10, is the positive feedback hysteresis resistor, exemplarily 2MΩ. Together with comparator U1, they form a Schmitt trigger structure. The sixth resistor, R6, is the pull-up resistor at the output of comparator U1, exemplarily 10MΩ. To compensate for the turn-off delay that might be introduced by the high pull-up resistance, the second equivalent impedance of the auxiliary charging path can be appropriately increased (e.g., adjusting the eighth resistor R8 from 2.2kΩ to 2.4kΩ) to provide a turn-off margin, ensuring that the voltage across the target capacitor during turn-off does not exceed the steady-state voltage. The second switch, Q2, is a PNP transistor, exemplarily an MMBT3906, with a saturation on-state voltage drop of less than 0.2V. The seventh resistor R7 is the base current limiting resistor for the second switch Q2, with an exemplary value of 10kΩ. The eighth resistor R8 is the charging resistor, with an exemplary value of 2.2kΩ. Together with the second switch Q2, they form an auxiliary charging path. The third switch Q3 is an N-channel MOSFET, with an exemplary model AO3400. The ninth resistor R9 is the discharging resistor, with an exemplary value of 2.2kΩ. Together, they form an auxiliary discharging path. The clamping transistor DZ is a Zener diode with an exemplary breakdown voltage of 7.5V. The first capacitor C1 is the target capacitor with an exemplary capacitance of 10µF. The power supply voltage is an exemplary 12V, and the steady-state voltage is 6V.

[0061] In this embodiment, the circuit operates as follows: During the steady-state maintenance phase, both the first control signal line CTRL1 and the second control signal line CTRL2 remain at a low level, and both the first switch Q1 and the third switch Q3 are turned off. The second capacitor C2 is fully charged to the power supply voltage through the third resistor R3, and the voltage at the second node is approximately 12V. This voltage is coupled to the non-inverting input of comparator U1 through the eleventh resistor Rin, which is much higher than the reference voltage of 6V. Comparator U1 outputs a high level, and the emitter junction voltage of the second switch Q2 is zero, ensuring reliable cutoff. The voltage of the first capacitor C1 is determined by the voltage division of the first resistor R1 and the second resistor R2, and is maintained at 6V. When fast charging is required, the controller sends a positive pulse to the first control signal line CTRL1, turning on the first switch Q1. The second capacitor C2 instantly discharges to zero, and the voltage at the second node drops to 0V. The non-inverting input of comparator U1 is grounded through the eleventh resistor Rin, which is lower than the reference voltage, and the output of comparator U1 flips to a low level. The base of the second switch Q2 is pulled low via the seventh resistor R7, forward biasing the emitter junction. Q2 is saturated and conducting, and power is rapidly charging the first capacitor C1 via Q2 and the eighth resistor R8. After the first control signal line CTRL1 returns to low, Q1 is turned off, and the third resistor R3 begins charging the second capacitor C2, causing the second node voltage to rise exponentially. When the second node voltage reaches the forward flip threshold, the comparator U1 output flips to high, Q2 turns off, and the rapid charging ends. The first capacitor C1 is then slowly replenished to 6V via the first resistor R1. When rapid discharge is needed, the controller sends a positive pulse to the second control signal line CTRL2, turning on the third switch Q3. The first capacitor C1 rapidly discharges to ground via the ninth resistor R9 and the third switch Q3. If the first node voltage exceeds 7.5V due to an abnormality, the clamping transistor DZ breaks down and conducts, clamping the voltage within a safe range.

[0062] In actual mass production, factors such as the parameter tolerances of the third resistor R3 and the second capacitor C2, the proportional error of the reference voltage divider network R4 / R5, and the input offset of the comparator U1 can all cause the preset time constant and forward flip threshold of the timing network to deviate from the design nominal value, thus causing a distributed drift in the conduction duration of the auxiliary charging path. To suppress the impact of this drift on the consistency of the target capacitor voltage at the turn-off moment, in addition to using an adjustable resistor for the eighth resistor R8 in the auxiliary charging path, the third resistor R3 and / or the fourth resistor R4 and fifth resistor R5 in the reference voltage divider network can be further configured as adjustable (e.g., laser adjustment, fuse adjustment, or digital potentiometer). By calibrating both the conduction duration determination side and the charging rate side, the voltage of the target capacitor when the auxiliary charging path is turned off under mass production conditions can be precisely controlled within the range that does not exceed the steady-state voltage. Even if the target capacitor voltage slightly exceeds the steady-state value at the moment of shutdown due to extreme operating conditions, the charging circuit formed by the first resistor R1 and the first capacitor C1 in the steady-state voltage divider network will continue to replenish the charge to the first capacitor C1. At the same time, the clamping transistor DZ can provide a discharge path when there is overvoltage. The two work together to bring the target capacitor voltage back to the steady-state nominal value within several steady-state time constants, without affecting the normal operation of the subsequent circuit.

[0063] It should be noted that when the system is first powered on, the initial voltage of the second capacitor C2 is zero, the voltage at the non-inverting input of comparator U1 is lower than the reference voltage, comparator U1 outputs a low level, and the second switch Q2 automatically turns on to perform fast charging of the first capacitor C1. This automatic fast charging behavior upon power-on allows the first capacitor C1 to quickly build up to a near-steady-state voltage after power-on, without waiting for the controller to send a reset pulse on the first control signal line CTRL1, which helps to shorten the system's initial readiness time. After the initial fast charging is completed, the second capacitor C2 has been charged to the power supply voltage, comparator U1 outputs a high level, and the second switch Q2 turns off. Subsequent fast charging requires a reset pulse from the controller via the first control signal line CTRL1. If the power supply voltage rises at a relatively gentle rate in the application scenario, a power supply voltage detection circuit can be added before the first control signal line CTRL1. This circuit releases the charging start event only after the power supply voltage enters the guaranteed operating range of comparator U1, preventing malfunctions in the auxiliary charging path due to the comparator's uncertain output state during low power supply voltage phases.

[0064] In the above embodiments, the conduction time of the auxiliary charging path is determined by the timing network parameters and is on the order of milliseconds. If it is necessary to further shorten the conduction time to the order of microseconds in a specific application, the resistance value of the sixth resistor R6 can be appropriately reduced to reduce the charging time constant of the second capacitor C2 through the tenth resistor R10 when the output of comparator U1 flips from low to high, making the flip edge of the hysteresis comparator module steeper and meeting the timing accuracy requirements at higher speeds; or a push-pull output comparator can be used to replace the open-drain output comparator U1, fundamentally eliminating the constraint of the pull-up resistor on the flip edge.

[0065] It should also be noted that the charging current of the second capacitor C2, in addition to coming from the third resistor R3, also includes a weak bypass current through the eleventh resistor Rin and the tenth resistor R10. This current has a negligible effect of less than 5% on the charging time constant of the second capacitor C2. Since the resistance of the tenth resistor R10 is much larger than that of the third resistor R3, the shunt effect on the charging time constant is within 5%, which is within an acceptable engineering approximation range. If higher precision timing control is required, this shunt effect can be included in the calculation during parameter design. Furthermore, when the second capacitor C2 is charged to near the power supply voltage, the voltage at the non-inverting input of comparator U1 may exceed its guaranteed input common-mode range. However, at this time, the comparator has already output a high level, the auxiliary charging path has been turned off, and this state does not affect the normal operation of the circuit. If a wider margin of input common-mode range is required, a rail-to-rail input comparator can be used instead. In another preferred embodiment, the eighth resistor R8 can be an adjustable resistor to calibrate the charging termination voltage during production or commissioning, overcome the influence of component parameter dispersion, and ensure that the voltage of the target capacitor does not exceed the steady-state voltage when the auxiliary charging path is turned off.

[0066] In steady-state operation, both the auxiliary charging and discharging paths are off. The total steady-state power consumption of the system consists of a steady-state voltage divider network, a reference voltage divider network, a hysteresis comparator module, and its pull-up resistors. For example, when the first resistor R1 and the second resistor R2 are both 1MΩ and the power supply voltage is 12V, the current of the steady-state voltage divider network is approximately 6µA; when the fourth resistor R4 and the fifth resistor R5 are both 1MΩ, the current of the reference voltage divider network is approximately 6µA; when comparator U1 is an LMC7221 (open-drain output, typical quiescent current 10µA), the sixth resistor R6 is 10MΩ, and its pull-up current is approximately 1.2µA. Combined, the total steady-state current can be controlled in the tens of microamps range (approximately 23.2µA in the example), and the total steady-state power consumption is approximately several hundred microwatts (approximately 278µW in the example), meeting the design requirements for low-power steady-state operation.

[0067] In another implementation, to achieve better dynamic characteristics, comparator U1 can be replaced with a push-pull output type low-power comparator (such as the LMC7211, TLV7031, MAX40000, or other rail-to-rail push-pull output models from the same series), thus eliminating the need for the sixth resistor R6. This approach not only further eliminates the steady-state current of the pull-up resistor, but also allows the push-pull output structure to actively drive the output when it transitions from low to high, resulting in an extremely short turn-off delay. This avoids the edge smoothing problem that may be introduced by high-value pull-up resistors, achieving better dynamic characteristics while maintaining low power consumption.

[0068] This embodiment achieves functional decoupling between steady-state power consumption and charge / discharge speed by constructing the specific circuit using all general-purpose discrete components. The total steady-state current can be as low as tens of microamps, and the charge / discharge settling time can be shortened from tens of seconds to tens of milliseconds. It also boasts comprehensive performance advantages such as high timing accuracy and good consistency between continuous power-on and power-off cycles. Furthermore, the optional discharge and clamping modules further enhance the scalability and reliability of the solution.

[0069] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A method for improving the slope of a capacitor charging and discharging voltage waveform, characterized in that, include: S1: A stable DC voltage is established and maintained across the target capacitor through a steady-state voltage divider network with a first equivalent impedance; S2: Under the condition that the steady-state voltage divider network maintains the DC voltage, in response to the charging start event, the energy storage state is reset for the timing capacitor set independently of the target capacitor, triggering the hysteresis comparison module to output the first logic signal; wherein, before the charging start event is triggered, the target capacitor is in a preset initial voltage state; S3: During the first logic signal output period, the reset constraint on the timing capacitor is released, so that the timing capacitor is continuously charged based on the preset time constant of the timing network, and the target capacitor is fast charged through an auxiliary charging path with a second equivalent impedance, wherein the second equivalent impedance is not greater than one-tenth of the first equivalent impedance. S4: During the fast charging process of the target capacitor, the voltage of the timing capacitor is monitored for a threshold. Before the voltage of the timing capacitor rises to the positive flip threshold, the first logic signal is maintained to keep the auxiliary charging path on, and the timing control is decoupled from the charging power link of the target capacitor. S5: When the voltage of the waiting capacitor rises to the positive flip threshold, the hysteresis comparison module outputs a second logic signal to turn off the auxiliary charging path, and the steady-state voltage divider network continues to maintain the steady-state voltage of the target capacitor; wherein, the conduction time of the auxiliary charging path is configured such that, when the initial voltage of the target capacitor is lower than the steady-state voltage, the voltage of the target capacitor is not higher than the steady-state voltage when it is turned off.

2. The method according to claim 1, characterized in that, In step S2, resetting the energy storage state of the timing capacitor specifically includes: S21: In response to the charging start event, generate a reset pulse of a preset width; S22: Based on the reset pulse, control the low-impedance discharge path to be turned on, connect the non-grounded terminal of the timing capacitor to ground potential, eliminate the residual charge of the previous working cycle, and keep the initial level of the timing capacitor consistent before each charging start.

3. The method according to claim 2, characterized in that, In step S22, the discharge time constant of the low-impedance discharge path in the conducting state is not greater than one-tenth of the charging time constant of the timing network, and the width of the reset pulse ensures that the voltage across the timing capacitor is completely discharged to the preset initial level.

4. The method according to claim 1, characterized in that, In step S4, the threshold monitoring of the voltage of the timing capacitor specifically includes: S41: A reference voltage is generated by a voltage divider network connected between the power supply and ground, and the reference voltage is proportional to the power supply voltage. S42: Couple the voltage of the timing capacitor to the first input terminal of the hysteresis comparator module, and couple the reference voltage to the second input terminal of the hysteresis comparator module; S43: The output of the hysteresis comparator module is coupled to the first input terminal through a positive feedback impedance network to form a Schmitt trigger structure, so that the hysteresis comparator module has different positive and negative flip thresholds, and the flip thresholds change proportionally with the reference voltage.

5. The method according to claim 4, characterized in that, The input of the hysteresis comparison module is coupled only to the voltage of the timing capacitor and the reference voltage. There is no feedback loop between it and the target capacitor, so that the conduction time of the auxiliary charging path is independently determined by the charging process of the timing network and is not affected by the charging state of the target capacitor.

6. The method according to claim 4, characterized in that, The absolute values ​​of the positive flip threshold, negative flip threshold, and hysteresis window are all proportional to the power supply voltage, so that the conduction time of the auxiliary charging path remains stable when the power supply voltage fluctuates, and the relative level of hysteresis immunity remains consistent across the entire power supply voltage range.

7. The method according to claim 1, characterized in that, In step S5, the voltage of the target capacitor during the turn-off is not higher than the steady-state voltage. This is achieved by matching the second equivalent impedance of the auxiliary charging path with the preset time constant of the timing network and the positive flip threshold of the hysteresis comparison module. The conduction duration of the auxiliary charging path is determined by the preset time constant and the positive flip threshold. The second equivalent impedance is determined based on the conduction duration, the capacitance of the target capacitor, and the steady-state voltage, so that the target capacitor is charged to a level not higher than the steady-state voltage within the conduction duration.

8. The method according to claim 1, characterized in that, Also includes: S6: In response to a discharge trigger signal independent of the charging start event, conduct an auxiliary discharge path connected in parallel with the target capacitor, wherein the equivalent impedance of the auxiliary discharge path is not greater than one-tenth of the equivalent impedance of the steady-state voltage divider network.

9. The method according to claim 8, characterized in that, In step S6, the conduction and cutoff of the auxiliary discharge path are directly controlled by an independent discharge trigger signal. Its control link is electrically and logically independent from the control link of the auxiliary charging path, so that the charging and discharging operations can be triggered independently in any order without interference between the timing. The charging start event and the discharge trigger signal are both kept at an invalid level under normal conditions, and are only briefly switched to an effective level when fast charging or fast discharging is required. This ensures that during steady-state maintenance, both the auxiliary charging path and the auxiliary discharge path are in a turned-off state, and the voltage of the target capacitor is independently maintained by the steady-state voltage divider network.

10. A circuit for increasing the slope of a capacitor charging and discharging voltage waveform, used to implement the method described in any one of claims 1 to 9, characterized in that, include: Target capacitance; A steady-state voltage divider network is connected between the power supply and ground, with its intermediate node connected to the first end of the target capacitor and having a first equivalent impedance; An auxiliary charging path is connected between the power supply and the first terminal of the target capacitor, and its equivalent impedance is no more than one-tenth of the equivalent impedance of the steady-state voltage divider network. An auxiliary discharge path is connected in parallel with the target capacitor. Its equivalent impedance is no more than one-tenth of the equivalent impedance of the steady-state voltage divider network. Its conduction and cutoff are controlled by a discharge trigger signal independent of the charging start event. A timing network includes a timing resistor and a timing capacitor connected in series. One end of the timing resistor is connected to a power supply, and one end of the timing capacitor is grounded. The connection node of the two outputs a timing voltage. A forced reset module, connected in parallel with the timing capacitor, has a control input terminal for receiving a reset signal, and is used to reset the voltage of the timing capacitor to a preset initial level in response to the reset signal; A reference voltage divider network, connected between the power supply and ground, is used to provide a reference voltage that is in a fixed proportion to the power supply voltage. The hysteresis comparison module includes a comparator, an input resistor, and a positive feedback resistor. The non-inverting input of the comparator is coupled to the timing voltage via the input resistor, the inverting input receives the reference voltage, and the output is coupled to the non-inverting input via the positive feedback resistor to form a Schmitt trigger structure. The auxiliary charging path has a control terminal, which is coupled to the output terminal of the hysteresis comparison module, so that the conduction and cutoff of the auxiliary charging path are controlled by the output terminal of the hysteresis comparison module. The input of the hysteresis comparator module is coupled only to the timing voltage and the reference voltage, and does not sample the voltage of the target capacitor. There is no feedback loop between the hysteresis comparator module and the target capacitor. The equivalent impedance of the auxiliary charging path is configured to match the preset time constant of the timing network and the positive flip threshold of the hysteresis comparator module. The conduction duration of the auxiliary charging path is determined by the preset time constant and the positive flip threshold. The equivalent impedance of the auxiliary charging path is determined based on the conduction duration, the capacitance of the target capacitor, and the steady-state voltage maintained across the target capacitor by the steady-state voltage divider network, so that the target capacitor is charged to a level not higher than the steady-state voltage within the conduction duration.

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