A photovoltaic inverter PV common SPS intermittent switching power supply control method

Abstract

The application relates to the technical field of power distribution circuit device, and discloses a photovoltaic inverter PV shared SPS intermittent switching power supply control method, which comprises the following steps: connecting an isolated switching power supply input end with a photovoltaic direct current and a rectified commercial power channel and supplying power to an auxiliary power supply; cutting off energy transmission to run in a low-power consumption working condition when the battery voltage is higher than a wake-up reference and there is no grid-connected instruction; latching a suspended shutdown cancellation instruction when the voltage drops to the reference; releasing a signal to restart a power switch tube at a ripple bottom angle based on a commercial power zero crossover point, the application dynamically compensates a wake-up threshold according to a voltage discharge rate, smooths power supply rail fluctuation, eliminates a low-voltage bus transient undershoot to maintain power supply continuity; locks a restart in a ripple valley low stress interval, reduces impact current and weakens device commutation thermal stress.

Description

Technical Field

[0001] This invention relates to the field of power supply and distribution circuit technology, specifically to a method for controlling the intermittent switching of power supply between photovoltaic inverters and shared SPS. Background Technology

[0002] In current multi-source complementary power distribution systems with diversified photovoltaic DC high-voltage input and grid-side AC power supply, configuring multi-input switching power supplies to provide low-voltage DC regulated power to the secondary-side control board, sampling circuit, and drive network is a common method to ensure the operation of the inverter topology. The general architecture relies on the multi-winding electromagnetic coupling of the isolation transformer in conjunction with the secondary voltage regulation closed loop to convert the high-transient-fluctuation input source into a stable independent voltage output rail. With increasing demands for reduced standby power consumption and improved power distribution efficiency, switching power supply circuits adopt intermittent switching control schemes to reduce resting losses. However, in multi-source... During alternating power supply switching, the energy build-up time of the front-end topology generation circuit lags, and the secondary load exhibits a sudden jump state. This causes the static hysteresis comparison triggering method to fail to match the energy storage discharge slope, resulting in a momentary drop in the low-voltage rail voltage during the power restart transient phase. This endangers the sampling accuracy and causes a secondary undervoltage lockout anomaly. At the same time, the grid-side rectified DC bus is accompanied by a power frequency double-frequency ripple. If the power switching transistor is blindly turned on in the peak range of the ripple voltage, the device will be subjected to a high current spike and voltage change rate, which is more likely to trigger the transient overcurrent protection of the control chip and cause the auxiliary power supply to be interrupted.

[0003] To suppress the aforementioned voltage drops and turn-on surges, common practices tend to increase the capacitance of the secondary filter capacitor or improve the voltage rating of the switching transistor. However, such linear superposition of increasing device physical specifications not only increases hardware cost and space but also leads to deterioration in power loss due to increased equivalent series resistance of the capacitor and increased leakage current. This fails to decouple the inherent conflict between low-power operation and dynamic response at the control logic level. Simply relying on external hardware parameters is insufficient to completely eliminate transient drops, and existing control strategies also have shortcomings in their logic architecture for handling multi-source switching. For example, Chinese invention patent application CN106059280A discloses a photovoltaic inverter auxiliary... The auxiliary power supply and start-stop control method introduces the rectifier branch of the grid supply and uses a static hysteresis comparator to perform static threshold comparison of the photovoltaic module voltage to determine the start-stop of the auxiliary power supply. However, in the case of multi-source complementary operation including independent power supply of downstream energy storage batteries and sudden load jumps, the static voltage preset mechanism implicitly relied on by this scheme cannot dynamically shift the start-up boundary with the change of load energy consumption rate. Under the constraint of energy build-up time lag, it still cannot eliminate the transient downsurge of the low-voltage power supply rail. Moreover, this strategy fails to establish a coordinated clamping mechanism between the restart timing of the switching power transistor and the phase of the double-frequency ripple of the grid-side DC bus, which makes the current-voltage stress of the device too high when the converter restarts, or even triggers the overcurrent false protection.

[0004] Therefore, the technical problem to be solved by this invention is to utilize the input voltage evolution characteristics and ripple phase coordination relationship under the multiple input source alternating switching conditions to dynamically shift and restore the power supply voltage trigger threshold and lock the converter enable signal in the low stress range of rectification, so as to avoid transient undercurrent and overcurrent impact of re-ignition excitation and maintain continuous power supply under intermittent power supply. Summary of the Invention

[0005] To address the problems in the background art, this invention proposes a method for controlling intermittent switching power supply of a photovoltaic inverter using a shared SPS, comprising the following steps: Step S101: Electrically connect the input terminal of the isolated switching power supply to the photovoltaic DC input channel and the AC mains input channel after rectification by the body diode of the inverter full-bridge power switch tube, and make the output terminal of the isolated switching power supply supply power to the secondary auxiliary power supply containing the battery. When it is detected that the current voltage of the battery is higher than the predictive wake-up reference voltage and the photovoltaic inverter has no grid connection command, the power transmission path from the front-end DC high-voltage bus to the secondary auxiliary power supply is cut off through the soft turn-off circuit of the switching tube, so that the isolated switching power supply is degraded to the intermittent quiet low power consumption condition. Step S102: The current voltage of the battery and the AC voltage of the grid side collected by the grid side voltage sampling transformer are obtained by the microprocessor. The current voltage is compared with the predictive wake-up reference voltage. When the current voltage drops to the predictive wake-up reference voltage, the turn-off cancellation command originally applied to the soft turn-off circuit of the switching transistor is latched and suspended. Step S103: The voltage comparator is used to capture the AC mains zero-crossing point of the grid-side AC voltage. After the grid-side AC voltage is detected to cross the AC mains zero-crossing point, the delay time is calculated. When the delay time reaches the valley electrical angle of the rectified ripple of the front-stage DC high-voltage bus, a low-level enable signal is released to the isolation optocoupler in the soft turn-off circuit of the switching transistor, so that the isolation optocoupler is transiently cut off, and the enable terminal potential of the pulse width modulation control chip is restored to the working high level, and the drive pulse sequence of the inverter full-bridge power switching transistor is restarted.

[0006] Preferably, the step of obtaining the predictive wake-up reference voltage in step S102 includes the following steps: step S1021, obtaining the loop response time compensation constant of the isolated switching power supply conversion circuit and the real-time drop rate of the battery voltage in the intermittent resting low power consumption condition; step S1022, multiplying the loop response time compensation constant by the real-time drop rate to calculate the transient drop of the low voltage power supply rail.

[0007] Preferably, step S101, which electrically connects the input terminal of the isolated switching power supply to the photovoltaic DC input channel and the AC mains input channel rectified by the inverter full-bridge power switch diodes, includes the following steps: Step S1011, using the inverter full-bridge power switch diodes to build an uncontrolled rectified topology path for the AC input; Step S1012, using the normally closed relay contacts and current-limiting resistors in the mains soft-start circuit to perform voltage division and limitation, connecting the rectified DC power and the photovoltaic DC input channel in parallel to the front-end DC high-voltage bus to supply power to the isolated switching power supply.

[0008] Preferably, the step of latching and suspending the turn-off cancellation instruction originally applied to the soft turn-off circuit of the switching transistor in step S102 includes the following steps: Step S1024, when the current voltage meets the preset turn-off threshold, output a high-level turn-off signal through the microprocessor; Step S1025, transmit the high-level turn-off signal to the isolation optocoupler in the soft turn-off circuit of the switching transistor, drive the transistor inside the isolation optocoupler to saturate and conduct, and pull down the enable terminal potential of the pulse width modulation control chip.

[0009] Preferably, the step of capturing the AC mains zero-crossing point of the grid-side AC voltage using a voltage comparator in step S103 includes the following steps: step S1031, obtaining a sinusoidal AC full-wave signal using a grid-side voltage sampling transformer; step S1032, inputting the sinusoidal AC full-wave signal to a voltage comparator to capture the positive and negative polarity crossover points of the sinusoidal AC full-wave signal in order to determine the AC mains zero-crossing point.

[0010] Preferably, the step of releasing the turn-off cancellation command when the delay time reaches the valley electrical angle of the rectified ripple of the preceding DC high-voltage bus includes the following steps: Step S1033, obtaining the grid-side power frequency of the AC mains input channel; Step S1034, determining a rectified ripple period twice the power frequency based on the grid-side power frequency; Step S1035, taking the AC mains zero-crossing point as the time starting point, delaying by 1 / 4 of the rectified ripple period to lock the voltage minimum phase of the preceding DC high-voltage bus.

[0011] Preferably, the delay time is configured as a value obtained by dividing 1 by 4 times the grid-side power frequency.

[0012] Preferably, the step of supplying power from the output of a single isolated switching power supply to a secondary auxiliary power supply containing a battery in step S101 includes the following steps: Step S1013, implementing high and low voltage graded electrical isolation for the electrical energy input to the isolated switching power supply through a multi-stage isolation transformer topology; Step S1014, constructing a voltage regulation loop using an optocoupler negative feedback network to output the adjusted DC voltage to the secondary auxiliary power supply.

[0013] Preferably, the step of calculating the delay time in step S103 includes the following sub-steps: Step S1036, obtaining the cutoff delay time of the isolation optocoupler in the soft turn-off circuit of the switching transistor and the start-up dead time of the pulse width modulation control chip; Step S1037, adding the cutoff delay time and the start-up dead time to obtain the inherent turn-on hysteresis parameter; Step S1038, subtracting the turn-on hysteresis parameter from the originally set delay time to perform advance deduction correction on the delay time.

[0014] Preferably, the step of degrading the isolated switching power supply to an intermittent quiescent low-power condition in step S101 includes the following sub-steps: Step S1015, when the soft shutdown circuit keeps the enable terminal potential of the pulse width modulation control chip at a low level, blocking the drive pulse of the power switch transistor; Step S1016, maintaining the front-end power conversion loop of the isolated switching power supply in an intermittent quiescent state to reduce the standby energy transfer loss from the front-end DC high-voltage bus to the low-voltage side.

[0015] The beneficial effects of this invention are: 1. In the intermittent switching power supply control of PV shared SPS in photovoltaic inverters, the control unit collects the transient voltage on the battery side and calculates the discharge gradient. Based on the discharge rate, it dynamically compensates the basic wake-up voltage threshold and establishes a predictive start-up boundary that shifts positively as the load consumption rate increases. This is used to offset the inherent time lag in energy establishment on the secondary side of the upstream isolation transformer. This closed-loop control mechanism, which is based on the dual dependence of transformer dynamic response and downstream energy consumption characteristics, ensures that the power supply track fluctuation trajectory released by the shared power supply during the intermittent recovery phase smoothly converges within the safe power supply range. This eliminates the transient undershoot fault of the low-voltage bus that occurs under conventional static hysteresis comparison control and maintains the continuity of power supply to the control unit in the intermittent power supply cycle.

[0016] 2. The control unit, in conjunction with the grid-side voltage sampling path, locks the zero-crossing point of the AC mains waveform. When the battery voltage reaches the predictive wake-up boundary, the shutdown cancellation timing is suspended until the mains rectified ripple crosses the preset electrical angle corresponding to the valley of the preceding DC high-voltage bus voltage, releasing a low-level signal. This timing clamping coupling mechanism ensures that the power switch is in the low-stress range of the preceding bus transient voltage valley during the first reignition cycle, limiting the rate of change of the excitation impact current caused by the transformer parasitic capacitance, blocking false protection caused by transient overcurrent in the control chip's internal current detection pin, and weakening the dynamic commutation thermal stress of the switching power devices without changing the hardware energy storage filter network.

[0017] 3. On the input side, the inherent power switching diodes of the inverter full-bridge are used to construct a unidirectional uncontrolled rectification path for the AC input. With the voltage attenuation of the normally closed relay contacts and current-limiting resistors in the mains soft-start circuit, the rectified high-voltage DC and the photovoltaic DC input are converged to the same input bus to supply power to the reusable switching power supply circuit with power conversion function. This dual-path reusable hardware architecture without independent transformer and rectifier branches eliminates the need for a dedicated switching power conversion loop on the AC input side. In standby and resting conditions, low-power operation is achieved by cutting off the energy transmission path from the high-voltage bus to the secondary low-voltage side, avoiding the power circulating current risk caused by the parallel switching of multiple power supply circuits. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart of the intermittent switching power supply control method for voltage drop determination and ripple locking according to the present invention; Figure 2 This is a diagram showing the state transition between resting degradation and reignition on-state of the photovoltaic inverter using a shared SPS according to the present invention. Detailed Implementation

[0020] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0021] A method for controlling intermittent switching power supply of a photovoltaic inverter using a shared SPS includes the following steps: Step S101: Electrically connect the input terminal of the isolated switching power supply to the photovoltaic DC input channel and the AC mains input channel after rectification by the body diode of the inverter full-bridge power switch tube, and make the output terminal of the isolated switching power supply supply power to the secondary auxiliary power supply containing the battery. When it is detected that the current voltage of the battery is higher than the predictive wake-up reference voltage and the photovoltaic inverter has no grid connection command, the power transmission path from the front-end DC high-voltage bus to the secondary auxiliary power supply is cut off through the soft turn-off circuit of the switching tube, so that the isolated switching power supply is degraded to the intermittent quiet low power consumption condition. Step S102: The current voltage of the battery and the AC voltage of the grid side collected by the grid side voltage sampling transformer are obtained by the microprocessor. The current voltage is compared with the predictive wake-up reference voltage. When the current voltage drops to the predictive wake-up reference voltage, the turn-off cancellation command originally applied to the soft turn-off circuit of the switching transistor is latched and suspended. Step S103: The voltage comparator is used to capture the AC mains zero-crossing point of the grid-side AC voltage. After the grid-side AC voltage is detected to cross the AC mains zero-crossing point, the delay time is calculated. When the delay time reaches the valley electrical angle of the rectified ripple of the front-stage DC high-voltage bus, a low-level enable signal is released to the isolation optocoupler in the soft turn-off circuit of the switching transistor, so that the isolation optocoupler is transiently cut off, and the enable terminal potential of the pulse width modulation control chip is restored to the working high level, and the drive pulse sequence of the inverter full-bridge power switching transistor is restarted.

[0022] Preferably, the step of obtaining the predictive wake-up reference voltage in step S102 includes the following steps: step S1021, obtaining the loop response time compensation constant of the isolated switching power supply conversion circuit and the real-time drop rate of the battery voltage in the intermittent resting low power consumption condition; step S1022, multiplying the loop response time compensation constant by the real-time drop rate to calculate the transient drop of the low voltage power supply rail.

[0023] Preferably, step S101, which electrically connects the input terminal of the isolated switching power supply to the photovoltaic DC input channel and the AC mains input channel rectified by the inverter full-bridge power switch diodes, includes the following steps: Step S1011, using the inverter full-bridge power switch diodes to build an uncontrolled rectified topology path for the AC input; Step S1012, using the normally closed relay contacts and current-limiting resistors in the mains soft-start circuit to perform voltage division and limitation, connecting the rectified DC power and the photovoltaic DC input channel in parallel to the front-end DC high-voltage bus to supply power to the isolated switching power supply.

[0024] Preferably, the step of latching and suspending the turn-off cancellation instruction originally applied to the soft turn-off circuit of the switching transistor in step S102 includes the following steps: Step S1024, when the current voltage meets the preset turn-off threshold, output a high-level turn-off signal through the microprocessor; Step S1025, transmit the high-level turn-off signal to the isolation optocoupler in the soft turn-off circuit of the switching transistor, drive the transistor inside the isolation optocoupler to saturate and conduct, and pull down the enable terminal potential of the pulse width modulation control chip.

[0025] Preferably, the step of capturing the AC mains zero-crossing point of the grid-side AC voltage using a voltage comparator in step S103 includes the following steps: step S1031, obtaining a sinusoidal AC full-wave signal using a grid-side voltage sampling transformer; step S1032, inputting the sinusoidal AC full-wave signal to a voltage comparator to capture the positive and negative polarity crossover points of the sinusoidal AC full-wave signal in order to determine the AC mains zero-crossing point.

[0026] Preferably, the step of releasing the turn-off cancellation command when the delay time reaches the valley electrical angle of the rectified ripple of the preceding DC high-voltage bus includes the following steps: Step S1033, obtaining the grid-side power frequency of the AC mains input channel; Step S1034, determining a rectified ripple period twice the power frequency based on the grid-side power frequency; Step S1035, taking the AC mains zero-crossing point as the time starting point, delaying by 1 / 4 of the rectified ripple period to lock the voltage minimum phase of the preceding DC high-voltage bus.

[0027] Preferably, the delay time is configured as a value obtained by dividing 1 by 4 times the grid-side power frequency.

[0028] Preferably, the step of supplying power from the output of a single isolated switching power supply to a secondary auxiliary power supply containing a battery in step S101 includes the following steps: Step S1013, implementing high and low voltage graded electrical isolation for the electrical energy input to the isolated switching power supply through a multi-stage isolation transformer topology; Step S1014, constructing a voltage regulation loop using an optocoupler negative feedback network to output the adjusted DC voltage to the secondary auxiliary power supply.

[0029] Preferably, the step of calculating the delay time in step S103 includes the following sub-steps: Step S1036, obtaining the cutoff delay time of the isolation optocoupler in the soft turn-off circuit of the switching transistor and the start-up dead time of the pulse width modulation control chip; Step S1037, adding the cutoff delay time and the start-up dead time to obtain the inherent turn-on hysteresis parameter; Step S1038, subtracting the turn-on hysteresis parameter from the originally set delay time to perform advance deduction correction on the delay time.

[0030] Preferably, the step of degrading the isolated switching power supply to an intermittent quiescent low-power condition in step S101 includes the following sub-steps: Step S1015, when the soft shutdown circuit keeps the enable terminal potential of the pulse width modulation control chip at a low level, blocking the drive pulse of the power switch transistor; Step S1016, maintaining the front-end power conversion loop of the isolated switching power supply in an intermittent quiescent state to reduce the standby energy transfer loss from the front-end DC high-voltage bus to the low-voltage side.

[0031] Example 1: When the system faces continuous operation of the photovoltaic inverter auxiliary power supply system including a 48V battery system, the photovoltaic DC input channel and the AC mains input channel rectified by the body diodes of the inverter full-bridge power switch are connected in parallel to the DC high-voltage bus BUS to supply power to the input terminal of the isolated switching power supply; when the microprocessor detects that the current voltage of the battery is higher than the predictive wake-up reference voltage constructed by the dynamic compensation of the discharge gradient and the whole machine is in a standby low-power condition, the control signal S2 drives the soft turn-off circuit of the switching transistor to pull down the enable pin potential of the pulse width modulation control chip U15, turn off the drive pulse of the power switch Q83, and the front-stage isolated switch The power supply is degraded to operate in an intermittent, low-power, quiet mode to reduce the quiet loss of the auxiliary power supply system. During the sleep period when the downstream battery and the secondary auxiliary power supply BATSPS circuit independently bear the power supply of the low-voltage control load, the load continues to consume power, and the battery voltage drops dynamically. Due to the inherent settling time and energy transfer response lag of the front-end flyback topology control loop and the external filter network, simply triggering the re-wake-up of the front-end isolated switching power supply based on a fixed static voltage threshold will cause a transient undershoot in the secondary low-voltage power supply rail under multi-source high-frequency alternating switching or load power sudden change conditions, triggering the undervoltage lockout protection of the secondary auxiliary power supply and causing the power supply to be interrupted.

[0032] To offset the voltage drop caused by the hysteresis of the front-end flyback topology and the transient load changes in the secondary side, the microprocessor continuously collects the current battery voltage and calculates the discharge gradient according to a preset time step. Based on the discharge gradient, it performs dynamic feedforward compensation on the rigid lower limit voltage of 45V to maintain the stable operation of the secondary auxiliary power supply, thereby constructing a predictive wake-up reference voltage in real time. In specific execution, the microprocessor performs absolute value processing on the real-time rate of decline of the battery voltage acquired in the current acquisition cycle. It then multiplies this absolute rate of decline with the loop response time compensation constant stored in its internal register to accurately calculate the transient down-voltage millivolt value of the control rail within the energy build-up time delay of the isolation conversion circuit. Subsequently, it controls the internal central processing unit to arithmetically add the 45V rigid stable operating lower limit voltage reference value to the transient down-voltage millivolt value. The final sum is written as the current predictive wake-up reference voltage threshold into a dedicated comparison register. This threshold dynamically adjusts between 45.06V and 45.60V as the discharge rate varies discretely between 0.5V / s and 5.0V / s, thus achieving closed-loop updates at the data level without relying on algebraic equations or variable formulas, ensuring the predictive wake-up reference voltage. The calculation formula is ,in, The 45V voltage serves as the predictive wake-up reference voltage, while 45V is the rigid lower limit voltage for maintaining stable operation of the secondary auxiliary power supply. This is the loop response time compensation constant. Predictive wake-up reference voltage for real-time rate of battery voltage drop. As the load consumption rate increases, a positive shift occurs. A closed-loop correlation is established between the energy consumption rate of the downstream battery and the energy setup time constant of the upstream flyback topology. Feedforward control of the discharge rate is used to pre-determine the compensation margin for the charging delay of the secondary capacitor. The battery voltage is monotonically charged to the predictive wake-up reference voltage. During the transient response, the microprocessor maintains the output of control signal S2, uses a voltage comparator to capture the AC mains zero-crossing point of the grid-side AC voltage sampled by the grid-side voltage sampling transformer, and maintains a high-level 5V digital latch control state in the internal register to control the internal transistor of the isolation optocoupler in the soft-shutdown circuit to remain continuously saturated and conducting. This forces the enable pin potential of the pulse width modulation control chip to be clamped at a low level of 0V, physically blocking the drive pulse of the power switch transistor, so that the system remains in a dormant blocking state where the restart action is suspended until the optimal restart phase is reached; when the grid-side AC voltage is detected to cross the AC mains zero-crossing point... When the delay time after the overshoot reaches one-quarter of the rectification ripple cycle twice the power frequency, at the preset electrical angle phase corresponding to the valley of the rectification ripple of the preceding DC high-voltage bus BUS, the microprocessor releases a low-level enable signal to the isolation optocoupler U17 in the soft-shutdown circuit of the switching transistor to transiently cut it off. This causes the enable terminal potential of the pulse width modulation control chip U15 to be restored to the operating high level through the voltage divider network, thereby restarting the drive pulse sequence of the power switching transistor Q83. The microprocessor executes first-order digital differential calculation logic to obtain the real-time voltage drop rate within the current sampling period of the battery, and compares this real-time voltage drop rate with a preset range of 0.05 seconds to 0.30 seconds. The transient sag of the low-voltage power supply rail is calculated by multiplying the loop response time compensation constant within a second range. This transient sag is then added to the 45-volt lower limit voltage for stable operation of the secondary auxiliary power supply to dynamically generate a predictive wake-up reference voltage. The output drive recovery pulse acts on the front-stage power conversion transistor Q83 of the isolated switching power supply, restoring the power transmission path to the secondary auxiliary power supply. During inverter standby debugging, a dual-channel oscilloscope with a bandwidth of at least 100 MHz is used to acquire the sinusoidal full-wave signal output from the grid-side voltage sampling transformer and the voltage ripple waveform of the DC high-voltage bus. The transient zero-crossing point where the sinusoidal full-wave signal crosses 0 volts is captured as a timing parameter. The starting moment of the hardware timing is when the DC high-voltage bus voltage ripple waveform reaches a local minimum value. The time of the ripple valley is read. It is determined that there is a 2.5 millisecond time difference between the valley of the 100 Hz double frequency bus pulsating ripple generated by the uncontrolled rectification of the 50 Hz mains power and the zero crossing point. The sum of the cutoff delay time of the isolation optocoupler U17 and the start dead time of the pulse width modulation control chip U15 is subtracted from the initial set delay time of 2.5 milliseconds to deduct the inherent turn-on hysteresis parameter, so as to obtain the target delay parameter of the microprocessor's internal timer, so that the timing of the released low-level enable signal is clamped in the valley range of the DC high-voltage bus voltage ripple.

[0033] Because the power switch Q83 is forcibly clamped and coupled in the low-stress range of the power frequency rectification ripple trough of the transient voltage of the front-end DC high-voltage bus BUS during the initial cycle of restarting, the system controls the transient current and voltage stress of the power device during startup while maintaining the volume of the secondary filter capacitor and the cost of hardware materials. This limits the rate of change of the excitation impact current caused by the parasitic capacitance of the transformer TX11 and prevents the current detection pin of the pulse width modulation control chip U15 from causing false protection faults due to transient overcurrent. The 12V, -12V and 5V DC rails output by the secondary auxiliary power supply BATSPS circuit converge within the preset safe supply voltage range during the intermittent power supply full cycle. This closed-loop interdependent control mechanism, composed of the enable sequence of the front-end high-voltage energy storage topology and the power flow state of the back-end, transforms the input ripple evolution law under the multi-source alternating switching condition into a control boundary that ensures the low-stress restart of the power device. In the layout of the front-end multi-source complementary power distribution system, it maintains the power balance between standby energy efficiency and high dynamic power supply continuity.

[0034] Example 2: On a power distribution test platform including an on-orbit simulation simulator for power hardware, dual-channel DC regulated power sources, and a simulated AC grid load, dynamic response data of the power supply system are acquired through a physical data acquisition module. The dual-channel DC regulated power sources supply both the photovoltaic DC input and the AC mains input rectified by the diodes of the inverter full-bridge power switch. The physical data acquisition module has a voltage measurement range of 0V to 1000V, a voltage resolution of 0.01V, and a sampling frequency of 100kHz to reflect transient pulsations during high-frequency switching. A loop response time compensation constant is selected. When determining the physical parameters, the main technical factors affecting their values ​​include the energy build-up time constant of the flyback transformer secondary side and the commutation lag time of the soft turn-off circuit of the switching transistor. This parameter, as a time-domain feedforward adjustment scalar in the control core memory, aims to balance the system's resting energy-saving cycle span at low discharge rates with the control rail voltage drop space at high discharge rates. Its internal control flow logic is as follows: when an increase in the real-time rate of battery voltage drop is detected, to ensure that the output DC power supply rail of the secondary auxiliary power supply remains above 45V during the transient waveform downsampling process... The lower limit voltage of the rigid plate is locked, and the constant is limited to a discrete value range of 0.05s to 0.30s. Under the specific hardware configuration of this test platform, when the excitation inductance time constant of the flyback transformer is 12.5ms and the inherent transmission cutoff delay time of the software-controlled soft turn-off isolation optocoupler is 4.2μs, the stable engineering reference parameter of the response time compensation constant of the circuit is finally determined to be 0.12s through hardware timing physical network matching and open-loop step response test calibration. In addition, Gaussian white noise with a signal-to-noise ratio of 20dB is superimposed in the test signal source to simulate the electromagnetic interference conditions in the industrial field.

[0035] The experimental group used a constant including loop response time compensation. A control scheme with a value of 0.12s is used in a simulated battery discharge rate gradient condition where the discharge rate increases gradually over time. This is achieved when the real-time rate drops... At a negative discharge rate of -0.5V / s, the microprocessor calculates the predictive wake-up reference voltage. Shifting to 45.06V, the lowest transient drop value of the secondary auxiliary power supply DC voltage rail was measured to be 44.82V; when the real-time drop rate... When the voltage changes to -2.5V / s, the microprocessor calculates the predictive wake-up reference voltage. Adjusted to 45.30V, the lowest undershoot position of the corresponding DC voltage rail was measured to remain at 44.75V; when facing the limit of the problem intensity, i.e., the real-time rate of drop. Predictive wake-up reference voltage at -5.0V / s in the high discharge rate range. Shifted to 45.60V, predictive wake-up reference voltage The calculation formula is ,in, This is the predictive wake-up reference voltage, with 45 being a constant, corresponding to the rigid lower limit voltage for maintaining stable operation of the secondary auxiliary power supply. This is the loop response time compensation constant. The real-time rate of decline of the battery voltage is measured at this point. The transient valley of the DC voltage rail stabilizes at 44.68V, which is higher than the critical dead zone voltage of 44.0V for hardware restart of the control board. As the discharge rate increases, the electrical space for the start-up warning expands accordingly, thereby maintaining continuous power supply to the control system within a wide load transition range. The battery voltage monotonically rises to the predictive wake-up reference voltage. In the transient state after the wake-up boundary, the microprocessor maintains the output of control signal S2, uses a voltage comparator to capture the AC mains zero-crossing point of the grid-side AC voltage collected by the grid-side voltage sampling transformer, and latches the suspended shutdown cancellation command; when the delay time after detecting that the grid-side AC voltage crosses the AC mains zero-crossing point reaches one-quarter of the rectification ripple period twice the power frequency, at the preset electrical angle phase corresponding to the bottom of the DC high-voltage bus BUS rectification ripple, the microprocessor releases a low-level enable signal to the isolation optocoupler U17 in the soft shutdown circuit of the switching transistor to make it transiently cut off, and the enable terminal potential of the pulse width modulation control chip U15 is restored to the working high level through the voltage divider network to restart the drive pulse sequence of the power switching transistor Q83.

[0036] Control group 1 lacks loop response time compensation constant The shift feedforward control, under the same load jump, i.e., real-time drop rate Under the condition of -5.0V / s, due to the response time lag in the establishment of electrical energy in the secondary winding of the isolation transformer, the DC voltage rail of the secondary auxiliary power supply transiently surges to 43.12V, which is lower than the critical dead zone voltage of 44.0V for hardware restart of the control board, resulting in a power supply interruption. Control group two includes gradient feedforward control but lacks pulse turn-on timing constraints based on the bus ripple phase. Power switch Q83 is turned on at the peak electrical angle phase of the rectified ripple, and the measured peak value of the excitation impulse current pulse during the turn-on transient increases to 4.85A, and the commutation voltage stress of the power switch increases to 368.5V, triggering current protection. In the out-of-range control group used to verify the parameter range boundaries, when the loop response time compensation constant is... When set to 0.01s, the feedforward pre-duty time is insufficient, and the measured DC voltage rail drops to 43.35V, failing to suppress undervoltage failure; when the loop response time compensation constant is adjusted... When set to 0.85s, the predictive wake-up reference voltage A translational overload occurs, triggering the system to respond to voltage fluctuations within 10mV and entering a high-frequency repetitive switching state. The measured quiet low-power loss of the auxiliary power supply system increases from 0.18W under normal conditions to 2.43W. This increase in loss is due to the high-frequency commutation, affecting the circuit response time compensation constant. Within the range of 0.05s to 0.30s, a working window is formed that balances energy efficiency and DC power distribution continuity. Under the condition of fluctuations in the capacity of the DC high-voltage bus hardware filter capacitor and the equivalent impedance of the secondary auxiliary power supply load, the analog-to-digital conversion channel of the microprocessor samples the actual voltage value of the DC high-voltage bus cycle by cycle during the transient restart of the power switch Q83. It compares the current cycle sampling value with the historical data of the previous cycle. When the restart transient sampling value increases monotonically, the microprocessor fine-tunes the preset comparison register value of the timer with a correction step of 50 microseconds to change the release time of the low-level enable signal until the restart transient sampling value within 10 consecutive rectification ripple cycles converges to the local minimum value of the ripple waveform, thus completing the alignment of the delay control parameters with the ripple valley phase.

[0037] Example 3: This example combines Figures 1 to 2 This document describes a method for controlling the intermittent switching of power supply between a photovoltaic inverter and a shared SPS (Special Power Supply System). Figure 1As shown, the system enters the voltage status detection step, confirming that the current battery voltage is higher than the predicted reference and that the photovoltaic inverter has no grid connection command. It then enters the energy transmission cut-off step, cutting off the path from the front-end DC high-voltage bus to the secondary auxiliary power supply via a soft-shutdown circuit. This causes the system to enter a degraded low-power operation state, allowing the isolated switching power supply to operate in an intermittent, quiet, low-power condition. During this process, the microprocessor performs voltage comparison and data acquisition, triggering a voltage data acquisition step to obtain the current battery voltage and the grid-side AC voltage. The acquired data is used in the voltage drop comparison judgment step to compare and determine if the current voltage has dropped to the predicted wake-up reference voltage. When the condition is met, the system executes... The system initiates a cancellation instruction suspension step, latching and suspending the cancellation instruction originally applied to the soft shutdown circuit. This instruction acts on the soft shutdown circuit of the switching transistor to enable it to receive the cancellation and latching instructions. Next, it enters the zero-crossing point capture step, capturing the AC mains zero-crossing point and crossing it before starting to calculate the delay time. As the delay progresses, the system enters the ripple valley locking step, confirming that the delay time has reached the valley electrical angle of the rectified ripple of the front-stage DC high-voltage bus. This triggers the enable signal release step, releasing a low-level enable signal to the isolation optocoupler to transiently cut it off. Finally, it enters the reignition drive sequence, restoring the control chip's enable terminal potential to the working high level and restarting the power switching transistor drive pulse sequence.

[0038] like Figure 2 As shown, during the initial stable turn-on phase, the output of a single isolated switching power supply normally supplies power to the secondary auxiliary power supply containing the battery. When the triggering conditions are met—that the current battery voltage is higher than the predictive wake-up reference voltage and the photovoltaic inverter has no grid connection command—the system executes the action of cutting off the energy transmission path of the upstream DC high-voltage bus through the soft turn-off circuit of the switching transistor, and then transitions to the intermittent quiet low-power mode. In this state, the upstream conversion loop is in a quiet state to reduce standby losses. When the current battery voltage monotonically decreases and drops to the predicted voltage, the system continues to operate. When the trigger condition for waking up the reference voltage is met, the system executes the action of latching and suspending the turn-off cancellation instruction originally applied to the soft turn-off circuit of the switching transistor, thereby entering the instruction latch-suspended state. At this time, the microprocessor latches and suspends the turn-off cancellation instruction and captures the AC mains zero crossover point. Finally, when the trigger condition of the delay time reaching the valley electrical angle phase of the rectified ripple of the front-stage DC high-voltage bus is met, the system executes the action of releasing the low-level enable signal to the isolation optocoupler and restarting the drive pulse sequence, so that the system state returns to the stable turn-on stage, realizing the closed loop cycle.

[0039] Example 4: When long-term system operation causes irreversible changes in the equivalent internal resistance of the battery, and the DC high-voltage bus BUS generates high-frequency high-voltage switching transistor pulse radiation interference, a voltage transient spike superimposed on the current battery voltage is generated on the acquisition path. This voltage transient spike causes discrete numerical distortion in the calculation of the battery voltage discharge gradient, resulting in a change in the predictive wake-up reference voltage. Fluctuations can cause erroneous wake-ups of isolated switching power supplies during standby operation, reducing the voltage stability of the low-voltage power rail. To eliminate sampling deviations caused by radiated interference, a moving average digital filter circuit with a time constant of 10ms is used to collect discrete battery voltage samples over 10 cycles with a sampling step size of 100μs. After removing high-frequency interference components exceeding the voltage resolution by 0.01V, the true current battery voltage is reconstructed and input into a first-order digital differential circuit to calculate the real-time rate of voltage drop unaffected by high-frequency pulse interference. .

[0040] When a battery ages due to long-term charge-discharge cycles, the instantaneous fluctuation of its terminal voltage under sudden load increases. The fixed loop response time compensation constant cannot adapt to the energy build-up time constant after the change in polarization internal resistance. To achieve formulaless and conceptually independent parameter adaptive adjustment, the system connects an active sampling branch in parallel across the battery, consisting of a low-power field-effect transistor and a 1Ω precision non-inductive sampling resistor. When the single-set isolated switching power supply is in the stable turn-on phase, the microprocessor's pulse-width modulation peripheral hardware directly injects an alternating digital drive pulse with a working frequency of 1000Hz and a duty cycle of 10% into the gate of the field-effect transistor, thereby inducing a low-amplitude alternating current excitation signal of 50mA at the battery output. Simultaneously, a high-speed differential operational amplifier connected in parallel across the battery retrieves the transient response voltage waveform signal of the battery in real time and synchronously sends this AC voltage signal and the AC current signal across the precision non-inductive sampling resistor into the microprocessor's dual-channel analog-to-digital converter interface. The internally integrated Discrete Fourier Transform digital filtering program directly extracts the amplitude of the alternating voltage component and the amplitude of the alternating current component at a specific operating frequency of 1000Hz, and performs a digital division operation on the two to obtain the current true polarization internal resistance value of the battery. When the measured current polarization internal resistance value monotonically increases from the initial unaged 50mΩ to the aged 100mΩ, the microprocessor performs a division ratio operation on the current 100mΩ internal resistance value and the initial reference internal resistance value of 50mΩ stored in non-volatile memory to obtain a pure scalar amplification factor of 2.0. Subsequently, the microprocessor controls the arithmetic logic unit to multiply the initial loop response time compensation constant reference value of 0.12s with the pure scalar amplification factor of 2.0, seamlessly updating the running compensation control parameter in the target register to 0.24s. This increases the physical span of the feedforward time compensation window and dynamically raises the judgment boundary of the subsequent wake-up threshold, thereby achieving online accurate acquisition of internal resistance without interfering with the normal power supply of the main and auxiliary power supplies of the system.

[0041] Under the coordinated adjustment of the moving average digital filter circuit and the parameter adaptive update circuit, the sampling delay lag and amplitude deviation caused by aging and high-frequency interference are compensated for in the first stage, thus reducing the real-time rate of battery voltage drop when the battery is operating at low voltage. When the limit rate of change is reached -5.0V / s, the predictive wake-up reference voltage is adjusted by the updated formula. The voltage is accurately shifted to 43.8V, providing a precise advance offset time for the isolated flyback topology startup of the secondary auxiliary power supply. The microprocessor captures the trough phase of the pulsating power frequency ripple of the front-end DC high-voltage bus BUS and activates the drive pulse sequence of the power switch Q83. This ensures that the lowest point of the transient voltage of the 12V DC control rail output by the secondary auxiliary power supply BATSPS circuit stably converges to 44.68V, without touching the undervoltage protection dead zone of the control chip, thus maintaining continuous power supply to the power distribution system of the photovoltaic inverter in extreme standby loss mode.

[0042] Example 5: When the system faces initial power-on initialization or field deployment after battery replacement, zero-point drift of the sampling circuit will introduce measurement bias, causing deviation in the current battery voltage acquired by the microprocessor. To eliminate static errors in the initial stage, when the secondary load of transformer TX11 is disconnected, the control unit reads the initial bias voltage of the path and writes it into memory for subsequent automatic subtraction. The control unit also injects a standard calibration voltage of 48V into the input terminal and calibrates the gain coefficient according to the register value. Its formula is ,in, For gain coefficient, The standard voltage is 48V, while To read the voltage value.

[0043] When the system is under commissioning in an outdoor distribution box environment with large temperature differences, the ambient temperature fluctuations cause a temperature drift delay in the isolation optocoupler U17 in the soft turn-off circuit of the switching transistor, changing the turn-on electrical angle timing of the power switch Q83. To compensate for the temperature drift delay, the microprocessor reads the real-time temperature value from the temperature sensor, retrieves the corresponding delay compensation time base from the internal correction table, and fine-tunes the timer count value accordingly to correct the output timing of the cancellation control signal S2. In practical applications, the aforementioned internal correction table is established through actual measurement in an environmental temperature control chamber during the system's factory calibration phase and is pre-stored in the microprocessor's read-only memory. The calibration process uses a temperature step of 5°C, and within a temperature range of -40°C to 85°C, the transmission delay time of the isolation optocoupler at different temperature nodes is measured using a high-precision timing analysis instrument, and its time delay relative to 25°C is calculated. The delay drift of the reference ambient temperature is used to construct a discrete image array of temperature on the delay compensation time base. For example, when the temperature sensor reports that the current real-time temperature is 60℃, the correction table outputs a corresponding delay compensation time base of 1.2 microseconds. The microprocessor then subtracts the count value corresponding to 1.2 microseconds from the preset comparison value of the timer, thereby achieving precise advance of the control signal output time. This fundamentally offsets the temperature drift lag at the hardware level. The dynamic fine-tuning of the time constant is used to compensate for the commutation response lag generated by the optocoupler, so that the initial period of the drive pulse coincides with the trough of the high-voltage bus power frequency rectification ripple. Finally, the voltage ripple fluctuation amplitude of the 12V DC control rail output by the secondary auxiliary power supply BATSPS circuit is stabilized within 0.12V. The auxiliary power supply system maintains the transient stability of the power distribution circuit under sudden environmental changes.

[0044] Example 6: When the system faces the low-power standby condition of a photovoltaic inverter containing a 48V battery system in an outdoor environment with large temperature differences, the response time compensation constant of the parameter calibration loop inside the microprocessor is used to determine the target operating point of the isolated switching power supply in the intermittent resting low-power condition and transient reignition wake-up process. In the pre-deployment calibration stage, the high-voltage DC regulated power supply and the AC grid simulated load are connected to the entire power supply system. The input voltage of the DC high-voltage bus is set to 380V, and the temperature control box controls the test environment temperature to be stable at 25℃. The test system controls the simulated battery side to discharge energy at different discharge rates. The microprocessor collects the current voltage of the battery through a moving average digital filter loop. The first-order digital differential loop calculates the real-time drop rate based on the current voltage. The control system records the lowest drop transient value of the secondary auxiliary power supply DC voltage rail and the system standby power loss under the intermittent resting low-power condition under different loop response time compensation constants configured in the test system. This is used to compare and select the target operating point that takes into account both the stability and energy efficiency of the low-voltage power supply rail. The first test group is configured with loop response time compensation constants. The time is 0.05s. When the real-time voltage drop rate on the simulated battery side reaches -5.0V / s under extreme load conditions, the microprocessor calculates the predictive wake-up reference voltage according to a specific formula. It is 45.25V. ,in, 45 is the predictive wake-up reference voltage, and 45 is the lower limit voltage for maintaining stable operation of the secondary auxiliary power supply. This is the loop response time compensation constant. This represents the real-time rate of decrease in battery voltage.

[0045] When the battery voltage monotonically drops to 45.25V, the microprocessor latches the suspended shutdown cancellation command and releases a low-level enable signal after a 2.5ms delay after detecting that the grid-side AC voltage crosses the AC mains zero-crossing point. This delay corresponds to the trough of the 100Hz bus ripple after uncontrolled rectification of the 50Hz mains power. At this time, due to the inherent response time lag between the isolated switching power supply recovering from the drive pulse and the establishment of the secondary voltage, the small compensation constant leads to insufficient feedforward advance. The lowest point of the transient voltage of the 12V DC control rail of the secondary auxiliary power supply drops to 44.15V, which is near the critical dead zone voltage of 44.0V for the hardware restart of the control board. The dynamic power supply voltage margin of the system is less than the preset safety margin. The standby power loss of the auxiliary power supply system under intermittent quiet low-power conditions is measured to be 0.15W. The second test group configures the loop response time compensation constant. With a time interval of 0.30s, under the same load change condition (i.e., a real-time voltage drop rate of -5.0V / s), the microprocessor calculates the predictive wake-up reference voltage according to the aforementioned formula. The voltage is 46.50V. When the current battery voltage drops to 46.50V, the control system restarts the power switch at the bottom of the bus ripple. Because the early start-up amount is greater than the design requirement, the energy on the secondary side of the transformer begins to replenish while the battery voltage is still high. The lowest point of the transient voltage of the 12V DC control rail of the secondary auxiliary power supply is stable at 45.25V. Although it is higher than the hardware restart dead zone voltage, raising the wake-up threshold causes the system to over-trigger small voltage fluctuations, causing the isolated switching power supply to frequently restart during standby. The rest period of intermittent hibernation is shortened, and the standby power loss of the auxiliary power supply system increases to 2.15W, making it impossible to maintain a low-power operation.

[0046] The third test group configured the loop response time compensation constant. The value is 0.12s. This value was obtained by calibrating the relationship model based on the energy settling time constant of 12.5ms on the secondary side of the flyback transformer and the transmission delay of 4.2μs for the soft-turn-off optocoupler. Under the same extreme load condition, i.e., a real-time drop rate of -5.0V / s, the microprocessor calculates the predictive wake-up reference voltage according to the aforementioned formula. The voltage is 45.60V. When the current battery voltage drops to 45.60V, the microprocessor restarts the power switch in the low-stress range of the mains rectification ripple trough. The minimum transient voltage of the 12V DC control rail of the secondary auxiliary power supply stabilizes at 44.68V, avoiding the risk of undervoltage lockout. At the same time, the isolated switching power supply maintains a long-cycle intermittent quiet sleep. The standby power loss of the auxiliary power supply system remains at 0.18W. This set of parameters coordinates the balance between power supply continuity and standby loss within a wide load transition range. Therefore, 0.12s is determined as the target parameter for this application condition. By calibrating the parameter to 0.12s, the photovoltaic inverter auxiliary power supply system maintains a steady-state output of 12V, -12V, and 5V DC low-voltage rails under a wide range of dynamic surge loads, and the energy flow from the DC high-voltage bus to the secondary side is cut off during deep sleep.

[0047] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for controlling intermittent switching power supply of a photovoltaic inverter using a shared SPS, characterized in that, Includes the following steps: Step S101: Electrically connect the input terminal of the isolated switching power supply to the photovoltaic DC input channel and the AC mains input channel after rectification by the body diode of the inverter full-bridge power switch tube, and make the output terminal of the isolated switching power supply supply power to the secondary auxiliary power supply containing the battery. When it is detected that the current voltage of the battery is higher than the predictive wake-up reference voltage and the photovoltaic inverter has no grid connection command, the power transmission path from the front-end DC high-voltage bus to the secondary auxiliary power supply is cut off through the soft turn-off circuit of the switching tube, so that the isolated switching power supply is degraded to the intermittent quiet low power consumption condition. Step S102: The current voltage of the battery and the AC voltage of the grid side collected by the grid side voltage sampling transformer are obtained by the microprocessor. The current voltage is compared with the predictive wake-up reference voltage. When the current voltage drops to the predictive wake-up reference voltage, the turn-off cancellation command originally applied to the soft turn-off circuit of the switching transistor is latched and suspended. Step S103: The voltage comparator is used to capture the AC mains zero-crossing point of the grid-side AC voltage. After the grid-side AC voltage is detected to cross the AC mains zero-crossing point, the delay time is calculated. When the delay time reaches the valley electrical angle of the rectified ripple of the front-stage DC high-voltage bus, a low-level enable signal is released to the isolation optocoupler in the soft turn-off circuit of the switching transistor, so that the isolation optocoupler is transiently cut off, and the enable terminal potential of the pulse width modulation control chip is restored to the working high level, and the drive pulse sequence of the inverter full-bridge power switching transistor is restarted.

2. The photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 1, characterized in that, The step of obtaining the predictive wake-up reference voltage in step S102 includes the following steps: Step S1021, obtaining the loop response time compensation constant of the isolated switching power supply conversion circuit and the real-time drop rate of the battery voltage in the intermittent rest low power consumption condition; Step S1022, multiplying the loop response time compensation constant by the real-time drop rate to calculate the transient drop of the low voltage power supply rail.

3. The photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 1, characterized in that, The step S101, which electrically connects the input terminal of the isolated switching power supply to the photovoltaic DC input channel and the AC mains input channel rectified by the inverter full-bridge power switch diodes, includes the following steps: Step S1011, using the inverter full-bridge power switch diodes to build an uncontrolled rectified topology path for the AC input; Step S1012, using the normally closed relay contacts and current-limiting resistors in the mains soft-start circuit to perform voltage division and limitation, connecting the rectified DC power and the photovoltaic DC input channel in parallel to the front-end DC high-voltage bus to supply power to the isolated switching power supply.

4. The photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 1, characterized in that, The step of latching and suspending the turn-off cancellation instruction originally applied to the soft turn-off circuit of the switching transistor in step S102 includes the following steps: Step S1024, when the current voltage meets the preset turn-off threshold, the microprocessor outputs a high-level turn-off signal; Step S1025, the high-level turn-off signal is transmitted to the isolation optocoupler in the soft turn-off circuit of the switching transistor, driving the transistor inside the isolation optocoupler to saturate and conduct, and pulling down the enable terminal potential of the pulse width modulation control chip.

5. The photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 1, characterized in that, The step of capturing the AC mains zero-crossing point of the grid-side AC voltage using a voltage comparator in step S103 includes the following steps: Step S1031, obtaining a sinusoidal AC full-wave signal using a grid-side voltage sampling transformer; Step S1032, inputting the sinusoidal AC full-wave signal to a voltage comparator to capture the positive and negative polarity crossover points of the sinusoidal AC full-wave signal in order to determine the AC mains zero-crossing point.

6. The photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 1, characterized in that, The step of releasing the turn-off cancellation command when the delay time reaches the valley electrical angle of the rectified ripple of the front-stage DC high-voltage bus includes the following steps: Step S1033, obtaining the grid-side power frequency of the AC mains input channel; Step S1034, determining the rectified ripple period twice the power frequency based on the grid-side power frequency; Step S1035, taking the AC mains zero-crossing point as the time starting point, delaying by 1 / 4 of the rectified ripple period to lock the voltage minimum phase of the front-stage DC high-voltage bus.

7. The photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 6, characterized in that, The delay time is configured as 1 divided by 4 times the grid-side power frequency.

8. The photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 1, characterized in that, The step of supplying power from the output of a single isolated switching power supply to a secondary auxiliary power supply containing a battery in step S101 includes the following steps: Step S1013, implementing high and low voltage graded electrical isolation of the electrical energy input to the isolated switching power supply through a multi-stage isolation transformer topology; Step S1014, constructing a voltage regulation loop using an optocoupler negative feedback network, and outputting the adjusted DC voltage to the secondary auxiliary power supply.

9. A method for controlling intermittent switching power supply of a photovoltaic inverter using a shared SPS according to claim 1, characterized in that, The step of calculating the delay time in step S103 includes the following sub-steps: Step S1036, obtaining the cutoff delay time of the isolation optocoupler in the soft turn-off circuit of the switching transistor and the start-up dead time of the pulse width modulation control chip; Step S1037, adding the cutoff delay time and the start-up dead time to obtain the inherent turn-on hysteresis parameter; Step S1038, subtracting the turn-on hysteresis parameter from the originally set delay time to perform advance deduction correction on the delay time.

10. A photovoltaic inverter PV shared SPS intermittent switching power supply control method according to claim 1, characterized in that, The step of degrading the isolated switching power supply to intermittent quiescent low-power operation in step S101 includes the following sub-steps: Step S1015, when the soft shutdown circuit keeps the enable terminal potential of the pulse width modulation control chip at a low level, the drive pulse of the power switch is blocked; Step S1016, the front-end power conversion loop of the isolated switching power supply is kept in an intermittent quiescent state to reduce the standby energy transfer loss from the front-end DC high-voltage bus to the low-voltage side.

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