Inverter multi-modal data acquisition and processing method based on convolutional neural network

Abstract

The application discloses an inverter multi-modal data acquisition and processing method based on a convolutional neural network, and the method comprises the following steps: deploying a multi-modal data continuous extraction module and a central controller of an integrated data processing unit on a working node; the extraction module acquires physical environment signals and converts the physical environment signals into a feature vector set; the central controller calculates the ratio of the global semantic variance and the local manifold density of the feature vector set to generate information temperature; the cluster management end calculates the spatial gradient based on the information temperature of each node, and issues a feedforward cooperative sampling instruction when the set condition is met; the extraction module responds to the instruction, performs cross-modal resource zero-sum scheduling and sampling parameter closed-loop reconstruction; the data processing unit reconstructs a multi-resolution tensor, and uses a temperature sensing gate routing operator to distribute the multi-resolution tensor to the convolutional neural network to output an inverter running state. The application realizes early perception of cross-node physical disturbance propagation, meets the high-frequency sampling burst data throughput demand, and improves the system state diagnosis accuracy.

Description

Technical Field

[0001] This invention relates to the field of inverter monitoring and data processing technology, specifically to a method for acquiring and processing multimodal data of inverters based on convolutional neural networks. Background Technology

[0002] Inverters, as core devices for power electronic conversion, are widely used in industrial cluster systems such as photovoltaics, wind power, and microgrids. The stability of their operation directly affects the reliable operation of the entire system.

[0003] In current industrial applications, monitoring of inverter arrays primarily relies on a distributed data acquisition architecture. Sensors are installed at each inverter node to achieve real-time monitoring of physical parameters such as voltage, current, and mechanical vibration. The acquired data is typically preprocessed by a local controller or transmitted via a communication network to an upper-level management platform for fault alarms and energy efficiency assessments.

[0004] Existing monitoring solutions primarily focus on anomaly detection within individual inverter nodes, lacking effective logical connections and data collaboration between nodes at the sensing level. When a node in the cluster experiences an electrical transient switch or a minor fault disturbance, the resulting physical impact propagates rapidly along the electrical topology path to adjacent nodes. Because existing acquisition and processing mechanisms struggle to quantify and characterize the propagation trend of physical disturbances in real time at the cluster topology level, adjacent nodes often only passively trigger high-frequency resampling of underlying data after being affected by the disturbance and generating a substantial abnormal response. This makes it impossible to establish a feedforward collaborative sampling and intervention mechanism for cross-node physical disturbance propagation, failing to meet the real-time requirements for accurate extraction of transient features under complex operating conditions. Summary of the Invention

[0005] The technical problem to be solved by this invention is that the existing inverter cluster monitoring scheme lacks the perception logic association between nodes, which makes it impossible to quantify and characterize the propagation trend of physical disturbances in the topology network in real time. As a result, it is difficult to establish a feedforward collaborative sampling mechanism before the disturbance reaches the target node. Furthermore, the underlying hardware is unable to meet the burst data throughput requirements generated by transient high-frequency sampling and improve the accuracy of state diagnosis under complex operating conditions without increasing physical storage elements.

[0006] This invention provides a method for multimodal data acquisition and processing of inverters based on convolutional neural networks. Relying on a cloud-native cluster environment, it constructs a closed-loop control system through hardware modules that interconnects physical underlying acquisition parameters and feature space information measurement for data acquisition and processing. The cloud-native cluster environment includes a cloud-native cluster management terminal and multiple working nodes. The method includes the following steps:

[0007] Step S100: Deploy a multimodal data continuous extraction module on each working node in the cloud-native cluster environment and configure a central controller that integrates the internal data processing unit.

[0008] Step S200: The multimodal data continuous extraction module acquires the physical environment signal of the corresponding working node at a preset basic sampling frequency and converts it into a feature vector set. ;

[0009] In step S300, the central controller uses the data processing unit to calculate the global semantic variance and local manifold density of the feature vector set within the current time window, and calculates the information temperature of the working node using the ratio of the two. ;

[0010] In step S400, the cloud-native cluster management terminal receives the information temperature sent by the worker node and calculates the spatial gradient. When the gradient meets the set conditions, it issues a feedforward collaborative sampling command.

[0011] In step S500, the multimodal data continuous extraction module responds to local information temperature changes or feedforward collaborative sampling commands by performing closed-loop reconstruction of the underlying sampling parameters.

[0012] In step S600, the data processing unit reconstructs the multi-resolution tensor and inputs it into the convolutional neural network model to output the inverter's operating status.

[0013] Preferably, step S200 specifically includes:

[0014] Step S210: The clock management circuit inside the field-programmable gate array chip generates and distributes a global synchronization clock signal to the analog-to-digital converter array.

[0015] In step S220, after receiving the global synchronization clock signal, the analog-to-digital converter array synchronously discretizes the physical environment signal at the inverter operating node at a preset base sampling frequency, thereby converting it into a discrete multi-dimensional time series matrix. ;

[0016] Step S230: The programmable gain amplifier circuit maintains the amplitude of the analog signal by adjusting the basic gain multiple during steady-state acquisition.

[0017] In step S240, the data processing unit inside the central controller calls the orthogonal principal component analysis algorithm code to process the multidimensional time series matrix. The mean-free process is performed and the covariance matrix is ​​calculated. Then, eigenvalue decomposition is performed to extract the corresponding eigenvalues ​​with the largest values. Construct a projection matrix of dimension M×d from eigenvectors. The data processing unit (93) processes the multidimensional time series matrix. With projection matrix The transpose of the vector is used for matrix multiplication to map the signals acquired by the basic sensor to a low-dimensional feature manifold, ultimately generating and outputting a set of feature vectors. .

[0018] Preferably, step S300 specifically includes:

[0019] Step S310: The data processing unit calculates the global semantic variance. The calculation formula is:

[0020] ,

[0021] In the formula, For the set of feature vectors The mean vector, Denotes the Euclidean norm. For the first One feature point, This represents the total number of sampling points;

[0022] In step S320, the data processing unit constructs a spatial index structure and calculates the local manifold density. The calculation formula is:

[0023]

[0024] In the formula, The set number of nearest neighbor nodes, Represents the midpoint of the feature space of The set of nearest neighbors For feature points Its nearest neighbor The Euclidean distance between them;

[0025] Step S330, the data processing unit will calculate the global semantic variance. Divide by local manifold density Accurately calculate the temperature information that characterizes the current topology state of the working node. ,Right now ,in, To prevent smooth minimum constants with denominators of zero.

[0026] Preferably, the calculation of the spatial gradient in step S400 specifically includes:

[0027] Step S420: The server array of the cloud-native cluster management terminal traverses all combinations of worker nodes to generate comprehensive topology distance parameters. The calculation formula is:

[0028] ,

[0029] In the formula, These are the impedance parameters of the electrical connection lines. The physical straight-line distance parameter in space, and the impedance weighting coefficient. With distance weight coefficient satisfy ;

[0030] Step S430: The server array extracts the source worker node. Information temperature With the target working node Information temperature Calculate the spatial gradient vector of temperature information. ;

[0031] Step S440: The server array aggregates spatial gradient vectors to generate and updates the global information temperature spatial gradient field matrix in real time. .

[0032] Preferably, the step S400 of issuing the feedforward collaborative sampling command specifically includes:

[0033] In step S450, the comparator logic core will convert the information temperature spatial gradient vector... The magnitude and the preset spatial gradient feedforward safety threshold Perform numerical judgment;

[0034] Step S460: When the feedforward triggering condition is met, extract the discrete contribution values ​​of each physical sensing mode within the current time window. The sensing modes with the largest discrete contribution values ​​are selected by sorting algorithm and identified as the perturbation-dominant modes, and then feedforward cooperative sampling data packets are constructed.

[0035] In step S480, the central controller of the target inverter working node parses the feedforward cooperative sampling data packet and outputs a level trigger signal with the disturbance dominant mode identifier to the internally connected multi-mode data continuous extraction module.

[0036] Preferably, the closed-loop reconstruction of the underlying sampling parameters in step S500 includes hardware resource reallocation, specifically including:

[0037] Step S520: The field-programmable gate array (FPGA) chip parses the reallocation control word and performs weighted dynamic cache reallocation on the internal cache resource pool according to the resource allocation weight coefficient. Adjust the depth parameters of the first-in-first-out memory logic cores corresponding to each mode, and allocate the cache capacity surplus generated by rounding down to the dominant mode;

[0038] In step S540, the field-programmable gate array chip synchronously performs cross-modal zero-sum scheduling on the communication time slice of the direct memory access bus. The time-division multiplexing polling arbitrator allocates the number of valid transmission clock cycles to each sensing mode and compensates the remaining clock cycle value generated by rounding down to the dominant mode.

[0039] Preferably, the closed-loop reconstruction of the underlying sampling parameters in step S500 further includes:

[0040] Step S560: The field-programmable gate array chip determines the dynamic gain coefficient after target mode reconstruction. ;

[0041] In step S570, the programmable gain amplifier circuit increases the amplification factor of the target modal analog signal from the steady-state gain coefficient to the dynamic gain coefficient.

[0042] In step S580, the clock management circuit reduces the clock division ratio of the output to the analog-to-digital converter array corresponding to the target mode, thereby reducing the actual dynamic sampling frequency. Meets the high-frequency reference clock frequency With dynamic frequency division coefficient The ratio of .

[0043] Preferably, the reconstruction of the multi-resolution tensor in step S600 specifically includes:

[0044] In step S620, the data processing unit performs a linear interpolation alignment operation on the steady-state mode sequence using the relative hardware timestamp of the transient mode sequence as the reference axis.

[0045] Step S630: The data processing unit performs physical dimension elimination and amplitude normalization operations on each aligned modal sequence;

[0046] In step S640, the data processing unit fuses and reconstructs the normalized sequence into a three-dimensional dynamic tensor along a preset feature dimension. Its dimensions are fixed. .

[0047] Preferably, the input to the convolutional neural network model in step S600 specifically includes:

[0048] Step S650: A first convolutional branch network with small-sized convolutional kernels and a second convolutional branch network with large-sized convolutional kernels are configured.

[0049] In step S660, the temperature-sensing gated routing operator (230) uses the information temperature scalar T as a system state metric to perform gated dynamic routing on the incoming three-dimensional dynamic tensor Z.

[0050] In step S6601, the data processing unit executes the routing control vector through the underlying tensor arithmetic multiplication. With three-dimensional dynamic tensors The combination of these signals is transformed into activation or inhibition signals for the underlying matrix channels.

[0051] Preferably, the operating state of the output inverter specifically includes:

[0052] In step S670, the activated convolutional branch network performs convolution operations on the corresponding input tensor to extract local correlation features, generates a deep feature mapping matrix, and performs a flattening operation to convert it into a one-dimensional hidden layer feature vector. ;

[0053] Step S680, hidden layer feature vector After dimensionality mapping via a fully connected layer, the input is fed into a normalized activation function to calculate the probability, and the output is a classification label vector. Then, the final system state diagnosis result is determined based on the index of the element with the highest probability value.

[0054] The present invention, by adopting the above technical solution, can bring the following beneficial effects:

[0055] 1. This invention extracts multimodal data from inverter working nodes and calculates global semantic variance and local manifold density to construct information temperature. Then, the cloud-native cluster management terminal calculates the spatial gradient vector of information temperature by combining the topological distance matrix and issues feedforward collaborative sampling instructions. This realizes a feedforward collaborative control mechanism that extends the data perception capability of a single node to the cluster topology dimension. It takes advantage of the time difference between the photoelectric signal transmission speed of industrial communication networks and the physical propagation speed of mechanical and thermal disturbances, so that the system can establish a feedforward control benchmark for cross-node disturbance propagation and trigger intervention operations in advance before the physical disturbance actually affects the target node and triggers an abnormal response.

[0056] 2. This invention uses a field-programmable gate array (FPGA) chip to parse the redistribution control word and perform weighted dynamic cache redistribution. While maintaining the total cache and bandwidth limit unchanged, it calculates the resource allocation weight based on the discrete contribution of the sensing modes, dynamically compresses the storage depth and communication time slice of non-dominant modes and compensates them to the high-frequency dominant modes. Combined with dynamic gain switching and clock frequency division adjustment, it achieves the data acquisition effect of coping with the sudden data throughput demand caused by transient high-frequency sampling and avoiding communication link blockage without increasing the underlying hardware storage elements.

[0057] 3. This invention uses a data processing unit to perform interpolation, alignment, and normalization on a steady-state sequence based on a transient sequence hardware timestamp to reconstruct a multi-resolution three-dimensional dynamic tensor. It also uses a temperature-sensing gated routing operator to use the information temperature scalar as a physical prior routing instruction to perform hard routing allocation on the incoming three-dimensional dynamic tensor to trigger convolutional branch networks with convolutional kernels of different sizes. This achieves deep coupling between the underlying physical signal features and the high-level deep learning inference path, enabling the network to dynamically adapt to the complex working conditions of the system and output accurate state diagnosis results. Attached Figure Description

[0058] Figure 1 This is a flowchart of the multimodal data acquisition and processing method for inverters based on convolutional neural networks according to the present invention.

[0059] Figure 2 This is a schematic diagram of the inverter multi-mode data acquisition and processing system of the present invention;

[0060] Figure 3 This is a closed-loop reconstruction logic diagram of the underlying sampling parameters and hardware resources of this invention;

[0061] Figure 4 This is a schematic diagram of the multi-resolution tensor reconstruction and gated routing convolutional neural network structure of the present invention. Detailed Implementation

[0062] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0063] A Multimodal Data Acquisition and Processing Method for Inverters Based on Convolutional Neural Networks

[0064] Example 1

[0065] See attached document Figure 1-2 This embodiment provides a method for multimodal data acquisition and processing of inverters based on convolutional neural networks. Relying on a cloud-native cluster environment 10, a closed-loop control system is constructed through hardware modules that links physical underlying acquisition parameters and feature space information measurement. The overall process of the aforementioned processing method includes the following steps:

[0066] In step S100, a multimodal data continuous extraction module 100 is deployed on each working node 30 of the cloud-native cluster environment 10, and a central controller 90 integrating an internal data processing unit 93 is configured. The multimodal data continuous extraction module 100 includes a field-programmable gate array (FPGA) chip 110, an analog-to-digital converter (ADC) chip array 120 connected to the aforementioned FPGA chip 110 via an interface, and a programmable gain amplifier hardware circuit 130. By independently deploying the above-mentioned continuous extraction module on each working node 30, node-level edge data extraction is implemented. The data processing unit 93 is integrated on the internal processing motherboard 91 of the central controller 90, sharing a single physical entity with the control logic circuit 92 as an internal component of the central controller 90. The data processing unit 93 adopts a system-level microprocessor 94 containing a tensor processing core 931. This configuration structure enables the central controller 90 and the internal data processing unit 93 to directly exchange instructions and data through the onboard high-speed bus 95, eliminating cross-device communication latency.

[0067] In step S200, the multimodal data continuous extraction module 100 acquires the physical environment signal of the corresponding working node 30 at a preset basic sampling frequency and converts it into a feature vector set. During the steady-state operation phase, the analog-to-digital converter chip array 120 performs asynchronous sampling on the voltage sequence, current sequence, mechanical vibration sequence, and infrared temperature sequence output by the inverter. The field-programmable gate array chip 110 provides a global clock signal for each analog-to-digital converter to trigger synchronously, converting the analog signal into a discrete multidimensional time series matrix. The big data processing unit 93 in the central controller 90 calls the fixed orthogonal principal component analysis algorithm code to perform high-dimensional feature space mapping on the aforementioned multidimensional time series matrix and outputs the dimensionality-reduced feature vector set. Let the feature vector set be ,in Indicates the first The feature vector corresponding to each sampling time. This represents the total number of sampling points within the current time window.

[0068] In step S300, the central controller 90 uses the data processing unit 93 to calculate the global semantic variance and local manifold density of the feature vector set within the current time window, and calculates the information temperature of the working node using the ratio of the two. The data processing unit 93 extracts the squared mean of the Euclidean distances from all feature points in the feature vector set to the geometric mean center to generate the global semantic variance. The specific calculation formula is as follows:

[0069] ,

[0070] In the formula, For the set of feature vectors The mean vector, Denotes the Euclidean norm. For the first One feature point, This represents the total number of sampling points;

[0071] Data processing unit 93 synchronously calculates the inverse mean of the local spatial distances between each feature point in the feature vector set and its preset number of nearest neighbor feature points, generating the local manifold density. The specific calculation formula is as follows:

[0072]

[0073] In the formula, The set number of nearest neighbor nodes, Represents the midpoint of the feature space of The set of nearest neighbors For feature points Its nearest neighbor The Euclidean distance between them;

[0074] Data processing unit 93 divides the calculated global semantic variance by the local manifold density to generate information temperature, which characterizes the current physical and information space topological coupling state of working node 30. ,Right now ;

[0075] In step S400, the cloud-native cluster management terminal 20 receives the information temperature sent by the worker node 30 and calculates the spatial gradient. When the gradient meets the set conditions, it issues a feedforward collaborative sampling command. The cloud-native cluster management terminal 20 obtains the electrical connection distance parameter between the source worker node and the adjacent target worker node according to the pre-configured inverter array topology relationship matrix. The management terminal divides the information temperature difference between the two nodes by the aforementioned electrical connection distance parameter to generate the information temperature spatial gradient vector. The specific calculation formula is as follows:

[0076]

[0077] In the formula, Source working node Information temperature, For adjacent target working nodes Information temperature, Source working node With adjacent target working nodes When the magnitude of the aforementioned information temperature spatial gradient vector exceeds the system's preset safety threshold, the cloud-native cluster management terminal 20 sends a feedforward collaborative sampling data packet containing a trigger identifier and a target modality field to the central controller 90 of the aforementioned adjacent target working nodes through the communication link 50.

[0078] In step S500, the multimodal data continuous extraction module 100 responds to local information temperature changes or feedforward collaborative sampling instructions by performing closed-loop reconstruction of the underlying sampling parameters. After the central controller 90 identifies that the locally calculated information temperature exceeds the set upper limit or receives the aforementioned feedforward collaborative sampling data packet, it writes a reconfiguration register instruction to the field programmable gate array chip 110 through the internal communication interface 96. The field programmable gate array chip 110 modifies the operating clock division coefficient of the analog-to-digital converter of the corresponding sensing channel to increase the sampling frequency and synchronously adjusts the feedback resistor network configuration of the programmable gain amplifier hardware circuit 130 to improve the gain resolution. The multimodal data continuous extraction module 100 switches from the basic sampling mode to the broadband high-frequency sampling mode.

[0079] In step S600, the data processing unit 93 reconstructs the multi-resolution tensor and inputs it into the convolutional neural network (CNN) model 200 to output the inverter's operating status. The data processing unit 93 uses nanosecond-level hardware timestamps to perform time-dimensional matrix concatenation of the data segments obtained at the basic sampling frequency and the feature segments obtained in the broadband high-frequency mode, generating a three-dimensional dynamic tensor containing time dimension, modality dimension and resolution level dimension. The data processing unit 93 inputs the aforementioned three-dimensional dynamic tensor into the CNN model 200 loaded in memory to perform feedforward propagation. After convolution and pooling operations, the CNN model 200 outputs a classification label vector indicating the operating status and fault type of the corresponding working node.

[0080] Example 2

[0081] See attached document Figure 1-2Based on Embodiment 1, this embodiment relies on a cloud-native cluster environment 10 to construct a closed-loop control system that links physical underlying acquisition parameters and feature spatial information measurement. The cloud-native cluster environment 10 includes a cloud-native cluster management terminal 20 and several inverter working nodes 30 connected through a communication network. The cloud-native cluster management terminal 20 is configured with a server array. The aforementioned server array is used to receive data uploaded by each inverter working node 30 and calculate the spatial gradient field. The cloud-native cluster management terminal 20 and each inverter working node 30 use a fiber optic ring network or industrial Ethernet to construct a physical communication link. For the design of the underlying isolation circuit of the fiber optic ring network and industrial Ethernet interface, those skilled in the art can refer to existing industrial communication hardware standards for implementation. The physical layer transceiver circuit structure of the aforementioned fiber optic ring network and industrial Ethernet interface is a well-known technology in the field and will not be described in detail here.

[0082] The multimodal data continuous extraction module 100 is deployed at each inverter working node 30 in the cloud-native cluster environment 10. Each inverter working node 30 manages an inverter hardware unit 40. The multimodal data continuous extraction module 100 is configured inside the casing of the inverter hardware unit 40 or directly attached near the heat and vibration source to sense the underlying physical environment signals.

[0083] Each inverter working node 30 is equipped with a central controller 90, which contains a data processing unit. Since the data processing unit is located inside the central controller 90, it is integrated with the main control logic circuit of the central controller 90 on the same printed circuit board. The central controller 90 and the data processing unit are not separate components, but constitute a single physical entity. The microprocessor in the central controller 90 directly allocates memory address space for the built-in data processing unit through the on-chip high-speed bus. The data processing unit directly accesses the direct memory access register of the central controller 90. This integrated structure eliminates the bus communication delay between the controller and external processing devices in the traditional architecture.

[0084] Since the central controller 90 and the data processing unit are not separate components, the central controller 90 adopts a system-on-a-chip containing a tensor processing core 91. The tensor processing core 91 has an arithmetic logic unit array 92 built inside, which is dedicated to matrix multiplication and addition operations. The arithmetic logic unit array 92 provides hardware acceleration support for the forward propagation of the convolutional neural network and feature dimensionality reduction projection.

[0085] The multi-mode data continuous extraction module 100 deployed in each inverter working node 30 includes a field-programmable gate array chip 110, an analog-to-digital converter array 120, and a programmable gain amplifier circuit 130. The analog input terminals of the analog-to-digital converter array 120 are respectively connected to the voltage transformer 41, the current transformer 42, the piezoelectric mechanical vibration sensor 43, and the infrared temperature sensor 44 of the inverter working node 30. The digital output terminals of the analog-to-digital converter array 120 are connected to the data pins of the field-programmable gate array chip 110.

[0086] The field-programmable gate array chip 110 is internally configured with a clock management circuit 111 and a control state machine 116. The clock management circuit 111 generates a high-frequency reference clock signal through a phase-locked loop 112. The clock management circuit 111 outputs a nanosecond-level synchronous clock signal from the same source to each analog-to-digital converter chip in the analog-to-digital converter array 120. Sensor data of each mode are sampled under the unified hardware clock drive, realizing time alignment of multi-dimensional data at the physical level.

[0087] A programmable gain amplifier circuit 130 is connected in series between the analog signal output terminals of the aforementioned sensors and the analog input terminals of the analog-to-digital converter array 120. The programmable gain amplifier circuit 130 includes a digital potentiometer 131 and a multiplexed switch network 132. The field-programmable gate array chip 110 sends a resistance adjustment command to the digital potentiometer 131 through a serial peripheral interface. The resistance adjustment command changes the feedback resistor network structure of the programmable gain amplifier circuit 130, dynamically adjusting the amplification factor of the analog front-end signal.

[0088] The data bus interface of the multimodal data continuous extraction module 100 is connected to the central controller 90 via a ribbon cable or backplane connector. The central controller 90 directly pushes the acquired multimodal discrete data to the internal data processing unit for feature processing. The pin output terminals of the central controller 90 are connected to the configuration pins of the field-programmable gate array chip 110. Based on the results calculated by the data processing unit, the central controller 90 sends a level signal to the field-programmable gate array chip 110 to change the frequency division coefficient, triggering the sampling rate reconstruction action of the underlying hardware, and the actual sampling frequency of the analog-to-digital converter array 120. The clock division logic of the field-programmable gate array chip 110 satisfies the following formula:

[0089]

[0090] In the formula, The high-frequency reference clock frequency output by the clock management circuit 111 The frequency division coefficient is dynamically configured by instructions from the central controller 90.

[0091] Example 3

[0092] See attached document Figure 3-4 Based on Embodiment 1, step S200, the basic data acquisition and feature space mapping, includes the following steps:

[0093] In step S210, the clock management circuit 111 inside the field-programmable gate array chip 110 generates and distributes a global synchronization clock signal to the analog-to-digital converter array 120. The clock management circuit 111 uses its internal crystal oscillator to provide a basic reference clock. The clock management circuit 111 performs frequency multiplication and phase alignment processing on the basic reference clock through the phase-locked loop 112 and outputs a high-frequency reference clock signal. The field-programmable gate array chip 110 uses its internal global clock network to fan out the high-frequency reference clock signal to multiple independent clock output pins of the field-programmable gate array chip 110. Each clock output pin is connected to the clock input terminal of each analog-to-digital converter chip in the analog-to-digital converter array 120 using an equal-length trace routing method to eliminate clock skew caused by parasitic capacitance and inductance of the printed circuit board traces.

[0094] In step S220, after receiving the global synchronization clock signal, the analog-to-digital converter array 120 synchronously discretizes the physical environment signal at the inverter operating node 30 at a preset basic sampling frequency. During the steady-state operation of the inverter, the central controller 90 writes the steady-state frequency divider register value to the field-programmable gate array chip 110. The field-programmable gate array chip 110 performs a frequency division operation on the high-frequency reference clock signal according to the steady-state frequency divider register value, generating a basic sampling clock pulse to trigger the analog-to-digital converter array 120. The continuous analog signals output by the sensors of various modes at the inverter operating node 30, including the voltage transformer 41, current transformer 42, piezoelectric mechanical vibration sensor 43, and infrared temperature sensor 44, are simultaneously captured by the sample-and-hold circuit inside the analog-to-digital converter array 120 at the same effective edge of the basic sampling clock pulse. The aforementioned hardware parallel capture process aligns the multi-modal data with different physical characteristics on the physical time axis, thereby converting them into a discrete multi-dimensional time series matrix. ,matrix The dimension is ,in This represents the total number of sensor modal channels connected. This represents the total number of sampling points within the current time window.

[0095] In step S230, the programmable gain amplifier circuit 130 maintains the amplitude of the analog signal by adjusting the basic gain during steady-state acquisition. The field-programmable logic gate and array chip 110 write a steady-state resistance control word to the digital potentiometer 131 within the programmable gain amplifier circuit 130 via the serial peripheral interface bus. The programmable gain amplifier circuit 130 selects the corresponding channel of the multiplexed switching network 132 according to the steady-state resistance control word, sets the feedback resistor network of the operational amplifier, and amplifies the analog signals from each mode sensor to match the amplitude range of the full-scale input voltage of the analog-to-digital converter array 120. The steady-state gain coefficient of each mode channel is set to... The initial analog voltage input to the sensor is The conditioned voltage actually received by the analog-to-digital converter array 120 Satisfying the formula:

[0096]

[0097] In the formula, The fixed DC offset voltage is introduced by the hardware circuit bias. The aforementioned fixed DC offset voltage is measured and recorded during the factory calibration stage.

[0098] In step S240, the field-programmable gate array chip 110 converts the multidimensional time series matrix. The data is pushed to the central controller 90 via direct memory access (DMI) mechanism. The field-programmable gate array (FPGA) chip 110 is internally configured with a first-in-first-out (FIFO) memory logic core 113. The digital signals output by each analog-to-digital converter (ADC) chip are encapsulated and cached in the FIFO memory logic core 113. Since the internal data processing unit 93 is configured within the central controller 90 as a single physical entity, the main control logic circuit of the central controller 90 directly allocates a continuous system memory address to map the aforementioned multi-dimensional time series matrix. When the amount of data in the first-in-first-out memory logic core 113 reaches a preset single-transmission threshold, the field-programmable gate array chip 110 sends an interrupt request to the direct memory access controller of the central controller 90 via the data bus. The direct memory access controller then takes over bus control and moves the cached multidimensional time series matrix... The data is directly moved to the memory address allocated inside the central controller 90. The data processing unit 93 inside the central controller 90 calls the orthogonal principal component analysis algorithm code to process the multidimensional time series matrix. The mean-free process is performed and the covariance matrix is ​​calculated. Then, eigenvalue decomposition is performed to extract the corresponding eigenvalues ​​with the largest values. Construct a projection matrix of dimension M×d from eigenvectors. The data processing unit (93) processes the multidimensional time series matrix. With projection matrix The transpose of the vector is used for matrix multiplication to map the signals acquired by the basic sensor to a low-dimensional feature manifold, ultimately generating and outputting a set of feature vectors corresponding to the current time window. .

[0099] Furthermore, in step S300, the calculation of the information temperature includes the following steps:

[0100] Step S310, the data processing unit 93, based on the feature vector set Physical calculation of global semantic variance Global semantic variance To quantify the overall discrete fluctuation of the inverter's operating node state within the current time window, the data processing unit 93 traverses the feature vector set. All feature points are vector-added using an internal accumulator, and the accumulated result is divided by the total number of sampling points. Obtain the geometric mean center vector of the high-dimensional characteristic manifold. The data processing unit 93 calls the hardware multiplier to calculate the geometric mean center vector of each eigenvector. The data processing unit 93 calculates the square of the Euclidean distance between the values, performs summation and averaging operations on all the obtained squares, and generates and writes the global semantic variance into the on-chip register. The specific calculation formula and the interpretation of the symbols in the formula are the same as those in the aforementioned step S300, and will not be repeated here;

[0101] In step S320, data processing unit 93 constructs a spatial index structure and calculates the local manifold density. Local manifold density The data processing unit 93 represents the degree of clustering of system characteristic states in phase space as a set of feature vectors in system memory. Dynamically construct a K-dimensional tree data index structure for a set of feature vectors. For each benchmark point, data processing unit 93 traverses the K-dimensional tree to... Search in 3D space for the closest Euclidean distance to the aforementioned benchmark test point. For each neighboring point, generate the corresponding nearest neighbor set. The arithmetic logic unit 92 inside the data processing unit 93 calculates the aforementioned benchmark test point and nearest neighbor set. The average spatial distance between all points within the data processing unit 93 traversed all points. The average distance between each feature point is obtained. The reciprocal of the average distance is then calculated using a hardware divider to generate and output the local manifold density. The specific calculation formula and the interpretation of the symbols in the formula are the same as those in step S300 above, and will not be repeated here;

[0102] In step S330, the central controller 90 accurately calculates the information temperature scalar using the extracted feature measurement data. The data processing unit 93 will calculate the extracted global semantic variance. The local manifold density will be acquired synchronously as the dividend. As the divisor, the data processing unit 93 executes the underlying hardware-level floating-point division instruction to perform global semantic variance. Divide by local manifold density Accurately calculate the temperature information that characterizes the current topology state of the working node. ,Right now ,in, To prevent a smoothing minimum constant with a denominator of zero, when the inverter is in normal steady state, the multidimensional feature points exhibit high-density clustering and the overall fluctuation is extremely low, generating a global semantic variance. Low numerical value and local manifold density A higher numerical value indicates a higher temperature reading. Maintaining within the safe lower limit range, when the system experiences high-frequency transient switching or early weak fault disturbances, local topology breaking leads to a decrease in manifold density, and a surge in overall divergence leads to an increase in global semantic variance. The information temperature obtained from division operations... The increase is non-linear, providing a basis for triggering judgments for subsequent determination of hardware reconfiguration of the multimodal acquisition system.

[0103] Furthermore, in step S400, the spatial gradient calculation and feedforward command issuance specifically include the following steps:

[0104] In step S410, the central controller 90 of each inverter working node 30 synchronizes the real-time calculated information temperature to the cloud-native cluster management terminal 20 of the cloud-native cluster environment 10. The direct memory access controller inside the central controller 90 extracts the information temperature scalar value stored in the on-chip register and writes it into the transmission buffer of the network controller 97 according to the preset synchronization cycle. The network controller 97 packages the aforementioned information temperature scalar value, working node identification code and hardware timestamp into an industrial communication data frame and sends it to the server array 21 of the cloud-native cluster management terminal 20 via the optical fiber ring network.

[0105] In step S420, the cloud-native cluster management terminal 20 establishes and maintains the topology distance matrix of the inverter array in memory space. The server array 21 of the cloud-native cluster management terminal 20 reads the system topology configuration file. The aforementioned system topology configuration file records the electrical connection line impedance parameters and spatial physical straight-line distance parameters between all inverter working nodes 30 in the cluster. The server array 21 uses the underlying floating-point arithmetic unit to perform linear weighted calculation with the electrical connection line impedance parameters between nodes as the primary weight and the spatial physical straight-line distance parameters as the secondary weight, to generate the comprehensive topology distance parameters between any two inverter working nodes 30, and sets the working nodes. With working nodes The impedance parameters of the electrical connection lines between them are The spatial physical straight-line distance parameter is The impedance weighting coefficient is The distance weighting coefficient is And impedance weighting coefficient With distance weight coefficient satisfy The generated comprehensive topological distance parameters The calculation formula is:

[0106]

[0107] Server array 21 iterates through all worker node combinations, sequentially writing all calculated comprehensive topological distance parameters into contiguous memory addresses, forming a structure with dimension [missing information]. Symmetric topological distance matrix ,in The total number of inverter worker nodes within a cloud-native cluster environment (10);

[0108] In step S430, the cloud-native cluster management terminal 20 calculates the spatial gradient vector of information temperature between adjacent nodes. The processor of the server array 21 extracts the information temperature of the source working node and the information temperature of the topologically adjacent target working node, executes a subtraction instruction to obtain the temperature difference between the two, and the processor retrieves the topological distance matrix based on the node identifier code. The corresponding comprehensive topological distance parameter is used to divide the temperature difference by the aforementioned comprehensive topological distance parameter using a hardware divider, generating a directional temperature spatial gradient vector. The specific calculation formula and the interpretation of the symbols in the formula are the same as those in step S400 above. The magnitude of the aforementioned information temperature spatial gradient vector represents the propagation potential energy of electrical or physical abnormal disturbances of the inverter in the topology network.

[0109] In step S440, the cloud-native cluster management terminal 20 aggregates spatial gradient vectors to generate a global information temperature spatial gradient field and performs dynamic updates. The server array 21 maps the calculated information temperature spatial gradient vectors between all adjacent nodes to a matrix derived from the topological distance matrix. In the constructed virtual multidimensional spatial coordinate system, a global information temperature spatial gradient field matrix is ​​generated. Global information temperature space gradient field matrix for Mathematical matrix of dimension, matrix The first in Line 1 The values ​​of the columns correspond to the calculated source worker nodes. Point to adjacent target working node Information temperature space gradient vector The aforementioned matrix Non-zero elements in the matrix represent gradient vectors between nodes with direct topological connections. The server array 21 of the cloud-native cluster management terminal 20 continuously receives the latest information temperature reported by each inverter working node 30 in a high-frequency polling manner, and writes the new data into the computation buffer using direct memory overwrite operations, cyclically triggering arithmetic logic operations from steps S420 to S440. The aforementioned cyclic operation mechanism maintains the information temperature spatial gradient field matrix. Strict synchronization with the underlying physical environment establishes a feedforward control data benchmark for determining the propagation of physical disturbances across nodes;

[0110] Step S450: The server array 21 of the cloud-native cluster management terminal 20 traverses the global information temperature spatial gradient field matrix. The numerical elements in the matrix are compared using spatial gradient thresholds, and the comparator logic core 22 inside the server array 21 reads the matrix. Non-zero information temperature space gradient vector The comparator logic core 22 will extract the information temperature spatial gradient vector. The magnitude and the preset spatial gradient feedforward safety threshold Perform numerical judgment operations, and when the feedforward triggering condition is met. At that time, server array 21 determines that the source inverter working node The generated physical anomalies are propagating along the electrical interconnection topology towards the target inverter operating node. spread;

[0111] In step S460, in response to the aforementioned comparison and judgment result, server array 21 generates a feedforward cooperative sampling command containing disturbance dominant mode information, and server array 21 retrieves the source inverter working node. The feature space dimension calculation parameters are reported synchronously, and the discrete contribution values ​​of each physical sensing mode within the current time window are extracted. The specific calculation formula is as follows: In the formula, For the first The discrete contribution value of each sensing mode. This represents the total number of sampling points within the time window. For the first The sensing mode in the first... Data values ​​at each sampling time, For the first The average data of each sensing mode within the time window;

[0112] Server array 21 uses a sorting algorithm to select the sensing mode component with the largest discrete contribution value, and identifies the sensing mode with the largest discrete contribution value as the disturbance-dominant mode. Server array 21 then targets the inverter working node. The media access control address identifier, system-level trigger action identifier, and the aforementioned disturbance dominant mode field are concatenated into underlying binary data bits to construct a feedforward cooperative sampling data packet;

[0113] In step S470, the cloud-native cluster management terminal 20 sends the feedforward collaborative sampling data packet to the target inverter working node 30 through the industrial communication network. The network switching device 23 of the cloud-native cluster management terminal 20 identifies the medium access control address identifier code in the data packet and establishes a point-to-point downlink transmission link. The feedforward collaborative sampling data packet is transmitted to the physical port of the network controller 97 of the target inverter working node 30 via the optical fiber ring network. The network controller 97 performs hardware-level cyclic redundancy check on the received bit stream. After confirming that the data frame is complete and no bit flip error has occurred, the network controller 97 extracts the payload and writes it into the first-in-first-out receive buffer 98 inside the network controller 97.

[0114] In step S480, the central controller 90 of the target inverter working node 30 parses the feedforward cooperative sampling data packet and performs a cross-node feedforward triggering operation. The central controller 90 extracts the data in the first-in-first-out receive buffer 98 of the network controller 97 through the internal system bus. The instruction decoding circuit 99 inside the central controller 90 restores the extracted data frame and parses out the trigger action identifier and the disturbance dominant mode field. Taking advantage of the high speed of the fiber optic ring network transmission and the time difference between the high speed and the hysteresis of the physical disturbance propagation, before the physical disturbance at the source actually affects the target inverter working node 30 and causes the sensor configured inside the target inverter working node 30 to produce an abnormal response, the central controller 90 outputs a level trigger signal with the aforementioned disturbance dominant mode identifier to the internally connected multi-mode data continuous extraction module 100. The aforementioned level trigger signal instructs the local hardware to perform hardware reconfiguration intervention operation under the drive of the feedforward instruction.

[0115] Furthermore, in step S500, the closed-loop reconstruction of the underlying sampling parameters and resources specifically includes the following steps:

[0116] In step S510, the central controller 90 determines the dominant mode for hardware resource reallocation based on the locally calculated temperature surge state or the received feedforward cooperative sampling command. The data processing unit 93 within the central controller 90 extracts the discrete contribution values ​​of each sensing mode. The data processing unit 93 uses the discrete contribution values ​​of each sensing mode to calculate the resource allocation weight coefficient for each mode, setting the total number of modes to [value missing]. , No. The discrete contribution value of each sensing mode is Then the first Resource allocation weight coefficients for each sensing mode The calculation formula is:

[0117]

[0118] In the formula, For summation traversal indexes of sensing modes;

[0119] The central controller 90 will include resource allocation weighting coefficients. The redistribution control word of the dominant mode identifier is sent to the field programmable gate array chip 110 via the internal communication bus;

[0120] In step S520, the field-programmable gate array (FPGA) chip 110 parses the reallocation control word and performs weighted dynamic cache reallocation on the cache resource pool composed of internal static random access memory. The memory management logic core 114 inside the FPGA chip 110 reads the base address and offset of the currently allocated cache block for each mode. The memory management logic core 114 keeps the total cache capacity limit unchanged and performs reallocation according to the resource allocation weight coefficient. The depth parameters of the first-in-first-out memory logic core 113 corresponding to each mode are dynamically adjusted, and the total cache capacity of the field-programmable gate array chip 110 is set to [value missing]. , No. The target cache capacity after sensor mode reallocation is: Then the formula is satisfied:

[0121]

[0122] In the formula, This indicates a round-down operation. For the cache capacity surplus generated by the round-down operation, the storage management logic core 114 will fully compensate and allocate the aforementioned cache capacity surplus to the resource allocation weight coefficient. The dominant mode is the one that maintains the zero-sum conservation of total cache capacity.

[0123] In step S530, the field-programmable gate array (FPGA) chip 110 performs a low-level physical address mapping change. The FPGA chip 110 reduces the cache space configuration of the non-dominant mode and simultaneously maps the address of the released static random access memory (SRAM) physical block to the storage control domain of the dominant mode. Through a dynamic time-division multiplexing mechanism, the FPGA chip 110 reduces the cache resources of low-frequency change modes such as thermodynamics or mechanical vibration without adding additional hardware storage elements. The released SRAM physical block is directly injected into the dominant mode channel of high-frequency change such as electrical, so as to meet the data throughput requirements generated by the high-frequency broadband sampling of the dominant mode.

[0124] In step S540, the field-programmable gate array (FPGA) chip 110 synchronously performs cross-modal zero-sum scheduling on the communication time slices of the direct memory access bus. The FPGA chip 110 is internally configured with a time-division multiplexing polling arbitrator 115. The time-division multiplexing polling arbitrator 115 manages the data transmission link from the FPGA chip 110 to the central controller 90. Within a fixed-length bus scheduling cycle, the time-division multiplexing polling arbitrator 115 allocates resources based on the resource allocation weight coefficients. Allocate a valid number of transmission clock cycles to each sensing mode, and set the total number of clock cycles for the bus scheduling cycle to [value missing]. , No. The number of clock cycles obtained from the sensor mode allocation is Then the formula is satisfied:

[0125]

[0126] Similarly, the time-division multiplexing polling arbitrator 115 adds the remaining clock cycle value generated by rounding down the aforementioned formula to the time slice allocation register corresponding to the dominant mode as compensation.

[0127] Step S550, the time-division multiplexing polling arbitrator 115 determines the number of clock cycles. The frequency of data transmission on the control bus is reduced by the time-division multiplexing polling arbitrator 115, which reduces the transmission frequency of non-dominant mode data frames on the bus and increases the occupation time of dominant mode data frames. Through the aforementioned dual zero-sum allocation strategy of storage and bandwidth, the multimodal data continuous extraction module 100 is kept from data overflow and link blockage under high overall communication bandwidth load.

[0128] In step S560, the field-programmable gate array (FPGA) chip 110 parses the reconstruction instruction and determines the dynamic amplification factor parameter. The central controller 90 sends a low-level hardware reconfiguration instruction to the FPGA chip 110 via the internal bus. The control state machine 116 inside the FPGA chip 110 extracts the target mode identifier and frequency multiplication factor contained in the aforementioned low-level hardware reconfiguration instruction. The FPGA chip 110 determines the corresponding target sampling frequency based on the aforementioned frequency multiplication factor. For the signal amplitude attenuation phenomenon caused by the shortened sampling and holding time in the transient high-frequency sampling mode, the FPGA chip 110 synchronously calculates the dynamic gain adjustment amount to compensate for the aforementioned amplitude attenuation, setting the frequency multiplication factor to... The preset amplitude compensation constant is The target modal steady-state gain coefficient is The dynamic gain coefficient after target mode reconstruction The calculation formula is: The field-programmable gate array chip 110 will calculate the obtained dynamic gain coefficient. Convert it to the corresponding serial peripheral interface bus control word;

[0129] In step S570, the programmable gain amplifier circuit 130 performs the amplification factor switching of the target mode hardware channel. The field programmable gate array chip 110 sends the aforementioned serial peripheral interface bus control word to the programmable gain amplifier circuit 130 corresponding to the target mode. The digital potentiometer 131 inside the programmable gain amplifier circuit 130 responds to the aforementioned control word and changes the access position of the sliding terminal to adjust the equivalent resistance value of the access multiplexer switch network 132. The aforementioned resistance change directly changes the attenuation ratio of the negative feedback network loop of the operational amplifier, increasing the amplification factor of the target mode analog signal from the steady-state gain coefficient to the dynamic gain coefficient. For the specific circuit connection structure of the digital potentiometer's resistance step response and the operational amplifier feedback network, those skilled in the art can refer to the standard analog front-end design specifications for implementation. The construction of the aforementioned analog signal conditioning circuit is a well-known technology in this field and will not be described in detail here.

[0130] In step S580, the clock management circuit 111 performs high-frequency resampling clock configuration on the analog-to-digital converter channel corresponding to the target mode. The field-programmable gate array chip 110 sends a frequency division coefficient update pulse to the phase-locked loop 112 in the clock management circuit 111. The clock management circuit 111 maintains the basic reference clock frequency at the input of the phase-locked loop 112 unchanged. By modifying the reload value of the programmable counter, the clock division ratio output to the analog-to-digital converter array 120 corresponding to the target mode is reduced, and the steady-state frequency division coefficient is set to [value missing]. The dynamic frequency division coefficients corresponding to the target mode The calculation formula is:

[0131]

[0132] In the formula, Indicating a round-down operation, the clock management circuit 111 writes the aforementioned dynamic frequency division coefficient into the corresponding channel register. The conversion chip in the analog-to-digital converter array 120 corresponding to the target mode then performs the rounding based on the increased actual dynamic sampling frequency. Running, actual dynamic sampling frequency The above-mentioned actual sampling frequency calculation logic is satisfied, namely the high-frequency reference clock frequency. With dynamic frequency division coefficient The ratio of the aforementioned clock configuration causes the target mode to switch from the steady-state basic low-frequency sampling mode to the broadband high-frequency sampling mode;

[0133] In step S590, the field-programmable gate array (FPGA) chip 110 performs cross-modal clock synchronization compensation and steady-state recovery. Since different modes use different sampling clock frequencies after reconstruction, the FIFO memory core 113 inside the FPGA chip 110 adds a relative hardware timestamp based on the high-frequency clock cycle to the data frame acquired by the target mode channel. When splicing multidimensional tensors, the data processing unit 93 in the central controller 90 uses the aforementioned relative hardware timestamp to align the high-frequency discrete sequence with the unreconstructed low-frequency steady-state sequence in the physical time dimension. The data processing unit 93 uses the relative hardware timestamp of the high-frequency discrete sequence as the reference time axis. The system performs zero-order hold or linear interpolation on the unreconstructed low-frequency steady-state sequence to generate data nodes with uniform high time resolution, achieving mathematical alignment of multi-resolution sequences before matrix splicing. When the central controller 90 detects that the information temperature scalar value has fallen back to the preset safe range, or the internal hardware timer has reached the upper limit of the preset transient capture time window, the central controller 90 sends a system recovery command to the field programmable gate array chip 110. The field programmable gate array chip 110 resets the control state machine 116 and forces the frequency division coefficient of the clock management circuit 111 and the gain parameter of the programmable gain amplifier circuit 130 back to the steady-state initial value.

[0134] Furthermore, in step S600, tensor reconstruction and CNN state diagnosis classification specifically include the following steps:

[0135] In step S610, the data processing unit 93 inside the central controller 90 receives the heterogeneous data sequence extracted from the underlying layer and performs time-domain analysis. The data processing unit 93 reads the discrete data packets uploaded by the multimodal data continuous extraction module 100 from the memory address. The data processing unit 93 parses the frame header of the aforementioned discrete data packets, extracts the relative hardware timestamp sequence and hardware reconfiguration flag bit corresponding to each sensing mode, and the data processing unit 93 divides the sequence in the data buffer into a steady-state mode sequence that maintains basic low-frequency sampling and a transient mode sequence that is in a broadband high-frequency sampling state according to the aforementioned hardware reconfiguration flag bit.

[0136] In step S620, the data processing unit 93 performs time-domain interpolation alignment on the steady-state mode sequence using the relative hardware timestamp of the transient mode sequence as the reference axis. The transient mode sequence has higher time resolution and denser sampling points. The arithmetic logic unit 92 inside the data processing unit 93 traverses the time interval between two adjacent sampling points of the steady-state mode sequence and inserts virtual data nodes matching the timestamp of the transient mode sequence within the aforementioned time interval between two adjacent sampling points. The target alignment timestamp on the reference axis is set as... In the steady-state mode sequence and Two adjacent original timestamps are and And satisfy The modal channel identifier of the steady-state modal sequence is set as... The sampled values ​​at the corresponding times are respectively and The value of the inserted virtual data node Satisfies the linear interpolation formula:

[0137]

[0138] The data processing unit 93 uses the aforementioned interpolation operation to increase the number of data points and physical time scale of all steady-state mode sequences to a state aligned with the transient mode sequences, thereby eliminating time-domain misalignment caused by sampling rate differences between multi-mode channels;

[0139] In step S630, the data processing unit 93 performs physical dimension elimination and amplitude normalization operations on each aligned modal sequence. Different physical modes, such as voltage, current, vibration, and temperature, have numerical ranges with orders of magnitude differences. The data processing unit 93 suppresses the dominant effect of wide-amplitude modes during matrix multiplication accumulation through normalization operations. The data processing unit 93 calculates the arithmetic mean and standard deviation of each modal sequence within the current time window. The data processing unit 93 subtracts the corresponding arithmetic mean from each data node in the sequence and divides the difference by the standard deviation, setting the... The modality at time... The normalized value is The aligned sequence values ​​are The sequence mean is The standard deviation is Then the formula is satisfied:

[0140]

[0141] The aforementioned normalization process maps each modal data to a dimensionless numerical space that follows a standard normal distribution;

[0142] In step S640, the data processing unit 93 fuses and reconstructs the normalized sequence into a three-dimensional dynamic tensor along a preset feature dimension. The data processing unit 93 allocates a multi-dimensional matrix space in the register of the tensor processing core 91. The data processing unit 93 uses the time scale as the first dimension column index of the tensor, the physical sensor mode as the second dimension row index, and the resolution level as the third dimension depth index. The total number of aligned time nodes is set to... The total number of connected physical sensor modes is The total number of resolution levels is The aforementioned resolution levels include two fixed levels: a fundamental low-frequency level and a broadband high-frequency level. The data processing unit 93 maps the interpolated sequence at the basic low-frequency sampling level to the depth plane corresponding to the basic resolution level. The data processing unit 93 simultaneously maps the transient mode sequence at the broadband high-frequency sampling level to the depth plane corresponding to both the basic resolution level and the high-frequency resolution level. The data processing unit 93 automatically fills the high-frequency resolution depth plane region corresponding to the steady-state mode that has not undergone hardware reconstruction with zero values. The data processing unit 93 generates a three-dimensional dynamic tensor containing the time dimension, modal dimension, and resolution level dimension. 3D dynamic tensor The dimensions are fixed as 3D dynamic tensor This forms the standard input data structure for the subsequent forward propagation of the convolutional neural network.

[0143] In step S650, the data processing unit 93 processes the aforementioned reconstructed three-dimensional dynamic tensor The input is fed into the convolutional neural network model 200, which contains multiple parallel convolutional branch networks. Different convolutional branch networks are configured with convolutional kernels of different sizes to form differentiated receptive fields. Specifically, it includes a first convolutional branch network 210 configured with small-sized convolutional kernels to extract micro-temporal abrupt change features, and a second convolutional branch network 220 configured with large-sized convolutional kernels to extract macro-trend features. For the initial setting of convolutional kernel parameters and the mapping calculation of specific receptive field size, those skilled in the art can refer to the standard deep learning network structure design specifications for implementation. The aforementioned convolutional kernel configuration method is a well-known technology in this field and will not be described in detail here.

[0144] In step S660, the gated logic core performs dynamic routing allocation in response to the information temperature scalar. The front end of the convolutional neural network model 200 is configured with a temperature-sensing gated routing operator 230. The data processing unit 93 inputs a three-dimensional dynamic tensor into the convolutional neural network model 200. During the synchronization phase, the temperature scalar information calculated within the time window is... The input is sent to the temperature-sensing gating routing operator 230, which then converts the temperature information into a scalar value. As a system state metric, the incoming three-dimensional dynamic tensor Perform gated dynamic routing, setting a preset temperature gating safety threshold. The routing control vector output by the temperature-sensing gated routing operator 230 is: When the information temperature scalar At that time, the routing control vector output by the temperature-sensing gated routing operator 230 When the information temperature scalar At that time, the temperature-sensing gated routing operator 230 uses a smooth activation function to calculate continuous routing control vectors. ,in , , To smooth the scaling factor, the activation weights of the network branches are calculated using this continuous probability distribution, so that the activation weights of the network branches smoothly and adaptively change with the degree of temperature anomaly.

[0145] In step S6601, the data processing unit 93 performs the combination of the routing vector and the input tensor through the underlying tensor arithmetic multiplication, and sets the actual input tensor of the first convolutional branch network 210 as... The actual input tensor of the second convolutional branch network 220 is Then, data processing unit 93 executes the following scalar and tensor multiplication logic:

[0146]

[0147]

[0148] Through the aforementioned multiplication logic, the data processing unit 93 converts the value of the routing control vector into the activation or suppression signal of the underlying matrix channel, thereby completing the hard data routing action.

[0149] In step S670, the active convolutional branch network performs two-dimensional and one-dimensional convolution operations on the corresponding input tensor. The active convolutional branch network extracts local correlation features and performs dimensionality reduction through the corresponding pooling layer 250 to generate a deep feature mapping matrix. The data processing unit 93 performs a flattening operation on the aforementioned deep feature mapping matrix to convert the two-dimensional or three-dimensional feature space into a one-dimensional hidden layer feature vector. ;

[0150] Step S680: The normalized activation function outputs the final state diagnosis result, and the hidden layer feature vector. Dimensional mapping is performed via a fully connected layer 260, which includes a weight matrix and a bias vector. The mapped result is input to a normalized activation function for probability calculation. The data processing unit 93 outputs a classification label vector indicating the operating status and fault type of the inverter's working node 30 through the normalized activation function. Classification label vector Satisfy the following formula: In the formula, This is the weight matrix of the fully connected layer 260. This is the bias vector for the fully connected layer 260. The data processing unit 93 uses the Softmax normalized activation function based on the classification label vector. The index of the element with the highest probability value is used to determine and output the final system status diagnosis result.

Claims

1. A method for multimodal data acquisition and processing of inverters based on convolutional neural networks, relying on a cloud-native cluster environment (10), and constructing a closed-loop control system that links physical underlying acquisition parameters and feature space information measurement through hardware modules for data acquisition and processing, wherein the cloud-native cluster environment (10) includes a cloud-native cluster management terminal (20) and multiple working nodes (30), characterized in that, The method includes the following steps: Step S100: Deploy a multimodal data continuous extraction module (100) on each working node (30) of the cloud-native cluster environment (10) and configure a central controller (90) that integrates an internal data processing unit (93). In step S200, the multimodal data continuous extraction module (100) acquires the physical environment signal of the corresponding working node (30) at a preset basic sampling frequency and converts it into a feature vector set. ; In step S300, the central controller (90) uses the data processing unit (93) to calculate the global semantic variance and local manifold density of the feature vector set within the current time window, and calculates the information temperature of the working node using the ratio of the two. ; Step S400: The cloud-native cluster management terminal (20) receives the information temperature sent by the working node (30) and calculates the spatial gradient. When the gradient meets the set conditions, it issues a feedforward collaborative sampling instruction. In step S500, the multimodal data continuous extraction module (100) responds to local information temperature change or feedforward collaborative sampling command and performs closed-loop reconstruction of the underlying sampling parameters; In step S600, the data processing unit (93) reconstructs the multi-resolution tensor and inputs it into the convolutional neural network model (200) to output the inverter operating status.

2. The method for acquiring and processing multimodal data of an inverter based on a convolutional neural network according to claim 1, characterized in that, Step S200 specifically includes: In step S210, the clock management circuit (111) inside the field programmable gate array chip (110) generates and distributes a global synchronization clock signal to the analog-to-digital converter array (120); In step S220, after receiving the global synchronization clock signal, the analog-to-digital converter array (120) performs synchronous discretization conversion on the physical environment signal at the inverter working node (30) at a preset basic sampling frequency, and then converts it into a discrete multi-dimensional time series matrix. ; In step S230, the programmable gain amplifier circuit (130) maintains the amplitude of the analog signal by adjusting the base gain multiple during steady-state acquisition; In step S240, the data processing unit (93) inside the central controller (90) calls the orthogonal principal component analysis algorithm code to process the multidimensional time series matrix. The mean-free process is performed and the covariance matrix is ​​calculated. Then, eigenvalue decomposition is performed to extract the corresponding eigenvalues ​​with the largest values. Construct a projection matrix of dimension M×d from eigenvectors. The data processing unit (93) processes the multidimensional time series matrix. With projection matrix The transpose of the vector is used for matrix multiplication to map the signals acquired by the basic sensor to a low-dimensional feature manifold, ultimately generating and outputting a set of feature vectors. .

3. The method for multimodal data acquisition and processing of inverters based on convolutional neural networks according to claim 1, characterized in that, Step S300 specifically includes: Step S310, the data processing unit (93) calculates the global semantic variance. The calculation formula is: ， In the formula, For the set of feature vectors The mean vector, Denotes the Euclidean norm. For the first One feature point, This represents the total number of sampling points; Step S320, the data processing unit (93) constructs the spatial index structure and calculates the local manifold density. The calculation formula is: In the formula, The set number of nearest neighbor nodes, Represents the midpoint of the feature space of The set of nearest neighbors For feature points Its nearest neighbor The Euclidean distance between them; In step S330, the data processing unit (93) calculates the global semantic variance. Divide by local manifold density Accurately calculate the temperature information that characterizes the current topology state of the working node. ,Right now ,in, To prevent smooth minimum constants with denominators of zero.

4. The method for acquiring and processing multimodal data of an inverter based on a convolutional neural network according to claim 1, characterized in that, The calculation of the spatial gradient in step S400 specifically includes: In step S420, the server array (21) of the cloud-native cluster management terminal (20) traverses all worker node combinations to generate comprehensive topology distance parameters. The calculation formula is: ， In the formula, These are the impedance parameters of the electrical connection lines. For the straight-line distance parameter in space physics, and the impedance weighting coefficient. With distance weight coefficient satisfy ; Step S430, server array (21) extracts source worker node Information temperature With the target working node Information temperature Calculate the spatial gradient vector of temperature information. ; Step S440: The server array (21) aggregates the spatial gradient vectors, generates and updates the global information temperature spatial gradient field matrix in real time. .

5. The method for multimodal data acquisition and processing of inverters based on convolutional neural networks according to claim 1, characterized in that, The specific steps in step S400, including issuing the feedforward collaborative sampling command, include: Step S450, the comparator logic core (22) converts the information temperature spatial gradient vector The magnitude and the preset spatial gradient feedforward safety threshold Perform numerical judgment; Step S460: When the feedforward triggering condition is met, extract the discrete contribution values ​​of each physical sensing mode within the current time window. The sensing modes with the largest discrete contribution values ​​are selected by sorting algorithm and identified as the perturbation-dominant modes, and then feedforward cooperative sampling data packets are constructed. In step S480, the central controller (90) of the target inverter working node (30) parses the feedforward cooperative sampling data packet and outputs a level trigger signal with the disturbance dominant mode identifier to the internally connected multi-mode data continuous extraction module (100).

6. The method for multimodal data acquisition and processing of inverters based on convolutional neural networks according to claim 1, characterized in that, The closed-loop reconstruction of the underlying sampling parameters in step S500 includes hardware resource reallocation, specifically including: In step S520, the field-programmable gate array chip (110) parses the reallocation control word and performs weighted dynamic cache reallocation on the internal cache resource pool according to the resource allocation weight coefficient. Adjust the depth parameters of the first-in-first-out memory logic core (113) corresponding to each mode, and allocate the cache capacity surplus generated by rounding down to the dominant mode; In step S540, the field programmable gate array chip (110) synchronously performs cross-modal zero-sum scheduling on the communication time slice of the direct memory access bus, and the time-division multiplexing polling arbitrator (115) allocates the number of valid transmission clock cycles for each sensing mode and compensates the remaining clock cycle value generated by rounding down to the dominant mode.

7. The method for multimodal data acquisition and processing of inverters based on convolutional neural networks according to claim 1, characterized in that, The closed-loop reconstruction of the underlying sampling parameters in step S500 also includes: Step S560: The field-programmable gate array chip (110) determines the dynamic gain coefficient after the target mode reconstruction. ; In step S570, the programmable gain amplifier circuit (130) increases the amplification factor of the target modal analog signal from the steady-state gain coefficient to the dynamic gain coefficient; In step S580, the clock management circuit (111) reduces the clock division ratio of the output to the analog-to-digital converter array (120) corresponding to the target mode, and the actual dynamic sampling frequency... Meets the high-frequency reference clock frequency With dynamic frequency division coefficient The ratio of .

8. The method for acquiring and processing multimodal data of an inverter based on a convolutional neural network according to claim 1, characterized in that, The reconstruction of the multi-resolution tensor in step S600 specifically includes: In step S620, the data processing unit (93) performs a linear interpolation alignment operation on the steady-state mode sequence with the relative hardware timestamp of the transient mode sequence as the reference axis; In step S630, the data processing unit (93) performs physical dimension elimination and amplitude normalization operations on each aligned modal sequence; In step S640, the data processing unit (93) fuses and reconstructs the normalized sequence into a three-dimensional dynamic tensor along the preset feature dimension. Its dimensions are fixed. .

9. The method for acquiring and processing multimodal data of an inverter based on a convolutional neural network according to claim 8, characterized in that, The input to the convolutional neural network model in step S600 specifically includes: In step S650, a first convolutional branch network (210) with small-sized convolutional kernels and a second convolutional branch network (220) with large-sized convolutional kernels are configured. In step S660, the temperature-sensing gating routing operator (230) transmits the information temperature scalar As a system state metric, the incoming three-dimensional dynamic tensor Perform gated dynamic routing; In step S6601, the data processing unit (93) executes the routing control vector through the underlying tensor arithmetic multiplication. With three-dimensional dynamic tensors The combination of these signals is transformed into activation or inhibition signals for the underlying matrix channels.

10. The method for acquiring and processing multimodal data of an inverter based on a convolutional neural network according to claim 9, characterized in that, The operating status of the output inverter specifically includes: In step S670, the activated convolutional branch network performs convolution operations on the corresponding input tensor to extract local correlation features, generates a deep feature mapping matrix, and performs a flattening operation to convert it into a one-dimensional hidden layer feature vector. ; Step S680, hidden layer feature vector After dimensionality mapping via a fully connected layer (260), the input is fed into a normalized activation function to calculate the probability, and the output is a classification label vector. Then, the final system state diagnosis result is determined based on the index of the element with the highest probability value.

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