Communication method and communication system for a parallel single-stage inverter based on a dual active bridge

Abstract

The application provides a communication method and a communication system of a parallel single-stage inverter based on a dual active bridge, and the method comprises the following steps: a host machine issues a control frame of a current period to a slave machine corresponding to each inverter through an FSI; a DMA controller of the slave machine byte by byte carries and stores the received control frame into a background buffer; at the starting moment of a next control period, the slave machine CPU switches the original background buffer to a foreground buffer and switches the original foreground buffer to a background buffer, so that the DMA controller starts to receive the control frame of the next period. Two buffer zones are configured for the FSI receiving end in the memory of the slave machine controller, the DMA controller switches the buffer zones after the whole frame is carried, the communication process and the control process are decoupled in time sequence, the input data of the controller is always delivered in the unit of the whole frame, so that the cross-frame data aliasing is avoided, and the consistent update of the reference quantity issued by the host machine among the modules is ensured.

Description

Technical Field

[0001] This invention relates to the field of communication technology, specifically to a communication method and a communication system based on a parallel single-stage inverter with dual active bridges. Background Technology

[0002] In scenarios such as distributed renewable energy power supply and residential energy storage, multiple single-stage series resonant dual active bridge DC / AC inverters are often connected in parallel to improve system capacity and power supply reliability.

[0003] When multiple single-stage series resonant dual active bridge DC / AC inverters are operated in parallel, the control cycle and synchronization requirements of the communication system are very high. Currently, most communication systems based on dual active bridge parallel single-stage inverters use a controller area network bus or serial peripheral interface bus as the communication link between modules. Although the above methods achieve bus-based parallel control, when the system faces shorter control cycles and higher synchronization accuracy requirements, the transmission rate and synchronization performance of the above communication buses are difficult to fully meet the requirements.

[0004] Furthermore, if the reception and parsing of communication data are completed using a communication interrupt method, data consistency issues may arise when the arrival time of a communication frame overlaps with the time when the control program reads the shared buffer. Specifically, if the control program has not yet finished reading the current frame data, and the next frame data has already begun to be written to the same buffer, the data obtained in a single control calculation will no longer correspond to a complete communication frame, but will instead contain partial fields from both the preceding and following frames, resulting in cross-cycle aliasing. This causes the controller to read incorrectly pieced-together instructions, thereby disrupting the reference synchronization relationship between the master and slave devices. Summary of the Invention

[0005] To address the aforementioned technical problems, the first objective of this invention is to propose a communication method for a parallel single-stage inverter based on dual active bridges.

[0006] The second objective of this invention is to propose a communication system based on a parallel single-stage inverter with dual active bridges.

[0007] The technical solution adopted in this invention is as follows:

[0008] A first aspect of the present invention provides a communication method for a parallel single-stage inverter based on a dual active bridge, comprising the following steps:

[0009] The master sends the control frame for the current cycle to each slave device corresponding to the inverter via FSI (Fast Serial Interface); the slave device's DMA (Direct Memory Access) controller moves and stores the received control frame byte by byte into the back buffer; at the beginning of the next control cycle, the slave CPU (Central Processing Unit) performs a buffer switching operation, switching the original back buffer to the foreground buffer for the CPU to read and use in the current cycle, and switching the original foreground buffer to the back buffer for the DMA controller to start receiving control frames for the next cycle.

[0010] The communication method for parallel single-stage inverters based on dual active bridges proposed in this invention may also have the following additional technical features:

[0011] According to one embodiment of the present invention, the control frame includes: a phase angle reference and a current reference value for the inverter.

[0012] According to one embodiment of the present invention, the above-described communication method further includes: after each slave device completes the reception of the control frame sent by the master device, it sequentially replies to the master device with its own operating status data in a predetermined order.

[0013] According to an embodiment of the present invention, the above-described communication method further includes: during the initialization access or communication fault recovery phase of the parallel single-stage inverter, when the master sends the control frame of the current cycle to each slave corresponding to the inverter via FSI, it also sends a Flush signal (containing a specific communication sequence of data line flipping and continuous clock pulses) to each slave corresponding to the inverter as a receive enable trigger; after receiving the Flush signal, each slave transmits its own operating status data back to the master in a predetermined order; when all valid operating status data transmitted back by the slaves are received by the master, the master stops sending the Flush signal.

[0014] According to an embodiment of the present invention, the above-described communication method further includes: after receiving the local operating status data replied by the slave device, the host obtains the FSI receive event flag and the CRC field in the local operating status data replied by the slave device, and determines whether there is a communication software fault based on the FSI receive event flag and the CRC field, wherein the communication software fault includes: format-type communication software fault and data-type communication software fault; after receiving the local operating status data replied by the slave device, the host extracts a discriminant from the local operating status data replied by the slave device using a sliding array of a set length, and determines whether there is a communication hardware fault based on the discriminant; after receiving the local operating status data replied by the slave device, the host obtains the fault code and the local protection status identifier in the local operating status data replied by the slave device, and determines whether there is a device-side abnormality based on the fault code and the local protection status identifier.

[0015] According to one embodiment of the present invention, determining whether a communication software fault exists based on the FSI receive event flag and the CRC (Cyclic Redundancy Check) field specifically includes: if the received FSI receive event flag is CRC error and the accumulated CRC error count in the system exceeds a set threshold, then a data-related communication software fault is determined to exist; if the received FSI receive event flag is Frame type error and EOF error, then a format-related communication software fault is determined to exist.

[0016] According to one embodiment of the present invention, determining whether a communication hardware fault exists based on the discrimination word specifically includes: when the discrimination words extracted in four consecutive control cycles in the sliding array are completely consistent, it is determined that a communication hardware fault exists; when the discrimination words extracted in four consecutive control cycles in the sliding array maintain a predetermined change, it is determined that no communication hardware fault exists.

[0017] According to an embodiment of the present invention, after determining that there is a communication software fault, a communication hardware fault, or a device-side abnormality, the method further includes the following steps: if a data-related communication software fault is determined to exist and the CRC error count does not exceed the threshold, the current abnormal frame is discarded and the valid value of the previous period is maintained; if the CRC error count exceeds the threshold or a format-related communication software fault is determined to exist, the receiving state machine is reset and the buffer is cleared, and the host continues to send Flush signals and control frames to rebuild the receiving boundary; if a communication hardware fault or a fault in the slave device is determined to exist in the slave link, the faulty slave is isolated and the remaining nodes continue to operate; after the faulty slave recovers, it re-enters the receiving and responding process under the action of the continuously sent Flush signals from the host; if a communication hardware fault or a fault in the host device is determined to exist in the host link, the entire machine is prioritized for protection and shutdown; after the host recovers to normal, the host re-initiates periodic broadcasting, and each slave re-connects to the system under the action of the Flush signals.

[0018] A second aspect of the present invention provides a communication system for a parallel single-stage inverter based on a dual active bridge, comprising: a master unit, which is configured to send control frames for the current cycle to each slave unit corresponding to the inverter via FSI; and a slave unit, which is configured to transfer and store the received control frames byte by byte into a background buffer via a DMA controller. At the beginning of the next control cycle, the slave CPU performs a buffer switching operation, switching the original background buffer to a foreground buffer for the CPU to read and use in the current cycle, and switching the original foreground buffer to a background buffer for the DMA controller to start receiving control frames for the next cycle.

[0019] The communication system of the parallel single-stage inverter based on dual active bridges described above in this invention also has the following additional technical features:

[0020] According to one embodiment of the present invention, the slave device is further configured to: after receiving the control frame sent by the master device, reply to the master device with its own operating status data in a predetermined order.

[0021] According to one embodiment of the present invention, the host is further configured to: when sending the control frame of the current cycle to each slave device corresponding to the inverter via FSI, also send a Flush signal to each slave device corresponding to the inverter as a receive enable trigger; the slave device is further configured to: after receiving the Flush signal, transmit its own operating status data back to the host in a predetermined order; the host is further configured to: stop sending the Flush signal after all valid local operating status data transmitted back by the slave devices have been received by the host.

[0022] The beneficial effects of this invention are:

[0023] The FSI-based communication architecture designed in this invention uses master broadcasting and slave orderly reply as the basic organizational form. While ensuring high-speed data exchange capability, it also takes into account the determinism, consistency and scalability of the communication process, and can better meet the requirements of multi-machine parallel system for master-slave collaborative communication.

[0024] This invention configures two buffers for the FSI receiver in the memory of the slave controller. The DMA controller switches the buffers after the entire frame is transferred, so that the communication process and the control process are decoupled in terms of timing. The controller's input data is always delivered in whole frames, thereby avoiding cross-frame data aliasing and ensuring that the reference values ​​sent by the host are updated consistently among the modules.

[0025] FSI communication, through a combination of CRC checksum and frame event flags, provides basic error detection and link status characterization capabilities for high-speed serial communication, which helps improve the reliability of data transmission and provides a foundation for subsequent system anomaly identification and status management. Attached Figure Description

[0026] Figure 1 This is a flowchart of a communication method for a parallel single-stage inverter based on a dual active bridge according to an embodiment of the present invention;

[0027] Figure 2 This is a topology diagram of a parallel single-stage inverter based on dual active bridges according to an embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of a communication system based on a parallel single-stage inverter with dual active bridges according to an embodiment of the present invention;

[0029] Figure 4 This is a communication timing diagram within a cycle according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of a communication method for a parallel single-stage inverter based on dual active bridges according to an embodiment of the present invention.

[0031] Figure 6 This is a schematic diagram of the interaction timing between the host and slave devices according to an embodiment of the present invention;

[0032] Figure 7 This is a schematic diagram illustrating the principle of communication hardware fault detection according to an embodiment of the present invention. Detailed Implementation

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Figure 1 This is a flowchart of a communication method for a parallel single-stage inverter based on a dual active bridge according to an embodiment of the present invention. Figure 2 This is a topology diagram of a parallel single-stage inverter based on dual active bridges according to an embodiment of the present invention. Figure 2 Taking two single-stage inverters connected in parallel as an example, namely the first single-stage inverter and the second single-stage inverter.

[0035] like Figure 1 As shown, the communication method for a parallel single-stage inverter based on dual active bridges includes the following steps:

[0036] S1, the master sends the control frame for this cycle to the slave corresponding to each inverter through FSI.

[0037] In one embodiment of the present invention, the control frame includes: the phase angle reference of the inverter and the current reference value.

[0038] Specifically, such as Figure 2 As shown, to meet the voltage stability and power sharing requirements of multiple inverters operating in parallel, a master-slave parallel control method based on interconnection information sharing is constructed. The basic idea is that in parallel mode, the master unit uniformly provides the control frame (inverter phase angle reference and current reference value), and the slave unit no longer independently establishes a voltage reference, but performs current following control under a unified phase reference. This division of labor transforms the parallel problem from multiple voltage sources in parallel to a single voltage reference + multiple current executions, thereby reducing the circulating current risk caused by phase drift and reference inconsistency, and providing a clear control interface for multi-unit expansion.

[0039] For parallel master-slave control, reference quantities and status quantities have strong periodicity and synchronization requirements. Delay fluctuations in the communication link weaken the phase consistency and current tracking consistency of slave reference updates. This invention implements master-slave communication based on an FSI communication link. FSI is a point-to-point high-speed serial link, with a single frame capable of carrying 16×16 bits of data. It can complete the synchronous transmission of reference quantities and critical status quantities with a fixed frame length within a control cycle. Its link delay is controllable, jitter is low, and it is easy to incorporate into deterministic scheduling within the control cycle.

[0040] like Figure 3As shown, the master side is equipped with one set of transmitters (TX) and multiple sets of receivers (RX). The transmitters (TX) are used to uniformly send control reference values ​​to all slaves, and each receiver (RX) is used to receive feedback information from different slaves. Each slave node is equipped with one set of receivers (RX) and one set of transmitters (TX), responsible for receiving broadcast information from the master and feeding back its own status data to the master, respectively. When the number of parallel nodes increases, the system scale can be expanded simply by expanding the corresponding receiving channels on the master side and adding the corresponding node response order definition, without changing the overall master-slave structure. Therefore, the above-described FSI communication architecture can well meet the requirements of high-speed, reliable, and deterministic communication for multi-machine parallel systems and provides a foundation for subsequent communication timing design.

[0041] S2, the slave DMA controller moves the received control frames byte by byte and stores them in the background buffer.

[0042] S3, at the beginning of the next control cycle, the slave CPU performs a buffer switching operation, switching the original back buffer to the front buffer for the CPU to read and use in this cycle, and switching the original front buffer to the back buffer so that the DMA controller can start receiving control frames for the next cycle.

[0043] Specifically, to ensure that data exchange between master and slave nodes has defined time boundaries and to avoid overlap between communication and control processes that could affect data consistency, the FSI communication process in this invention incorporates corresponding timing design, such as... Figure 4 As shown, at the beginning of a single control cycle k, a timer triggers the AD (Analog-to-Digital Converter) to sample and acquire state quantities such as voltage and current. Then, the control calculation phase begins, sequentially completing sample value reading and filtering, PI loop calculation, control strategy solution, and drive signal generation. At this point, all control calculations related to power conversion within this cycle k are completed, and the updated drive signal results are applied to the power stage operation in the next time period. After the control calculation is completed, the system enters the communication processing phase, parsing and latching the received control frames. The control loop and communication loop form a clear sequential relationship within a single cycle: the current cycle first completes local sampling and control calculation, then completes the reception, parsing, and latching of communication information; the latched communication data is used in the next control cycle. This ensures both the real-time performance of control execution and improves the consistency and determinism of communication data updates.

[0044] Data exchange between master and slave nodes is scheduled to occur at fixed points within the control cycle. If the reception and parsing of communication data are still performed using communication interrupts, data consistency issues may arise when the arrival time of a communication frame overlaps with the time when the control program reads the shared buffer. Specifically, if the control program has not yet finished reading the current frame data, and the next frame data has already begun to be written to the same buffer, the data obtained in a single control calculation will no longer correspond to a complete communication frame, but will instead contain partial fields from both the preceding and following frames, resulting in cross-cycle aliasing.

[0045] To address the aforementioned problems, this invention embeds master-slave data exchange within a fixed control cycle. For example... Figure 5 As shown, firstly, two buffers are configured in the slave controller's memory for the FSI receiver. The DMA only switches buffers after the entire frame has been transferred. At the start of the current control cycle, the master sends the control frame for that cycle via FSI. The slave's DMA controller transfers the received complete frame data byte by byte and stores it in the background buffer. At the start of the next control cycle, the slave CPU performs a buffer switching operation, turning the previously full background buffer into a foreground buffer for the CPU to read in the current cycle, while the previously full foreground buffer becomes a background buffer for the DMA to begin receiving the next frame. During this control cycle, the CPU consistently and stably reads the complete control frame for the current cycle to perform current loop calculations, while the DMA receives the control frame for the next cycle in the background. That is, the DMA only switches buffers after the entire frame has been transferred, and the control program reads the fully latched data frame at fixed control times. This decouples the communication and control processes in terms of timing. The controller's input data is always delivered in whole frames, thus avoiding cross-frame data aliasing and ensuring consistent updates of the reference values ​​sent by the master across modules.

[0046] In one embodiment of the present invention, the communication method of the parallel single-stage inverter based on dual active bridges further includes: S4, after each slave device completes the reception of the control frame sent by the master device, it sequentially replies to the master device with its own operating status data in a predetermined order.

[0047] Therefore, adopting a sequential return method can avoid data conflicts caused by multiple slave devices sending data simultaneously, thereby improving the determinism of information exchange in parallel systems.

[0048] In one embodiment of the present invention, the above-described communication method for a parallel single-stage inverter based on dual active bridges further includes: during the initialization access or communication fault recovery phase of the parallel single-stage inverter, when the master sends the control frame of the current cycle to the slave corresponding to each inverter through FSI, it also sends a Flush signal to the slave corresponding to each inverter as a receive enable trigger; after receiving the Flush signal, each slave transmits its own operating status data back to the master in a predetermined order; when all valid operating status data transmitted back by the slaves are received by the master, the master stops sending the Flush signal.

[0049] Specifically, such as Figure 6 As shown, the master uses the Flush signal as the receive enable trigger. During periodic communication, the master sends a Flush signal and sends a control frame. After receiving the data, the slave device sends back its own operating status data based on the polling identifier in the control frame. The master then dynamically updates the access status based on the results sent back by each slave and continues subsequent polling. Once all valid operating status data sent back by the slaves has been received by the master, the master stops sending Flush signals and switches to the normal periodic communication mode, maintaining efficient data exchange and control synchronization. Therefore, link access no longer relies on a separate handshake phase but is completed synchronously during normal data exchange, thus shortening initialization and recovery latency and avoiding error propagation caused by cross-frame mixing. This provides support for rapid access and stable communication under continuous operation conditions in parallel systems.

[0050] In parallel single-stage inverters, the FSI link simultaneously handles two types of information exchange tasks: sending control reference values ​​and transmitting operating status. For parallel systems, the main risk of communication anomalies lies not in the loss of single-frame data, but in the disruption of the effective boundaries of control values ​​between different units, leading to asynchrony at parallel points and circulating current problems. Therefore, it is necessary to first establish a clear fault diagnosis method to achieve timely identification and classification of abnormal states. Based on the operating characteristics and available observables of parallel single-stage inverters based on dual active bridges, this invention classifies faults into three categories: communication software faults, communication hardware faults, and equipment body faults. The specific identification methods are as follows.

[0051] In one embodiment of the present invention, the communication method of the parallel single-stage inverter based on dual active bridges described above further includes the following steps S5-S7 after the master receives the local operating status data replied by the slave:

[0052] S5. Obtain the FSI receive event flag and CRC field from the local operating status data replied by the slave device. Based on the FSI receive event flag and CRC field, determine whether there is a communication software fault. Communication software faults include: format-related communication software faults and data-related communication software faults.

[0053] In one specific embodiment of the present invention, if the received FSI receive event flag is CRC error and the accumulated CRC error count in the system exceeds a set threshold, it is determined that there is a data communication software fault; if the received FSI receive event flag is Frame type error and EOF error, it is determined that there is a format communication software fault.

[0054] Specifically, communication software failure refers to a disruption of the reliability of data within a frame or the rules governing frame boundaries, even after the receiving side has received the data frame. After receiving the local operating status data returned by the slave device, the host determines whether an FSI (Frame overrun Indicator) event flag exists. Based on the FSI event flag and the requirements for control boundary consistency in parallel systems, it classifies these failures into two categories: format-related communication software failures and data-related communication software failures. The main FSI event flags include: Frame_Done, DataFrame, Ping Frame, Err Frame, Buf Overrun, Buf UnderrunN, Frame Overrun, CRC error, Data Tag Match, and Ping Tag Match.

[0055] Frame type error and EOF error correspond to abnormal frame type field and abnormal frame end boundary, respectively. Their common characteristic is that the receiver state machine may fail to identify frame boundaries. Therefore, if an FSI receive event flag for Frame type error or EOF error is received, a format-related communication software fault is identified. Data-related communication software faults are characterized by the frame boundary usually still existing, but the reliability of the data in this frame decreases. Therefore, if an FSI receive event flag for CRC error is received and the accumulated CRC error count in the system exceeds a set threshold, a format-related communication software fault is identified. This allows for the differentiation between frame boundary abnormalities and data reliability abnormalities.

[0056] Therefore, by combining CRC checksum with frame event flags, basic error detection and link status characterization capabilities are provided for high-speed serial communication, which helps improve the reliability of data transmission and provides a foundation for subsequent system anomaly identification and status management.

[0057] S6 extracts a discriminant from the local operating status data replied by the slave device using a sliding array of a set length, and determines whether there is a communication hardware fault based on the discriminant.

[0058] In a specific embodiment of the present invention, determining whether a communication hardware fault exists based on a discrimination word specifically includes: when the discrimination words extracted in four consecutive control cycles within the sliding array are completely identical, it is determined that a communication hardware fault exists; when the discrimination words extracted in four consecutive control cycles within the sliding array maintain a predetermined change, it is determined that no communication hardware fault exists.

[0059] Specifically, communication hardware failures differ from software failures. They don't necessarily manifest as obvious format errors; a more common characteristic is that the receiving end stops continuously providing valid updates. For example, when a downstream node loses power, the transmission link is damaged, or the transceiver malfunctions, the receiving side may still read data in a valid format, but its content has lost its periodic update characteristics. This invention extracts discriminants reflecting periodic evolution characteristics from the slave's reply data in each frame of local operating status data and constructs a sliding array of length 4, such as... Figure 7 As shown, when the discriminant extracted in four consecutive control cycles in the array is completely consistent, it is determined that the other end has not continuously provided effective updates, thus identifying it as a communication hardware failure; conversely, if the discriminant remains to change within the sliding window, it is considered that the link is still in a normal update state.

[0060] Communication software failures can be caused by hardware failures in either the slave or master links. The master has multiple independent receiving channels. After determining a hardware failure based on a criterion, the specific slave link with the failure can be pinpointed using the receiving channel number. If the master detects an anomaly in the backbone used for global broadcasting (e.g., the master's transmitter TX itself, or the backbone communication line) or receives a master communication loss status signal from a slave, it determines that a hardware failure exists in the master link.

[0061] Therefore, using periodic consistency rather than single-error flags for discrimination can better distinguish between short-term disturbances and true loss of connection.

[0062] S7: Obtain the fault code and local protection status indicator from the local operating status data replied by the slave device, and determine whether there is an abnormality on the device side based on the fault code and local protection status indicator.

[0063] Specifically, the communication link itself may remain normal, but the node power level or protection link may have detected anomalies such as overcurrent, overvoltage, or overtemperature. In this case, relying solely on FSI to receive event flags may not accurately reflect the source of the fault. Device-side anomalies include slave device faults and master device faults. This invention uniformly maps device-side protection information to fault codes (FaultCode) and combines them with local protection status flags as observations of device-side faults. After detecting its own anomaly, the slave device uniformly maps its protection information to fault codes (FaultCode) and then sends its local operating status data with the fault code (FaultCode) to the master device. Upon receiving the data, the master device can accurately locate which slave device has experienced a device-side fault by combining the FaultCode with the channel number. When the master device's protection module detects overcurrent / overvoltage faults, it generates a local protection status flag. The master device determines that a master device-side fault exists based on the local protection status flag.

[0064] By separating and differentiating between device operating status and link communication status, misjudging device anomalies as general communication failures can be avoided. Specifically, communication software failures are identified based on FSI (Feedforward Successor Indicator) receive event flags; communication hardware failures are identified based on a sliding window of discrimination words; and device-specific failures are identified based on FaultCode and local protection status. These methods provide clear fault inputs and classification criteria for subsequent fault tolerance and rapid recovery strategies.

[0065] According to one embodiment of the present invention, after determining that there is a communication software fault, a communication hardware fault, or a device-side abnormality, the following steps are further included: if a data-related communication software fault is determined to exist and the CRC error count does not exceed the threshold, the current abnormal frame is discarded and the valid value of the previous period is maintained; if the CRC error count exceeds the threshold or a format-related communication software fault is determined to exist, the receiving state machine is reset and the buffer is cleared, and the host continues to send Flush signals and control frames to rebuild the receiving boundary; if a communication hardware fault or a fault in the slave device is determined to exist in the slave link, the faulty slave is isolated and the remaining nodes continue to operate; after the faulty slave recovers, it re-enters the receiving and responding process under the action of the Flush signals continuously sent by the host; if a communication hardware fault or a fault in the host device is determined to exist in the host link, the entire machine is protected and shut down first; after the host recovers to normal, the host re-initiates periodic broadcasting, and each slave re-connects to the system under the action of the Flush signal.

[0066] Specifically, when a fault is detected, the impact range on the communication boundary and parallel topology is first determined according to the fault type, and then measures such as maintaining the old value, resetting the state, isolating the node, or protecting the system are taken respectively. After the fault condition is cleared, the Flush enable and polling access mechanism in the handshake-free communication are used to enable the node to return to the periodic communication sequence without re-entering the independent handshake stage, thereby shortening the recovery delay and reducing the impact on the continuous operation of the system.

[0067] Specifically, in the case of communication software failure, the physical link usually remains normal, but the reliability of frame content or frame boundary rules has been disrupted. For a single CRC error, the current abnormal frame is discarded while the valid value of the previous cycle is maintained to preserve short-term control continuity. When consecutive CRC errors exceed the threshold, or when format-related communication software failures such as frame type errors or frame end errors occur, the current reception boundary is considered invalid. In this case, the receiver state machine should be reset and relevant buffers and flags cleared. After the reset, the master continues to send Flush signals and data frames according to the established timing sequence, and the slave re-enters the reception state after detecting a valid reception condition.

[0068] For communication hardware failures, the essence is an abnormality in the physical channel of the link or the transceiver unit, causing the peer to be unable to continuously provide effective updates. Once such a failure is identified, the information currently provided by the abnormal node will no longer be used. Instead, node isolation and degradation will be performed according to the master-slave structure. If the failure occurs on a slave link, the master will temporarily remove it from the cooperative control set, and the remaining nodes will determine whether to reset and restart based on their operating status. After the link is restored, the faulty node will first complete the local communication state reset, and then re-enter the receiving and acknowledging process under the action of the continuous Flush signal sent by the master. If the failure occurs on the master side or a critical link, due to the failure of the unified reference source, the whole machine protection should be implemented first. After the master recovers, the master will re-initiate periodic broadcasts to enable each slave to quickly reconnect to the system in a predetermined order.

[0069] The characteristic of equipment-side anomalies is that the communication link may still remain normal, but the node or protection link has entered an abnormal state. In this case, the faulty node first executes local protection actions, blocking power control signals and ceasing power transmission, while simultaneously reporting the fault information to the host. The host performs system-level coordinated handling based on the type and severity of the faulty node: if the fault occurs on a slave device, it is isolated, and the system's restart depends on the remaining unit capacity; if the fault occurs on the host side, a shutdown command is broadcast to shut down the entire system. After the faulty node completes its self-test and the protection conditions are released, it can re-enter the access standby state and restore communication using the Flush signal periodically sent by the host, after which it resumes normal operation.

[0070] In summary, the communication method for parallel single-stage inverters based on dual active bridges according to embodiments of the present invention is designed with an FSI communication architecture based on master broadcasting and slave orderly reply as the basic organizational form. While ensuring high-speed data exchange capability, it also takes into account the determinism, consistency and scalability of the communication process, and can better meet the requirements of master-slave collaborative communication in multi-machine parallel systems. The present invention configures two buffers for the FSI receiver in the memory of the slave controller. The DMA controller switches the buffers after the whole frame is transferred, so that the communication process and the control process are decoupled in timing. The controller's input data is always delivered in whole frames, thereby avoiding cross-frame data aliasing and ensuring consistent updates of the reference values ​​sent by the master across modules. FSI communication provides basic error detection and link status characterization capabilities for high-speed serial communication through a combination of CRC check and frame event flags, which helps to improve the reliability of data transmission and provides a foundation for subsequent system anomaly identification and status management.

[0071] Corresponding to the communication method for parallel single-stage inverters based on dual active bridges described above, this invention also proposes a communication system for parallel single-stage inverters based on dual active bridges. The system implementation of this invention corresponds to the method embodiments described above. For details not disclosed in the system embodiments, please refer to the method embodiments described above; further details will not be repeated here.

[0072] like Figure 3 As shown, the communication system of the parallel single-stage inverter based on dual active bridges includes a master unit and a slave unit. The master unit sends control frames for the current cycle to the corresponding slave unit of each inverter via FSI. The slave unit uses a DMA controller to transfer and store the received control frames byte by byte into a back buffer. At the beginning of the next control cycle, the slave CPU performs a buffer switching operation, switching the original back buffer to a front buffer for the CPU to read and use in the current cycle, and switching the original front buffer to a back buffer for the DMA controller to begin receiving control frames for the next cycle.

[0073] According to one embodiment of the present invention, the slave device is further configured to: after receiving the control frame sent by the master device, reply to the master device with its own operating status data in a predetermined order.

[0074] According to one embodiment of the present invention, the master unit is further configured to: when sending the control frame of the current cycle to the slave unit corresponding to each inverter via FSI, also send a Flush signal to the slave unit corresponding to each inverter as a receive enable trigger; the slave unit is further configured to: after receiving the Flush signal, send back its own operating status data to the master unit in a predetermined order; the master unit is further configured to: stop sending the Flush signal after all valid local operating status data sent back by the slave units has been received by the master unit.

[0075] The communication system of a parallel single-stage inverter based on dual active bridges according to an embodiment of the present invention is designed based on an FSI communication architecture with master broadcast and slave orderly reply as the basic organizational form. While ensuring high-speed data exchange capability, it also takes into account the determinism, consistency and scalability of the communication process, and can better meet the requirements of master-slave collaborative communication in multi-machine parallel systems. Two buffers are configured in the memory of the slave controller for the FSI receiver. The DMA controller switches the buffers after the whole frame is transferred, so that the communication process and the control process are decoupled in timing. The controller's input data is always delivered in whole frames, thereby avoiding cross-frame data aliasing and ensuring consistent updates of the reference values ​​sent by the master among the modules.

[0076] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0077] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A communication method for a parallel single-stage inverter based on dual active bridges, characterized in that, Includes the following steps: The host sends the control frame for the current cycle to the slave device corresponding to each inverter via FSI; The slave DMA controller moves the received control frames byte by byte and stores them in the background buffer; At the start of the next control cycle, the slave CPU performs a buffer switching operation, switching the original back buffer to the front buffer for the CPU to read and use in this cycle, and switching the original front buffer to the back buffer so that the DMA controller can start receiving control frames for the next cycle.

2. The communication method for a parallel single-stage inverter based on a dual active bridge according to claim 1, characterized in that, The control frame includes: the inverter's phase angle reference and current reference value.

3. The communication method for a parallel single-stage inverter based on a dual active bridge according to claim 1, characterized in that, Also includes: After receiving the control frames sent by the master, each slave device replies to the master with its own operating status data in a predetermined order.

4. The communication method for a parallel single-stage inverter based on a dual active bridge according to claim 2, characterized in that, Also includes: During the initialization access or communication fault recovery phase of the parallel single-stage inverter, when the host sends the control frame of the current cycle to the slave corresponding to each inverter through FSI, it also sends a Flush signal to the slave corresponding to each inverter as a receive enable trigger. After receiving the Flush signal, each slave device transmits its own operating status data back to the master device in a predetermined order; Once the host receives all valid local operating status data returned by the slave devices, the host stops sending the Flush signal.

5. The communication method for a parallel single-stage inverter based on dual active bridges according to claim 1, characterized in that, After receiving the local operating status data from the slave device, the host also includes: Obtain the FSI receive event flag and the CRC field from the local operating status data replied by the slave device. Based on the FSI receive event flag and the CRC field, determine whether there is a communication software fault. The communication software fault includes: format-related communication software faults and data-related communication software faults. Extract a discriminant from the local operating status data replied by the slave device using a sliding array of a set length, and determine whether there is a communication hardware failure based on the discriminant; Obtain the fault code and local protection status identifier from the local operating status data replied by the slave device, and determine whether there is an abnormality on the device side based on the fault code and local protection status identifier.

6. The communication method for a parallel single-stage inverter based on a dual active bridge according to claim 5, characterized in that, Based on the FSI receive event flag and the CRC field, it is determined whether a communication software fault exists, specifically including: If the received FSI receive event flag is CRC error and the accumulated CRC error count in the system exceeds the set threshold, then a data communication software fault is determined to exist. If the received FSI receive event flags are Frame type error and EOF error, it is determined that there is a format-related communication software fault.

7. The communication method for a parallel single-stage inverter based on a dual active bridge according to claim 5, characterized in that, Determining whether a communication hardware fault exists based on the aforementioned discrimination word specifically includes: When the discriminant extracted in four consecutive control cycles within the sliding array is completely identical, a communication hardware fault is determined to exist. If the discriminant extracted from the sliding array remains unchanged for four consecutive control cycles, it is determined that there is no communication hardware fault.

8. The communication method for a parallel single-stage inverter based on a dual active bridge according to claim 5, characterized in that, After determining that there is a communication software fault, a communication hardware fault, or a device-side abnormality, the following steps are also included: If a data communication software fault is detected and the CRC error count does not exceed the threshold, the current abnormal frame is discarded and the valid value of the previous cycle is maintained; if the CRC error count exceeds the threshold or a format communication software fault is detected, the receiving state machine is reset and the buffer is cleared, and the host continues to send Flush signals and control frames to rebuild the receiving boundary. If it is determined that there is a communication hardware failure or a failure of the slave device itself in the slave link, the faulty slave will be isolated and the remaining nodes will continue to operate; after the faulty slave recovers, it will re-enter the receiving and responding process under the action of the Flush signal continuously sent by the master. If a communication hardware failure or a failure of the host device itself is detected in the host link, the entire machine will be protected and shut down first. After the host recovers, the host will re-initiate the periodic broadcast, and each slave device will reconnect to the system under the action of the Flush signal.

9. A communication system based on a parallel single-stage inverter with dual active bridges, characterized in that, include: The host is used to send the control frame of the current cycle to the slave corresponding to each inverter via FSI; The slave device is used to transfer and store the received control frames byte by byte into the background buffer through the DMA controller. At the beginning of the next control cycle, the slave CPU performs a buffer switching operation, switching the original background buffer to the foreground buffer for the CPU to read and use in this cycle, and switching the original foreground buffer to the background buffer for the DMA controller to start receiving control frames for the next cycle.

10. The communication system based on a parallel single-stage inverter with dual active bridges according to claim 9, characterized in that, The slave device is also used for: After receiving the control frames sent by the host, the machine replies with its operating status data to the host in a predetermined order.

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