A multi-stage clock variable frequency intermittent control-based direct current level converter wake-up method and system

Abstract

The application discloses a DC level converter wake-up method and system based on multi-stage clock frequency conversion intermittent control, the method comprises the following steps: detecting the charging signal of the DC level converter through the comparator; when the DC level converter switches from the intermittent working mode to the always-on mode, if the comparator detects the charging signal in the continuous three clock periods, the multi-stage clock frequency conversion is carried out in each clock period through the oscillator, the first mode switching signal is generated through the mode switching circuit, and the mode switching is completed; when the DC level converter switches from the always-on mode to the intermittent working mode, if the comparator does not detect the charging signal in the continuous three clock periods, the second mode switching signal is generated through the mode switching circuit, and the mode switching is completed. According to the multi-stage clock frequency adjustment according to the triggering of the charging signal, the wake-up system can be accelerated, the synergistic optimization of lower static power consumption and better transient response can be realized, and the method can be widely applied to the technical field of integrated circuit design.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design technology, and in particular to a method and system for waking up a DC-DC level converter based on multi-level clock frequency conversion intermittent control. Background Technology

[0002] In the design of low-power single-inductor multi-output DC-level converters for Internet of Things (IoT) applications, the system is in standby mode most of the time, making static power consumption a key factor limiting efficiency under light loads. To improve converter efficiency under ultra-light load scenarios while maintaining good transient response, designing a suitable low-power control method is crucial for optimizing system efficiency. Existing low-power control methods have the following drawbacks and limitations: First, in IoT applications, the system is in standby mode for a long time, and the static power consumption of the system becomes a key factor restricting the efficiency of the system under light load, making it difficult to meet the low power consumption application requirements of ultra-long standby.

[0003] Second, simply reducing static power consumption will lead to narrowing of system bandwidth, a significant decrease in transient response speed, and a tendency to generate large output voltage overshoot / undershoot when the load changes suddenly, affecting the stable operation of the system.

[0004] Third, as the load current increases, the conduction and drive losses of the system power transistors become dominant, and the static power consumption is no longer the key factor constraining system efficiency. If the system response speed is excessively limited in order to reduce static power consumption, the output voltage ripple will be further increased, making it impossible to adapt to efficient and stable operation over a wide load range. Summary of the Invention

[0005] The main objective of this application is to propose a DC-DC level converter wake-up method and system based on multi-level clock frequency conversion intermittent control, which can achieve synergistic optimization of lower static power consumption and better transient response.

[0006] To achieve the above objectives, one aspect of this application proposes a DC-DC level converter wake-up method based on multi-level clock frequency conversion intermittent control, comprising the following steps: The charging signal of the DC-DC level converter is detected by a comparator; When the DC-DC level converter switches from intermittent working mode to normally open mode, if the comparator detects the charging signal in three consecutive clock cycles, the oscillator performs multi-level clock frequency conversion in each clock cycle, and the mode switching circuit generates a first mode switching signal to complete the mode switching. When the DC-DC level converter switches from normally open mode to intermittent operating mode, if the comparator does not detect the charging signal for three consecutive clock cycles, the mode switching circuit generates a second mode switching signal to complete the mode switching.

[0007] In some embodiments, when the comparator detects the charging signal for three consecutive clock cycles, the step of performing multi-level clock frequency conversion by the oscillator in each clock cycle specifically includes: When the comparator detects the charging signal in the first clock cycle, it generates a first frequency switching signal through the control module, and the oscillator converts the first clock cycle signal into a second clock cycle signal according to the first frequency switching signal. When the comparator detects the charging signal in the second clock cycle, it generates a second frequency switching signal through the control module, and the oscillator converts the second clock cycle signal into a third clock cycle signal according to the second frequency switching signal. When the comparator detects the charging signal in the third clock cycle, it generates a third frequency switching signal through the control module, and the oscillator converts the third clock cycle signal into the first clock cycle signal according to the third frequency switching signal. Wherein, the first clock cycle signal is greater than the second clock cycle signal, and the second clock cycle signal is greater than the third clock cycle signal.

[0008] In some embodiments, the mode switching circuit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, and a NOR gate. Specifically, when the comparator fails to detect the charging signal for three consecutive clock cycles, the mode switching circuit generates a second mode switching signal. When the comparator does not detect the charging signal for three consecutive clock cycles, it outputs an enable signal through the first D flip-flop, the second D flip-flop, the third D flip-flop, and the NOR gate. The fourth D flip-flop then outputs the second mode switching signal based on the enable signal.

[0009] In some embodiments, the oscillator adjusts the number of parallel capacitors according to the first frequency switching signal, the second frequency switching signal, and the third frequency switching signal to achieve multi-level clock frequency conversion.

[0010] In some embodiments, the first clock cycle signal is 33 μs, the second clock cycle signal is 6 μs, and the third clock cycle signal is 4 μs.

[0011] In some embodiments, the first mode switching signal is high level and the second mode switching signal is low level.

[0012] To achieve the above objectives, another aspect of this application proposes a DC-level converter wake-up system based on multi-level clock frequency conversion intermittent regulation, used to execute the DC-level converter wake-up method as described above, including a control module, a comparator, an oscillator, and a mode switching circuit. The control module, the oscillator, and the mode switching circuit are all connected to the comparator, and the control module and the mode switching circuit are also connected to the oscillator.

[0013] In some embodiments, the mode switching circuit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, and a NOR gate. The input of the first D flip-flop is connected to the DC-DC level converter, the output of the first D flip-flop is connected to the input of the second D flip-flop, the output of the second D flip-flop is connected to the input of the third D flip-flop, the outputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop are all connected to the input of the NOR gate, and the output of the NOR gate is connected to the input of the fourth D flip-flop.

[0014] To achieve the above objectives, another aspect of the embodiments of this application proposes a DC-DC level converter, including the DC-DC level converter wake-up system as described above.

[0015] The embodiments of this application include at least the following beneficial effects: The DC-level converter wake-up method and system based on multi-level clock frequency conversion intermittent regulation of this application detects the charging signal of the DC-level converter through a comparator; when the DC-level converter switches from intermittent working mode to normally open mode, if the comparator detects the charging signal for three consecutive clock cycles, the oscillator performs multi-level clock frequency conversion in each clock cycle, and a first mode switching signal is generated by the mode switching circuit to complete the mode switching; when the DC-level converter switches from normally open mode to intermittent working mode, if the comparator does not detect the charging signal for three consecutive clock cycles, a second mode switching signal is generated by the mode switching circuit to complete the mode switching. This application performs multi-level clock frequency adjustment based on the triggering of the charging signal, which can accelerate the wake-up of the system and achieve synergistic optimization of lower static power consumption and better transient response. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the embodiments of this application are described below. It should be understood that the drawings described below are only for the purpose of clearly illustrating some embodiments of the technical solutions in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1A flowchart illustrating the steps of a DC-DC level converter wake-up method based on multi-level clock frequency conversion intermittent control according to an embodiment of this application; Figure 2 A timing diagram showing the conversion of a DC-DC level converter from intermittent operating mode to normally open mode according to one embodiment of this application; Figure 3 This is a circuit diagram of an oscillator provided in one embodiment of this application; Figure 4 A circuit diagram of a comparator provided in one embodiment of this application; Figure 5 A timing diagram showing the conversion of a DC-DC level converter from normally open mode to intermittent operating mode according to an embodiment of this application; Figure 6 A partial circuit diagram of a mode switching circuit provided in one embodiment of this application; Figure 7 A schematic diagram of the circuit implementation of a DC-level converter wake-up system based on multi-level clock frequency conversion intermittent control according to an embodiment of this application; Figure 8 This is a schematic block diagram of a controller and driver provided in one embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0019] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0020] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0021] In the design of low-power single-inductor multi-output DC-level converters for Internet of Things (IoT) applications, the system is in standby mode most of the time, making static power consumption a key factor limiting efficiency under light loads. To improve converter efficiency under ultra-light load scenarios while maintaining good transient response, designing a suitable low-power control method is crucial for optimizing system efficiency. Existing low-power control methods have the following drawbacks and limitations: First, in IoT applications, the system is in standby mode for a long time, and the static power consumption of the system becomes a key factor restricting the efficiency of the system under light load, making it difficult to meet the low power consumption application requirements of ultra-long standby.

[0022] Second, simply reducing static power consumption will lead to narrowing of system bandwidth, a significant decrease in transient response speed, and a tendency to generate large output voltage overshoot / undershoot when the load changes suddenly, affecting the stable operation of the system.

[0023] Third, as the load current increases, the conduction and drive losses of the system power transistors become dominant, and the static power consumption is no longer the key factor constraining system efficiency. If the system response speed is excessively limited in order to reduce static power consumption, the output voltage ripple will be further increased, making it impossible to adapt to efficient and stable operation over a wide load range.

[0024] In view of this, this application proposes a DC-DC level converter wake-up method based on multi-level clock frequency conversion intermittent regulation. A comparator detects the charging signal of the DC-DC level converter. When the DC-DC level converter switches from intermittent operation mode to normally open mode, if the comparator detects a charging signal for three consecutive clock cycles, a multi-level clock frequency conversion is performed in each clock cycle by an oscillator, and a first mode switching signal is generated by a mode switching circuit to complete the mode switching. When the DC-DC level converter switches from normally open mode to intermittent operation mode, if the comparator does not detect a charging signal for three consecutive clock cycles, a second mode switching signal is generated by the mode switching circuit to complete the mode switching. This application performs multi-level clock frequency adjustment based on the triggering of the charging signal, which can accelerate the wake-up of the system and achieve synergistic optimization of lower static power consumption and better transient response.

[0025] Reference Figure 1 , Figure 1This is a flowchart illustrating the steps of a DC-DC level converter wake-up method based on multi-level clock frequency conversion intermittent control according to an embodiment of this application. This application proposes a DC-DC level converter wake-up method based on multi-level clock frequency conversion intermittent control, which may include, but is not limited to, the following steps S101 to S103: Step S101: Detect the charging signal of the DC-DC level converter using a comparator; Step S102: When the DC level converter switches from intermittent working mode to normally open mode, if the comparator detects the charging signal in three consecutive clock cycles, the oscillator performs multi-level clock frequency conversion in each clock cycle, and the mode switching circuit generates the first mode switching signal to complete the mode switching. Step S103: When the DC level converter switches from normally open mode to intermittent working mode, if the comparator does not detect a charging signal for three consecutive clock cycles, a second mode switching signal is generated through the mode switching circuit to complete the mode switching.

[0026] It should be noted that excessively low clock frequencies can affect the output ripple of the DC-DC level converter, thereby impacting its load-carrying capacity. Therefore, this application introduces a multi-level clock frequency conversion intermittently adjustable control method. The clock frequency increases with the triggering of the charging signal, thereby accelerating the detection of output voltage changes and optimizing the undershoot / overshoot of the output voltage under load transients.

[0027] As a further optional implementation, when the comparator detects a charging signal in three consecutive clock cycles, the step of performing multi-stage clock frequency conversion by the oscillator in each clock cycle can be further divided into the following steps S1021 to S1023: Step S1021: When the comparator detects a charging signal in the first clock cycle, it generates a first frequency switching signal through the control module, and converts the first clock cycle signal into a second clock cycle signal through the oscillator according to the first frequency switching signal. Step S1022: When the comparator detects a charging signal in the second clock cycle, it generates a second frequency switching signal through the control module, and the oscillator converts the second clock cycle signal into a third clock cycle signal according to the second frequency switching signal. Step S1023: When the comparator detects a charging signal in the third clock cycle, the control module generates a third frequency switching signal, and the oscillator converts the third clock cycle signal into a first clock cycle signal according to the third frequency switching signal. The first clock cycle signal is greater than the second clock cycle signal, and the second clock cycle signal is greater than the third clock cycle signal.

[0028] As an optional implementation, the oscillator adjusts the number of parallel capacitors according to the first frequency switching signal, the second frequency switching signal, and the third frequency switching signal to achieve multi-level clock frequency conversion.

[0029] As an optional implementation, the first clock cycle signal is 33μs, the second clock cycle signal is 6μs, and the third clock cycle signal is 4μs.

[0030] As an optional implementation, the first mode switching signal is high and the second mode switching signal is low.

[0031] Specifically, such as Figure 2 The diagram shown is a timing diagram of a DC-DC level converter switching from intermittent operation mode to normally open mode. Figure 3 The diagram shown is a circuit diagram of an oscillator. Figure 4 The circuit diagram of the comparator is shown. The oscillator (frequency-variable oscillator) will adaptively adjust according to the frequency switching signal FS[1:3] output by the control module, thereby achieving the effect of frequency conversion.

[0032] In some optional embodiments, after the DC-DC level converter load changes from light load to heavy load, the comparator outputs high when the first clock arrives, and the control module generates a first frequency switching signal FS[1] with a value of 100. The oscillator switches the clock period from 33μs to 6μs by adjusting the number of capacitors. In the next clock cycle, if the comparator outputs high again, the control module generates a second frequency switching signal FS[2] with a value of 110. The oscillator adjusts the number of capacitors again to further switch the clock period from 6μs to 4μs. If the comparator output is still high in the next clock cycle, the control module generates a third frequency conversion signal FS[3] with a value of 111. At this time, all three frequency conversion signals are high, and the mode switching circuit immediately triggers a first mode conversion signal MS with a high level. The clock frequency returns to 33μs, the system is in a normally open state, and the comparator detects the output voltage change in real time.

[0033] The system adjusts the parallel capacitance of the oscillator via FS[1:2]. Figure 3 M6, M7, M 10 The number of comparators is adjusted to successively change the frequency of the oscillator. The comparator bias is turned on only when the clock CLK is high, thereby reducing the static losses in the system standby state.

[0034] It should be noted that, in the embodiments of this application, the transition conditions between the normally open mode and the intermittent working mode are different. For example... Figure 2As shown, since the clock CLK period is 33μs, the longest time required to switch from normally open mode to intermittent operating mode is 99μs. However, thanks to the variable frequency clock, the DC-DC level converter controlled by this embodiment of the application only needs to take a minimum of 43μs to switch from intermittent operating mode to normally open mode, thus avoiding the problem of switching back and forth between the two modes.

[0035] As an optional implementation, the mode switching circuit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, and a NOR gate. The step of generating a second mode switching signal through the mode switching circuit when the comparator has not detected a charging signal for three consecutive clock cycles can be further divided into the following steps: S1031. Step S1031: When the comparator does not detect a charging signal for three consecutive clock cycles, it outputs an enable signal through the first D flip-flop, the second D flip-flop, the third D flip-flop, and the OR gate, and outputs a second mode switching signal through the fourth D flip-flop based on the enable signal.

[0036] Specifically, such as Figure 5 The diagram shown is a timing diagram of a DC-DC level converter switching from normally open mode to intermittent operating mode. Figure 6 The diagram shows a partial circuit diagram of the mode switching circuit, where S2 is the trigger signal for the lower transistor on the left side of the inductor of the Buck-Boost DC-Level Converter.

[0037] In some optional embodiments, when the system triggers a charging signal, S2 is high, the shift register in the mode switching circuit records the current charging signal and switches EN[1:3] to 100, and rst refreshes the EN[1] signal to 0 on each rising edge of the clock. On the next rising edge of the clock, the shift register switches EN[1:3] to 010. Since S2 has not been high during this clock cycle, it indicates that the converter has not received a charging signal during this clock cycle, and the EN[1] signal remains 0. The shift register switches EN[1:3] to 001 on the rising edge of the third clock cycle. Since no charging signal has been received yet, EN[1] remains 0. If the system has no charging signal for three consecutive clock cycles, EN[1:3] is 000, which means that the converter output has entered a light load state. The mode switching circuit immediately triggers the second mode conversion signal MS, which is low, and the converter switches to intermittent working mode.

[0038] The charging state of the system is saved by the output of the three-shift register in the mode switching circuit, and the last D flip-flop triggers the mode switching signal MS.

[0039] The above describes the DC-DC converter wake-up method based on multi-level clock frequency conversion intermittent control according to embodiments of this application. It can be recognized that the embodiments of this application have the following advantages: I. Based on the characteristics of DC-DC level converters in IoT applications that are in standby mode for a long time, the frequency of the system's output voltage detection is adjusted according to the load conditions, making full use of the advantages brought by different controls and achieving higher system efficiency.

[0040] Second, a multi-level clock frequency conversion intermittent adjustable control method is introduced. The clock frequency will increase with the triggering of the charging signal, thereby speeding up the detection of output voltage changes and optimizing the undershoot / overshoot of output voltage under load transients.

[0041] Third, an asymmetric switching method is proposed, meaning the switching conditions between the two modes are different. The minimum switching time from intermittent operation mode to normally open mode is 43μs, thus avoiding the problem of switching back and forth between the two modes.

[0042] Fourth, the two proposed control methods use the same control loop, thus avoiding the problem of inconsistent DC levels of the DC-to-DC level converter output voltage when switching between the two modes. By rationally configuring the comparator's power consumption through the two control methods, the system's static power consumption can also be better reduced.

[0043] Reference Figure 7 , Figure 7 This is a circuit implementation diagram of a DC-level converter wake-up system based on multi-level clock frequency conversion intermittent regulation provided in one embodiment of this application. This application also provides a DC-level converter wake-up system based on multi-level clock frequency conversion intermittent regulation, including a control module, a comparator, an oscillator, and a mode switching circuit. The control module, the oscillator, and the mode switching circuit are all connected to the comparator, and the control module and the mode switching circuit are also connected to the oscillator.

[0044] Specifically, when the mode switching signal MS output by the mode switching circuit is high, the DC-DC level converter is in a normally open state, the comparator continuously monitors changes in the output voltage, and CLK cannot control the switching of the comparator. However, when the output load of the DC-DC level converter becomes lighter, and there is no charging signal for three consecutive CLK cycles, the mode switching circuit switches the DC-DC level converter to intermittent operation mode, the mode switching signal MS switches to 0, and the comparator only operates when the clock signal is high, greatly reducing the comparator's power consumption. When the output load becomes heavier, the mode switching signal detects that the comparator outputs high for three consecutive CLK cycles, triggering the mode switching signal MS to switch high, and the DC-DC level converter switches to normally open mode.

[0045] As a further optional implementation, the mode switching circuit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, and a NOR gate. The input of the first D flip-flop is connected to a DC-DC level converter, the output of the first D flip-flop is connected to the input of the second D flip-flop, the output of the second D flip-flop is connected to the input of the third D flip-flop, the outputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop are all connected to the input of the NOR gate, and the output of the NOR gate is connected to the input of the fourth D flip-flop.

[0046] like Figure 8 The diagram shown is a schematic block diagram of the controller and driver. In this embodiment, the comparator, mode switching circuit, and frequency adaptive adjustable oscillator are all integrated on a silicon wafer using integrated circuit technology. The signal interaction between the three is shown in the timing diagram above. The oscillator controls the operation of the comparator, and the output of the comparator adjusts the oscillator frequency through the mode switching circuit.

[0047] Furthermore, in addition to the power stage, to ensure the normal operation of the proposed power supply topology, the controller structure includes: a feedback network (resistive voltage divider feedback network), a comparator (comparing the reference voltage and the feedback voltage), dead-time control logic (preventing the power transistor from generating instantaneous large current), a level shifter, and a drive circuit.

[0048] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0049] This application also provides a DC level converter, including the aforementioned DC level converter wake-up system.

[0050] Similarly, the content of the above method embodiments is applicable to this DC-DC level converter embodiment. The specific functions implemented by this DC-DC level converter embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0051] In the foregoing description of this specification, the references to terms such as "one embodiment," "another embodiment," or "some embodiments," etc., indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0052] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

[0053] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.

Claims

1. A wake-up method for a DC-DC level converter based on multi-level clock frequency conversion intermittent control, characterized in that, Includes the following steps: The charging signal of the DC-DC level converter is detected by a comparator; When the DC-DC level converter switches from intermittent working mode to normally open mode, if the comparator detects the charging signal in three consecutive clock cycles, the oscillator performs multi-level clock frequency conversion in each clock cycle, and the mode switching circuit generates a first mode switching signal to complete the mode switching. When the DC-DC level converter switches from normally open mode to intermittent operating mode, if the comparator does not detect the charging signal for three consecutive clock cycles, the mode switching circuit generates a second mode switching signal to complete the mode switching.

2. The DC-DC level converter wake-up method according to claim 1, characterized in that, When the comparator detects the charging signal for three consecutive clock cycles, the oscillator performs multi-level clock frequency conversion in each clock cycle, specifically including: When the comparator detects the charging signal in the first clock cycle, it generates a first frequency switching signal through the control module, and the oscillator converts the first clock cycle signal into a second clock cycle signal according to the first frequency switching signal. When the comparator detects the charging signal in the second clock cycle, it generates a second frequency switching signal through the control module, and the oscillator converts the second clock cycle signal into a third clock cycle signal according to the second frequency switching signal. When the comparator detects the charging signal in the third clock cycle, it generates a third frequency switching signal through the control module, and the oscillator converts the third clock cycle signal into the first clock cycle signal according to the third frequency switching signal. Wherein, the first clock cycle signal is greater than the second clock cycle signal, and the second clock cycle signal is greater than the third clock cycle signal.

3. The DC-DC level converter wake-up method according to claim 1, characterized in that, The mode switching circuit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, and a NOR gate. When the comparator fails to detect the charging signal for three consecutive clock cycles, the mode switching circuit generates a second mode switching signal, specifically: When the comparator does not detect the charging signal for three consecutive clock cycles, it outputs an enable signal through the first D flip-flop, the second D flip-flop, the third D flip-flop, and the NOR gate. The fourth D flip-flop then outputs the second mode switching signal based on the enable signal.

4. The DC-DC level converter wake-up method according to claim 2, characterized in that, The oscillator adjusts the number of parallel capacitors according to the first frequency switching signal, the second frequency switching signal, and the third frequency switching signal to achieve multi-level clock frequency conversion.

5. The DC-DC level converter wake-up method according to claim 2, characterized in that, The first clock cycle signal is 33μs, the second clock cycle signal is 6μs, and the third clock cycle signal is 4μs.

6. The DC-DC level converter wake-up method according to claim 1, characterized in that, The first mode switching signal is high level, and the second mode switching signal is low level.

7. A DC-DC level converter wake-up system based on multi-level clock frequency conversion intermittent control, characterized in that, The method for performing a DC-DC level converter wake-up method as described in any one of claims 1 to 6 includes a control module, a comparator, an oscillator, and a mode switching circuit, wherein the control module, the oscillator, and the mode switching circuit are all connected to the comparator, and the control module and the mode switching circuit are also connected to the oscillator.

8. The DC-DC level converter wake-up system according to claim 7, characterized in that, The mode switching circuit includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a fourth D flip-flop, and a NOR gate. The input of the first D flip-flop is connected to the DC-DC level converter. The output of the first D flip-flop is connected to the input of the second D flip-flop. The output of the second D flip-flop is connected to the input of the third D flip-flop. The outputs of the first D flip-flop, the second D flip-flop, and the third D flip-flop are also connected to the input of the NOR gate. The output of the NOR gate is connected to the input of the fourth D flip-flop.

9. A DC-DC level converter, characterized in that, Includes a DC level converter wake-up system as described in any one of claims 7 to 8.

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