A method for locating short circuit faults of an inverter IGBT

Abstract

This invention relates to the field of frequency converter control technology for new energy vehicles, and particularly to a method for locating short-circuit faults in inverter IGBTs. The method includes the following steps: During the pre-charge phase of the frequency converter controller, multiple timing steps with unique count values ​​are divided. Preset delays are inserted between adjacent timing steps. The overall process is divided into initialization, lower bridge arm detection, isolation, and upper bridge arm detection phases. In the upper and lower bridge arm detection phases, each subsequent timing step, compared to the previous one, only adds the activation of one IGBT, while the remaining IGBTs remain off. During the execution of the timing steps, the hardware overcurrent protection signal is continuously monitored. Once an overcurrent fault is triggered, the count value of the current timing step is immediately recorded. Based on a preset timing step-IGBT fault mapping table, the short-circuited IGBT is accurately determined, and a fault response and information reporting are executed. This invention abandons the traditional independent and time-consuming self-test process and complex timing algorithms, completely reusing the pre-charge process to achieve zero additional time overhead.

Description

Technical Field

[0001] This invention relates to the field of frequency conversion control technology for new energy vehicles, and in particular to a method for locating short-circuit faults in inverter IGBTs. Background Technology

[0002] In the field of frequency conversion control for new energy vehicles, the three-phase inverter frequency converter is the core power conversion device of the electric drive system. It mainly consists of six IGBT power devices in the upper and lower bridge arms of the three phases. The operational reliability of the IGBT directly determines the safety and stability of the entire electric drive system. Among them, short-circuit breakdown is the most common and most harmful failure mode of IGBT. After a short circuit, the IGBT will be permanently in a conducting state and will not be controlled by the gate signal. This can easily cause a shoot-through fault in the same phase bridge arm, resulting in an extremely large short-circuit current, burning out the power devices and controller, and causing serious problems such as equipment shutdown and power interruption. Therefore, accurate detection and location of IGBT short-circuit faults are crucial for the safe operation of the equipment.

[0003] Currently, the mainstream IGBT short-circuit protection method in the industry is hardware overcurrent protection, which quickly blocks the PWM by current sampling and comparator triggering. This method can quickly detect system overcurrent anomalies and block the drive signal, but it can only determine whether a fault exists, and cannot accurately locate which specific IGBT has short-circuited. After a fault occurs, all six IGBTs need to be manually checked and repaired one by one, which is inefficient, costly to maintain, and results in long equipment downtime.

[0004] Current self-testing solutions often employ narrow pulses to each phase arm during the pre-charge phase to detect current. However, these solutions generally suffer from the following problems: complex pulse timing design requiring precise pulse width control to avoid damage; poor anti-interference capability due to complex current threshold comparisons in the detection logic; and failure to deeply integrate pre-charge operation with fault location, resulting in additional system time consumed during the detection process. Therefore, there is an urgent need for a precise fault location method that can utilize the inherent flow of the system's pre-charge phase and, through simple and reliable timing logic, directly map hardware overcurrent signals to specific faulty IGBTs. Summary of the Invention

[0005] The purpose of this invention is to address the technical problems of existing frequency converters in locating IGBT short-circuit faults during the pre-charge stage, which involve complex timing design, independent time consumption of the process, and additional startup time. This invention provides a method for locating IGBT short-circuit faults in inverters.

[0006] The technical solution adopted by this invention to solve its technical problem is: a method for locating short-circuit faults in inverter IGBTs, comprising the following steps: S1. The pre-charge stage of the frequency converter is divided into multiple timing steps, and a preset delay is inserted between adjacent timing steps. Each timing step corresponds to a unique count value. S2. The complete timing steps include the initialization stage, the lower arm detection stage, the isolation stage, and the upper arm detection stage. In the lower arm detection stage and the upper arm detection stage, the latter timing step only adds one IGBT to be turned on compared to the former timing step, while the other IGBTs remain off. S3. Sequentially execute multiple timing steps and continuously monitor hardware overcurrent protection signals; S4. If a hardware overcurrent protection signal is triggered when executing a specific timing step, the count value of the current timing step is recorded, and the specific IGBT short-circuit fault location is determined according to the preset timing step-IGBT fault mapping table. S5. Perform fault response and information reporting.

[0007] Furthermore, in step S1, the multiple time steps are consecutive.

[0008] Furthermore, the delay between adjacent timing steps is greater than the response time of the hardware overcurrent protection circuit but less than the total duration of the precharge phase.

[0009] Furthermore, in step S1, multiple timing steps include: Step 1: Initialization phase; Step 2: Only activate the IGBT of the lower arm of phase A; Step 3: Activate the IGBTs of the lower arm of phase A and the lower arm of phase B; Step 4: Turn on the IGBTs of the lower arms of phases A, B, and C; Step 5: Isolation Phase; Step 6: Only activate the IGBT of the upper arm of phase A; Step 7: Activate the IGBTs of Phase A upper arm and Phase B upper arm; Step 8: Turn on the IGBTs of the upper bridge arms of phases A, B, and C.

[0010] Furthermore, step 1 is the initialization phase, where all PWM outputs are set to high impedance or a safe level; step 5 is the isolation phase, where all IGBTs are turned off, isolating the lower bridge arm detection from the upper bridge arm detection; the lower bridge arm detection phase includes steps 2, 3, and 4; the upper bridge arm detection phase includes steps 6, 7, and 8.

[0011] Furthermore, in step S2, the method of turning on the IGBT includes: by modifying the manual output control register of the PWM controller, forcibly specifying which IGBT is turned on in each timing step.

[0012] Furthermore, in step S4, the timing step-IGBT fault mapping table is as follows: When the hardware overcurrent protection signal occurs during the stage where only the lower arm of phase A is conducting, it is determined that the IGBT of the upper arm of phase A is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the lower bridge arm of phase A and phase B, it is determined that the IGBT of the upper bridge arm of phase B is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the lower bridge arm of phases A, B, and C, it is determined that the IGBT of the upper bridge arm of phase C is short-circuited. When the hardware overcurrent protection signal occurs during the stage where only the upper arm of phase A is conducting, it is determined that the IGBT of the lower arm of phase A is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the upper bridge arm of phase A and phase B, it is determined that the IGBT of the lower bridge arm of phase B is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the upper bridge arm of phases A, B, and C, it is determined that the IGBT of the lower bridge arm of phase C is short-circuited.

[0013] Furthermore, in step S5, the method of performing fault response and information reporting includes: blocking all PWM outputs, putting the system into a fault-safe state, and reporting a fault code containing the specific fault IGBT number.

[0014] Furthermore, if all timing steps are completed without triggering the hardware overcurrent protection signal, it is determined that all six IGBTs are free from short-circuit faults, and the system proceeds with the normal startup process.

[0015] The beneficial effects of this invention are: This invention abandons the traditional independent fault detection timing architecture, fully integrating the IGBT single-tube short-circuit self-test function into the inherent pre-charge stage of the frequency converter. No separate testing procedure is required, completely eliminating the technical problems of independent process time consumption and additional startup time caused by traditional self-test methods. It achieves fault detection with zero additional time overhead, ensuring efficient equipment startup. Simultaneously, it innovatively adopts a phase-by-phase incremental approach, with only one IGBT added to the detection stage of the upper and lower bridge arms in a single step, achieving fault determination through a unique mapping relationship between timing steps and IGBT faults. This avoids the complex timing control and cumbersome calculation logic of traditional methods, significantly simplifying program design. This invention requires no new hardware circuitry, fully reusing existing hardware overcurrent protection resources, resulting in zero incremental hardware cost. Reasonable delays are reserved between timing steps to ensure reliable hardware protection response, accurately locating short-circuit faults in any of the six IGBTs in the inverter, effectively avoiding the risks of bus shoot-through and device burnout, and significantly improving the reliability, safety, and versatility of the frequency converter's pre-charge stage self-test. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall process of a method for locating short-circuit faults in an inverter IGBT according to the present invention.

[0017] Figure 2This is a schematic diagram of the IGBT switching process in the method for locating short-circuit faults in an inverter IGBT according to the present invention.

[0018] Figure 3 This is a table showing the mapping relationship between timing steps and IGBT faults. Detailed Implementation

[0019] The embodiments are further described below with reference to the accompanying drawings.

[0020] To address the technical problems of existing frequency converters in locating IGBT short-circuit faults during the pre-charge phase, such as complex timing design, independent time consumption of the process, and additional startup time, this embodiment provides a method for locating IGBT short-circuit faults in inverters.

[0021] like Figure 1 As shown, this embodiment specifically includes the following steps: S1. The pre-charge phase of the frequency converter is divided into multiple timing steps, with a preset delay inserted between adjacent timing steps. Each timing step corresponds to a unique count value. Specifically, in step S1, this embodiment divides the entire pre-charge stage of the frequency converter start-up into several consecutive timing steps. Each timing step corresponds to a unique count value. A preset fixed delay is inserted between adjacent timing steps. The delay duration is longer than the response time of the hardware overcurrent protection circuit to ensure that the protection signal can be reliably triggered when a short circuit occurs, while avoiding the total pre-charge stage time from exceeding the standard due to excessive delay duration.

[0022] Specifically, such as Figure 2 As shown, this embodiment divides the pre-charging stage into the following sequential steps: Step 1 (PRE_CHARGE_STEP1): Initialization phase, set all PWM outputs to high impedance or safe level; Step 2 (PRE_CHARGE_STEP2): Only activate the IGBT of the lower arm of phase A; Step 3 (PRE_CHARGE_STEP3): Activate the IGBTs of the lower arm of phase A and the lower arm of phase B (add a lower arm of phase B). Step 4 (PRE_CHARGE_STEP4): Activate the IGBTs of the lower arms of phases A, B, and C (add a lower arm of phase C). Step 5 (PRE_CHARGE_STEP5): Shut down all IGBTs (isolation phase); Step 6 (PRE_CHARGE_STEP6): Only activate the upper arm IGBT of phase A; Step 7 (PRE_CHARGE_STEP7): Activate the IGBTs of Phase A upper arm and Phase B upper arm (add Phase B upper arm). Step 8 (PRE_CHARGE_STEP8): Activate the upper arm IGBTs of phases A, B, and C (add a new upper arm of phase C).

[0023] When the frequency converter is powered on the bus capacitor, it must go through a pre-charge stage to prevent inrush current. In this embodiment, this process is also used as the detection window for IGBT short circuit. There is no need to plan the self-test time separately. It makes full use of the inherent process of the pre-charge stage and does not require additional time overhead.

[0024] S2. The complete timing sequence includes the initialization phase, the lower bridge arm detection phase, the isolation phase, and the upper bridge arm detection phase. Among them, in the lower bridge arm detection phase and the upper bridge arm detection phase, the latter timing step only adds the activation of one IGBT compared to the former timing step, while the other IGBTs remain in the off state. In step S2, the frequency converter executes the timing steps in step S1 sequentially according to the incrementing timing step counter value. In each timing step, by modifying the PWM manual output control register, a specific IGBT is forced to be in the on state, while the remaining IGBTs remain in the off state.

[0025] In this embodiment, the timing step in the lower arm detection stage and the upper arm detection stage only adds one IGBT to the current timing step compared to the previous timing step. This added IGBT is the only variable that changes in the current timing step, which simplifies the complex multivariate short circuit troubleshooting problem into a single variable judgment problem. This enables the accurate differentiation of any short circuit among the six IGBTs, providing the most direct guidance for maintenance and replacement.

[0026] S3. Sequentially execute multiple timing steps and continuously monitor hardware overcurrent protection signals: In step S3, this embodiment is designed so that the hardware overcurrent protection circuit continues to operate during the execution of multiple timing steps. If a short circuit failure exists in the complementary bridge arm of the IGBT newly turned on in the current timing step, a bus straight-through loop will be formed at the moment of turn-on, triggering the hardware overcurrent protection signal (HW_OCP). Once this signal is captured, the count value corresponding to the current timing step is immediately recorded, and timing incrementing stops.

[0027] S4. If a hardware overcurrent protection signal is triggered during the execution of a specific timing step, the count value of the current timing step is recorded, and the specific IGBT short-circuit fault location is determined according to the preset timing step-IGBT fault mapping table: In step S4, the frequency converter uses the timing step count value when the overcurrent occurs to query the preset "Timing Step-IGBT Fault Mapping Table" to uniquely identify the short-circuited IGBT.

[0028] like Figure 3 As shown, the mapping relationship in this embodiment is as follows: When the overcurrent signal occurs in step 2 (only A is conducting), it is determined that the upper arm IGBT (UH0) of phase A is short-circuited; When the overcurrent signal occurs in step 3 (A down + B down conduction), it is determined that the upper bridge arm IGBT (WH0) of phase B is short-circuited; When the overcurrent signal occurs in step 4 (three-phase conduction), it is determined that the upper arm IGBT (VH0) of phase C is short-circuited; When the overcurrent signal occurs in step 6 (only A is conducting), it is determined that the lower arm IGBT (UL0) of phase A is short-circuited; When the overcurrent signal occurs in step 7 (A on + B on conduction), it is determined that the IGBT (WL0) of the lower arm of phase B is short-circuited; When the overcurrent signal occurs in step 8 (three-phase conduction), it is determined that the lower arm IGBT (VL0) of phase C is short-circuited.

[0029] The design logic of step S4 in this embodiment is as follows: Since no overcurrent protection signal was triggered in any previous timing steps, it can be determined that if an overcurrent protection signal is generated in the current timing step, the only cause is a short circuit in the complementary bridge arm device of the newly activated IGBT in the current timing step. This establishes a unique mapping relationship between the timing steps and the faulty IGBT. Without adding an independent detection process or occupying extra startup time, this solves the technical pain points of complex traditional timing design and time-consuming independent detection.

[0030] S5. Perform fault response and information reporting: In step S5, according to the short-circuited IGBT determined in step S4, this embodiment sets the corresponding IGBT short-circuit record fault flag in the inverter controller error flag register (e.g., HW_ERR_IGBT_A_H indicates that the upper IGBT of A is short-circuited, and HW_ERR_IGBT_A_L indicates that the lower IGBT of A is short-circuited). Then, it immediately blocks the PWM drive signals of all IGBTs to safely shut down the system and reports a fault code containing the specific faulty IGBT number through the communication interface.

[0031] If all timing steps from step 1 to step 8 are executed successfully without triggering any overcurrent protection signal, it is determined that all six IGBTs are free from short-circuit faults, and the subsequent normal startup process (such as entering FOC positioning) continues.

[0032] This embodiment fully utilizes the inherent bus pre-charging process of the frequency converter controller to simultaneously complete the IGBT short-circuit fault self-check, without adding extra detection timing and startup time. Without affecting system startup efficiency, it transforms the complex multi-tube short-circuit troubleshooting problem into a single-variable precise judgment by adding single-tube conduction timing logic step by step. This can accurately locate any faulty IGBT in the three-phase inverter topology, effectively solving the shortcomings of traditional hardware overcurrent protection that can only detect faults but cannot locate the fault location, significantly shortening equipment fault diagnosis and repair time and reducing operation and maintenance costs. Furthermore, this embodiment… It requires no complex algorithms or additional hardware circuits, fully reusing the original overcurrent protection and PWM control resources of the equipment. It has the advantages of zero additional hardware cost, fast response speed, strong anti-interference ability and high reliability. Furthermore, through the preset delay design to match the hardware protection response speed, the PWM drive signal is blocked immediately in case of a fault, so that the system can be safely shut down. The design of reporting fault codes effectively suppresses short-circuit current surges, avoids secondary damage to power devices, and significantly improves the power-on self-test safety of the frequency converter and the stability of equipment operation. It has strong versatility and good portability, and is compatible with various three-phase inverters and new energy frequency conversion control equipment.

Claims

1. A method for locating short-circuit faults in an inverter's IGBT, characterized in that, Includes the following steps: S1. The pre-charge stage of the frequency converter is divided into multiple timing steps, and a preset delay is inserted between adjacent timing steps. Each timing step corresponds to a unique count value. S2. The complete timing steps include the initialization stage, the lower arm detection stage, the isolation stage, and the upper arm detection stage. In the lower arm detection stage and the upper arm detection stage, the latter timing step only adds one IGBT to be turned on compared to the former timing step, while the other IGBTs remain off. S3. Sequentially execute multiple timing steps and continuously monitor hardware overcurrent protection signals; S4. If a hardware overcurrent protection signal is triggered when executing a specific timing step, the count value of the current timing step is recorded, and the specific IGBT short-circuit fault location is determined according to the preset timing step-IGBT fault mapping table. S5. Perform fault response and information reporting.

2. The method for locating short-circuit faults in an inverter's IGBT according to claim 1, characterized in that, In step S1, the multiple timing steps are consecutive.

3. The method for locating short-circuit faults in an inverter's IGBT according to claim 2, characterized in that, The delay between adjacent timing steps is greater than the response time of the hardware overcurrent protection circuit but less than the total duration of the precharge phase.

4. The method for locating short-circuit faults in an inverter's IGBT according to claim 1, characterized in that, In step S1, multiple timing steps include: Step 1: Initialization phase; Step 2: Only activate the IGBT of the lower arm of phase A; Step 3: Activate the IGBTs of the lower arm of phase A and the lower arm of phase B; Step 4: Turn on the IGBTs of the lower arms of phases A, B, and C; Step 5: Isolation Phase; Step 6: Only activate the upper arm IGBT of phase A; Step 7: Activate the IGBTs of Phase A upper arm and Phase B upper arm; Step 8: Turn on the IGBTs of the upper bridge arms of phases A, B, and C.

5. The method for locating a short-circuit fault in an inverter's IGBT according to claim 4, characterized in that, Step 1 is the initialization phase, setting all PWM outputs to high impedance or safe level; Step 5 is the isolation phase, turning off all IGBTs and isolating the lower bridge arm detection and upper bridge arm detection; the lower bridge arm detection phase includes steps 2, 3, and 4; the upper bridge arm detection phase includes steps 6, 7, and 8.

6. The method for locating a short-circuit fault in an inverter's IGBT according to claim 1, characterized in that, In step S2, the IGBTs are turned on by modifying the manual output control register of the PWM controller to force the specific IGBT to be turned on in each timing step.

7. The method for locating a short-circuit fault in an inverter's IGBT according to claim 1, characterized in that, In step S4, the timing step - IGBT fault mapping table is as follows: When the hardware overcurrent protection signal occurs during the stage where only the lower arm of phase A is conducting, it is determined that the IGBT of the upper arm of phase A is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the lower bridge arm of phase A and phase B, it is determined that the IGBT of the upper bridge arm of phase B is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the lower bridge arm of phases A, B, and C, it is determined that the IGBT of the upper bridge arm of phase C is short-circuited. When the hardware overcurrent protection signal occurs during the stage where only the upper arm of phase A is conducting, it is determined that the IGBT of the lower arm of phase A is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the upper bridge arm of phase A and phase B, it is determined that the IGBT of the lower bridge arm of phase B is short-circuited. When the hardware overcurrent protection signal occurs during the conduction stage of the upper bridge arm of phases A, B, and C, it is determined that the IGBT of the lower bridge arm of phase C is short-circuited.

8. The method for locating a short-circuit fault in an inverter's IGBT according to claim 1, characterized in that, In step S5, the method of performing fault response and information reporting includes: blocking all PWM outputs, putting the system into a fault-safe state, and reporting a fault code containing the specific fault IGBT number.

9. The method for locating a short-circuit fault in an inverter's IGBT according to claim 1, characterized in that, If all timing steps are completed and no hardware overcurrent protection signal is triggered, it is determined that there is no short circuit fault in all six IGBTs, and the system proceeds with the normal startup process.

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