Switching converter comprising an auxiliary bootstrap capacitor

Abstract

The present application relates to a switched converter comprising an auxiliary bootstrap capacitor. An apparatus comprises a first transistor (M1) having a first transistor terminal and a second transistor terminal. A second transistor (M2) has a third transistor terminal coupled to the second transistor terminal and has a fourth transistor terminal. A third transistor (HS) has a control terminal and a fifth transistor terminal. A driver (110) has a driver output coupled to the control terminal and has a first driver terminal and a second driver terminal. The first driver terminal is coupled to the fourth terminal. A capacitor (C3) has a first capacitor terminal coupled to the first driver terminal and has a second capacitor terminal coupled to the second driver terminal and the fifth transistor terminal.

Description

Technical Field

[0001] This application relates to a switching converter that includes an auxiliary bootstrap capacitor. Background Technology

[0002] Some switching converters have a high-side (HS) transistor coupled to a low-side (LS) transistor. Due to the traces coupling the HS transistor to the LS transistor, such switching converters have a parasitic inductance between the HS and LS transistors. During each switching cycle of the switching converter, the HS transistor turns on and off. When the HS transistor turns on, the sudden increase in current through the HS transistor causes a voltage to be generated across the parasitic inductance connected in series with the source of the HS transistor. Similarly, when the HS transistor turns off, the sudden decrease in current causes a voltage of opposite polarity to be generated across the parasitic inductance connected in series with the source of the HS transistor. The voltage across the parasitic inductance can slow down the switching speed of the HS transistor and / or damage the driver controlling the HS transistor. Summary of the Invention

[0003] In one example, a device includes a first transistor having a first transistor terminal and a second transistor terminal. A second transistor has a third transistor terminal coupled to the second transistor terminal and a fourth transistor terminal. The third transistor has a control terminal and a fifth transistor terminal. A driver has a driver output coupled to the control terminal and has a first driver terminal and a second driver terminal. The first driver terminal is coupled to the fourth terminal. A capacitor has a first capacitor terminal coupled to the first driver terminal and a second capacitor terminal coupled to the second driver terminal and the fifth transistor terminal.

[0004] In another example, a power converter includes a first transistor having a first control terminal, a first transistor terminal, and a second transistor terminal. The first transistor terminal is coupled to a first voltage terminal. A first driver has a first driver output, a first driver terminal, and a second driver terminal. The first driver output is coupled to the first control terminal. A second transistor has a second control terminal, a third transistor terminal, and a fourth transistor terminal. The third transistor terminal is coupled to the second transistor terminal, and the fourth transistor terminal is coupled to the second voltage terminal. The second driver has a second driver output, a third driver terminal, and a fourth driver terminal. The second driver output is coupled to the second control terminal. The third transistor has a third control terminal, a fifth transistor terminal, and a sixth transistor terminal. The sixth transistor terminal is coupled to the first driver terminal. A capacitor has a first capacitor terminal and a second capacitor terminal. The first capacitor is coupled to the first driver terminal and the sixth transistor terminal. The second capacitor terminal is coupled to the second driver terminal, the second transistor terminal, and the third transistor terminal. The fourth transistor has a seventh transistor terminal coupled to the fifth transistor terminal.

[0005] In another example, a device includes a first transistor having a first transistor terminal and a second transistor terminal. A second transistor has a first control terminal, a third transistor terminal, and a fourth transistor terminal. The third transistor terminal is coupled to the second transistor terminal. The third transistor has a second control terminal and a fifth transistor terminal. A driver has a driver output coupled to the second control terminal and has a first driver terminal and a second driver terminal. The first driver terminal is coupled to the fourth transistor terminal. A first capacitor has a first capacitor terminal and a second capacitor terminal, the first capacitor terminal being coupled to the first driver terminal and the fourth transistor terminal, and the second capacitor terminal being coupled to the second driver terminal and the fifth transistor terminal. A second capacitor has a third capacitor terminal and a fourth capacitor terminal. The third capacitor terminal is coupled to the second transistor terminal and the third transistor terminal, and the fourth capacitor terminal is coupled to the fifth transistor terminal. A control circuit has a control input and a control output, the control output being coupled to a first switch control terminal, the control circuit being configured to: immediately disconnect the second transistor after the driver turns on the third transistor to allow current from the first capacitor to flow to the first driver terminal, and then turn on the second transistor while the third transistor is still on, thereby allowing current from the second capacitor to flow through the second transistor to the first driver terminal. Attached Figure Description

[0006] Figure 1 This is a schematic diagram of a switching converter in an example.

[0007] Figure 2 This is a schematic diagram of a switching converter containing control circuitry in another example.

[0008] Figure 3 It is an example Figure 2 A schematic diagram of the control circuit.

[0009] Figure 4 In another instance Figure 2 A schematic diagram of the control circuit.

[0010] Figure 5 It is shown Figure 2 Switching converter and Figure 1 The waveform shows the technological advantages of the switching converter compared to other methods. Detailed Implementation

[0011] Use the same reference numerals or other reference indicators in the drawings to indicate the same or similar features (functionally and / or structurally).

[0012] Figure 1 This is a schematic diagram of an example switching converter 100. The switching converter 100 includes HS and LS transistors, capacitors COUT, CIN, C1 and C2, transistor M1, drivers 110 and 120, and a controller 130. The HS transistor is coupled to the LS transistor at switch terminal 102. In this example, the HS and LS transistors are n-channel field-effect transistors (NFETs). The source of the HS transistor is coupled to the drain of the LS transistor. The drain of the HS transistor is coupled to input voltage terminal 101 (VIN). The source of the LS transistor is coupled to ground terminal 103. A parasitic inductance LPAR lies between the source of the HS transistor and switch terminal 102. The voltage at the source of the HS transistor is V_HS_SW. The parasitic inductance LPAR represents the parasitic inductance of the trace between the source of the HS transistor and the drain of the LS transistor. Inductor L1 has one terminal coupled to switch terminal 102 and another terminal coupled to output voltage terminal 104 (VOUT). Capacitor COUT is coupled between output voltage terminal 104 and ground terminal 103. Capacitor CIN is coupled between input voltage terminal 101 and ground terminal 103.

[0013] Driver 110 has an input 110a, an output 110b, and driver terminals 110c and 110d. Driver 120 has an input 120a, an output 120b, and driver terminals 120c and 120d. Output 110b of driver 110 is coupled to the gate of an HS transistor. Output 120b of driver 120 is coupled to the gate of an LS transistor. Controller 130 has outputs 130a, 130b, and 130c. Controller 130 generates control signals HSDRV and LSDRV at the corresponding outputs 130a and 130b. Output 130a of controller 130 is coupled to input 110a of driver 110, and output 130b is coupled to input 120a of driver 120.

[0014] Transistor M1 is an NFET whose gate is coupled to the output 130c of controller 130. The drain of transistor M1 is coupled at startup terminal 105 to driver terminal 110c of driver 110. The voltage at startup terminal 105 is VBOOT. One terminal of capacitor C2 is coupled to startup terminal 105, and therefore to driver terminal 110c of driver 110. The other terminal of capacitor C2 is coupled to switch terminal 102 and driver terminal 110d. The source of transistor M1 is coupled to one terminal of capacitor C1 and driver terminal 120c of driver 120. The other terminal of capacitor C1 is coupled to driver terminal 120d of driver 120 and ground terminal 103. Voltage rail 115 provides a voltage VDRV (e.g., from an externally supplied voltage source or an internal voltage source) to driver terminal 120c of driver 120 and the source of transistor M1.

[0015] In one instance, Figure 1 Some of the components shown are fabricated on the same integrated circuit (IC), while others are external to the IC. In one example, HS and LS transistors, drivers 110 and 120, transistor M1, and controller 130 are fabricated on the IC. Inductor L1 and capacitors C1, C2, CIN, and COUT may be external to the IC and coupled to the IC via traces, for example, on a printed circuit board. In other examples, Figure 1 Different combinations of components are on the IC. The IC may have externally accessible terminals coupled to the input voltage terminal 101, the switch terminal 102, the ground terminal 103, the start terminal 105, and the voltage rail 115.

[0016] Capacitor C2 is also referred to as a bootstrap capacitor. The terminals of capacitor C2 are coupled between driver terminals 110c and 110d of driver 110. In an example where the IC provides an externally accessible switch terminal 102 and an externally accessible start terminal 105, capacitor C2 is coupled between switch terminal 102 and start terminal 105. The charge on capacitor C2 is used to provide power to driver 110, thereby turning on the HS transistor.

[0017] At the start of each switching cycle, controller 130 asserts the control signal HSDRV to driver 110 and the control signal LSDRV to driver 120 with the appropriate polarity level to turn on the HS transistor and turn off the LS transistor. Controller 130 also asserts the control signal M1_CTRL to the gate of transistor M1 at output 130c, thereby turning off transistor M1. To turn on the HS transistor, the charge on capacitor C2 is used to power driver 110. The charge on capacitor C2 is at least partially dissipated when the HS transistor is turned on.

[0018] During another part of the switching cycle, controller 130 asserts control signals HSDRV, LSDRV, and M1_CTRL with appropriate polarity to turn off the HS transistor and turn on the LS transistor and transistor M1. With transistor M1 on, current from voltage rail 115 flows through transistor M1 to charge capacitor C2, which was previously partially discharged to turn on the HS transistor.

[0019] The current through the HS transistor is I_HS. When the HS transistor is initially turned on, the current I_HS rises rapidly, resulting in a large current variation with respect to time (high di / dt). Due to the reverse recovery of the body diode D3 of the LS transistor, the current I_HS can even be higher than the load current through the inductor L1. The high di / dt of the current I_HS causes a voltage drop VPAR across the parasitic inductance LPAR. The polarity makes the source of the HS transistor more positive than the switching terminal 102. Ideally, the voltage across capacitor C2 is applied to terminals 110c and 110d of driver 110 to turn on the HS transistor. For example, if capacitor C2 is charged to 5V, then driver 110 is powered by 5V between its terminals 110c and 110d when controller 130 asserts the control signal HSDRV to turn on the HS transistor. However, because one terminal of capacitor C2 is coupled to switch terminal 102, as current I_HS ramps up, the voltage drop across the parasitic inductor LPAR results in a smaller voltage being applied across driver terminals 110c and 110d of driver 110. This smaller driver voltage, generated by the voltage drop across parasitic inductor LPAR, leads to a slower switching speed for turning on the HS transistor. This slower HS transistor switching speed results in high switching losses.

[0020] When the HS transistor is initially turned off, the current I_HS drops very rapidly, resulting in a negative voltage VPAR across the parasitic inductance LPAR. This negative voltage VPAR means that the voltage at driver terminal 110d is less than the voltage at switch terminal 102. As a result of the negative voltage VPAR when the HS transistor is initially turned off, the voltage drop between driver terminals 110c and 110d is greater than the voltage across capacitor C2. For example, if capacitor C2 is charged to 5V, the voltage supplied to driver 110 will be greater than 5V. This increased voltage between terminals 110c and 110d can exceed the safe operating area (SOA) of at least some of the transistors in driver 110. For example, it can exceed the rated maximum drain-to-source voltage of the transistors within driver 110. Exceeding the SOA of the transistors within driver 110 can damage such transistors and cause driver 110 to malfunction.

[0021] One possible solution to the above problem is for the IC to include an additional externally accessible terminal directly coupled to the source (terminal 110d) of the HS transistor. Terminal C2b can be directly coupled to terminal 110d, thereby eliminating the effect of LPAR on the HS driver 110. Then, the voltage VPAR will not affect the voltage across terminals 110c and 110d. However, this solution would require an additional externally accessible terminal, which would unnecessarily increase the IC package size.

[0022] Figure 2 This is a schematic diagram of a switching converter 200 in another example. Figure 2 The switching converter 200 in the middle is similar to Figure 1 The switching converter 100 is present, but the switching converter 200 includes transistor M2, capacitor C3, and control circuitry 230, which is not present in the switching converter 100. Similar to the switching converter 100, the switching converter 200 includes HS and LS transistors, capacitors COUT, CIN, C1 and C2, transistor M1, drivers 110 and 120, and controller 130.

[0023] In one instance, Figure 2 Some components shown are fabricated on the same IC, while others are external to the IC. For example, HS and LS transistors, drivers 110 and 120, capacitor C3, transistors M1 and M2, control circuitry 230, and controller 130 can be fabricated on the IC. Inductor L1 and capacitors C1, C2, CIN, and COUT can be external to the IC and coupled to the IC via traces on, for example, a printed circuit board on which the IC is mounted. In other examples, Figure 2Different combinations of components are on the IC. The IC may have externally accessible terminals coupled to the input voltage terminal 101, the switch terminal 102, the ground terminal 103, the start terminal 105, and the voltage rail 115.

[0024] The source of the HS transistor is coupled to the drain of the LS transistor. The drain of the HS transistor is coupled to the input voltage terminal 101. The source of the LS transistor is coupled to the ground terminal 103. The inductor L1 has one terminal coupled to the switch terminal 102 and another terminal coupled to the output voltage terminal 104. The capacitor COUT is coupled between the output voltage terminal 104 and the ground terminal 103. The capacitor CIN is coupled between the input voltage terminal 101 and the ground terminal 103. As described above, the output 110b of the driver 110 is coupled to the gate of the HS transistor, and the output 120b of the driver 120 is coupled to the gate of the LS transistor. The output 130a of the controller 130 is coupled to the input 110a of the driver 110, and the output 130b is coupled to the input 120a of the driver 120.

[0025] Transistor M2 is a p-channel field-effect transistor (PFET). The drain of transistor M2 is coupled to the drain of transistor M1 at the startup terminal 105. The source of transistor M2 is coupled to the driver terminal 110c of driver 110 and the terminal C3a of capacitor C3 at the VBOOT_INT terminal 205. The other terminal C3b of capacitor C3 is coupled to the driver terminal 110d and the source of the HS transistor, instead of being coupled to the switch terminal 102 as in the case of capacitor C2. In other words, terminal C3a is coupled to driver terminal 110d, bypassing the parasitic inductance LPAR. Because capacitor C3 is fabricated on the same IC as driver 110 and HS transistor, terminal C3b can be connected to driver terminal 110d via a shorter trace that does not include the parasitic inductance LPAR. Control circuit 230 has an input 230a and an output 203b. Input 230a is coupled to the output 130a of controller 130 and receives the control signal HSDRV. The output 230b of the control circuit 230 is coupled to the gate of the transistor M2.

[0026] The gate of transistor M1 is coupled to the output 130c of controller 130. The drain of transistor M1 is coupled to one terminal of capacitor C2 and the drain of transistor M2, instead of... Figure 1In the example, it is coupled to driver terminal 110c as in the example. Therefore, the start terminal 105 is not coupled to driver terminal 110c of driver 110, but is coupled to the drain of transistor M2. The other terminal of capacitor C2 is coupled to switch terminal 102 and driver terminal 110d. The source of transistor M1 is coupled to one terminal of capacitor C1 and driver terminal 120c of driver 120. The other terminal of capacitor C1 is coupled to driver terminal 120d of driver 120 and ground terminal 103.

[0027] In operation, control circuit 230 turns transistor M2 on and off based on control signal HSDRV. When controller 130 asserts control signal HSDRV as a logic level (e.g., logic high) to turn on HS transistor, control circuit 230 responds to control signal HSDRV by turning off transistor M2 for a short time (e.g., less than the period of the switching cycle). With transistor M2 off, the voltage at startup terminal 105 is decoupled from VBOOT_INT terminal 205. Capacitor C3 is an auxiliary bootstrap capacitor that provides a voltage across driver terminals 110c and 110d to allow driver 110 to begin turning on HS transistor. Because transistor M2 is off, the voltage drop VPAR across parasitic inductance LPAR does not affect (e.g., does not decrease) the voltage applied across driver terminals 110c and 110d of driver 110.

[0028] In one example, control circuit 230 keeps transistor M2 off during a blanking period approximately equal to the time it takes for the ramp-up of current I_HS to cause a voltage drop VPAR across the parasitic inductance LPAR. At the end of the blanking period, control circuit 230 turns on transistor M2 to allow the voltage across capacitor C2 to power driver 110 and replenish the charge lost by capacitor C3 during the initial blanking period.

[0029] When controller 130 asserts control signals HSDRV and LSDRV to a logic state to turn off the HS transistor and turn on the LS transistor (terminal 102 is pulled to GND), controller 130 asserts control signal M1_CTRL to a logic state to turn on transistor M1 to charge capacitor C2. Furthermore, control circuit 230 continues to keep transistor M2 on to charge capacitor C3.

[0030] Figure 3This is a schematic diagram of an example embodiment of control circuit 230. In this example, control circuit 230 includes a single-trigger circuit 330. The single-trigger circuit 330 generates a pulse at output 230b in response to, for example, the rising edge of a control signal HSDRV. The width of the pulse generated by the single-trigger circuit 330 is approximately equal to the blanking period. Therefore, the single-trigger circuit 330 generates a pulse to turn off transistor M2 for a duration equal to the pulse width (e.g., approximately equal to the blanking period). At the end of the time delay implemented by the pulse generated by the single-trigger circuit 330, the signal at output 230b becomes a logic level (e.g., logic low), thereby turning on transistor M2 to allow capacitor C2 to continue powering driver 110.

[0031] Figure 4 This is a schematic diagram of another example embodiment of control circuit 230. In this example, control circuit 230 includes comparator 402 and latch 406. Comparator 402 has positive (+) and negative (-) inputs and an output. The positive input receives a reference voltage REFA relative to terminal 110d, and the negative input is coupled to capacitor terminal C3a of capacitor C3. Therefore, as described above, control circuit 230 includes input 230a and output 230b, and is also coupled to capacitor C3. Latch 406 has a data (D) input, a clear (CLR) input, and a Q output. The control signal HSDRV is provided to the D input. The output of comparator 402 is coupled to the CLR input. The Q output of latch 406 represents output 230b of control circuit 230. When the voltage across capacitor C3 drops below REFA, the output of comparator 402 goes high, thereby clearing latch 406 and turning on transistor M2 to recharge capacitor C3.

[0032] Figure 5 Waveforms 501 and 502 represent the voltage difference between the voltage at the startup terminal 105 (VBOOT) and the voltage at the source of the HS transistor (V_HS_SW), or in other words, the voltage difference between the driver terminals 110c and 110d of the driver 110. Waveform 501 represents... Figure 1 The voltage difference VBOOT-V_HS_SW of the switching converter 100. Waveform 502 represents... Figure 2 The voltage difference VBOOT_INT-V_HS_SW of the switching converter 100. The waveform shows an example (511) of the voltage difference across the driver 110 when the HS transistor is turned on. For waveform 501 ( Figure 1 The switching converter 100), the voltage difference VBOOT-V_HS_SW drops to a minimum of approximately 1.4V, as shown by reference numeral 521 in the attached figure. However, for waveform 502 ( Figure 2The switching converter 200 has a minimum voltage difference VBOOT_INT-V_HS_SW of approximately 2.9V, which is advantageously 1.5V higher than that of the switching converter 100. As a result, the driver 110 for the switching converter 200 can turn on the HS transistor faster and with lower switching losses.

[0033] The waveform also shows an example (512) of the voltage difference VBOOT-V_HS_SW when the HS transistor is off. For waveform 501 ( Figure 1 The voltage difference VBOOT-V_HS_SW increases to a peak of approximately 11.6V, as shown in figure 531. However, for waveform 502 ( Figure 2 The peak voltage difference VBOOT_INT-V_HS_SW of the switching converter 200 is approximately 7.3V, which is advantageously 4.3V lower than that of the switching converter 100. Therefore, the driver 110 for the switching converter 200 has a lower peak operating voltage than the driver for the switching converter 100, and thus has a lower risk of damage.

[0034] In this specification, the term "coupling" may encompass a connection, transmission, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, if intermediate component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C, such that device B is controlled by the control signal generated by device A.

[0035] Furthermore, in this description, the statement "based on" means "at least partially based on". Therefore, if X is based on Y, then X can depend on Y and any number of other factors.

[0036] A device “configured to” perform a task or function can be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform a function and / or can be configured (or reconfigured) by the user after manufacturing to perform a function and / or other additional or alternative functions. Such configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0037] As used herein, the terms “terminal,” “node,” “interconnect,” “lead,” and “pin” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components. The circuits described herein (e.g., switching converters) are devices.

[0038] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, the described circuits, such as those comprising one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources), may conversely comprise semiconductor elements within only a single physical device (e.g., semiconductor dies and / or integrated circuit (IC) packages), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacture by an end user and / or a third party.

[0039] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuit system. For example, field-effect transistors (“FETs”) (such as n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs, such as NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0040] Reference may be made to the control input and current terminals of the transistor in the claims. In the context of a FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter. The gate, source, and drain of the FET, and the base, collector, and emitter of the BJT, are the terminals of the transistor.

[0041] In this article, "FET on" or "enabled" means that a conductive channel exists in the FET and drain current can flow through it. "FET off" or "disabled" means that no conductive channel exists, and therefore drain current does not flow through the FET. However, an "off" FET can have current flowing through the body diode of the transistor.

[0042] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0043] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be contained within the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0044] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings herein. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0045] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. An apparatus comprising: A first transistor having a first transistor terminal and a second transistor terminal; The second transistor has a third transistor terminal coupled to the second transistor terminal and a fourth transistor terminal; The third transistor has a control terminal and a fifth transistor terminal; A driver having a driver output coupled to the control terminal and having a first driver terminal and a second driver terminal, the first driver terminal being coupled to the fourth terminal; as well as A capacitor having a first capacitor terminal coupled to the first driver terminal and a second capacitor terminal coupled to the second driver terminal and the fifth transistor terminal.

2. The device according to claim 1, wherein the capacitor is a first capacitor, and the device further comprises: A fourth transistor having a sixth transistor terminal coupled to the fifth transistor terminal and a seventh transistor terminal coupled to a ground terminal; as well as The second capacitor has a third capacitor terminal and a fourth capacitor terminal, the third capacitor terminal being coupled to the second transistor terminal and the third transistor terminal, and the fourth capacitor terminal being coupled to the fifth transistor terminal.

3. The device of claim 1, wherein the third transistor is a field-effect transistor having a drain and a source, the third transistor terminal is the drain of the second transistor, and the fourth transistor terminal is the source of the second transistor.

4. The device of claim 3, wherein the second transistor is a p-channel field-effect transistor.

5. The device of claim 3, wherein the driver has a driver input, the third transistor has a control terminal, and the device further includes a control circuit having a control input and a control output, the control input being coupled to the driver input and the control output being coupled to the control terminal of the third transistor.

6. The device of claim 5, wherein the control circuit comprises a single-trigger circuit having a single-trigger input coupled to the control input and a single-trigger output coupled to the control output.

7. The device of claim 5, wherein the control circuitry is configured to respond to the edges of the control signals at the control input and the driver input by generating pulses at the control output.

8. The device of claim 7, wherein the second transistor is configured to disconnect during the pulse generated by the control circuit.

9. The device of claim 5, wherein the control circuitry includes a comparator having a first comparator input coupled to the terminal of the first capacitor and a second comparator input configured to receive a reference voltage.

10. The device of claim 9, wherein the control circuit is configured to: Responding to the edges of the control signals at the control input and the driver input by disconnecting the second transistor; and The second transistor is turned on in response to a comparator signal from the comparator indicating that the voltage at the first capacitor terminal is lower than the reference voltage.

11. A power converter comprising: A first transistor has a first control terminal, a first transistor terminal, and a second transistor terminal, wherein the first transistor terminal is coupled to a first voltage terminal; A first driver has a first driver output, a first driver terminal, and a second driver terminal, wherein the first driver output is coupled to the first control terminal; The second transistor has a second control terminal, a third transistor terminal and a fourth transistor terminal, the third transistor terminal being coupled to the second transistor terminal and the fourth transistor terminal being coupled to the second voltage terminal; The second driver has a second driver output, a third driver terminal and a fourth driver terminal, wherein the second driver output is coupled to the second control terminal; The third transistor has a third control terminal, a fifth transistor terminal and a sixth transistor terminal, the sixth transistor terminal being coupled to the first driver terminal; A capacitor having a first capacitor terminal and a second capacitor terminal, the first capacitor being coupled to a first driver terminal and a sixth transistor terminal, and the second capacitor terminal being coupled to a second driver terminal, a second transistor terminal and a third transistor terminal; as well as The fourth transistor has a seventh transistor terminal coupled to the terminal of the fifth transistor.

12. The power converter of claim 11, wherein the first transistor, the second transistor, the third transistor and the fourth transistor are provided on an integrated circuit, and the integrated circuit has externally accessible terminals coupled to the fifth transistor terminal and the seventh transistor terminal.

13. The power converter of claim 12, wherein the capacitor is a first capacitor, and the power converter includes a second capacitor having a terminal coupled to the externally accessible terminal.

14. The power converter of claim 11, further comprising control circuitry having a control input coupled to the first driver input and a driver output coupled to the third control terminal, wherein in response to signals at the control input and the first driver input: The first driver is configured to turn on the first transistor; and The control circuit is configured to disconnect the third transistor.

15. The power converter of claim 14, wherein the control circuitry is configured to turn on the third transistor after a time delay and while the first transistor is still on.

16. The power converter of claim 11, wherein the third transistor is a p-channel field-effect transistor (PFET), the fifth transistor terminal is the drain of the PFET, and the sixth transistor terminal is the source of the PFET.

17. An apparatus comprising: A first transistor having a first transistor terminal and a second transistor terminal; The second transistor has a first control terminal, a third transistor terminal and a fourth transistor terminal, wherein the third transistor terminal is coupled to the second transistor terminal; The third transistor has a second control terminal and a fifth transistor terminal; A driver having a driver output coupled to the second control terminal and having a first driver terminal and a second driver terminal, the first driver terminal being coupled to the fourth transistor terminal; A first capacitor has a first capacitor terminal and a second capacitor terminal, the first capacitor terminal being coupled to a first driver terminal and a fourth transistor terminal, and the second capacitor terminal being coupled to a second driver terminal and a fifth transistor terminal; A second capacitor has a third capacitor terminal and a fourth capacitor terminal, the third capacitor terminal being coupled to the second transistor terminal and the third transistor terminal, and the fourth capacitor terminal being coupled to the fifth transistor terminal; as well as A control circuit having a control input and a control output, the control output being coupled to the first control terminal, the control circuit being configured to: The second transistor is immediately turned off after the driver turns on the third transistor to allow current from the first capacitor to flow to the first driver terminal. Then, while the third transistor remains on, the second transistor is turned on, thereby allowing current from the second capacitor to flow through the second transistor to the first driver terminal.

18. The device of claim 17, wherein the control circuit is configured to disconnect the second transistor for a predetermined delay period.

19. The device of claim 17, wherein the second transistor is a p-channel field-effect transistor having a source and a drain, the source being the fourth transistor terminal and the drain being the third transistor terminal.

20. The device of claim 17, wherein the device is a switching converter.

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