Switching control system

Abstract

A switching control system for controlling a switching bank comprising two or more switches to generate a switching output signal comprising more than two discrete voltage levels can comprise a sequencer configurable to control respective on and off states of one or more of the two or more switches to generate the switching output signal. This can comprise controlling the two or more switches by a specified sequence of switch states, where each switch state can comprise a respective state of one or more of the two or more switches. The switch states can comprise two or more power states configurable to generate a portion of the switching output signal. The switch states can further comprise one or more transition states configurable to prevent at least one of a shoot-through, reverse current condition, or switching bank damage from occurring when switching between the power states.

Description

Technical Field

[0001] This disclosure relates to the control of switches, and more specifically, but not limited to, a system for controlling switches using a software-defined pattern. Background Technology

[0002] A switch output system can generate a switch output signal from an input source using a switch. This switch output signal can be used to power or control electrical loads, devices, or equipment. The switch output signal can be used for power conversion (such as AC to DC, DC to AC, AC to AC, DC to DC, etc.). The switch output system can be configured to avoid entering an "illegal" state, where current may flow in an undesirable manner. Summary of the Invention

[0003] In one example, a switch control system for controlling a switch group comprising two or more switches to generate a switch output signal comprising more than two discrete voltage levels may include a sequencer configured to control respective on and off states of one or more of the two or more switches to generate the switch output signal. This may include controlling the two or more switches by a specified sequence of switch states, wherein each switch state may include a corresponding state of one or more of the two or more switches. The switch states may include two or more power states configured to be part of generating the switch output signal. The switch states may include one or more transition states configured to prevent at least one of shoot-through, reverse current conditions, or switch group failure during power state switching.

[0004] In one example, a method for generating a switch output signal comprising more than two discrete voltage levels may include controlling at least two switches in a switch group using a sequencer. This may include controlling respective on and off states of the two or more switches to generate the switch output signal. The method may also include controlling the two or more switches through a specified sequence of switch states, wherein each switch state may include a corresponding state of each of the at least two switches. The method may further include controlling the switch group into switch states comprising: two or more power states configured to generate a portion of the switch output signal; and one or more transition states configured to prevent at least one of shoot-through, reverse current, or switch group damage when switching power states.

[0005] In one example, a switch control system for controlling a switch group comprising six or more switches to generate a switch output signal comprising five or more discrete voltage levels may include a sequencer configured to control respective on and off states of the six or more switches to generate the switch output signal. This may include controlling the six or more switches by a specified sequence of switch states, wherein each switch state includes a corresponding state of one or more of the six or more switches. The switch control system may also include a sequencer configured to control the respective on and off states of the six or more switches to generate the switch output signal. The switch control system may also include a controller configured to send configuration information to the sequencer. The sequencer may be configured to control the respective on and off states of the six or more switches using a PWM signal based on the received configuration information, wherein the switch states include two or more power states configured to generate a portion of the switch output signal; and one or more switching states configured to prevent at least one of shoot-through, reverse current conditions, or switch group damage when switching power states. Attached Figure Description

[0006] In the accompanying drawings, the figures may not be drawn to scale, and the same reference numerals may be used to describe substantially similar components in one or more views. The same numbers with different letter suffixes may indicate different instances of substantially similar components. The accompanying drawings are generally illustrative rather than restrictive.

[0007] Figure 1A An example of a portion of a switch control system is shown.

[0008] Figure 1B An example of a switch control system including a switch group is shown.

[0009] Figure 2 An example of a portion of the switch output signal is shown.

[0010] Figure 3 Showing Figure 2 An example of a portion of the output signal of a switch.

[0011] Figure 4 An example showing a portion of the state table is provided.

[0012] Figure 5A A timeline diagram showing an example of the operation section of a switch control system.

[0013] Figure 5B A timeline diagram showing an example of the operation section of a switch control system.

[0014] Figure 6A block diagram showing a portion of an example sequencer.

[0015] Figure 7 A block diagram showing a portion of an example sequencer.

[0016] Figure 8 Examples show a portion of the state table, pattern table, and transformation lookup table.

[0017] Figure 9 An example illustrating a portion of the operation method of a switch control system is shown.

[0018] Figure 10 This is a block diagram illustrating an example of a part of a machine that can implement one or more parts of the present invention. Detailed Implementation

[0019] In one approach, dedicated hardware circuitry can be used to check for and / or prevent illegal states. Such hardware circuitry may be costly, consume significant power or area, or have limited functionality. Therefore, using a switch control system that is at least partially software-based may be preferable.

[0020] Among other things, the inventors also recognize that software-based switching control systems can be configured to check for illegal states and / or utilize transition states to avoid entering illegal states. This is advantageous in multi-level (e.g., more than 2 levels) switching output systems, such as power inverters. Multi-level switching output systems may include multiple switches, which can increase the number of illegal states, increase the difficulty of predicting, detecting, and / or avoiding illegal states, or both.

[0021] Furthermore, the inventors have recognized that programming a switch control system to have defined switch state patterns may be desirable, as these patterns can be used to form specific portions of the switch output signal. Using patterns can create a degree of abstraction, which can simplify the programming, structure, and / or operation of the switch control system, or both.

[0022] Figure 1A and Figure 1B An example of a portion of the switch control system 100 is shown. Figure 1A and Figure 1B The switch control system 100 shown may include a controller 118 and a sequencer 140. Figure 1A and Figure 1B The switch control system 100 is also shown to include or be connected to a switch group 102. The switch group 102 can generate one or more switch output signals at a corresponding switch output signal node 126, for example, it can be used to power a load 130.

[0023] Switch group 102 may include any number of switches 110, which may include one switch, two switches, three switches, four or more switches, six or more switches, eight or more switches, or 24 or more switches. The switches 110 may be arranged in any configuration. Switch group 102 may also include other components and / or circuitry, such as one or more capacitors 124. Switch group 102 may be included in any system. Switch group 102 may be configured for any function and / or purpose. In one example, part or all of switch group 102 may be included in switch control system 100. In one example, part or all of switch group 102 may be separable from switch control system 100.

[0024] In one example (such as) Figure 1A and Figure 1B As shown, switch group 102 can be used in a power inverter that can use power received from input source 122 to generate a specified switching output signal at the corresponding switching output signal node 126. For example, switch group 102 can be used to generate an AC switching output signal with a specified frequency and / or amplitude at switching output signal node 126. The switching output signal at switching output signal node 126 may be filtered, such as filter 142, before reaching load 130. Input source 122 can be any power source, including DC power (such as...). Figure 1B (as shown in the example) or an AC power source with any voltage. In one example, input source 122 may be a DC power source generated by rectifying an AC source (e.g., mains power). Switch group 102 may be, include, or be included in an inverter, such as a power inverter and / or a frequency converter.

[0025] Figure 1A and Figure 1B The diagram illustrates that switch group 102 may include more than one phase, for example, three phases. This facilitates the generation of a three-phase power signal by switch group 102. Switch group 102 may include a first phase switch group 104, a second phase switch group 106, and a third phase switch group 108. The configurations of the second phase switch group 106 and the third phase switch group 108 may be similar to those of the first phase switch group 104, or they may differ in one or more aspects.

[0026] The first phase switch group 104 can be configured to generate a first phase switch output signal 206 having any number of discrete (e.g., quantized, digital) voltage levels at the first phase switch output signal node 128 (e.g., as described below). Figure 2These voltage levels may include two discrete voltage levels, three discrete voltage levels, four discrete voltage levels, or five or more discrete voltage levels. For example, the first phase switch group 104 may be a five-level inverter with output values ​​of: ½ VDC, ¼ VDC, 0, -¼ VDC, and -½ VDC.

[0027] Sequencer 140 can be configured to control respective on and off states of one or more switches 110 to generate switch output signals at corresponding switch output signal nodes 126. For example, one or more switches 110 can be binary switches (such as digital switches) that can include an "on" state (e.g., electrically coupling or substantially electrically coupling the switch nodes together) and an "off" state (e.g., electrically decoupling or substantially decoupling the switch nodes). In one example, switch 110 can be configured for binary switch operation (e.g., transistors biased and / or controlled to operate as substantially binary switches). In one example, sequencer 140 can include a first phase sequencer 112, a second phase sequencer 114, and a third phase sequencer 116. The first phase sequencer 112 can be configured to control respective "on" and "off" states of one or more switches 110 in a first phase switch group 104. The second phase sequencer 114 can be configured to control respective "on" and "off" states of one or more switches 110 in a second phase switch group 106. The third phase sequencer 116 can be configured to control the "on" and "off" states of one or more switches 110 in the third phase switch group 108. In one example, one or more of the first phase sequencer 112, the second phase sequencer 114, and the third phase sequencer 116 can be at least partially combined. For example, one or more of the first phase sequencer 112, the second phase sequencer 114, or the third phase sequencer 116 can be located on the same chip, executed by the same circuit, or both. In one example, one or more of the first phase sequencer 112, the second phase sequencer 114, or the third phase sequencer 116 can be located on different chips.

[0028] The first phase sequencer 112 may include a processor, a memory, and a communication interface. The configurations of the second phase sequencer 114 and the third phase sequencer 116 may be similar to those of the first phase sequencer 112, or they may differ in one or more aspects.

[0029] Controller 118 can be any system capable of executing instructions. Controller 118 can be configured to communicate with sequencer 140 (e.g., with first phase sequencer 112). The controller can generate one or more signals to configure the operation of sequencer 140. In one example, these signals can be sent to sequencer 140 via an internal bus (e.g., controller 118 and sequencer 140 can be included on the same chip, circuit board, or both). Controller 118 can receive feedback signals (e.g., on digital feedback signal bus 136) indicating the switch output signal at switch output signal node 126. For example, the feedback signal can indicate the voltage level and / or frequency of the switch output signal at switch output signal node 126. Controller 118 can send signals to sequencer 140 to adjust the switch output signal at switch output signal node 126, for example, based on the received feedback signal. For example, it may be necessary to adjust the duty cycle of the switch output signal at switch output signal node 126 to generate a specified output voltage, for example, due to differences in the size (e.g., impedance) of load 130. In one example, one or more features of controller 118 may be executed by sequencer 140, and vice versa. In one example, controller 118 and sequencer 140 may be at least partially combined.

[0030] The switch control system 100 may include a feedback circuit 134. The feedback circuit 134 may receive any signal indicating the switch output signal node 126 and may send a feedback signal to the controller 118 based on the received signal. The feedback circuit 134 may receive analog feedback signals (e.g., via analog feedback signal line 132) and generate digital feedback signals (e.g., via digital feedback signal bus 136). The feedback circuit 134 may include an analog-to-digital converter (ADC). The feedback circuit 134 may also include processing or computational circuitry that processes the output of the ADC. In one example, the feedback circuit 134 may be at least partially omitted, and the feedback signal may be sent directly to the controller 118.

[0031] exist Figure 1B In this example, the signal received by the feedback circuit 134 may include an indication of voltage or current at the switch output signal node 126. In one example, the feedback signal may be an encoder, such as a rotary encoder, which may provide an indication of the position or angular velocity of a motor shaft, for example. The feedback circuit 134 may include one or more resolvers, Hall sensors, encoders, optional Σ-Δ ADCs with SINC filters, successive approximation register (SAR) type ADCs, etc.

[0032] Figure 2 An example is shown, comprising a portion of the switch output signal of switch group 102. For example, Figure 2An example of the first phase switch output signal 206 can be shown, for example, it may be located at the first phase switch output signal node 128 (e.g., the switch output signal of the first phase switch group 104). Figure 2 The first phase switch output signal 206 at the first phase switch output signal node 128 is shown to be configured to simulate a specified target signal 202, such as an analog signal (e.g., a non-discrete voltage level signal, such as an AC signal). Figure 2 As shown above, the first phase switch output signal 206 at the first phase switch output signal node 128 may include five discrete voltage levels 208-216.

[0033] Figure 3 Showing Figure 2 An example of a portion of the first phase switch output signal 206 at node 128 of the first phase switch output signal, such as... Figure 2 As shown in region 204. Figure 3 The switching state for generating the first phase switch output signal 206 at the first phase switch output signal node 128 is shown. Figure 4 An example of a portion of the state table is shown, such as the state table for the first phase switch group 104. Figure 4 This demonstrates that each state can include one or more switches 110 in the first phase switch group 104 (e.g., each of the eight switches 110 S1 to S8).

[0034] Switch states may include a vector representation of the states of one or more switches 110 (e.g., all switches) in a switch group (e.g., the first phase switch group 104). For example, switch states may include a linear array of digital values ​​(e.g., 1 and 0) representing the individual switch states (e.g., 1 for on and 0 for off). One or more switch states (e.g., each state) may include the corresponding state of one or more (e.g., each) switches 110 in the first phase switch group 104. Figure 3 The diagram illustrates that switching states can include one or more power supply states (e.g., denoted by V) and one or more transition states (e.g., denoted by T). Power states can be configured to generate a portion of the first-phase switch output signal 206 at the first-phase switch output signal node 128. In one example, any number of power states can exist, including two, three, four, five, or six or more. In one example, more than one switching state can generate the same discrete voltage level (e.g., both V2 and V3 can output ¼ VDC).

[0035] The transition states can be configured to suppress, prevent, reduce, or otherwise adjust one or more of the following conditions: (1) shoot-through (e.g., short-circuit conditions, conditions where current flows along an unexpected path); (2) reverse current conditions (e.g., when current flows in an unexpected direction through a portion of the first phase switch group 104 (e.g., through switch 110 in the wrong direction)); (3) damage to the first phase switch group 104 (e.g., due to overcurrent, reverse current, etc.), such as when switching between power states; or (4) reduce glitch energy when switching between states. In one example, the number of transition states can be arbitrary and may include one, two, three, four, or five or more transition states.

[0036] For example, when switching from one power state to another (e.g., from V1 to V2), one or more of the timing of the various switches (e.g., synchronous, sequential, or delayed) may be uncertain or difficult to determine, the switching speed (e.g., the speed at which a switch switches from off to on, from on to off, or both simultaneously) may be non-zero, or another circuit characteristic (e.g., inductance) may make the switching unpredictable. Due to one or more of these effects, switch states may overlap (e.g., two switches are at least partially on simultaneously), resulting in one or more undesirable circuit conditions, which may include one or more shoot-through, reverse current conditions, or damage to the first phase switch group 104. When switching between power states, transition states can serve as intermediate transition states. For example, transition states help prevent or reduce one or more undesirable circuit conditions such as shoot-through, reverse current conditions, or damage to the first phase switch group 104. For example, a transition to and / or from a specified transition state may be one or more safe transitions with a low risk or no risk of adverse circuit conditions, a transition with less stringent timing requirements (e.g., timing that is easier to achieve using the switch control system 100), or a transition that may exhibit adverse circuit conditions, but at least on average, to a lesser degree than a transition between power states without intermediate transition states. Transition states can be used to help reduce the occurrence of so-called “illegal” states, in which two or more switches 110 are simultaneously or at least partially simultaneously in an unwanted or incompatible state.

[0037] One or more transition states can be shared between one or more transitions. For example, a transition state can be used when transitioning between all power states. In one example, a specific transition state can be used for transitions between specific power states. In one example, transition states may not be used and / or are not expected to be used when switching between certain power states (e.g., due to lower risk of undesirable circuit conditions). In one example, transition patterns (e.g., state sequences) may be used in addition to transition states, or both may be used alternately.

[0038] The first phase sequencer 112 can be configured to control one or more switches 110 by a specified sequence of switch states. For example, the first phase sequencer 112 can generate signals to turn on and / or off corresponding switches in the switch group 110. For example, the first phase sequencer 112 can be coupled to the switches 110 of the first phase switch group 104 using a pulse width modulation (PWM) signal line 138. The PWM signal line 138 may include a connection to a control node (e.g., a gate node) of one or more switches 110 in the first phase switch group 104.

[0039] In one example, the first phase sequencer 112 may be configured to control switch 110 by a specified sequence of switching states such that the first phase switch group 104 is in a powered state for a longer period than it is in a transition state. For example, some or all of the time the first phase switch group 104 is in a transition state may not contribute to or benefit the first phase switch output signal 206 on the first phase switch output signal node 128. For example, the transition state may not be configured to power the load 130. In one example, the first phase sequencer 112 may be configured such that, during a particular sequence of switching states, the time the first phase switch group 104 is in a powered state is two, three, four, or even five or more times longer than the time the first phase switch group 104 is in a transition state.

[0040] In one example, the first phase switch group 104 may include at least six switches 110, and the first phase switch output signal 206 on the first phase switch output signal node 128 may include at least five discrete voltage levels, or both. In one example, the signal on the PWM signal line 138 may be generated at least partially using software (e.g., software within the sequencer 140).

[0041] In one example, controller 118 may be configured to send configuration information to first phase sequencer 112. First phase sequencer 112 may be configured to control the corresponding on and off states of switch 110 using signals (such as PWM signals) based on the received configuration information. The configuration information may include a mode identifier. The mode identifier allows the sequencer to operate in a specified sequence of switch states. For example, the mode may include a sequence of switch states (such as V1 to V2). First phase sequencer 112 may be configured to repeat the mode (e.g., loop through the mode and return to the beginning after the mode is completed), for example, until a new mode identifier is received.

[0042] In one example, the configuration information may include a duty cycle identifier. The duty cycle identifier may include an indication of the amount of time the first phase sequencer 112 should remain in one or more states.

[0043] Figure 5A and Figure 5B A time-concept diagram showing an example of the operation section of the switch control system 100. Figure 5A and Figure 5B They all exhibit the same pattern (e.g., V1 to V2 and back to V1), but the proportion of time spent in each switching state may differ (e.g., the ratio of R1 to R2, the ratio of (R1+R3) to R2). This proportion can be represented by a duty cycle identifier. For example, a duty cycle identifier of 50% represents a ratio of 1:1, a duty cycle identifier of 75% represents a ratio of 3:1, and so on.

[0044] Configuration information may also include a frequency identifier. The frequency identifier may include an indication of the pattern repetition frequency (e.g., the number of times the pattern repeats per second), the duration of each switching state (e.g., the average duration), or both. In one example, the specific length and / or sequence of the switching states may be determined at the first phase sequencer 112. This helps reduce and / or change the workload of the controller 118, for example, by offloading a portion of the workload to the first phase sequencer 112. In one example, the first phase sequencer 112 may include hardware and / or software configured (e.g., optimized) to perform the desired operations to determine the sequence and / or length of the switching states using one or more of the pattern identifier, duty cycle identifier, or frequency identifier. In one example, the duration of a pattern may remain constant over one or more cycles, but the duration of one or more states within the pattern may be adjusted.

[0045] The controller 118 can be configured to receive feedback information at the first phase switch output signal node 128 indicating the first phase switch output signal 206, which may include, for example, amplitude (such as current or voltage level), frequency, or other parameters. The controller 118 can be configured to adjust configuration information sent to the first phase sequencer 112 based on the received feedback information. For example, the duty cycle identifier may be adjusted in response to the amplitude indicated by the feedback signal.

[0046] As described above, the switch control system 100 can be configured to control the first phase switch group 104 to generate an alternating current (AC) signal in pulse-width modulation (PWM) form. Thus, the switch control system 100 can be used to drive a motor (e.g., in a variable frequency drive (VFD), for an inverter (e.g., to generate an AC output from a DC input, a DC output from a DC input, etc.), or both. In one example, the switch control system 100 can be used to control any switching system (e.g., switch group 102). For example, the switch control system 100 can be used with any inverter topology or other switching topology.

[0047] In one example, sequencer 140 (e.g., via second phase sequencer 114) may be configured to control the respective on and off states of at least two switches in a second switch group (e.g., second phase switch group 106) to generate a second phase switch output signal. Alternatively or supplementarily, sequencer 140 may be configured (e.g., via third phase sequencer 116) to control the respective on and off states of at least two switches in a third switch group (e.g., third phase switch group 108) to generate a third phase switch output signal.

[0048] In one example, the first-phase switch output signal 206, the second-phase switch output signal, and the third-phase switch output signal at the first-phase switch output signal node 128 can have different phases (e.g., these signals can reach their AC peak values ​​at different times, such as when sharing the same frequency). In another example, the first-phase switch output signal 206, the second-phase switch output signal, and the third-phase switch output signal at the first-phase switch output signal node 128 are substantially the same in amplitude and / or frequency, and are separated by a phase difference of approximately 120 degrees in time. Thus, the switch output signal at the switch output signal node 126 can form a three-phase AC signal, which can be used to power three-phase electrical equipment, for example.

[0049] Figure 6 A block diagram showing a portion of a sequencer 140 is provided. Figure 6 The sequencer 140 is shown to include a memory 602, a processor 604, a lookup table 606, a register 608, and a comparator 610. The memory 602 may store one or more pieces of data, such as configuration information received from the controller 118.

[0050] Register 608 may store information used by processor 604, such as timing information. The information in register 608 may be received or generated, at least in part, from information in the configuration information. Comparator 610 may determine when to change a state and / or mode based on a comparison result. For example, comparator 610 may receive feedback information (e.g., from controller 118) and compare the received information with a specified target value (e.g., a specified output) to determine when to change a state. Lookup table 606 may provide processor 604 with information about which transition state to use between power states.

[0051] The processor 604 can perform one or more operations, such as generating a signal on the PWM signal line 138 based on data in the memory 602, timing values ​​in the register 608, or the output of the comparator 610.

[0052] Figure 7 A block diagram showing an example of a portion of sequencer 140. Figure 7The sequencer 140 is shown to include a frequency band classifier 704, a mode selector 706, a state sequencer 708, and a timing generator 710.

[0053] Figure 7 The sequencer 140 is shown to receive configuration information 702, such as from the controller 118. Configuration information 702 may include mode information, reference value information, and other parameters (such as period, frequency, etc.). In one example, configuration information 702 may also include feedback information, such as indicating the value of the switch output signal at switch output signal node 126. Configuration information 702 can be used to generate an output signal on PWM signal line 138.

[0054] The band classifier 704 can receive a reference value (e.g., the desired output voltage, such as a root mean square (RMS) value). Based on this reference value and the signal phase, the band classifier 704 can determine which band the switch group 102 is operating in. The band classifier 704 can then send the band value to the mode selector 706.

[0055] The mode selector 706 can select a specified mode for the frequency band. For example, configuration information 702 may include modes from multiple (e.g., all) frequency bands. The mode selector 706 can then pass the mode to the state sequencer 708.

[0056] Timing generator 710 can control the timing of a selected mode, such as based on received or calibrated timing, or based on responsive timing, such as based on a feedback signal. Timing generator 710 can generate timing information (e.g., a signal for switching states) based on the information it receives. In one example, timing generator 710 may include comparator 610.

[0057] The state sequencer 708 can provide a specified output state to generate a switching output signal. The state sequencer 708 can use the mode received from the mode selector 706 and the timing information received from the timing generator 710 to sequence the output states.

[0058] Figure 8 Examples of a portion of state table 802, pattern table 804, transition state lookup table 806, and waveform editor 808 are shown. In one example, one or more of state table 802, pattern table 804, or transition state lookup table 806 may be stored in the memory of sequencer 140. In another example, one or more of these tables may be stored alternatively or additionally in controller 118. Figure 8In the example, the pattern definition does not need to include transition states. Instead, the sequencer 140 can use the transition state lookup table 806 to insert transition states between power states (e.g., when switching power states, the transition state lookup table 806 is referenced to determine whether a transition state is needed and / or which transition state to use). This makes pattern programming easier, reduces the amount of data that must be transferred between the controller 118 and the sequencer 140, or both.

[0059] In one example, a user can view one or more of the following in a programming interface (such as a graphical user interface): state table 802, pattern table 804, transition state lookup table 806, or waveform editor 808. Waveform editor 808 can be used to generate one or more of the following: state table 802, pattern table 804, or transition state lookup table 806, and vice versa. For example, a user can program waveform editor 808 and then convert the programmed waveform into state table 802 and pattern table 804. In one example, a user can program state table 802 and pattern table 804 and then view the switch states in waveform editor 808.

[0060] In one example, the various parts of the switch control system configuration can be constructed using a graphical user interface. State table 802 and / or mode table 804 can be programmed, for example, using a graphical user interface. The configuration can then be built (e.g., compiled) into the switch control system configuration, for example, it can be stored in sequencer 140. For example, switch control system configuration information 702 can be stored in a series of registers within sequencer 140. Controller 118 can send instructions to sequencer 140 to run a specific mode (e.g., a mode identifier). In response to this instruction, sequencer 140 can be configured to reference the register corresponding to this mode and order the modes according to the states contained in the mode. Furthermore, controller 118 can send configuration parameters (e.g., duty cycle identifier, frequency identifier) ​​that can be used to change how sequencer 140 orders the modes.

[0061] The sequencer 140 can use an internal processor to look up one or more of the state table 802, mode table 804, and transition state lookup table 806, and can control the switch group 102 based on the looked-up tables. For example, a series of operations can be performed in the software domain before signals are generated in the hardware domain. Signals on PWM signal line 138 can be generated using PWM output components, which can be controlled, for example, by the processor within the sequencer 140. These PWM output components can be configured to drive PWM signals, for example, including specified frequencies and duty cycles.

[0062] Figure 9An example of a portion of a method 900 for operating a switch control system (such as switch control system 100) is shown. Method 900 may include a method for generating a switch output signal comprising more than two discrete voltage levels. In step 902, a sequencer may be used to control one or more switches in a switch group. This may include using sequencer 140 to control one or more switches 110.

[0063] In step 904, the corresponding on and off states of one or more switches can be controlled to generate switch output signals. For example, a switch output signal can be generated at switch output signal node 126.

[0064] In step 906, one or more switches can be controlled to operate through a specified sequence of switch states. One or more of these switch states may include the corresponding state of each of at least two switches. This may include sequencing the switch states according to a specified pattern.

[0065] In step 908, the switch group can be controlled to enter a switching state that includes one or more power states, for example, these states can be configured to generate a part of the switch output feedback signal.

[0066] In step 910, the switch group can be controlled to enter a switching state including one or more transition states. For example, it can be configured to prevent one or more of the following conditions: reverse current or damage to the switch group, such as when switching between power states.

[0067] In one example, a pattern can be defined using a sequence of switch states. The switch group can be controlled to be ordered according to the defined pattern's sequence of switch states. The pattern can include the order of the corresponding switch states within a given pattern. In one example, controlling the switch group to be ordered by switch states according to a defined pattern can include at least partially using duty cycle identifiers to determine the length of time spent in each switch state (e.g., as discussed above).

[0068] In one example, a graphical user interface can be used to construct and / or specify switch states and / or modes. For example, a computer program can be used to configure state table 802 and mode table 804. This can reduce the skill level required to program the switch control system 100, reduce the likelihood of introducing errors when programming the switch control system 100, or both.

[0069] In one example, an operating mode can be constructed, such as a sequence of modes used in a graphical user interface. The operating mode can include a specified sequence of modes and an indication of when to switch between modes. A compiler can be used to configure a sequencer to control the switch group to execute the sequence of modes in the operating mode. In one example, the sequence of modes in the operating mode can be configured to generate a switch output signal representing a pulse-width modulation (PWM) form of an alternating current (AC) signal.

[0070] In one example, the build pattern could include selecting a specific order of power states, such as not requiring the selection of transition states. In this example, using a compiler could include selecting to insert transition states between the various power states, for example, using a lookup table (e.g., transition state lookup table 806). By offloading the work of selecting transition states to the compiler, sequencer 140, or both, this helps to simplify the configuration process.

[0071] The order of steps shown is not intended to restrict the order in which steps can be performed. In one example, two or more steps may be performed simultaneously, or at least partially in parallel.

[0072] Figure 10A block diagram of an example machine 1000 is shown, on which any one or more of the techniques (e.g., methods) discussed herein can be implemented. As described herein, the example may include, or be operable by, logic or components or mechanisms in, machine 1000. A circuit (e.g., a processing circuit) is a collection of circuits implemented in the tangible entity of machine 1000, including hardware (e.g., simple circuits, gate circuits, logic circuits, etc.). Circuit members may change over time. A circuit includes members that can perform a specified operation individually or in combination during runtime. In one example, the hardware of the circuit may be invariably designed to perform a specific operation (e.g., hardwired). In one example, the hardware of the circuit may include physically connected components (e.g., execution units, transistors, simple circuits, etc.) including physically modified machine-readable media (e.g., magnetic, electrical, movable placement of invariant aggregated particles, etc.) to encode instructions for a specific operation. When physical components are connected, the underlying electrical characteristics of the hardware components change, e.g., from an insulator to a conductor, and vice versa. Instructions enable embedded hardware (e.g., execution units or loading mechanisms) to create members of a circuit within the hardware via variable connections to perform a portion of a specific operation during operation. Thus, in one example, a machine-readable medium element is part of the circuit, or another component communicatively coupled to the circuit during device operation. In one example, any physical component can be used in multiple members of multiple circuits. For example, under operation, an execution unit may be used in a first circuit of a first circuit at one point in time and reused at different times by a second circuit in the first circuit or a third circuit in the second circuit. The following are other examples of these components concerning machine 1000.

[0073] In alternative examples, machine 1000 can operate as a standalone device or be connected (e.g., networked) to other machines. In a networked deployment, machine 1000 can operate as a server machine, a client machine, or both in a server-client network environment. In one example, machine 1000 can act as a peer-to-peer (P2P) (or other distributed) network environment. Machine 1000 can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), mobile phone, network device, network router, switch, or bridge, or any machine capable of executing instructions (sequentially or otherwise) specifying the actions to be taken by that machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered as including any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more methods discussed herein, such as cloud computing, Software as a Service (SaaS), and other computer cluster configurations.

[0074] Machine 1000 may include a hardware processor 1002 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), main memory 1004, static memory (e.g., memory or storage for firmware, microcode, basic input / output (BIOS), and mass storage 1008 (e.g., a hard disk drive, tape drive, flash memory, or other block device), some or all of which may communicate with each other via interconnect 1030 (e.g., a bus). Machine 1000 may also include a display unit 1010, an alphanumeric input device 1012 (e.g., a keyboard), and a user interface (UI) navigation device 1014 (e.g., a mouse). In one example, display unit 1010, input device 1012, and UI navigation device 1014 may be a touchscreen display. Machine 1000 may also include signal generating device 1018 (e.g., a speaker), network interface device 1020, and one or more sensors 1016, such as a Global Positioning System (GPS) sensor, compass, accelerometer, or other sensors. Machine 1000 may include output controller 1028, for example, a serial (e.g., Universal Serial Bus (USB), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection, to communicate with or control one or more peripheral devices (e.g., printer, card reader, etc.).

[0075] Registers of processor 1002, main memory 1004, static memory 1006, or mass storage 1008 may be or include machine-readable medium 1022, on which one or more sets of data structures or instructions 1024 (e.g., software) embodying or used by any one or more technologies or functions described herein may be stored. During execution of instructions 1024 by machine 1000, instructions 1024 may also reside wholly or at least partially within any register of processor 1002, main memory 1004, static memory 1006, or mass storage 1008. In one example, one or any combination of hardware processor 1002, main memory 1004, static memory 1006, or mass storage 1008 may constitute machine-readable medium 1022. While machine-readable medium 1022 is shown as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., centralized or distributed databases and / or associated caches and servers) configured to store one or more instructions 1024.

[0076] The term "machine-readable medium" can include any medium capable of storing, encoding, or carrying instructions executable by machine 1000 and enabling machine 1000 to perform any one or more of the technologies disclosed herein, or any medium capable of storing, encrypting, or carrying data structures used by or associated with those instructions. Examples of non-limiting machine-readable media can include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In one example, a non-transient machine-readable medium includes a machine-readable medium having multiple particles with invariant (e.g., stationary) masses, and thus being a component of matter. Therefore, a non-transient machine-readable medium is a machine-readable medium that does not include transiently propagating signals. Specific examples of non-transient machine-readable media may include: non-volatile memories such as semiconductor storage devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; disks such as internal hard disks and removable disks; magneto-optical disks; and CD-ROMs and DVD-ROMs.

[0077] In one example, information stored on or otherwise provided on machine-readable medium 1022 may represent instructions 1024, such as instructions 1024 themselves or a format from which instructions 1024 can be derived. Such a format from which instructions 1024 can be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., divided into multiple packages), etc. Information representing instructions 1024 in machine-readable medium 1022 can be processed by processing circuitry into instructions to perform any of the operations discussed herein. For example, deriving instructions 1024 from information (e.g., processed by processing circuitry) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamic or static linking), encoding, decoding, encrypting, decrypting, packaging, unpacking, or otherwise manipulating the information into instructions 1024.

[0078] In one example, the derivation of instruction 1024 may include assembling, compiling, or interpreting information (e.g., by processing circuitry) to create instruction 1024 from some intermediate or preprocessed format provided by machine-readable medium 1022. When provided in multiple parts, information can be combined, unpacked, and modified to create instruction 1024. For example, the information may reside in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or more remote servers. The source code packages may be encrypted when transmitted over a network, and may be decrypted, decompressed, assembled (e.g., linked), and compiled or interpreted on the local machine (e.g., compiled into libraries, standalone executables, etc.) if necessary, and then executed by the local machine.

[0079] Instruction 1024 can also use a transmission medium to transmit or receive data over a communication network 1026 via a network interface device 1020 using any of a variety of transmission protocols (e.g., Frame Relay, Internet Protocol (IP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), Hypertext Transfer Protocol (HTTP), etc.). Example communication networks may include local area networks (LANs), wide area networks (WANs), packet data networks (e.g., the Internet), LoRa / LoRaWAN or satellite communication networks, mobile phone networks (e.g., cellular networks, such as networks compliant with 3G, 4G LTE / LTE-A, or 5G standards), conventional telephone (POTS) networks, and wireless data networks (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 family of standards, known as Wi-Fi®, IEEE...). The 802.15.4 standard family, peer-to-peer (P2P) networks, etc. In one example, network interface device 1020 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to communication network 1026. In one example, network interface device 1020 may include multiple antennas to perform wireless communication using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technologies. The term "transmission medium" should be considered to include any intangible medium capable of storing, encoding, or carrying instructions executable by machine 1000, including digital or analog communication signals or other intangible media to facilitate communication of such software. The transmission medium is a machine-readable medium.

[0080] The following non-limiting examples illustrate certain aspects of this topic to address the challenges discussed herein and provide benefits, etc.

[0081] Example:

[0082] Example 1 is a switch control system for controlling a switch group comprising at least two switches to generate a switch output signal comprising more than two discrete voltage levels. The switch control system includes: a sequencer configured to control respective on and off states of the at least two switches to generate the switch output signal, comprising: controlling the at least two switches by a specified sequence of switch states, wherein each switch state includes a corresponding state of each of the at least two switches; and wherein the switch states include: at least two power states configured to generate a portion of the switch output signal; and at least one transition state configured to prevent at least one of shoot-through, reverse current condition, or switch group damage when switching power states.

[0083] In Example 2, the essence of Example 1 optionally includes the sorter being configured to control at least two switches by a specified sequence of switch states such that the switch group is in a power state for at least five times the time the switch group is in a transition state.

[0084] In Example 3, the subject matter of any one or more of Examples 1-2 may optionally include: the switch group comprises at least six switches; and the switch output signals comprise at least five discrete voltage levels.

[0085] In Example 4, the subject of any one or more of Examples 1-3 optionally includes a controller configured to: send configuration information to the sequencer; and wherein the sequencer is configured to use PWM signals to control the corresponding on and off states of at least two switches when power is off, based on the received configuration information.

[0086] In Example 5, the subject of Example 4 optionally includes the configuration information wherein the configuration information includes a pattern identifier that causes the sequencer to proceed through a specified sequence of switch states.

[0087] In Example 6, the subject of Example 5 optionally includes the configuration information including a duty cycle identifier, wherein the duty cycle identifier represents the amount of time the sequencer spends in one or more states.

[0088] In Example 7, the essence of Example 6 optionally includes the controller being configured to: receive feedback information indicating the output signal of the switch; and adjust the configuration information sent to the sequencer based on the received feedback information.

[0089] In Example 8, the subject of any one or more of Examples 1-7 may optionally include the fact that the sequencer is configured to control the switch group to generate a pulse width modulation (PWM) form of an alternating current (AC) signal.

[0090] In Example 9, the essence of Example 8 optionally includes: the sequencer is configured to control the respective on and off states of at least two switches in the second switch group to generate a second switch output signal; and the sequencer is configured to control the respective on and off states of at least two switches in the third switch group to generate a third switch output signal.

[0091] In Example 10, the essence of Example 9 is optionally included in which the switch output signal, the second switch output signal, and the third switch output signal have different phases.

[0092] In Example 11, the essence of Example 10 is optionally included in which the switch output signal, the second switch output signal, and the third switch output signal are substantially the same in amplitude and are separated by a phase difference of approximately 120 degrees in time.

[0093] In Example 12, the subject of any one or more of Examples 1-11 may optionally include a switch group.

[0094] Example 13 is a method for generating a switch output signal comprising more than two discrete voltage levels, the method comprising: controlling at least two switches in a switch group using a sequencer, comprising: controlling respective on and off states of the at least two switches to generate the switch output signal; controlling the at least two switches to proceed through a specified sequence of switch states, wherein each switch state comprises a respective state of each of the at least two switches; and controlling the switch group to enter a switch state comprising: at least two power states configured to generate a portion of the switch output signal; and at least one transition state configured to prevent at least one of shoot-through, reverse current, or switch group damage when switching power states.

[0095] In Example 14, the main idea of ​​Example 13 optionally includes using a sequence of switch states to define a pattern; and controlling the switch group to sequence the switch states according to the defined pattern.

[0096] In Example 15, the subject of Example 14 optionally includes the sequence of the corresponding switch states in the respective modes.

[0097] In Example 16, the essence of Example 15 optionally includes controlling the switch group to sequence the switch states in a defined pattern by: using at least a duty cycle identifier to determine the length of time spent in the respective switch state.

[0098] The main idea of ​​any one or more of Examples 17, 14-16 optionally includes using a graphical user interface to construct the switch states and modes; in the graphical user interface, constructing an operating mode using a pattern sequence; and using a compiler to configure the sequencer to control the switch group to execute the pattern sequence in the operating mode.

[0099] In Example 18, the main points of Example 17 are optionally included therein: the build pattern includes selecting a specified order of power states; and the use of the compiler includes using a lookup table to select the transition states to be inserted between the corresponding power states.

[0100] In Examples 19, 17-18, one or more of the main ideas optionally include the mode sequence in the said operating mode being configured to generate a switch output signal representing a pulse width modulation (PWM) form of an alternating current (AC) signal.

[0101] Example 20 is a switch control system for controlling a switch group comprising at least six switches to generate a switch output signal comprising at least five discrete voltage levels. The switch control system includes: a sequencer configured to control corresponding on and off states of the at least six switches to generate the switch output signal, comprising: controlling the at least six switches by a specified sequence of switch states, wherein each switch state includes a corresponding state of each of the at least six switches; and a controller configured to: send configuration information to the sequencer; wherein: the sequencer is configured to control the corresponding on and off states of the at least six switches using PWM signals based on the received configuration information, wherein the switch states include: at least two power states configured to generate a portion of the switch output signal; and at least one transition state configured to prevent at least one of shoot-through, reverse current conditions, or switch group damage when switching power states.

[0102] Example 21 is at least one machine-readable medium including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any one of Examples 1-20.

[0103] Example 22 is an apparatus including means for implementing any one of Examples 1 to 20.

[0104] Example 23 is a system that implements any one of Examples 1 through 20.

[0105] Example 24 is a method of implementing any one of Examples 1 through 20.

[0106] Each of the above non-limiting aspects may exist independently or may be arranged or combined in various ways with one or more other aspects or other subjects described in this invention.

[0107] The above detailed description includes reference to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific examples that can be practiced by way of illustration. These embodiments are also referred to herein as "examples". These examples may include elements other than those shown or described. However, the inventors have also contemplated examples that provide only the elements shown or described. Furthermore, the inventors have contemplated examples of any combination or substitution of those elements (or one or more aspects thereof) shown or described, whether with respect to a particular example (or one or more aspects thereof) or to other examples (or one or more aspects thereof) shown or described herein.

[0108] All publications, patents, and patent documents cited in this document are incorporated herein by reference in their entirety, as if individually incorporated. In the event of any inconsistency between the usage in this document and that in the documents included by reference, the usage in the included references shall be considered supplementary to the usage in this document; in the case of irreconcilable inconsistencies, the usage in this invention shall be controlled.

[0109] In this document, the terms “a” or “an” are used as commonly found in patent documents to include one or more, independent of any other instances or uses of “at least one” or “one or more.” In this document, the terms “or” and “and / or” are used to refer to non-exclusivity, or “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise stated. In the appended claims, the terms “comprising” and “wherein” are used as concise English equivalents to the corresponding terms “including” and “in which.” Furthermore, the terms “comprising” and “including” in the following claims are open-ended, meaning that a system, apparatus, article, or process that includes elements other than those listed after the term in the claim is still considered to be within the scope of that claim. Additionally, in the following claims, the terms “first,” “second,” and “third,” etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0110] The term “approximately” as used herein means approximately, within a certain range, roughly, or around. When the word “approximately” is used in conjunction with a numerical range, it modifies the range by extending the boundaries above and below the listed numerical value. Generally, the term “approximately” is used herein to modify numerical values ​​above and below the stated value by 10% of the variance. In one aspect, the term “approximately” refers to a numerical value plus or minus 10% of the number used. Thus, approximately 50% means within the range of 45%–55%. Numerical ranges referenced by endpoints in this document include all numbers and fractions contained within that range (e.g., 1 to 5 includes 1, 1.5, 2, 2.75, 3, 3.90, 4, 4.24, and 5). Similarly, the numerical ranges referenced by endpoints in this document include subranges contained within that range (e.g., 1 to 5 includes 1-1.5, 1.5-2, 2-2.75, 2.75-3, 3-3.90, 3.90-4, 4-4.24, 4.24-5, 2-5, 3-5, 1-4, and 2-4).

[0111] The methods described herein can be implemented, at least in part, by a machine or computer. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions operable to configure an electronic device to perform the methods described in the examples above. Implementations of these methods may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Such instructions may be read and executed by one or more processors to perform operations including, for example, methods. Instructions may be in any suitable form, such as, but not limited to, source code, compiled code, interpreted code, executable code, static code, dynamic code, etc.

[0112] Furthermore, in one example, the code may be tangibly stored on one or more volatile, non-transient, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., optical discs and digital video discs), magnetic tape cassettes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0113] The foregoing description is intended to be illustrative and not limiting. For example, the foregoing examples (or one or more aspects thereof) may be used in combination with each other. Other examples may be used, for instance, by those skilled in the art upon reading the foregoing description. The abstract is intended to allow the reader to quickly determine the nature of the technical disclosure and to understand, at the time of submission, that it is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the foregoing detailed description, various features may be combined to simplify this disclosure. This should not be construed as meaning that any unclaimed disclosed feature is essential to any claim. Rather, the subject matter of the invention may lie in certain features of a particular disclosed embodiment. Therefore, the following claims are hereby incorporated into the detailed specification, each claim existing independently as a separate embodiment. The scope of the examples should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A switch control system for controlling a switch group comprising at least two switches to generate a switch output signal comprising more than two discrete voltage levels, the switch control system comprising: A sequencer, configured to control the respective on and off states of the at least two switches to generate the switch output signals, includes: The at least two switches are controlled by a specified sequence of switch states, wherein each switch state includes a corresponding state of each of the at least two switches; and The switch states include: At least two power states are configured to generate a portion of the switching output signal; and At least one switching state is configured to prevent at least one of the following conditions when switching power states: shoot-through, reverse current condition, or switch group damage.

2. The switch control system of claim 1, wherein the sequencer is configured to control at least two switches by a specified sequence of switch states, such that the time the switch group is in the power state is at least five times longer than the time the switch group is in the transition state.

3. The switch control system according to claim 1, wherein: The switch group comprises at least six switches; and The switch output signal includes at least five discrete voltage levels.

4. The switch control system according to claim 1, comprising: The controller is configured as follows: Send configuration information to the sequencer; The sequencer is configured to use PWM signals to control the corresponding on and off states of at least two switches when power is off, based on received configuration information.

5. The switch control system according to claim 4, wherein the configuration information includes a mode identifier, the mode identifier causing the sequencer to operate through a specified sequence of switch states.

6. The switching control system according to claim 5, wherein the configuration information includes a duty cycle identifier, wherein the duty cycle identifier represents the amount of time spent by the sequencer in one or more states.

7. The switch control system according to claim 6, wherein the controller is configured to: Receive feedback information indicating the output signal of the switch; and Based on the received feedback information, the configuration information sent to the sequencer is adjusted.

8. The switch control system of claim 1, wherein the sequencer is configured to control the switch group to generate an AC signal in the form of pulse width modulation (PWM).

9. The switch control system according to claim 8, wherein: The sequencer is configured to control the corresponding on and off states of at least two switches in the second switch group to generate a second switch output signal; and The sequencer is configured to control the corresponding on and off states of at least two switches in the third switch group to generate a third switch output signal.

10. The switch control system according to claim 9, wherein: The switch output signal, the second switch output signal, and the third switch output signal have different phases.

11. The switch control system according to claim 10, wherein: The switch output signal, the second switch output signal, and the third switch output signal are basically the same in amplitude and are separated by a phase difference of approximately 120 degrees in time.

12. The switch control system according to claim 1, further comprising the switch group.

13. A method for generating a switching output signal comprising more than two discrete voltage levels, the method comprising: Use a sequencer to control at least two switches in a switch group, including: Controlling the corresponding open and closed states of the at least two switches to generate the switch output signal; Control the at least two switches via a specified sequence of switch states, wherein each switch state includes a corresponding state of each of the at least two switches; and Control the switch group to enter a switching state including the following states: At least two power states are configured to generate a portion of the switch output signal; and At least one switching state is configured to prevent at least one of the following conditions when switching power states: shoot-through, reverse current, or switch group damage.

14. The method of claim 13, comprising: Use a sequence of switch states to define the pattern; and The switch group is controlled to sequence the switch states according to a defined pattern.

15. The method of claim 14, wherein the mode includes the sequence of corresponding switch states in the corresponding mode.

16. The method of claim 15, wherein controlling the switch group to sequence the switch states according to a defined pattern comprises: At least in part, the duty cycle identifier is used to determine the length of time spent in the corresponding switching state.

17. The method of claim 14, comprising: The switch states and modes are constructed using a graphical user interface; In the graphical user interface, operation modes are constructed using pattern sequences; and The sequencer is configured using a compiler to control the switch group to execute the mode sequence in the operating mode.

18. The method of claim 17, wherein: The build pattern includes selecting a specified order of power states; and The compiler uses a lookup table to select the transition state to insert between the corresponding power states.

19. The method of claim 17, wherein: The mode sequence in the operating mode is configured to generate a switch output signal that represents a pulse width modulation (PWM) form of an alternating current (AC) signal.

20. A switch control system for controlling a switch group comprising at least six switches to generate switch output signals comprising at least five discrete voltage levels, the switch control system comprising: A sequencer, configured to control the corresponding on and off states of at least six switches to generate switch output signals, including: The at least six switches are controlled by a specified sequence of switch states, wherein each switch state includes the corresponding state of each of the at least six switches; and The controller is configured as follows: Send configuration information to the sequencer; wherein: The sequencer is configured to use PWM signals to control the corresponding on and off states of the at least six switches based on received configuration information. The switch states include: At least two power states are configured to generate a portion of the switch output signal; and At least one switching state is configured to prevent at least one of the following conditions when switching power states: shoot-through, reverse current condition, or switch group damage.

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