Method, device and equipment for driving parallel interleaved converters and storage medium

Abstract

This invention provides a driving method, apparatus, device, and storage medium for a parallel interleaved converter, relating to the field of converter technology and applied to converter circuits. The method includes: providing a driving signal to the control terminals of switching elements in the converter circuit; wherein the driving signal is used to simultaneously turn on the switching elements of the upper arm of a first bridge circuit and simultaneously turn on the switching elements of the upper arm of a second bridge circuit; or, the driving signal is used to simultaneously turn off the switching elements of the upper arm of the first bridge circuit and simultaneously turn off the switching elements of the upper arm of the second bridge circuit. The method provided by this invention can stagger the peak values ​​of the ripple current flowing into the DC bus electrolytic capacitors of the two bridge circuits, reducing the peak and effective values ​​of the capacitor ripple current, thereby reducing the required capacitor capacity and mitigating capacitor aging.

Description

Technical Field

[0001] This invention relates to the field of converter control technology, and in particular to a driving method, apparatus, equipment and storage medium for a parallel interleaved converter. Background Technology

[0002] With the development of power electronics technology, two-way interleaved parallel converters have gradually become the mainstream for high-power equipment due to their advantages such as effectively reducing input current ripple and increasing module power density. However, existing interleaved parallel converters still have many problems in practical applications.

[0003] The interleaved parallel control in related technologies often uses center-symmetric PWM (Pulse Width Modulation) for driving. This modulation method causes the current flowing into the DC side capacitor to be completely superimposed, resulting in the capacitor current ripple doubling, shortening the capacitor's lifespan, and requiring the circuit to use large-capacity, high-temperature resistant capacitors, which increases the circuit size and cost. Summary of the Invention

[0004] This invention provides a driving method, apparatus, device, and storage medium for a parallel-interleaved converter to solve the problem of current superposition in the DC-side capacitor, which doubles the capacitor current ripple and shortens the capacitor's lifespan.

[0005] In a first aspect, embodiments of the present invention provide a driving method for a parallel interleaved converter, applied to a converter circuit. The converter circuit includes a first bridge circuit, a second bridge circuit, and a DC bus capacitor connected in parallel. Both the first bridge circuit and the second bridge circuit include an upper bridge arm and a lower bridge arm, and both the upper bridge arm and the lower bridge arm include at least two and the same number of switching elements. The method includes: providing a driving signal to the control terminals of the switching elements in the converter circuit; wherein the driving signal is used to simultaneously turn on the switching elements of the upper bridge arm of the first bridge circuit and simultaneously turn on the switching elements of the upper bridge arm of the second bridge circuit; or, the driving signal is used to simultaneously turn off the switching elements of the upper bridge arm of the first bridge circuit and simultaneously turn off the switching elements of the upper bridge arm of the second bridge circuit.

[0006] In one possible implementation, the phase difference between the drive signals provided to the first bridge circuit and the second bridge circuit is 180 degrees.

[0007] In one possible implementation, the converter circuit further includes a power factor correction inductor and a coupling inductor; the upper and lower arms of the first bridge circuit are connected to the first winding of the coupling inductor via a power factor correction inductor, and the second winding of the coupling inductor is connected to the upper and lower arms of the second bridge circuit via another power factor correction inductor.

[0008] In one possible implementation, before providing a drive signal to the control terminal of the switching element in the converter circuit, the method further includes: providing a start signal to the control terminal of the switching element in the converter circuit, wherein the initial switching frequency of the start signal is greater than the switching frequency of the drive signal, and the initial dead time of the start signal is less than the dead time of the drive signal; within a preset time, reducing the switching frequency of the start signal to the switching frequency of the drive signal, and increasing the initial dead time of the start signal to the dead time of the drive signal.

[0009] In one possible implementation, the preset time includes a first preset time and a second preset time; the step of reducing the switching frequency of the start signal to the switching frequency of the drive signal and increasing the initial dead time of the start signal to the dead time of the drive signal within the preset time includes: maintaining the initial dead time of the start signal unchanged within the first preset time while reducing the switching frequency of the start signal to the switching frequency of the drive signal; and maintaining the current switching frequency of the start signal unchanged within the second preset time while increasing the initial dead time of the start signal to the dead time of the drive signal.

[0010] In one possible implementation, the initial switching frequency of the start signal is 1.1 to 1.3 times the switching frequency of the drive signal, and the initial dead time of the start signal is 0.2 to 0.4 times the switching period of the drive signal.

[0011] Secondly, embodiments of the present invention provide a driving device for a parallel interleaved converter, applied to a converter circuit. The converter circuit includes a first bridge circuit, a second bridge circuit, and a DC bus capacitor connected in parallel. Both the first bridge circuit and the second bridge circuit include an upper bridge arm and a lower bridge arm, and both the upper bridge arm and the lower bridge arm include at least two and the same number of switching elements. The device includes a driving module, which is used to: provide driving signals to the control terminals of the switching elements in the converter circuit; wherein the driving signals are used to simultaneously turn on the switching elements of the upper bridge arm of the first bridge circuit and simultaneously turn on the switching elements of the upper bridge arm of the second bridge circuit; or, the driving signals are used to simultaneously turn off the switching elements of the upper bridge arm of the first bridge circuit and simultaneously turn off the switching elements of the upper bridge arm of the second bridge circuit.

[0012] Thirdly, embodiments of the present invention provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the method described in the first aspect or any possible implementation thereof.

[0013] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect or any possible implementation thereof.

[0014] Fifthly, embodiments of the present invention provide a computer program product, including a computer program that, when executed by a processor, implements the method described in the first aspect or any possible implementation thereof.

[0015] The single-sided aligned PWM modulation method proposed in this invention can stagger the peak values ​​of the ripple current flowing into the DC bus electrolytic capacitors of the two bridge circuits, eliminating the problem of synchronous superposition of the currents of the two capacitors under traditional center-symmetric modulation. This significantly reduces the peak and effective values ​​of the capacitor ripple current, thereby reducing the required electrolytic capacitor capacity, lowering the overall hardware cost and equipment size, reducing capacitor heating and internal alternating stress, delaying electrolyte aging, and effectively extending the service life of the electrolytic capacitors and the entire power supply. This solves the technical pain point of excessive bus capacitor load in high-power energy storage, charging piles, and industrial converter scenarios, and improves the long-term operational reliability of the system. Attached Figure Description

[0016] Figure 1 This is a circuit schematic diagram of the converter circuit provided in an embodiment of the present invention; Figure 2 This is a waveform diagram of the relevant signal generated by the PWM modulation method in related technologies; Figure 3 This is a waveform diagram of the relevant signals generated by the driving method of the parallel interleaved converter provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the drive device for the parallel interleaved converter provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Detailed Implementation

[0017] The embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0018] Figure 1 The schematic diagram of the converter circuit used in the driving method of the parallel interleaved converter provided in the embodiments of the present invention is as follows: Figure 1 As shown, the converter circuit includes a first bridge circuit 10, a second bridge circuit 20, a DC bus capacitor Cdc, and a current-limiting resistor R connected in parallel. Both the first bridge circuit 10 and the second bridge circuit 20 include an upper bridge arm and a lower bridge arm, and each upper bridge arm and lower bridge arm includes at least two identical switching elements. Specifically, as shown... Figure 1 As shown, the first bridge circuit 10 includes a first switching element M1, a second switching element M2, a third switching element M3, a fourth switching element M4, a fifth switching element M5, and a sixth switching element M6, and the second bridge circuit 20 includes a seventh switching element M7, an eighth switching element M8, a ninth switching element M9, a tenth switching element M10, an eleventh switching element M11, and a twelfth switching element M12. Figure 1 The converter circuit shown is a three-phase converter. Ua, Ub, and Uc are the three-phase AC input terminals of a, b, and c, respectively. Therefore, in the first bridge circuit 10, the first switching element M1, the third switching element M3, and the fifth switching element M5 constitute the upper arms of the three phases, and the second switching element M2, the fourth switching element M4, and the sixth switching element M6 constitute the lower arms of the three phases. Similarly, in the second bridge circuit 20, the seventh switching element M7, the ninth switching element M9, and the eleventh switching element M11 constitute the upper arms of the three phases, and the eighth switching element M8, the tenth switching element M10, and the twelfth switching element M12 constitute the lower arms of the three phases. Figure 1 Other components will be described one by one in the following embodiments.

[0019] The above-mentioned interleaved parallel converter composed of two bridge circuits converts AC power into DC power or DC power into AC power by inputting PWM signals to multiple switching elements. The interleaved operation of the two modules cancels the inductor current ripple, thereby improving the overall power handling capacity and power density. It is often used in high-power energy storage, charging piles, and industrial power equipment.

[0020] Figure 2A PWM modulation method in a related art is shown to provide... Figure 1 The circuit shown displays the carrier and gate drive signal waveforms, where the horizontal axis represents time and the vertical axis represents voltage value. Figure 2 (a) is the carrier signal waveform, where f1 (green waveform) is the triangular carrier provided to the first bridge circuit 10, f2 (red waveform) is the triangular carrier provided to the second bridge circuit 20, and CAMPA is the carrier comparison reference level of the exemplary first switching element M1 and the eleventh switching element M11 (the carrier comparison reference levels of other switching elements are omitted). Figure 2 (b) is the drive signal waveform of the gate of the first switching element M1, the third switching element M3 and the fifth switching element M5 of the upper bridge arm of the first bridge circuit 10, wherein Ga1 (green waveform) is the drive signal waveform of the gate of the first switching element M1, Gb1 (red waveform) is the drive signal waveform of the gate of the third switching element M3, and Gc1 (blue waveform) is the drive signal waveform of the gate of the fifth switching element M5. Figure 2 (c) shows the drive signal waveforms of the gates of the seventh switching element M7, the ninth switching element M9, and the eleventh switching element M11 in the upper arm of the second bridge circuit 20. Among them, Ga1_2 (green waveform) is the drive signal waveform of the gate of the seventh switching element M7, Gb1_2 (red waveform) is the drive signal waveform of the gate of the ninth switching element M9, and Gc1_2 (blue waveform) is the drive signal waveform of the gate of the eleventh switching element M11.

[0021] Those skilled in the art will understand that, for the control signals of other switching elements in the circuit, the drive signal provided to the lower bridge arm is the inverted signal of the drive signal provided to the upper bridge arm, and the drive signals provided to the other two phases are similar to the drive signal of this phase; these will not be described again in this embodiment. The waveform signals in other figures of this embodiment can be referred to... Figure 2 The description of the above will not be repeated in this embodiment.

[0022] like Figure 2As shown, f1 and f2 are staggered by 180° and centrally symmetrical, making the high-frequency ripple generated by a single inductor out of phase. After superposition, the total input current ripple is greatly reduced, which can reduce the size of the input filter device and increase the power density. The above carrier design makes the duty cycle (high level) of the three driving signals Ga1 / Gb1 / Gc1 symmetrical about the peak / zero point of f1, and the duty cycle (high level) of the three driving signals Ga1_2 / Gb1_2 / Gc1_2 symmetrical about the peak / zero point of f2. Therefore, the moment when Ga1 / Gb1 / Gc1 is high at the same time is aligned with the moment when the three driving signals Ga1_2 / Gb1_2 / Gc1_2 are low at the same time. Conversely, the moment when Ga1 / Gb1 / Gc1 is low at the same time is also aligned with the moment when the three driving signals Ga1_2 / Gb1_2 / Gc1_2 are high at the same time.

[0023] Taking Ga1 / Gb1 / Gc1 as an example, when Ga1 / Gb1 / Gc1 are all high, all upper arms of the first bridge circuit 10 are turned on and all lower arms are turned off. In this three-phase three-wire system, there is no neutral line. At this time, all three-phase AC input terminals are directly connected to the positive terminal Vdc+ of the DC bus, and the potentials on the three-phase AC sides are completely equal. The three-phase AC currents Ia1, Ib1, and Ic1 of the first bridge circuit 10 cancel each other out. The total current Icdc1 provided by the first bridge circuit 10 to the DC bus capacitor Cdc is Ia1 + Ib1 + Ic1 = 0. Similarly, when Ga1 / Gb1 / Gc1 are all low, all three-phase AC input terminals are directly connected to the negative terminal Vdc- of the DC bus, and Ia1, Ib1, and Ic1 still cancel each other out, so Icdc1 = 0. The principle corresponding to the three driving signals Ga1_2 / Gb1_2 / Gc1_2 is the same and will not be elaborated further.

[0024] Figure 2 (d) also shows the waveform of the current signal supplied to the DC bus capacitor Cdc, with the horizontal axis representing time and the vertical axis representing the current value. Specifically, Figure 2 (d) The current signal waveforms provided to the DC bus capacitor Cdc by the first bridge circuit 10 and the second bridge circuit 20, wherein Icdc1 (green) is the current signal provided to the DC bus capacitor Cdc by the first bridge circuit 10, and Icdc2 (red) is the current signal provided to the DC bus capacitor Cdc by the second bridge circuit 20. Figure 2As shown in (d), it is precisely because the moment when Ga1 / Gb1 / Gc1 is at a high level simultaneously is aligned with the moment when the three driving signals Ga1_2 / Gb1_2 / Gc1_2 are at a low level simultaneously, that the moment when the current signal provided by the two bridge circuits to the DC bus capacitor Cdc is zero also overlaps. This leads to the overlap of the moment when the current signal is not zero (or even the peak moment), doubling the peak and effective values ​​of the capacitor ripple current, resulting in severe capacitor heating, accelerating electrolyte aging, and shortening the capacitor's lifespan. The circuit must use large-capacity, high-temperature resistant electrolytic capacitors, increasing the circuit size and cost.

[0025] In view of this, embodiments of the present invention provide a driving method for a parallel interleaved converter, applied to the aforementioned converter circuit, the method comprising: A drive signal is provided to the control terminal (i.e., gate) of the switching element in the converter circuit. This drive signal is used to simultaneously turn on the switching elements of the upper arm of the first bridge circuit 10 and the upper arm of the second bridge circuit 20; or, the drive signal is used to simultaneously turn off the switching elements of the upper arm of the first bridge circuit 10 and the upper arm of the second bridge circuit 20.

[0026] To address the aforementioned problems, embodiments of the present invention provide a PWM scheme with single-sided alignment of the drive signal. Figure 3 The method provided by the embodiments of the present invention is shown to be provided to Figure 1 The circuit shown includes a carrier waveform, a gate drive signal waveform, and a current signal waveform supplied to the DC bus capacitor Cdc. The horizontal axis represents time. Figure 3 (a) to Figure 3 (c) The vertical axis represents the voltage value. Figure 3 (d) The vertical axis represents the current value. Specifically... Figure 3 (a) is the carrier signal waveform, where f1 (green waveform) is the triangular carrier provided to the first bridge circuit 10, f2 (red waveform) is the triangular carrier provided to the second bridge circuit 20, and CAMPA is the carrier comparison reference level of the exemplary first switching element M1 and the eleventh switching element M11 (the carrier comparison reference levels of other switching elements are omitted). Figure 3 (b) is the drive signal waveform of the gate of the first switching element M1, the third switching element M3 and the fifth switching element M5 of the upper bridge arm of the first bridge circuit 10, wherein Ga1 (green waveform) is the drive signal waveform of the gate of the first switching element M1, Gb1 (red waveform) is the drive signal waveform of the gate of the third switching element M3, and Gc1 (blue waveform) is the drive signal waveform of the gate of the fifth switching element M5. Figure 3(c) shows the drive signal waveforms of the gates of the seventh switching element M7, the ninth switching element M9, and the eleventh switching element M11 in the upper arm of the second bridge circuit 20. Among them, Ga1_2 (green waveform) is the drive signal waveform of the gate of the seventh switching element M7, Gb1_2 (red waveform) is the drive signal waveform of the gate of the ninth switching element M9, and Gc1_2 (blue waveform) is the drive signal waveform of the gate of the eleventh switching element M11. Figure 3 (d) Provides the current signal waveforms to the DC bus capacitor Cdc for the first bridge circuit 10 and the second bridge circuit 20, wherein Icdc1 (green) is the current signal provided by the first bridge circuit 10 to the DC bus capacitor Cdc, and Icdc2 (red) is the current signal provided by the second bridge circuit 20 to the DC bus capacitor Cdc.

[0027] Depend on Figure 3 As can be seen, this embodiment of the invention simultaneously turns on the switching elements of the upper arm of a bridge circuit, thereby connecting the times when all switching elements on and off in that arm. This shifts the timing of the bridge circuit supplying current to the DC bus capacitor to one side of the entire cycle. Due to the phase difference, the timing of the other bridge circuit supplying current to the DC bus capacitor shifts to the other side of the entire cycle, thus achieving… Figure 3 The two bridge circuits shown provide current to the DC bus capacitor at staggered times. Similarly, the capacitor current waveforms generated by simultaneously turning off the switching elements of the upper arms of the two bridge circuits are described in the same manner, and will not be repeated in this embodiment of the invention.

[0028] The single-sided aligned PWM modulation method proposed in this invention can stagger the peak values ​​of the ripple current flowing into the DC bus electrolytic capacitors of the two bridge circuits, eliminating the problem of synchronous superposition of the currents of the two capacitors under traditional center-symmetric modulation. This significantly reduces the peak and effective values ​​of the capacitor ripple current, thereby reducing the required electrolytic capacitor capacity, lowering the overall hardware cost and equipment size, reducing capacitor heating and internal alternating stress, delaying electrolyte aging, and effectively extending the service life of the electrolytic capacitors and the entire power supply. This solves the technical pain point of excessive bus capacitor load in high-power energy storage, charging piles, and industrial converter scenarios, and improves the long-term operational reliability of the system.

[0029] It is understood that those skilled in the art can implement the single-sided alignment drive signal of the above embodiments of the present invention by setting different carrier comparison reference levels and carrier signals. The embodiments of the present invention do not impose too many limitations on the method of generating the single-sided alignment drive signal.

[0030] Figure 3The embodiment shown takes a phase difference of 180 degrees as an example. In actual implementation, the phase difference of the drive signals provided to the two bridge circuits may not be 180 degrees. Even when the phase difference is not 180 degrees, the currents provided to the DC bus capacitors by the two bridge circuits can still be staggered, which can alleviate the problem of peak capacitor current superposition to a certain extent.

[0031] In an alternative embodiment, to achieve better results, the phase difference between the drive signals provided to the first bridge circuit and the second bridge circuit is 180 degrees.

[0032] Single-sided alignment combined with 180-degree carrier stagger can completely offset and cancel out the peak values ​​of the ripple current flowing from the two converters to the DC bus capacitor, significantly reducing the total ripple current of the bus capacitor. This achieves optimal results in reducing capacitor size, reducing heat loss, extending capacitor life, and compressing overall costs.

[0033] In one alternative embodiment, such as Figure 1 As shown, the converter circuit described above also includes a power factor correction inductor Ls and a coupling inductor Lm.

[0034] The upper and lower arms of the first bridge circuit 10 are connected to the first winding of the coupling inductor Lm via a power factor correction inductor Ls, and the second winding of the coupling inductor Lm is connected to the upper and lower arms of the second bridge circuit 20 via another power factor correction inductor Ls.

[0035] In the above embodiment, the coupled inductor Lm and the independent PFC (Power Factor Correction) inductor Ls form a two-stage inductor structure to suppress magnetic saturation. Under normal steady-state conditions, the coupled inductor Lm can suppress high-frequency circulating current, while the independent PFC inductor Ls only shares the low-frequency ripple. Under load or grid impact, the coupled inductor Lm may experience magnetic flux saturation and a sudden decrease in equivalent inductance. At this time, the independent PFC inductor Ls can suppress the inductor current rise slope and prevent excessive current from causing the risk of failure.

[0036] Specifically, such as Figure 1 As shown, a bridge circuit includes three-phase bridge arms. Each phase is connected to a power factor correction inductor Ls through a node between the upper and lower bridge arms. In a parallel converter, each phase corresponds to one bridge arm of two bridge circuits, and the two windings of a coupling inductor Lm are connected together by the corresponding bridge arm.

[0037] In related technologies, when the entire system is powered on, since the output voltage has not yet been established, the duty cycle of the PWM signal is usually rapidly increased to establish the output voltage. However, this control method ignores the dynamic characteristics of the inductor current change rate with respect to the duty cycle and voltage difference change rate, resulting in an extremely high inductor current change rate during power-on, which in turn causes a sharp rise in the inductor inrush current. To reduce the soft-start inrush current, another related technology uses a method of slowly increasing the duty cycle. However, in practical applications, this method does not consider the periodic changes in AC side voltage, which can affect the high-performance requirements of high-power devices. In addition, some soft-start methods in related technologies often rely on an additional power resistor soft-start circuit, which not only increases the system cost but also increases the complexity of system control. In view of this, in some optional embodiments of the present invention, before providing the drive signal to the control terminal of the switching element in the converter circuit, the following is also included: S01. A start signal is provided to the control terminal of the switching element in the converter circuit, wherein the initial switching frequency of the start signal is greater than the switching frequency of the drive signal, and the initial dead time of the start signal is less than the dead time of the drive signal.

[0038] S02. Within a preset time period, reduce the switching frequency of the start signal to the switching frequency of the drive signal, and increase the initial dead time of the start signal to the dead time of the drive signal.

[0039] The above embodiments of the present invention provide a segmented frequency conversion dynamic dead-time soft start scheme. First, a start signal is output with a higher initial switching frequency and a smaller dead time. Then, the switching frequency is gradually reduced to the normal operating frequency within a preset time, and the dead time is synchronously amplified to the conventional drive dead time parameters. High-frequency start can reduce the peak value of inductor current ripple at the moment of power-on, and dynamic adjustment of the dead time can smoothly constrain the rate of change of inductor current. The combination of the two can effectively suppress the power-on inrush current, eliminating the need for an additional high-power soft start resistor, reducing device losses and overall hardware costs, and avoiding the volt-second imbalance problem caused by linearly increasing the duty cycle, thus achieving smooth and overshoot-free start-up of the converter.

[0040] Optionally, the initial switching frequency of the aforementioned start signal is 1.1 to 1.3 times the switching frequency of the aforementioned drive signal, preferably 1.2 times; the initial dead time of the aforementioned start signal is 0.2 to 0.4 times the switching period of the aforementioned drive signal, preferably 1 / 3 times, and the dead time of the drive signal is at least greater than 1 / 3 of the switching period.

[0041] The parameter settings of the above-mentioned start signal can slightly reduce the peak value of the power-on inductor current ripple by slightly increasing the switching frequency, without causing control failure due to excessive frequency exceeding the computing power limit of the control unit. At the same time, the use of a smaller dead zone in the initial start signal can avoid excessive loss of effective conduction pulse width in the early stage of start-up, prevent input current distortion and slow voltage build-up. Combined with the subsequent adjustment logic of gradually reducing the frequency and expanding the dead zone, the optimal balance is achieved between suppressing the power-on inrush current, ensuring the performance of the input current, and matching the computing power of the controller. This makes the slow start-up process smooth and controllable, while also suppressing inrush current and power quality, and improving the operational stability during the start-up phase.

[0042] In some optional embodiments, the preset time includes a first preset time and a second preset time; S02 includes: S021. During the first preset time period, the initial dead time of the start signal is kept unchanged, while the switching frequency of the start signal is reduced to the switching frequency of the drive signal.

[0043] Optionally, the first preset time can be from 0ms to 200ms.

[0044] S022. During the second preset time period, the current switching frequency of the start signal is kept unchanged, while the initial dead time of the start signal is increased to the dead time of the drive signal.

[0045] Optionally, the second preset time can be from 200ms to the time during which the circuit can output at its rated speed.

[0046] The above embodiments of the present invention adjust the switching frequency and dead zone in two stages. First, the frequency is reduced while the dead zone remains constant during the first preset time. The sudden change in inductor current during the initial power-on period is continuously suppressed by the gradual decline of the high frequency, avoiding a sudden surge. Then, the stable operating frequency is locked during the second preset time, and the dead zone is gradually increased to smoothly reduce the effective duty cycle and limit the current rise slope. The above embodiments adjust the two parameters independently in stages, avoiding control coupling disturbances caused by synchronous changes in frequency and dead zone. This makes the voltage and current changes more stable, reliably suppressing the power-on inrush current, and preventing input current distortion and bus voltage oscillation caused by synchronous adjustment. The start-up process is more controllable, ensuring stable power quality throughout the slow start-up process.

[0047] In another optional embodiment, the initial switching frequency of the start signal is first set to 1.2 times the switching frequency of the drive signal, and the initial dead time is 1 / 3 of the switching period of the drive signal.

[0048] During the first preset time period, which is the frequency soft-start phase of the circuit, the controller sets the dead time to 1 / 3 of the switching cycle, and simultaneously linearly reduces the PWM switching frequency from 1.2 times the normal switching frequency to the normal switching frequency. This phase effectively suppresses the inductor current rise rate during the rapid build-up of the output voltage through the combined effect of increasing the dead time and linearly controlling the switching frequency, thus avoiding the inrush current generated by the rapid charging of the output capacitor.

[0049] During the second preset time period, the circuit is in a stable ramp-up phase. The dead time is linearly reduced from 1 / 3 of the switching cycle to the normal dead time setting (which can be 300ns). At the same time, the output voltage setting is slowly raised to the rated value to achieve a smooth start-up of the circuit.

[0050] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0051] The following are device embodiments of the present invention. For details not described in detail, please refer to the corresponding method embodiments described above.

[0052] Figure 4 A schematic diagram of the drive device for the parallel-interleaved converter provided in an embodiment of the present invention is shown. For ease of explanation, only the parts related to the embodiment of the present invention are shown, and are described in detail below: like Figure 4 As shown, the parallel interleaved converter pulse width modulation control device provided in this embodiment of the invention includes a drive module 40 and is applied to the converter circuit 41, such as... Figure 1 As shown, the converter circuit 41 includes a first bridge circuit 10, a second bridge circuit 20, and a DC bus capacitor Cdc connected in parallel. Both the first bridge circuit 10 and the second bridge circuit 20 include an upper bridge arm and a lower bridge arm, and each upper bridge arm and lower bridge arm includes at least two identical switching elements. The drive module 40 is used for: A drive signal is provided to the control terminal of the switching element in the converter circuit 41; wherein the drive signal is used to simultaneously turn on the switching element of the upper arm of the first bridge circuit 10 and simultaneously turn on the switching element of the upper arm of the second bridge circuit 20; or, the drive signal is used to simultaneously turn off the switching element of the upper arm of the first bridge circuit 10 and simultaneously turn off the switching element of the upper arm of the second bridge circuit 20.

[0053] The single-sided aligned PWM modulation device proposed in this invention can stagger the peak values ​​of the ripple current flowing into the DC bus electrolytic capacitors of the two bridge circuits, eliminating the problem of synchronous superposition of the currents of the two capacitors under traditional center-symmetric modulation. This significantly reduces the peak and effective values ​​of the capacitor ripple current, thereby reducing the required electrolytic capacitor capacity, lowering the overall hardware cost and equipment size, reducing capacitor heating and internal alternating stress, delaying electrolyte aging, and effectively extending the service life of the electrolytic capacitors and the entire power supply. This solves the technical pain point of excessive bus capacitor load in high-power energy storage, charging piles, and industrial converter scenarios, and improves the long-term operational reliability of the system.

[0054] In one alternative embodiment, the phase difference between the drive signals provided to the first bridge circuit and the second bridge circuit is 180 degrees.

[0055] In an optional embodiment, before providing a drive signal to the control terminal of the switching element in the converter circuit, the drive module is further configured to: A start signal is provided to the control terminal of the switching element in the converter circuit, wherein the initial switching frequency of the start signal is greater than the switching frequency of the drive signal, and the initial dead time of the start signal is less than the dead time of the drive signal; within a preset time, the switching frequency of the start signal is reduced to the switching frequency of the drive signal, and the initial dead time of the start signal is increased to the dead time of the drive signal.

[0056] In one optional embodiment, the preset time includes a first preset time and a second preset time; the driving module is specifically used for: During the first preset time period, the initial dead time of the start signal is kept unchanged, while the switching frequency of the start signal is reduced to the switching frequency of the drive signal; during the second preset time period, the current switching frequency of the start signal is kept unchanged, while the initial dead time of the start signal is increased to the dead time of the drive signal.

[0057] In one optional embodiment, the initial switching frequency of the start signal is 1.1 to 1.3 times the switching frequency of the drive signal, and the initial dead time of the start signal is 0.2 to 0.4 times the switching period of the drive signal.

[0058] Figure 5 This is a schematic diagram of an electronic device provided in an embodiment of the present invention. Figure 5As shown, the electronic device 5 of this embodiment includes a processor 50 and a memory 51. The memory 51 stores a computer program 52. When the processor 50 executes the computer program 52, it implements the steps in the various method embodiments described above. Alternatively, when the processor 50 executes the computer program 52, it implements the functions of each module / unit in the various device embodiments described above.

[0059] For example, computer program 52 may be divided into one or more modules / units, which are stored in memory 51 and executed by processor 50 to complete the present invention. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 52 in electronic device 5.

[0060] Electronic device 5 may include, but is not limited to, processor 50 and memory 51. Those skilled in the art will understand that... Figure 5 This is merely an example of electronic device 5 and does not constitute a limitation on electronic device 5. It may include more or fewer components than shown, or combine certain components, or different components. For example, electronic device 5 may also include input / output devices, network access devices, buses, etc.

[0061] The processor 50 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0062] The memory 51 can be an internal storage unit of the electronic device 5, such as a hard disk or RAM. The memory 51 can also be an external storage device of the electronic device 5, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card. Furthermore, the memory 51 can include both internal and external storage units of the electronic device 5. The memory 51 is used to store the computer program 52 and other programs and data required by the electronic device 5. The memory 51 can also be used to temporarily store data that has been output or will be output.

[0063] For the sake of simplicity and clarity, only the above-described functional modules / units are used as examples. In practical applications, the functions described above can be assigned to different functional modules / units as needed. These modules / units can be implemented in hardware, software, or a combination of both.

[0064] This invention also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the methods described in the above-described method embodiments.

[0065] This invention also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the methods described in the above-described method embodiments.

[0066] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0067] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not detailed or described in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Unless otherwise specified or in conflict with logic, the terminology and / or descriptions between different embodiments are consistent and can be referenced interchangeably. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0068] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A driving method for a parallel interleaved converter, characterized in that, The converter circuit is applied to a converter circuit, which includes a first bridge circuit, a second bridge circuit, and a DC bus capacitor connected in parallel. Both the first bridge circuit and the second bridge circuit include an upper bridge arm and a lower bridge arm, and both the upper bridge arm and the lower bridge arm include at least two and the same number of switching elements. The method includes: A drive signal is provided to the control terminal of the switching element in the converter circuit; wherein the drive signal is used to simultaneously turn on the switching element of the upper arm of the first bridge circuit and simultaneously turn on the switching element of the upper arm of the second bridge circuit; or, the drive signal is used to simultaneously turn off the switching element of the upper arm of the first bridge circuit and simultaneously turn off the switching element of the upper arm of the second bridge circuit.

2. The driving method for a parallel interleaved converter according to claim 1, characterized in that, The phase difference between the drive signals provided to the first bridge circuit and the second bridge circuit is 180 degrees.

3. The driving method for a parallel interleaved converter according to claim 1, characterized in that, The converter circuit also includes a power factor correction inductor and a coupling inductor; The upper and lower arms of the first bridge circuit are connected to the first winding of the coupled inductor through a power factor correction inductor, and the second winding of the coupled inductor is connected to the upper and lower arms of the second bridge circuit through another power factor correction inductor.

4. The driving method for a parallel interleaved converter according to claim 1, characterized in that, Before providing a drive signal to the control terminal of the switching element in the converter circuit, the method further includes: A start signal is provided to the control terminal of the switching element in the converter circuit, wherein the initial switching frequency of the start signal is greater than the switching frequency of the drive signal, and the initial dead time of the start signal is less than the dead time of the drive signal. Within a preset time period, the switching frequency of the start signal is reduced to the switching frequency of the drive signal, and the initial dead time of the start signal is increased to the dead time of the drive signal.

5. The driving method for a parallel interleaved converter according to claim 4, characterized in that, The preset time includes a first preset time and a second preset time; The step of reducing the switching frequency of the start signal to the switching frequency of the drive signal and increasing the initial dead time of the start signal to the dead time of the drive signal within a preset time includes: During the first preset time period, the initial dead time of the start signal is kept unchanged, while the switching frequency of the start signal is reduced to the switching frequency of the drive signal. During the second preset time period, the current switching frequency of the start signal is kept unchanged, while the initial dead time of the start signal is increased to the dead time of the drive signal.

6. The driving method for a parallel interleaved converter according to claim 4, characterized in that, The initial switching frequency of the start signal is 1.1 to 1.3 times the switching frequency of the drive signal, and the initial dead time of the start signal is 0.2 to 0.4 times the switching period of the drive signal.

7. A drive device for a parallel interleaved converter, characterized in that, The converter circuit is applied to a converter circuit, which includes a first bridge circuit, a second bridge circuit, and a DC bus capacitor connected in parallel. Both the first bridge circuit and the second bridge circuit include an upper bridge arm and a lower bridge arm, and both the upper bridge arm and the lower bridge arm include at least two and the same number of switching elements. The device includes a drive module, the drive module being used for: A drive signal is provided to the control terminal of the switching element in the converter circuit; wherein the drive signal is used to simultaneously turn on the switching element of the upper arm of the first bridge circuit and simultaneously turn on the switching element of the upper arm of the second bridge circuit; or, the drive signal is used to simultaneously turn off the switching element of the upper arm of the first bridge circuit and simultaneously turn off the switching element of the upper arm of the second bridge circuit.

8. An electronic device, characterized in that, It includes a memory and a processor, the memory storing a computer program, and the processor executing the computer program to implement the method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 6.

10. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 6.

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