Voltage conversion circuit, chip, and electronic device

Abstract

The application relates to the field of electronic technology, in particular to a voltage conversion circuit, a chip and an electronic device. The voltage conversion circuit comprises a charge pump circuit and a step-down circuit. The charge pump circuit is used for performing step-up processing on an input voltage to obtain an intermediate voltage. The step-down circuit is used for performing step-down processing on the input voltage to obtain a first output voltage. Alternatively, the step-down circuit is used for receiving the input voltage and the intermediate voltage and performing step-down processing to obtain a second output voltage. The second output voltage is greater than the input voltage and smaller than the intermediate voltage. According to the voltage conversion circuit provided in the application, the voltage conversion circuit comprises the charge pump circuit and the step-down circuit. The charge pump circuit and the step-down circuit are controlled to work in cooperation, and the charge pump circuit and the step-down circuit work in different modes. The output end can output a continuous and stable output voltage, and the output voltage can be adjusted in a wide range, so as to adapt to different scene requirements.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and in particular to a voltage conversion circuit, chip, and electronic device. Background Technology

[0002] With the rapid development of electronic products, electronic devices are becoming increasingly powerful, have higher data processing efficiency, and display resolutions, leading to ever-increasing demands on charging efficiency. In related technologies, switched-capacitor voltage converters (SVCs) are commonly used to meet the fast charging needs of electronic devices. As a basic power conversion structure, SVCs are widely used in various power management applications. They utilize energy storage capacitors as energy storage elements and control the switching timing of transistors to change the capacitor connection method, achieving voltage-to-current conversion between input and output at various ratios. For complex voltage conversion requirements, multi-stage architectures can be used to construct corresponding SVCs. The main application scenario for SVCs is mobile devices. Their advantage lies in high efficiency and the ability to achieve fast charging in short periods. However, they limit the relative voltage range of input and output and cannot support continuous forward voltage regulation for constant current slow charging. Furthermore, considering battery life and safety, a constant current is required for slow charging during the pre-charging and trickle charging stages. Therefore, simply using SVCs to improve charging efficiency is not suitable for some application scenarios. Summary of the Invention

[0003] This application provides a voltage conversion circuit, chip, and electronic device to solve the technical problem of a narrow input-output voltage range in related technologies.

[0004] In a first aspect, this application provides a voltage conversion circuit, which includes a charge pump circuit and a step-down circuit. The first terminal of the charge pump circuit is electrically connected to the first terminal of the step-down circuit, and the second terminal of the charge pump circuit is connected to the second terminal of the step-down circuit. The first terminal of the charge pump circuit is used to receive the input voltage, the charge pump circuit is used to boost the input voltage to obtain an intermediate voltage, and the second terminal of the charge pump circuit is used to output the intermediate voltage. The first terminal of the step-down circuit is used to receive the input voltage. The step-down circuit is used to step down the input voltage to obtain a first output voltage, so that the third terminal of the step-down circuit outputs the first output voltage. Alternatively, the first terminal of the step-down circuit is used to receive the input voltage, the second terminal of the step-down circuit is used to receive the intermediate voltage, the step-down circuit is used to receive the input voltage and the intermediate voltage, and perform step-down processing to obtain a second output voltage, and the third terminal of the step-down circuit is used to output the second output voltage; the second output voltage is greater than the input voltage and less than the intermediate voltage.

[0005] In one possible design, the charge pump circuit includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first terminal of the first transistor is connected to the second terminals of the fifth transistor and the eighth transistor, respectively. The first terminal of the first transistor, the second terminal of the fifth transistor, and the second terminal of the eighth transistor together form the first terminal of the charge pump circuit. The first terminal of the eighth transistor is connected to the first terminal of the first capacitor, the first terminal of the third capacitor, and the second terminal of the seventh transistor, respectively. The first terminal of the seventh transistor is grounded. The second terminal of the first capacitor is connected to the second terminal of the first transistor and the first terminal of the second transistor, respectively. The second terminal of the third capacitor is connected to the second terminal of the third transistor and the first terminal of the fourth transistor, respectively. The second terminal of the fourth transistor is the second terminal of the charge pump circuit. The first terminal of the fifth transistor is connected to the second terminal of the sixth transistor and the first terminal of the second capacitor, respectively. The first terminal of the sixth transistor is grounded, and the second terminal of the second capacitor is connected to the second terminal of the second transistor and the first terminal of the third transistor, respectively. The control terminals of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are used to receive corresponding on / off control signals, which are used to control the on and off states of the corresponding transistors.

[0006] In one possible design, the buck circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and an inductor; The first terminal of the twelfth transistor is the first terminal of the buck circuit. The first terminal of the twelfth transistor is connected to the first terminal of the first transistor, the second terminal of the fifth transistor, and the second terminal of the eighth transistor. The second terminal of the twelfth transistor is connected to the second terminal of the thirteenth transistor, the first terminal of the eleventh transistor, and the first terminal of the inductor. The first terminal of the thirteenth transistor is grounded. The second terminal of the eleventh transistor is connected to the second terminal of the fourth transistor. The second terminal of the eleventh transistor is the second terminal of the buck circuit. The second terminal of the inductor is the third terminal of the buck circuit. The control terminals of the eleventh transistor, the twelfth transistor, and the thirteenth transistor are respectively used to receive corresponding on / off control signals, which are used to control the on and off states of the corresponding transistors.

[0007] In one possible design, the voltage conversion circuit includes a fourth capacitor, a fifth capacitor, and a sixth capacitor; The first terminal of the fourth capacitor is connected to the first terminal of the first transistor, the second terminal of the twelfth transistor, the second terminal of the fifth transistor, and the second terminal of the eighth transistor, respectively, and the second terminal of the fourth capacitor is grounded. The first terminal of the fifth capacitor is connected to the second terminal of the fourth transistor and the second terminal of the eleventh transistor, respectively, and the second terminal of the fifth capacitor is grounded. The first terminal of the sixth capacitor is connected to the second terminal of the inductor, and the second terminal of the sixth capacitor is grounded.

[0008] In one possible design, when the voltage conversion circuit operates in the first voltage conversion mode, within any first duty cycle: The control terminals of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the eleventh transistor are all used to receive a first shutdown control signal. The first shutdown control signal is used to control the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the eleventh transistor to be in a shutdown state during the first working cycle. In the first stage of the first working cycle, the control electrode of the twelfth transistor is used to receive a second conduction control signal, which is used to control the twelfth transistor to be in the conduction state in the first stage of the first working cycle; the control electrode of the thirteenth transistor is used to receive a second turn-off control signal, which is used to control the thirteenth transistor to be in the turn-off state in the first stage of the first working cycle. In the second phase of the first working cycle, the control electrode of the twelfth transistor is used to receive a third turn-off control signal, which is used to control the twelfth transistor to be in a turn-off state in the second phase of the first working cycle; the control electrode of the thirteenth transistor is used to receive a third turn-on control signal, which is used to control the thirteenth transistor to be in a turn-on state in the second phase of the first working cycle. The on / off control signal includes the first off control signal, the second off control signal, the third off control signal, the second on control signal, and the third on control signal.

[0009] In one possible design, when the voltage conversion circuit operates in the second voltage conversion mode: During each second operating cycle of the charge pump circuit, the control electrode of the second transistor and the control electrode of the third transistor are both used to receive a fourth conduction control signal, which is used to control the second transistor and the third transistor to be in the conduction state during the second operating cycle. In the first phase of the second operating cycle, the control electrodes of the first transistor, the sixth transistor, and the seventh transistor are all used to receive a fifth turn-on control signal. The fifth turn-on control signal is used to control the first transistor, the sixth transistor, and the seventh transistor to be in the turn-on state during the first phase of the second operating cycle. The control electrodes of the fourth transistor, the fifth transistor, and the eighth transistor are all used to receive a fifth turn-off control signal. The fifth turn-off control signal is used to control the fourth transistor, the fifth transistor, and the eighth transistor to be in the turn-off state during the first phase of the second operating cycle. In the second phase of the second operating cycle, the control electrodes of the first transistor, the sixth transistor, and the seventh transistor are all used to receive a sixth turn-off control signal. The sixth turn-off control signal is used to control the first transistor, the sixth transistor, and the seventh transistor to be in a turn-off state during the second phase of the second operating cycle. The control electrodes of the fourth transistor, the fifth transistor, and the eighth transistor are all used to receive a sixth turn-on control signal. The sixth turn-on control signal is used to control the fourth transistor, the fifth transistor, and the eighth transistor to be in a turn-on state during the first phase of the second operating cycle. The on / off control signals include the fourth on control signal, the fifth on control signal, the sixth on control signal, the fifth off control signal, and the sixth off control signal.

[0010] In one possible design, when the voltage conversion circuit operates in the third voltage conversion mode: In the first phase of each third operating cycle of the charge pump circuit, the control terminals of the first transistor, the third transistor, the fifth transistor, and the seventh transistor are all used to receive a seventh turn-on control signal. The seventh turn-on control signal is used to control the first transistor, the third transistor, the fifth transistor, and the seventh transistor to be in the turn-on state during the first phase of the third operating cycle. The control terminals of the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are all used to receive a seventh turn-off control signal. The seventh turn-off control signal is used to control the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor to be in the turn-off state during the first phase of the third operating cycle. In the second phase of the third operating cycle, the control electrodes of the first transistor, the third transistor, the fifth transistor, and the seventh transistor are all used to receive an eighth turn-off control signal. The eighth turn-off control signal is used to control the first transistor, the third transistor, the fifth transistor, and the seventh transistor to be in a turn-off state during the second phase of the third operating cycle. The control electrodes of the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are all used to receive an eighth turn-on control signal. The eighth turn-on control signal is used to control the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor to be in a turn-on state during the second phase of the third operating cycle. The on / off control signals include the seventh on control signal, the eighth on control signal, the seventh off control signal, and the eighth off control signal.

[0011] In one possible design, when the voltage conversion circuit operates in the second or third voltage conversion mode, during each fourth operating cycle of the buck circuit: The control electrode of the thirteenth transistor is used to receive the ninth turn-off control signal, which is used to control the thirteenth transistor to be in the off state during the fourth working cycle. In the first stage of each fourth cycle of the buck circuit, the control electrode of the eleventh transistor is used to receive a tenth turn-on control signal, which is used to control the eleventh transistor to be in the turn-on state in the first stage of the fourth cycle; the control electrode of the twelfth transistor is used to receive a tenth turn-off control signal, which is used to control the twelfth transistor to be in the turn-off state in the first stage of the fourth cycle. In the second phase of each fourth cycle of the buck circuit, the control electrode of the eleventh transistor is used to receive an eleventh turn-off control signal, which is used to control the eleventh transistor to be in the off state in the second phase of the fourth cycle; the control electrode of the twelfth transistor is used to receive an eleventh turn-on control signal, which is used to control the twelfth transistor to be in the turn-on state in the second phase of the fourth cycle. The on / off control signals include the ninth off control signal, the tenth off control signal, the eleventh off control signal, the tenth on control signal, and the eleventh on control signal.

[0012] Secondly, this application also provides a chip, the chip including the voltage conversion circuit as described in any of the preceding claims.

[0013] Thirdly, this application also provides an electronic device, which includes the voltage conversion circuit described in any of the above claims; or the electronic device includes the chip described above.

[0014] The voltage conversion circuit provided in the first aspect above includes a charge pump circuit and a buck circuit. A first terminal of the charge pump circuit is electrically connected to a first terminal of the buck circuit, and a second terminal of the charge pump circuit is connected to a second terminal of the buck circuit. The first terminal of the charge pump circuit receives an input voltage and boosts the input voltage to obtain an intermediate voltage. The second terminal of the charge pump circuit outputs the intermediate voltage. The first terminal of the buck circuit receives the input voltage and bucks the input voltage to obtain a first output voltage, such that the third terminal of the buck circuit outputs the first output voltage. Alternatively, the first terminal of the buck circuit receives the input voltage, the second terminal receives the intermediate voltage, and the buck circuit receives both the input voltage and the intermediate voltage, bucks them to obtain a second output voltage, and the third terminal outputs the second output voltage. The second output voltage is greater than the input voltage and less than the intermediate voltage. As can be seen, the voltage conversion circuit provided in this application includes a charge pump circuit and a step-down circuit. By controlling the charge pump circuit and the step-down circuit to work together and to operate in different modes, the output terminal can output a continuous and stable output voltage. The output voltage is adjustable within a wide range to adapt to a wide range of voltage conversion ratios, thereby meeting the needs of different scenarios.

[0015] The beneficial effects provided by the other aspects and the various possible designs of the other aspects can be found in the beneficial effects of the first aspect and the various possible implementations of the first aspect, and will not be repeated here. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the overall structure of the voltage conversion circuit provided in the embodiments of this application; Figure 2 This is a schematic diagram of the operation of the voltage conversion circuit provided in the embodiments of this application in the first voltage conversion mode; Figure 3 This is a schematic diagram of the control signal waveform of the voltage conversion circuit provided in the embodiments of this application in the first voltage conversion mode; Figure 4 This is one of the schematic diagrams of the operating mode of the voltage conversion circuit in the first voltage conversion mode provided in the embodiments of this application; Figure 5 This is a second schematic diagram of the operating mode of the voltage conversion circuit under the first voltage conversion mode provided in the embodiments of this application; Figure 6A schematic diagram of the control signal waveform for the voltage conversion circuit operating in the second voltage conversion mode provided in the embodiments of this application; Figure 7 This is one of the schematic diagrams of the operating mode of the voltage conversion circuit in the second voltage conversion mode provided in the embodiments of this application; Figure 8 This is a second schematic diagram of the operating mode of the voltage conversion circuit under the second voltage conversion mode provided in the embodiments of this application; Figure 9 An equivalent circuit diagram of the voltage conversion circuit provided in the embodiments of this application in the second voltage conversion mode; Figure 10 A schematic diagram of the control signal waveform of the voltage conversion circuit provided in the embodiment of this application operating in the third voltage conversion mode; Figure 11 One of the schematic diagrams showing the voltage conversion circuit provided in the embodiments of this application operating in the third voltage conversion mode; Figure 12 A second schematic diagram showing the voltage conversion circuit provided in the embodiments of this application operating in the third voltage conversion mode; Figure 13 This is a schematic diagram of the equivalent circuit of the voltage conversion circuit provided in the embodiment of this application operating in the third voltage conversion mode. Detailed Implementation

[0017] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c alone can mean: a alone, b alone, c alone, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] The terms “center,” “longitudinal,” “lateral,” “up,” “down,” “left,” “right,” “front,” and “rear,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0019] The terms "connected" and "connected" should be interpreted broadly. For example, in circuit structures, "connected" or "connected" can refer not only to physical connections but also to electrical or signal connections. This could be a direct connection (physical connection) or an indirect connection via at least one intermediate component, as long as the circuit is connected. It could also refer to the internal connection between two components. Similarly, a signal connection can refer to a connection via a circuit or a medium, such as radio waves. Those skilled in the art will understand the specific meaning of these terms in this application based on the specific circumstances.

[0020] The transistor in this application is a three-terminal transistor, with its three terminals being a control terminal, a first terminal, and a second terminal. The transistor can be a bipolar transistor (BJT) or a field-effect transistor (FET). For example, when the transistor is a BJT, its control terminal is the base, the first terminal can be the collector or emitter, and the corresponding second terminal can be the emitter or collector. When the transistor is an FET, its control terminal is the gate, the first terminal can be the drain or source, and the corresponding second terminal can be the source or drain. Furthermore, the transistor implementations provided in this application include, but are not limited to, gallium nitride (GaN) transistors, bipolar junction transistors (BJTs), insulated-gate bipolar transistors (IGBTs), metal-oxide-semiconductor (MODS) FETs, field-controlled thyristors (FETs), gate turn-off thyristors (GDSs), and transmission gates.

[0021] In related technologies, switched-capacitor voltage converters are commonly used to meet the fast charging requirements of electronic devices. As a basic power conversion structure, switched-capacitor voltage converters are widely used in various power management applications. They utilize energy storage capacitors as energy storage elements and change the capacitor connection method by controlling the on-time of the switching transistors to achieve various input-output voltage-to-current conversion ratios. For complex voltage conversion requirements, multi-stage architectures can be used to construct corresponding switched-capacitor voltage converters. However, the switched-capacitor voltage converters provided in related technologies have a narrow range of achievable input-output voltage ratios and cannot support continuous forward voltage regulation for constant current slow charging. Therefore, they are not suitable for some application scenarios.

[0022] Furthermore, in Buck-Boost converters, the voltage stress on the power switching devices is equal to the input or output voltage. Under high buck-boost gain conditions, there is significant overlap between voltage and current during the turn-on and turn-off moments, introducing substantial switching losses and limiting efficiency improvements in high-frequency, high-power applications. Simultaneously, due to the large voltage jumps during switching (i.e., a high dv / dt ratio), these converters are prone to generating high-frequency oscillations and electromagnetic radiation caused by parasitic parameters, increasing electromagnetic interference (EMI) issues and placing higher demands on input / output filtering and device withstand voltage margins.

[0023] Furthermore, the Buck-Boost converter exhibits discontinuous output current characteristics and significant output current ripple, which not only increases the design complexity of the output filter but also negatively impacts the stability of the power supply quality on the load side and the reliable operation of the system. In summary, the Buck-Boost topology circuits provided in related technologies struggle to balance efficiency, reliability, and electromagnetic compatibility performance in high-gain, high-power-density applications.

[0024] To overcome the shortcomings of the aforementioned related technologies, this application provides a voltage conversion circuit, which includes a charge pump circuit and a buck circuit. A first terminal of the charge pump circuit is electrically connected to a first terminal of the buck circuit, and a second terminal of the charge pump circuit is connected to a second terminal of the buck circuit. The first terminal of the charge pump circuit receives an input voltage and boosts the input voltage to obtain an intermediate voltage. The second terminal of the charge pump circuit outputs the intermediate voltage. The first terminal of the buck circuit receives the input voltage and bucks the input voltage to obtain a first output voltage, such that the third terminal of the buck circuit outputs the first output voltage. Alternatively, the first terminal of the buck circuit receives the input voltage, the second terminal receives the intermediate voltage, and the buck circuit receives both the input voltage and the intermediate voltage, bucks them to obtain a second output voltage, and the third terminal outputs the second output voltage. The second output voltage is greater than the input voltage and less than the intermediate voltage. As can be seen, the voltage conversion circuit provided in this application includes a charge pump circuit and a buck circuit. By controlling the charge pump circuit and the buck circuit to work together and operating them in different modes, a continuous and stable output voltage can be output at the output terminal. Furthermore, the output voltage is adjustable within a wide range to accommodate a wide range of voltage conversion ratios, thus meeting the needs of different scenarios. In addition, regarding device stress and switching losses, this application significantly reduces the voltage stress on the power switching devices by selecting appropriate operating modes according to different output voltage levels. Based on this, the overlap area between voltage and current during switching is effectively reduced, thereby significantly reducing switching losses and improving the overall conversion efficiency under high-frequency operating conditions.

[0025] Figure 1 For a schematic diagram of the overall structure of the voltage conversion circuit provided in the embodiments of this application, please refer to [link / reference]. Figure 1As shown, the voltage conversion circuit provided in this embodiment includes a charge pump circuit 100 and a buck circuit 200. The first terminal of the charge pump circuit 100 is electrically connected to the first terminal of the buck circuit 200, and the second terminal of the charge pump circuit 100 is connected to the second terminal of the buck circuit. The first terminal of the charge pump circuit 100 is used to receive the input voltage VIN, and the charge pump circuit 100 is used to boost the input voltage VIN to obtain an intermediate voltage VMID. The second terminal of the charge pump circuit 100 is used to output the intermediate voltage VMID. In one operating mode, the first terminal of the buck circuit 200 is used to receive the input voltage VIN, and the... A step-down circuit 200 is used to step down the input voltage VIN to obtain a first output voltage, so that the third terminal of the step-down circuit 200 outputs the first output voltage; or, the first terminal of the step-down circuit 200 is used to receive the input voltage VIN, the second terminal of the step-down circuit 200 is used to receive the intermediate voltage VMD, the step-down circuit 200 is used to receive the input voltage VIN and the intermediate voltage VMD, and perform step-down processing to obtain a second output voltage, the third terminal of the step-down circuit 200 is used to output the second output voltage; the second output voltage is greater than the input voltage VIN and less than the intermediate voltage VMD.

[0026] It should be noted that in the voltage conversion circuit of this embodiment, the first terminal of the charge pump circuit 100 and the first terminal of the buck circuit 200 are connected together to form the voltage input terminal A1 of the voltage conversion circuit; the second terminal of the charge pump circuit 100 and the second terminal of the buck circuit 200 are connected together to form the intermediate voltage node A2 of the voltage conversion circuit; the third terminal A3 of the buck circuit 200 is used to output the final converted output voltage VOUT, which corresponds to the first output voltage or the second output voltage mentioned above in different operating modes.

[0027] It is understood that the voltage conversion circuit in this embodiment includes a charge pump circuit 100 and a buck circuit 200, and the charge pump circuit 100 and the buck circuit 200 share a common voltage input terminal A1 and an intermediate voltage node A2. This allows the charge pump circuit 100 and the buck circuit 200 to operate in different modes during operation, thereby adjusting the input voltage V. IN By achieving different voltage conversion ratios, the third terminal A3 of the buck circuit 200 ultimately outputs different output voltages.

[0028] As can be seen, the voltage conversion circuit provided in this embodiment includes a charge pump circuit 100 and a buck circuit 200. By controlling the charge pump circuit 100 and the buck circuit 200 to work together and operate in different modes, a continuous and stable output voltage can be output at the output terminal. Furthermore, the output voltage is adjustable within a wide range to accommodate a wide range of voltage conversion ratios, thus meeting the needs of different scenarios. In addition, regarding device stress and switching losses, this embodiment selects appropriate operating modes according to different output voltage levels, significantly reducing voltage stress on the power switching devices. Based on this, the overlap area of ​​voltage and current during switching is effectively reduced, thereby significantly reducing switching losses and improving the overall conversion efficiency under high-frequency operating conditions.

[0029] Please continue reading Figure 1As shown, the charge pump circuit 100 provided in this embodiment includes a first capacitor CF1, a second capacitor CF2, a third capacitor CF3, a first transistor S1, a second transistor S2, a third transistor S3, a fourth transistor S4, a fifth transistor S5, a sixth transistor S6, a seventh transistor S7, and an eighth transistor S8; wherein, the first terminal of the first transistor S1 is connected to the second terminal of the fifth transistor S5 and the second terminal of the eighth transistor S8, and the first terminal of the first transistor S1, the second terminal of the fifth transistor S5, and the second terminal of the eighth transistor S8 together form the first terminal of the charge pump circuit 100; the first terminal of the eighth transistor S8 is connected to the first terminal of the first capacitor CF1, the first terminal of the third capacitor CF3, and the second terminal of the eighth transistor S8. The second terminal of the seventh transistor S7 is connected, and the first terminal of the seventh transistor S7 is grounded (GND). The second terminal of the first capacitor CF1 is connected to the second terminal of the first transistor S1 and the first terminal of the second transistor S2. The second terminal of the third capacitor CF3 is connected to the second terminal of the third transistor S3 and the first terminal of the fourth transistor S4, and the second terminal of the fourth transistor S4 is the second terminal of the charge pump circuit 100. The first terminal of the fifth transistor S5 is connected to the second terminal of the sixth transistor S6 and the first terminal of the second capacitor CF2, and the first terminal of the sixth transistor S6 is grounded. The second terminal of the second capacitor CF2 is connected to the second terminal of the second transistor S2 and the first terminal of the third transistor S3. The control terminals of the first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, the seventh transistor S7, and the eighth transistor S8 are respectively used to receive corresponding on / off control signals, which are used to control the on and off of the corresponding transistors.

[0030] In one embodiment of this application, the first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, the seventh transistor S7, and the eighth transistor S8 are all NMOS (N-Metal-Oxide-Semiconductor) transistors. In other embodiments, the first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, the seventh transistor S7, and the eighth transistor S8 may also be PMOS (P-Metal-Oxide-Semiconductor) transistors. For example, when the first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, the seventh transistor S7, and the eighth transistor S8 in this embodiment are all NMOS transistors, their first electrode is the source, their second electrode is the drain, and their control electrode is the gate.

[0031] The charge pump circuit 100 provided in this embodiment includes three capacitors: a first capacitor CF1, a second capacitor CF2, and a third capacitor CF3. During operation, the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3 mainly play the role of energy storage. By controlling the change in the electrical connection relationship of the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3, the intermediate voltage VMID output at the second terminal can be adjusted.

[0032] Please continue reading Figure 1 As shown, the buck circuit 200 provided in this embodiment includes an eleventh transistor SA1, a twelfth transistor SA2, a thirteenth transistor SB, and an inductor L. The first terminal of the twelfth transistor SA2 is the first terminal of the buck circuit 200. The first terminal of the twelfth transistor SA2 is connected to the first terminal of the first transistor S1, the second terminal of the fifth transistor S5, and the second terminal of the eighth transistor S8. The second terminal of the twelfth transistor S12 is connected to the second terminal of the thirteenth transistor SB, the first terminal of the eleventh transistor S11, and the first terminal of the inductor L. The first terminal of the thirteenth transistor SB is grounded. The second terminal of the eleventh transistor S11 is connected to the second terminal of the fourth transistor S4. The second terminal of the eleventh transistor SA1 is the second terminal of the buck circuit 200. The second terminal of the inductor L is the third terminal of the buck circuit 200, and the third terminal A3 is used to output the final converted output voltage VOUT.

[0033] In one embodiment of this application, the eleventh transistor SA1, the twelfth transistor SA2, and the thirteenth transistor SB are all NMOS (N-Metal-Oxide-Semiconductor) transistors. In other embodiments, the eleventh transistor SA1, the twelfth transistor SA2, and the thirteenth transistor SB may also be PMOS (P-Metal-Oxide-Semiconductor) transistors. For example, when the eleventh transistor SA1, the twelfth transistor SA2, and the thirteenth transistor SB in this embodiment are all NMOS transistors, their first electrode is the source, their second electrode is the drain, and their control electrode is the gate.

[0034] It should be noted that when the charge pump circuit 100 and the buck circuit 200 are operating in different modes, the magnitude of the converted output voltage used for output at the third terminal A3 is different.

[0035] In this embodiment, the control electrode of the eleventh transistor SA1, the control electrode of the twelfth transistor SA2, and the control electrode of the thirteenth transistor SB are respectively used to receive corresponding on / off control signals. The on / off control signals are respectively used to control the on and off states of the eleventh transistor SA1, the twelfth transistor SA2, and the thirteenth transistor SB.

[0036] Please continue reading Figure 1 As shown, the voltage conversion circuit provided in this embodiment includes a fourth capacitor CIN, a fifth capacitor CMID, and a sixth capacitor COUT; wherein, the first terminal of the fourth capacitor CIN is connected to the first terminal of the first transistor S1, the second terminal of the twelfth transistor SA2, the second terminal of the fifth transistor S5, and the second terminal of the eighth transistor S8, respectively, and the second terminal of the fourth capacitor CIN is grounded; the fourth capacitor CIN is used to convert the input voltage V IN It performs voltage regulation to ensure the input voltage V IN The stability of the fifth capacitor CMID is ensured. The first terminal of the fifth capacitor CMID is connected to the second terminal of the fourth transistor S4 and the second terminal of the eleventh transistor S11, while the second terminal of the fifth capacitor CMID is grounded. The fifth capacitor CMID is used to stabilize the intermediate voltage V. MID The sixth capacitor COUT serves to stabilize the output voltage VOUT, thereby ensuring the stability of the intermediate voltage VMID. The first terminal of the sixth capacitor COUT is connected to the second terminal of the inductor L, and the second terminal of the sixth capacitor COUT is grounded. The sixth capacitor COUT is used to stabilize the output voltage VOUT, thus ensuring the stability of the output voltage VOUT, which includes the aforementioned first and second output voltages.

[0037] In one embodiment of this application, when the voltage conversion circuit 100 operates in the first voltage conversion mode, the charge pump circuit 100 does not operate, and only the buck circuit 200 operates to convert the input voltage V. IN The purpose of stepping down the voltage is that the voltage conversion circuit is now a Buck circuit, outputting the first output voltage after conversion.

[0038] Figure 2 For a schematic diagram of the operation of the voltage conversion circuit provided in the embodiments of this application in the first voltage conversion mode, please refer to [link / reference]. Figure 2 As shown, specifically, in this embodiment, when the voltage conversion circuit operates in the first voltage conversion mode, in any first operating cycle: the control terminals of the first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, the seventh transistor S7, the eighth transistor S8, and the eleventh transistor SA1 are all used to receive a first shutdown control signal. The first shutdown control signal is used to control the first transistor S1, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, the sixth transistor S6, the seventh transistor S7, the eighth transistor S8, and the eleventh transistor SA1 to be in a shutdown state in the first operating cycle.

[0039] Figure 3 For a schematic diagram of the control signal waveform of the voltage conversion circuit provided in the embodiments of this application in the first voltage conversion mode, please refer to [link / reference]. Figure 3 As shown, Figure 3 V in g_SA2 This diagram illustrates the control voltage signal waveform on the gate of the twelfth transistor SA2, where V... g_SA2 When V is high, it indicates that the twelfth transistor SA2 is in the on state during this stage. g_SA2 When the level is low, it indicates that the twelfth transistor SA2 is in the off state during this stage. Figure 3 V in g_SB This diagram illustrates the control voltage signal waveform on the gate of the thirteenth transistor SB, where V... g_SB When V is high, it indicates that the thirteenth transistor SB is in the on state during this stage. g_SB When the level is low, it indicates that the thirteenth transistor SB is in the off state during this stage. Figure 3 I in L This indicates the trend of change in the inductor current on inductor L.

[0040] Figure 4 it is one of the working mode schematic diagrams of the voltage conversion circuit provided by the embodiment of the present application in the first voltage conversion mode, please refer to Figure 3 and Figure 4 as shown, in the first phase of the first working cycle, the control electrode of the twelfth transistor SA2 is configured to receive a second turn-on control signal, and the second turn-on control signal is configured to control the twelfth transistor SA2 to be in a conducting state in the first phase of the first working cycle; the control electrode of the thirteenth transistor SB is configured to receive a second turn-off control signal, and the second turn-off control signal is configured to control the thirteenth transistor SB to be in an off state in the first phase of the first working cycle. At this time, when the twelfth transistor SA2 is conducted and the thirteenth transistor SB is off, the input voltage V on the voltage input terminal A1 IN transfers energy to the third terminal A3 through the inductor L, so as to obtain the output voltage VOUT at the third terminal A3. At this time, the inductor L is excited, and the excitation voltage is (Vin-Vout), where Vin is the voltage value of the input voltage VIN, and Vout is the voltage value of the output voltage VOUT.

[0041] Figure 5 it is the second schematic diagram of working modes of the voltage conversion circuit provided by the embodiment of the present application in the first voltage conversion mode; please refer to Figure 4 and Figure 5 as shown, in the second phase of the first working cycle, the control electrode of the twelfth transistor SA2 is configured to receive a third turn-off control signal, and the third turn-off control signal is configured to control the twelfth transistor SA2 to be in an off state in the second phase of the first working cycle; the control electrode of the thirteenth transistor SB is configured to receive a third turn-on control signal, and the third turn-on control signal is configured to control the thirteenth transistor SB to be in a conducting state in the second phase of the first working cycle. At this time, when the twelfth transistor SA2 is off and the thirteenth transistor SB is conducted, the inductor L is in a demagnetization state, and the magnitude of the demagnetization voltage is Vout.

[0042] wherein, in this embodiment, the on-off control signals include the aforementioned first turn-off control signal, the second turn-off control signal, the third turn-off control signal, the second turn-on control signal and the third turn-on control signal.

[0043] wherein, in the first voltage conversion mode of the voltage conversion circuit, let the duration of one first working cycle be Ts, the excitation time of the inductor L be Ton, the demagnetization time of the inductor L be Toff, and the duty ratio be D1 (0<D1<1), the following formula (1) can be obtained from the working mode of the first voltage conversion mode: (1) From the volt-second balance of the inductor, the following formula (2) can be obtained: (2) The voltage gain in the first voltage conversion mode is:

[0044] in, .

[0045] As can be seen from the voltage gain formula, the first voltage conversion mode can achieve step-down output by adjusting the duty cycle D1.

[0046] It can be seen that when the voltage conversion circuit 100 is working in the first voltage conversion mode, the voltage conversion circuit is a Buck circuit, which converts the input voltage VIN into the first output voltage.

[0047] Figure 6 For a schematic diagram of the control signal waveform of the voltage conversion circuit operating in the second voltage conversion mode provided in the embodiments of this application, please refer to [link / reference]. Figure 6 As shown, Figure 6 V in g_S4 V g_S5 and V g_S8 The diagrams show the waveforms of the control voltages on the gates of the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8, respectively. When V... g_S4 V g_S5 and V g_S8 When V is high, it indicates that the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 are in the on state during this stage. g_S4 V g_S5 and V g_S8 When the level is low, it indicates that the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 are in the off state during this stage. Figure 6 V in g_S1 V g_S6 and V g_S7 The diagrams show the waveforms of the control voltages on the gates of the first transistor S1, the sixth transistor S6, and the seventh transistor S7, respectively. When V... g_S1 V g_S6 and V g_S7 When V is high, it indicates that the first transistor S1, the sixth transistor S6, and the seventh transistor S7 are in the on state during this stage. g_S1 V g_S6 and V g_S7 When the level is low, it indicates that the first transistor S1, the sixth transistor S6, and the seventh transistor S7 are in the off state during this stage. Figure 6 The diagram shows the change in the input voltage VIN. As can be seen, in this embodiment, the input voltage VIN remains stable. Figure 6 V in CF1 V CF2 and V CF3 The diagrams show the voltage waveforms across the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3, respectively. It can be seen that under the current second voltage conversion mode, the voltages across the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3 are equal and stable. Figure 6 V in MID This diagram shows the voltage waveform of the intermediate voltage VMID. It can be seen that in the current second voltage conversion mode, the intermediate voltage V... MID The voltage remains stable throughout.

[0048] It should be noted that the charge pump circuit 100 and the step-down voltage 200 in the voltage conversion circuit provided in this embodiment can work independently, and their working cycles do not need to be synchronized. The following descriptions illustrate the operation of the charge pump circuit 100 and the step-down voltage 200 in different modes.

[0049] When the voltage conversion circuit operates in the second voltage conversion mode, during each second operating cycle of the charge pump circuit 100, the control electrode of the second transistor S2 and the control electrode of the third transistor S3 are both used to receive a fourth conduction control signal. The fourth conduction control signal is used to control the second transistor S2 and the third transistor S3 to be in the conduction state during the second operating cycle.

[0050] Figure 7 For one of the operating mode diagrams of the voltage conversion circuit in the second voltage conversion mode provided in the embodiments of this application, please refer to [link / reference]. Figure 7 As shown, in the first stage of the second working cycle under the second voltage conversion mode, the control terminals of the first transistor S1, the sixth transistor S6, and the seventh transistor S7 are all used to receive a fifth turn-on control signal. The fifth turn-on control signal is used to control the first transistor S1, the sixth transistor S6, and the seventh transistor S7 to be in the turn-on state during the first stage of the second working cycle. The control terminals of the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 are all used to receive a fifth turn-off control signal. The fifth turn-off control signal is used to control the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 to be in the turn-off state during the first stage of the second working cycle.

[0051] In the first stage of the second operating cycle under the second voltage conversion mode, the second transistor S2, the third transistor S3, the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 are all in the on state, as are the first transistor S1, the sixth transistor S6, and the seventh transistor S7. The input voltage VIN transfers energy to the intermediate voltage node A2 through the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3, as shown in the following formula:

[0052]

[0053]

[0054] Where Vin is the input voltage VIN. The voltage value of the intermediate voltage VMID, V CF1 V is the voltage across the first capacitor CF1. CF2 V is the voltage across the second capacitor CF2. CF3 This is the voltage value across the third capacitor CF3.

[0055] Figure 8 This is the second schematic diagram of the operating mode of the voltage conversion circuit in the second voltage conversion mode provided in the embodiments of this application. Please refer to [link / reference]. Figure 6 and Figure 8 As shown, in the second stage of the second working cycle, the control terminals of the first transistor S1, the sixth transistor S6, and the seventh transistor S7 are all used to receive a sixth turn-off control signal. The sixth turn-off control signal is used to control the first transistor S1, the sixth transistor S6, and the seventh transistor S7 to be in the turn-off state during the second stage of the second working cycle. The control terminals of the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 are all used to receive a sixth turn-on control signal. The sixth turn-on control signal is used to control the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 to be in the turn-on state during the first stage of the second working cycle.

[0056] Please see the figure. Figure 8 As shown, in the second stage of the second working cycle, the second transistor S2, the third transistor S3, the first transistor S1, the sixth transistor S6, and the seventh transistor S7 are all turned on, while the fourth transistor S4, the fifth transistor S5, and the eighth transistor S8 are all turned off; the input voltage VIN charges the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3, resulting in:

[0057] By combining the above two equations, we can obtain:

[0058] It can be seen that when the voltage conversion circuit operates in the second voltage conversion mode, it can be regarded as a hybrid of a 1:2 charge pump circuit 100 and a step-down circuit 200. The two circuits operate independently of each other and can be analyzed separately; the thirteenth transistor SB remains off, the second transistor S2 and the third transistor S3 in the preceding-stage charge pump circuit 100 remain continuously on, and the fourth transistor S4, the fifth transistor S5, the eighth transistor S8, the first transistor S1, the sixth transistor S6, and the seventh transistor S7 are alternately turned on with a duty cycle of 0.5.

[0059] Figure 9 is an equivalent circuit diagram of the voltage conversion circuit provided in the embodiment of the present application in the second voltage conversion mode, please refer to Figure 9 , assuming that the duty cycle of the eleventh transistor SA1 is D2 (0<D2<1) and the duty cycle of the twelfth transistor SA2 is 1-D2, the converter gain can be obtained according to volt-second balance as:

[0060] It can be known from the voltage gain formula that the voltage conversion circuit can achieve Vin<Vout<2Vin by adjusting the duty cycle D2 in the second voltage conversion mode.

[0061] wherein, the on-off control signals in this embodiment include the above-mentioned fourth turn-on control signal, the fifth turn-on control signal, the sixth turn-on control signal, the fifth turn-off control signal, and the sixth turn-off control signal.

[0062] Figure 10 is a schematic waveform diagram of control signals when the voltage conversion circuit provided in the embodiment of the present application operates in the third voltage conversion mode, please refer to FIG. 10, Figure 10 V in g_S1 , V g_S3 and V g_S5 respectively represent the waveform diagrams of the control voltages on the gates of the first transistor S1, the third transistor S3, and the fifth transistor S5, wherein when V g_S1 , V g_S3 and V g_S5 are at a high level, it indicates that the first transistor S1, the third transistor S3, and the fifth transistor S5 are controlled to be in a conducting state during this stage, and when V g_S1 , V g_S3 and V g_S5 are at a low level, it indicates that the first transistor S1, the third transistor S3, and the fifth transistor S5 are controlled to be in an off state during this stage. Figure 10 V ing_S2 V g_S4 V g_S6 and V g_S8 The diagrams show the waveforms of the control voltages on the gates of the second transistor S2, the fourth transistor S4, and the eighth transistor S8, respectively. When V... g_S2 V g_S4 V g_S6 and V g_S8 When V is high, it indicates that the second transistor S2, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 are in the on state during this stage. g_S2 V g_S4 V g_S6 and V g_S8 When the level is low, it indicates that the second transistor S2, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 are in the off state during this stage. Figure 10 The diagram shows the change in the input voltage VIN. As can be seen, in this embodiment, the input voltage VIN remains stable. Figure 10 V in CF1 V CF2 and V CF3 The diagrams show the voltage waveforms across the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3, respectively. It can be seen that under the current third voltage conversion mode, the voltages across the first capacitor CF1, the second capacitor CF2, and the third capacitor CF3 are equal and remain stable. Figure 10 V in MID The diagram shows the voltage waveform of the intermediate voltage VMID. It can be seen that the voltage of the intermediate voltage VMID remains stable under the current second voltage conversion mode.

[0063] Figure 11 This is one of the schematic diagrams showing the voltage conversion circuit provided in the embodiments of this application operating in the third voltage conversion mode. Please refer to [link / reference]. Figure 10 and Figure 11As shown, when the voltage conversion circuit operates in the third voltage conversion mode: in the first stage of each third operating cycle of the charge pump circuit, the control terminals of the first transistor S1, the third transistor S3, the fifth transistor S5, and the seventh transistor S7 are all used to receive a seventh turn-on control signal. The seventh turn-on control signal is used to control the first transistor S1, the third transistor S3, the fifth transistor S5, and the seventh transistor S7 to be in the turn-on state in the first stage of the third operating cycle; the control terminals of the second transistor S4, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 are all used to receive a seventh turn-off control signal. The seventh turn-off control signal is used to control the second transistor S2, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 to be in the turn-off state in the first stage of the third operating cycle.

[0064] Please see Figure 11 As shown, when the voltage conversion circuit operates in the first stage of the third voltage conversion mode, the first transistor S1, the third transistor S3, the fifth transistor S5, and the seventh transistor S7 are all in the on state, while the second transistor S2, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 are all in the off state; according to the equivalent circuit... Figure 12 We can obtain:

[0065] Figure 12 This is the second schematic diagram showing the voltage conversion circuit provided in the embodiments of this application operating in the third voltage conversion mode. Please refer to [link / reference]. Figure 10 and Figure 12 As shown, in the second stage of the third working cycle, the control terminals of the first transistor S1, the third transistor S3, the fifth transistor S5, and the seventh transistor S7 are all used to receive an eighth turn-off control signal. The eighth turn-off control signal is used to control the first transistor S1, the third transistor S3, the fifth transistor S5, and the seventh transistor S7 to be in the turn-off state during the second stage of the third working cycle. The control terminals of the second transistor S2, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 are all used to receive an eighth turn-on control signal. The eighth turn-on control signal is used to control the second transistor S2, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 to be in the turn-on state during the second stage of the third working cycle.

[0066] Please see Figure 12 As shown, when the voltage conversion circuit operates in the second phase of the third voltage conversion mode, the second transistor S2, the fourth transistor S4, the sixth transistor S6, and the eighth transistor S8 are all in an on state, and the first transistor S1, the third transistor S3, the fifth transistor S5, and the seventh transistor S7 are all in an off state.

[0067] Figure 13 is a schematic diagram of an equivalent circuit when the voltage conversion circuit provided in the embodiment of the present application operates in the third voltage conversion mode, please refer to Figure 13 shown, it can be obtained from the equivalent circuit diagram that:

[0068] Simultaneously solving the two equations gives:

[0069] It can be obtained from this Figure 13 the equivalent circuit diagram in the third voltage conversion mode shown, let the duty cycle of the eleventh transistor SA1 be D3 (0<D3<1), and the duty cycle of the twelfth transistor SA2 be (1-D3). According to volt-second balance, the converter gain can be obtained as:

[0070] It can be known from the voltage gain formula that when the voltage conversion circuit operates in the third voltage conversion mode, adjusting the duty cycle D3 can achieve Vin<Vout<4Vin.

[0071] The above describes part of the operating modes of the voltage conversion circuit provided by the present application. In the second voltage conversion mode and the third voltage conversion mode, the eleventh transistor SA1 and the thirteenth transistor SB can also form the upper and lower tubes of a traditional Buck circuit. Similarly, assuming that the duty cycles of the second voltage conversion mode and the third voltage conversion mode are D2 and D3 respectively, it is easy to obtain that the voltage gains in the second voltage conversion mode and the third voltage conversion mode are 2*D2 and 4*D3 respectively.

[0072] In one embodiment of the present application, the on-off control signal includes the seventh turn-on control signal, the eighth turn-on control signal, the seventh turn-off control signal, and the eighth turn-off control signal.

[0073] In one embodiment of the present application, when the voltage conversion circuit operates in the second voltage conversion mode or the third voltage conversion mode, within each fourth operating cycle of the buck circuit: The control electrode of the thirteenth transistor SB is configured to receive a ninth turn-off control signal, and the ninth turn-off control signal is configured to control the thirteenth transistor SB to be in an off state within the fourth operating cycle.

[0074] In the first stage of each fourth cycle of the buck circuit 200, the control electrode of the eleventh transistor SA1 is used to receive the tenth turn-on control signal, which is used to control the eleventh transistor SA1 to be in the turn-on state in the first stage of the fourth cycle; the control electrode of the twelfth transistor SA2 is used to receive the tenth turn-off control signal, which is used to control the twelfth transistor SA2 to be in the turn-off state in the first stage of the fourth cycle.

[0075] In the second phase of each fourth cycle of the operation of the buck circuit 200, the control electrode of the eleventh transistor SA1 is used to receive an eleventh turn-off control signal, which is used to control the eleventh transistor SA1 to be in a turn-off state in the second phase of the fourth cycle; the control electrode of the twelfth transistor SA2 is used to receive an eleventh turn-on control signal, which is used to control the twelfth transistor SA2 to be in a turn-on state in the second phase of the fourth cycle.

[0076] In one embodiment of this application, the on / off control signal includes the aforementioned ninth off control signal, tenth off control signal, eleventh off control signal, tenth on control signal, and eleventh on control signal.

[0077] Analysis of the above embodiments reveals that the voltage conversion circuit provided in this application, composed of a charge pump circuit 100 and a step-down circuit 200, has the following advantages compared to voltage conversion circuits in related technologies: In terms of closed-loop control, the hybrid buck voltage conversion circuit provided in this application only needs to perform voltage closed-loop regulation on the subsequent buck stage. Its control structure is simple, and the system small-signal model does not include the right half-plane zero, thereby avoiding the inherent phase margin limitation problem in traditional buck-boost topologies. This is beneficial to improving the control loop bandwidth and system dynamic response performance, and simplifies the design of the compensation network.

[0078] Regarding device stress and switching losses, this application can significantly reduce voltage stress on power switching devices by selecting appropriate operating modes according to different output voltage levels. Based on this, the overlap area between voltage and current during switching is effectively reduced, thereby significantly reducing switching losses and improving overall conversion efficiency under high-frequency operating conditions.

[0079] In terms of electromagnetic compatibility performance, since the voltage jump amplitude of the power switching node in the voltage conversion circuit provided in this application is small, its dv / dt level is significantly lower than that of the traditional Buck-Boost converter, thereby effectively suppressing high-frequency parasitic oscillations and electromagnetic radiation, which is beneficial to improving the electromagnetic interference characteristics of the system and reducing the design difficulty of input and output filters.

[0080] In terms of output characteristics, this application connects the inductor directly to the output terminal, so that the output current remains continuous, improves the power quality on the load side, and helps to improve system stability and load transient response performance.

[0081] This application also provides a chip that includes the voltage conversion circuit provided in the above embodiments.

[0082] This application also provides an electronic device, which includes the voltage conversion circuit provided in the above embodiments; or the electronic device includes the chip provided in the above embodiments.

[0083] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A voltage conversion circuit, characterized in that, The voltage conversion circuit includes a charge pump circuit and a step-down circuit. The first terminal of the charge pump circuit is electrically connected to the first terminal of the step-down circuit, and the second terminal of the charge pump circuit is connected to the second terminal of the step-down circuit. The first terminal of the charge pump circuit is used to receive the input voltage, the charge pump circuit is used to boost the input voltage to obtain an intermediate voltage, and the second terminal of the charge pump circuit is used to output the intermediate voltage. The first terminal of the step-down circuit is used to receive the input voltage. The step-down circuit is used to step down the input voltage to obtain a first output voltage, so that the third terminal of the step-down circuit outputs the first output voltage. Alternatively, the first terminal of the step-down circuit is used to receive the input voltage, the second terminal of the step-down circuit is used to receive the intermediate voltage, the step-down circuit is used to receive the input voltage and the intermediate voltage, and perform step-down processing to obtain a second output voltage, and the third terminal of the step-down circuit is used to output the second output voltage; the second output voltage is greater than the input voltage and less than the intermediate voltage.

2. The voltage conversion circuit according to claim 1, characterized in that, The charge pump circuit includes a first capacitor, a second capacitor, a third capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first terminal of the first transistor is connected to the second terminal of the fifth transistor and the second terminal of the eighth transistor, respectively. The first terminal of the first transistor, the second terminal of the fifth transistor, and the second terminal of the eighth transistor together form the first terminal of the charge pump circuit. The first terminal of the eighth transistor is connected to the first terminal of the first capacitor, the first terminal of the third capacitor, and the second terminal of the seventh transistor, respectively, and the first terminal of the seventh transistor is grounded; the second terminal of the first capacitor is connected to the second terminal of the first transistor and the first terminal of the second transistor, respectively; the second terminal of the third capacitor is connected to the second terminal of the third transistor and the first terminal of the fourth transistor, and the second terminal of the fourth transistor is the second terminal of the charge pump circuit; The first terminal of the fifth transistor is connected to the second terminal of the sixth transistor and the first terminal of the second capacitor, respectively. The first terminal of the sixth transistor is grounded, and the second terminal of the second capacitor is connected to the second terminal of the second transistor and the first terminal of the third transistor, respectively. The control terminals of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are used to receive corresponding on / off control signals, which are used to control the on and off states of the corresponding transistors.

3. The voltage conversion circuit according to claim 2, characterized in that, The step-down circuit includes an eleventh transistor, a twelfth transistor, a thirteenth transistor, and an inductor; The first terminal of the twelfth transistor is the first terminal of the buck circuit. The first terminal of the twelfth transistor is connected to the first terminal of the first transistor, the second terminal of the fifth transistor, and the second terminal of the eighth transistor. The second terminal of the twelfth transistor is connected to the second terminal of the thirteenth transistor, the first terminal of the eleventh transistor, and the first terminal of the inductor. The first terminal of the thirteenth transistor is grounded. The second terminal of the eleventh transistor is connected to the second terminal of the fourth transistor. The second terminal of the eleventh transistor is the second terminal of the buck circuit. The second terminal of the inductor is the third terminal of the buck circuit. The control terminals of the eleventh transistor, the twelfth transistor, and the thirteenth transistor are respectively used to receive corresponding on / off control signals, which are used to control the on and off states of the corresponding transistors.

4. The voltage conversion circuit according to claim 3, characterized in that, The voltage conversion circuit includes a fourth capacitor, a fifth capacitor, and a sixth capacitor; The first terminal of the fourth capacitor is connected to the first terminal of the first transistor, the second terminal of the twelfth transistor, the second terminal of the fifth transistor, and the second terminal of the eighth transistor, respectively, and the second terminal of the fourth capacitor is grounded. The first terminal of the fifth capacitor is connected to the second terminal of the fourth transistor and the second terminal of the eleventh transistor, respectively, and the second terminal of the fifth capacitor is grounded. The first terminal of the sixth capacitor is connected to the second terminal of the inductor, and the second terminal of the sixth capacitor is grounded.

5. The voltage conversion circuit according to claim 4, characterized in that, When the voltage conversion circuit operates in the first voltage conversion mode, within any first operating cycle: The control terminals of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the eleventh transistor are all used to receive a first shutdown control signal. The first shutdown control signal is used to control the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, and the eleventh transistor to be in a shutdown state during the first working cycle. In the first stage of the first working cycle, the control electrode of the twelfth transistor is used to receive a second conduction control signal, which is used to control the twelfth transistor to be in the conduction state in the first stage of the first working cycle; the control electrode of the thirteenth transistor is used to receive a second turn-off control signal, which is used to control the thirteenth transistor to be in the turn-off state in the first stage of the first working cycle. In the second phase of the first working cycle, the control electrode of the twelfth transistor is used to receive a third turn-off control signal, which is used to control the twelfth transistor to be in a turn-off state in the second phase of the first working cycle; the control electrode of the thirteenth transistor is used to receive a third turn-on control signal, which is used to control the thirteenth transistor to be in a turn-on state in the second phase of the first working cycle. The on / off control signal includes the first off control signal, the second off control signal, the third off control signal, the second on control signal, and the third on control signal.

6. The voltage conversion circuit according to claim 4, characterized in that, When the voltage conversion circuit operates in the second voltage conversion mode: During each second operating cycle of the charge pump circuit, the control electrode of the second transistor and the control electrode of the third transistor are both used to receive a fourth conduction control signal, which is used to control the second transistor and the third transistor to be in the conduction state during the second operating cycle. In the first phase of the second operating cycle, the control electrodes of the first transistor, the sixth transistor, and the seventh transistor are all used to receive a fifth turn-on control signal. The fifth turn-on control signal is used to control the first transistor, the sixth transistor, and the seventh transistor to be in the turn-on state during the first phase of the second operating cycle. The control electrodes of the fourth transistor, the fifth transistor, and the eighth transistor are all used to receive a fifth turn-off control signal. The fifth turn-off control signal is used to control the fourth transistor, the fifth transistor, and the eighth transistor to be in the turn-off state during the first phase of the second operating cycle. In the second phase of the second operating cycle, the control electrodes of the first transistor, the sixth transistor, and the seventh transistor are all used to receive a sixth turn-off control signal. The sixth turn-off control signal is used to control the first transistor, the sixth transistor, and the seventh transistor to be in a turn-off state during the second phase of the second operating cycle. The control electrodes of the fourth transistor, the fifth transistor, and the eighth transistor are all used to receive a sixth turn-on control signal. The sixth turn-on control signal is used to control the fourth transistor, the fifth transistor, and the eighth transistor to be in a turn-on state during the first phase of the second operating cycle. The on / off control signals include the fourth on control signal, the fifth on control signal, the sixth on control signal, the fifth off control signal, and the sixth off control signal.

7. The voltage conversion circuit according to claim 4, characterized in that, When the voltage conversion circuit operates in the third voltage conversion mode: In the first phase of each third operating cycle of the charge pump circuit, the control terminals of the first transistor, the third transistor, the fifth transistor, and the seventh transistor are all used to receive a seventh turn-on control signal. The seventh turn-on control signal is used to control the first transistor, the third transistor, the fifth transistor, and the seventh transistor to be in the turn-on state during the first phase of the third operating cycle. The control terminals of the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are all used to receive a seventh turn-off control signal. The seventh turn-off control signal is used to control the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor to be in the turn-off state during the first phase of the third operating cycle. In the second phase of the third operating cycle, the control electrodes of the first transistor, the third transistor, the fifth transistor, and the seventh transistor are all used to receive an eighth turn-off control signal. The eighth turn-off control signal is used to control the first transistor, the third transistor, the fifth transistor, and the seventh transistor to be in a turn-off state during the second phase of the third operating cycle. The control electrodes of the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor are all used to receive an eighth turn-on control signal. The eighth turn-on control signal is used to control the second transistor, the fourth transistor, the sixth transistor, and the eighth transistor to be in a turn-on state during the second phase of the third operating cycle. The on / off control signals include the seventh on control signal, the eighth on control signal, the seventh off control signal, and the eighth off control signal.

8. The voltage conversion circuit according to claim 6 or 7, characterized in that, When the voltage conversion circuit operates in the second voltage conversion mode or the third voltage conversion mode, during each fourth operating cycle of the buck circuit: The control electrode of the thirteenth transistor is used to receive the ninth turn-off control signal, which is used to control the thirteenth transistor to be in the off state during the fourth working cycle. In the first stage of each fourth cycle of the buck circuit, the control electrode of the eleventh transistor is used to receive a tenth turn-on control signal, which is used to control the eleventh transistor to be in the turn-on state in the first stage of the fourth cycle; the control electrode of the twelfth transistor is used to receive a tenth turn-off control signal, which is used to control the twelfth transistor to be in the turn-off state in the first stage of the fourth cycle. In the second phase of each fourth cycle of the buck circuit, the control electrode of the eleventh transistor is used to receive an eleventh turn-off control signal, which is used to control the eleventh transistor to be in the off state in the second phase of the fourth cycle; the control electrode of the twelfth transistor is used to receive an eleventh turn-on control signal, which is used to control the twelfth transistor to be in the turn-on state in the second phase of the fourth cycle. The on / off control signals include the ninth off control signal, the tenth off control signal, the eleventh off control signal, the tenth on control signal, and the eleventh on control signal.

9. A chip, characterized in that, The chip includes the voltage conversion circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, The electronic device includes the voltage conversion circuit as described in any one of claims 1-8; or the electronic device includes the chip as described in claim 9.

Images