A bootstrap power supply circuit suitable for multi-level and hybrid power converters

Abstract

This invention proposes a bootstrap power supply circuit suitable for multi-level and hybrid power converters, including a charge pump circuit, a charge pump drive circuit, and a clock control circuit. The charge pump drive circuit includes first and second drive circuits. The charge pump circuit includes first to fourth switches, two storage capacitors, and a bootstrap capacitor. The first switch is connected to the first and fifth nodes, the second switch is connected to the first and sixth nodes, the third switch is connected to the fourth and fifth nodes, and the fourth switch is connected to the fourth and sixth nodes. The first storage capacitor is connected to the second and fifth nodes, and the second storage capacitor is connected to the third and sixth nodes. The bootstrap capacitor is connected to the first and fourth nodes, with the first node connected to a floating high potential and the fourth node connected to a floating low potential. The output of the first drive circuit is connected to the second node, and the output of the second drive circuit is connected to the third node. By controlling the on / off state of the switches, the two storage capacitors are alternately charged and discharged to charge the bootstrap capacitor. This invention achieves independent power supply for each floating domain, reduces the bootstrap capacitor, and saves area.

Description

Technical Field

[0001] This invention relates to the field of power management technology, and in particular to a bootstrap power supply circuit suitable for multi-level and hybrid power converters. Background Technology

[0002] With the development of integrated circuits and power management technology, multilevel and hybrid power converters are widely used in various high-power-density power supply scenarios because they can effectively reduce the voltage stress on power devices and improve converter efficiency. Taking a typical three-level flying capacitor converter as an example, all switches are usually implemented using N-type switches. The three-level converter contains two phase-interleaved control drive signals, both with the same switching frequency and pulse width, and a fixed 180° phase difference. In this topology, the floating switch node of the high-side power switch is in a state of long-term floating at a non-zero voltage. If the high-side power switch is directly driven by a low-voltage power supply, the bootstrap capacitor will not be able to charge because the floating switch node lacks a discharge path to ground, resulting in high-side drive failure.

[0003] To drive multiple high-side power transistors operating in a floating voltage domain, the industry commonly employs a stacked power supply architecture using cascaded diodes and bootstrap capacitors. However, with the increase in the number of converter stages and the growing demand for conversion efficiency, this stacked power supply scheme exhibits insurmountable system-level drawbacks: First, cascaded structures suffer from low charge transfer efficiency and severe voltage drops. In a stacked architecture, energy is typically transferred stepwise from low-voltage domains to high-voltage domains. Since each stage requires a bootstrap diode, the forward voltage drop of the diode accumulates with the increase in the number of cascaded layers. After multiple stages of stacking, the actual supply voltage obtained by the highest-level drive circuit will be significantly lower than the power supply voltage, resulting in insufficient gate-source drive voltage for the high-side power transistors. This increases the on-resistance of the power transistors and may even prevent them from fully turning on, seriously threatening the safety and reliability of the system. Secondly, in the stacked power supply logic, the bootstrap capacitor in the low-voltage domain not only needs to support the power consumption of its own drive circuit, but also must supply power to the bootstrap capacitor in the high-voltage domain. The capacitance value of the bootstrap capacitor in the low-voltage domain needs to increase exponentially to keep the voltage ripple within a reasonable range. In integrated circuit design, large-value capacitors occupy a huge amount of layout area, significantly increasing the cost of bare dies. For power management chips that need to be integrated on-chip, the area problem caused by this cascaded structure limits the possibility of converters evolving towards higher density and more layers. As converter systems evolve towards higher-order multilevel converters, the charge loss and area caused by this stacked architecture increase exponentially. The area of ​​the bottom bootstrap capacitor becomes completely insufficient for single-chip integration, while the high-side switches completely lose their effective driving capability due to accumulated voltage drops. Therefore, traditional cascaded bootstrap solutions face the dual failures of physical layout limitations and electrical driving capability in higher-order topologies, completely losing their technical feasibility and downstream expansion potential. Summary of the Invention

[0004] In view of the above situation, the main objective of the present invention is to provide a bootstrap power supply circuit suitable for multi-level and hybrid power converters to solve the above-mentioned technical problems.

[0005] This invention proposes a bootstrap power supply circuit suitable for multilevel and hybrid power converters, including a charge pump circuit, a charge pump drive circuit, and a clock control circuit; The charge pump drive circuit includes a first charge pump drive circuit and a second charge pump drive circuit. The charge pump circuit includes a first switch, a second switch, a third switch, a fourth switch, a first storage capacitor, a second storage capacitor, and a bootstrap capacitor; The first switch is connected between the first node and the fifth node, the second switch is connected between the first node and the sixth node, the third switch is connected between the fourth node and the fifth node, the fourth switch is connected between the fourth node and the sixth node, the first storage capacitor is connected between the second node and the fifth node, and the second storage capacitor is connected between the third node and the sixth node. The bootstrap capacitor is connected between the first node and the fourth node. The first node is used to connect to the high potential end of the floating voltage domain of the power switch in the power converter, and the fourth node is used to connect to the low potential end of the floating voltage domain of the power switch. The output of the first charge pump drive circuit is connected to the second node, and the output of the second charge pump drive circuit is connected to the third node. By controlling the on / off state of each switch, the charge pump circuit can achieve alternating charging and discharging of the first and second storage capacitors to charge the bootstrap capacitor.

[0006] Furthermore, the first charge pump drive circuit is provided with a fifth switch and a sixth switch, and the second charge pump drive circuit is provided with a seventh switch and an eighth switch; the fifth switch is connected between the power supply voltage terminal of the drive circuit and the second node, the sixth switch is connected between the second node and the ground terminal; the seventh switch is connected between the power supply voltage terminal and the third node, and the eighth switch is connected between the third node and the ground terminal.

[0007] Furthermore, the clock control circuit is used to generate a first clock signal and a second clock signal, which are inverses of each other and do not overlap; the first clock signal is used to control the on / off state of the second switch, the third switch, the sixth switch and the seventh switch; the second clock signal is used to control the on / off state of the first switch, the fourth switch, the fifth switch and the eighth switch.

[0008] Furthermore, the power converter is a multi-level or hybrid buck-boost converter; the power switch is a high-side power switch, and the power switch is N-type or P-type.

[0009] Furthermore, the bootstrap power supply circuit has a low-voltage control domain and a floating voltage domain, specifically: The low-voltage control domain uses ground as a reference, the high level of the low-voltage control domain is the power supply voltage terminal, and the low level of the low-voltage control domain is the ground terminal; the clock control circuit and the charge pump drive circuit operate in the low-voltage control domain. In the floating voltage domain: In the floating voltage domain, the voltage at the first node is at a high potential, and the voltage at the fourth node is at a low potential. When the power switch is N-type, the fourth node is connected to the switching node, that is, the source terminal of the power switch. The bootstrap capacitor is connected between the first node and the fourth node, with the upper plate of the bootstrap capacitor connected to the first node and the lower plate connected to the fourth node. When the power switch is P-type, the first node is connected to the switching node. That is, the bootstrap capacitor at the source of the power switch is connected between the first node and the fourth node, and the upper plate of the bootstrap capacitor is connected to the first node and the lower plate is connected to the fourth node.

[0010] Furthermore, it also includes a mode selection circuit; the mode selection circuit is used to receive an externally input mode selection signal, which is used to select the timing when the charge pump circuit charges the bootstrap capacitor; the mode selection signal is a two-bit binary number, and the voltage of the switching node alternates between a first voltage level and a second voltage level, with the second voltage level being higher than the first voltage level, specifically: When the power switching transistor is N-type: When the mode selection signal is in the first state, the control signal is at an effective level when the switching node voltage is at the first voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level. When the mode selection signal is in the second state, the control signal is active when the switching node voltage is at the second voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the second voltage level. When the mode selection signal is in the third state, the control signal is active when the switching node voltage is at the first voltage level and the second voltage level. The charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level and the second voltage level. When the power switching transistor is P-type: When the mode selection signal is in the first state, the control signal is at an effective level when the switching node voltage is at the first voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level. When the mode selection signal is in the second state, the control signal is active when the switching node voltage is at the second voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the second voltage level. When the mode selection signal is in the third state, the control signal is active when the switching node voltage is at the first voltage level and the second voltage level. The charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level and the second voltage level. When the mode selection signal is in the third state, the control signal is active when the switching node voltage is low or high, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is low or high.

[0011] Furthermore, when the charge pump circuit operates in the first phase, the second, third, sixth, and seventh switches are turned on, while the first, fourth, fifth, and eighth switches are turned off. The first storage capacitor is charged, and the second storage capacitor discharges onto the bootstrap capacitor. When the charge pump circuit operates in the second phase, the first, fourth, fifth, and eighth switches are turned on, while the second, third, sixth, and seventh switches are turned off. The second storage capacitor is charged, and the first storage capacitor discharges onto the bootstrap capacitor. The first and second phases operate alternately, causing the first and second storage capacitors to alternately charge the bootstrap capacitor.

[0012] Furthermore, when the voltage at the switching node changes from the first voltage level to the second voltage level, the fifth, sixth, seventh, and eighth switches are all in the off state, cutting off the current path from the fourth node to the power supply voltage terminal and the ground terminal to prevent charge backflow and block the charge loss of the bootstrap capacitor.

[0013] Furthermore, the capacitance values ​​of the first and second storage capacitors are equal, and the withstand voltage values ​​of the first and second storage capacitors are configured to be no less than the switching node voltage; the bootstrap capacitor is an on-chip integrated capacitor or an off-chip capacitor.

[0014] Furthermore, the first charge pump drive circuit and the second charge pump drive circuit are respectively provided with an enable terminal for receiving a mode selection signal; when the mode selection signal received by the enable terminal is at an effective level, the first charge pump drive circuit and the second charge pump drive circuit operate normally; when the mode selection signal received by the enable terminal is at an invalid level, the first charge pump drive circuit and the second charge pump drive circuit stop working, and the output node is in a high impedance state.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The bootstrap power supply circuit proposed in this invention, based on the switching node voltage inside the power converter, controls the timing of the switching transistors to achieve alternating charging and discharging of the storage capacitor in the charge pump, thus charging the bootstrap capacitor. When applied to multi-level or hybrid power converters, this structure, compared to the traditional stacked structure, achieves independent power supply for the floating voltage domain of each power transistor in the converter, reducing the overall size of the bootstrap capacitor, saving chip area, and lowering chip cost.

[0016] 2. This invention, through the combination of mode selection circuit and mode selection signal, can flexibly select the charging timing of the bootstrap capacitor according to the application scenarios of different duty cycles of the multilevel converter, and adapt to multiple working modes in which the switching node voltage is charged in the first voltage level stage, the first voltage level stage, or both voltage level stages, which significantly improves the application flexibility and adaptability of the circuit. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the bootstrap power supply circuit for multi-level and hybrid power converters proposed in this invention. Figure 2 This is a schematic diagram of the charge pump circuit structure of the bootstrap power supply circuit suitable for multi-level and hybrid power converters proposed in this invention. Figure 3 The diagram shows the working principle of the bootstrap capacitor charging in the bootstrap power supply circuit for multi-level and hybrid power converters proposed in this invention. (a) is a schematic diagram of the working principle when the charge pump is in the first working phase, and (b) is a schematic diagram of the working principle when the charge pump is in the second working phase. Figure 4 The diagram shows the working waveform of the bootstrap capacitor charging in the bootstrap power supply circuit for multi-level and hybrid power converters proposed in this invention. (a) is a working waveform diagram when the mode selection signal is 00, (b) is a working waveform diagram when the mode selection signal is 01, and (c) is a working waveform diagram when the mode selection signal is 10. Figure 5This is a schematic diagram of the switch implementation of the charge pump drive circuit for the bootstrap power supply circuit of the proposed invention, which is suitable for multi-level and hybrid power converters. In this diagram, (a) is the implementation of the output stage being a MOS switch, and (b) is the implementation of the output stage being a MOS switch and a diode. Figure 6 This is a schematic diagram comparing the bootstrap power supply circuit proposed in this invention for multi-level and hybrid power converters with the bootstrap capacitor size required by existing technologies. Figure 7 This is a schematic diagram of an improved charge pump circuit for a bootstrap power supply circuit suitable for multi-level and hybrid power converters proposed in this invention. Figure 8 This is a schematic diagram of the multilevel power converter structure to which this invention applies. Detailed Implementation

[0018] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0019] These and other aspects of the embodiments of the present invention will become clear from the following description and accompanying drawings. In these descriptions and drawings, some specific embodiments of the present invention are specifically disclosed to illustrate some ways of implementing the principles of the embodiments of the present invention; however, it should be understood that the scope of the embodiments of the present invention is not limited thereto.

[0020] Please see Figure 1 This invention proposes a bootstrap power supply circuit suitable for multilevel and hybrid power converters, including a charge pump circuit, a clock control circuit, and a drive circuit; the charge pump drive circuit includes a first charge pump drive circuit and a second charge pump drive circuit. The charge pump circuit includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a first storage capacitor CP1, a second storage capacitor CP2, and a bootstrap capacitor CBST. Specifically, the first switch S1 is connected between the VDDH node (first node) and the fifth node N5; the second switch S2 is connected between the VDDH node and the sixth node N6; the third switch S3 is connected between the VSSH node (fourth node) and the fifth node N5; and the fourth switch S4 is connected between the VSSH node and the sixth node N6. The first storage capacitor CP1 is connected between the second node N2 and the fifth node N5; the second storage capacitor CP2 is connected between the third node N3 and the sixth node N6; and the bootstrap capacitor CBST is connected between the VDDH node and the VSSH node. The VDDH node is used to connect to the high potential end of the floating voltage domain of the power switching transistor in the power converter, and the VSSH node is used to connect to the low potential end of the floating voltage domain of the power switching transistor. The output terminal of the first charge pump drive circuit is connected to the second node N2, and the output terminal of the second charge pump drive circuit is connected to the third node N3. By controlling the on / off state of each switch, the charge pump circuit can achieve alternating charging and discharging of the first storage capacitor CP1 and the second storage capacitor CP2 to charge the bootstrap capacitor CBST.

[0021] Preferably, the first charge pump drive circuit includes a fifth switch S5 and a sixth switch S6, and the second charge pump drive circuit includes a seventh switch S7 and an eighth switch S8. The fifth switch S5 is connected between the power supply voltage terminal VDD of the drive circuit and the second node N2, and the sixth switch S6 is connected between the second node N2 and the ground terminal GND; the seventh switch S7 is connected between the power supply voltage terminal VDD and the third node N3, and the eighth switch S8 is connected between the third node N3 and the ground terminal GND.

[0022] The clock control circuit generates a first clock signal CLK1 and a second clock signal CLK2. The first clock signal CLK1 and the second clock signal CLK2 are inversely phase and non-overlapping, with the non-overlapping time being 1 / 20 to 1 / 10 of the clock period. The frequency of the clock signal needs to be considered in conjunction with circuit power consumption, storage capacitor size, and the turn-on voltage of the power switches. Lower clock signal frequencies result in lower circuit power consumption, larger required storage capacitors, and lower turn-on voltages for the power switches; higher clock signal frequencies result in higher circuit power consumption, smaller required storage capacitors, and higher turn-on voltages for the power switches. In some applications, the clock frequency can be 5 to 10 times the switching frequency of the power converter. For example, if the switching frequency of the power converter is 1MHz, the clock signal frequency can be 5 to 10MHz. The first clock signal CLK1 controls the on / off state of the second switch S2, the third switch S3, the sixth switch S6, and the seventh switch S7; the second clock signal CLK2 controls the on / off state of the first switch S1, the fourth switch S4, the fifth switch S5, and the eighth switch S8.

[0023] This invention features a low-voltage control domain and a floating voltage domain. The low-voltage control domain uses ground (GND) as a reference, with a high level at the power supply voltage (VDD) and a low level at ground (GND). The clock control circuit and charge pump drive circuit operate within the low-voltage control domain. In the floating voltage domain, the voltage at the VDDH node is at a high potential, and the voltage at the VSSH node is at a low potential. When the power switch is N-type, the VSSH node is connected to the switching node VSW, i.e., the source terminal of the power switch. The bootstrap capacitor CBST is connected between the VDDH node and the VSSH node, with its upper plate connected to the VDDH node and its lower plate connected to the VSSH node. When the power switch is P-type, the VDDH node is connected to the switching node VSW, i.e., the source terminal of the power switch. The bootstrap capacitor CBST is connected between the VDDH node and the VSSH node, with its upper plate connected to the VDDH node and its lower plate connected to the VSSH node.

[0024] The power converter is a multi-level or hybrid buck-boost converter; the power switch is a high-side power switch, and the power switch is N-type or P-type.

[0025] The invention also includes a mode selection circuit. This circuit receives an externally input mode selection signal SELECT (a two-bit binary number), which selects the timing for the charge pump circuit to charge the bootstrap capacitor CBST. The switching node voltage VSW alternates between a first voltage level VL and a second voltage level VH, with VH being higher than VL.

[0026] The first charge pump drive circuit and the second charge pump drive circuit are each provided with an enable terminal for receiving a mode selection signal. When the mode selection signal received by the enable terminal is an active level (high level), the first charge pump drive circuit and the second charge pump drive circuit operate normally. When the mode selection signal received by the enable terminal is an inactive level (low level), the first charge pump drive circuit and the second charge pump drive circuit stop working, and the output nodes (i.e., the second node N2 and the third node N3) are in a high-impedance state to avoid charge backflow from the floating voltage domain to the low-voltage control domain and to block the charge loss of the bootstrap capacitor.

[0027] The following describes the working process of the present invention in detail, taking into account the different states of the power switch type and the mode selection signal: When the power switch is N-type, the VSSH node is connected to the switching node VSW, the upper plate of the bootstrap capacitor CBST is connected to VDDH, and the lower plate is connected to VSSH. The charge pump circuit needs to raise the VDDH voltage to a level higher than VSW to provide a positive gate-source drive voltage. Before the charge pump operates in positive steady state, the first storage capacitor CP1 and the second storage capacitor CP2 need to be pre-charged. During the pre-charge phase, switches S3, S4, S6, and S8 are turned on, and the first storage capacitor CP1 and the second storage capacitor CP2 are charged by the switch node voltage VSW until the voltage across the storage capacitors CP1 and CP2 is the same as the switch node voltage.

[0028] When the power switch is N-type and the mode selection signal SELECT=00 (first state): In this state, the control signal VCTRL is at an effective high level when the switching node voltage VSW=VL, and the charge pump circuit charges the bootstrap capacitor CBST only during the VSW=VL phase; when VSW jumps to VH, VCTRL becomes an ineffective low level, the charge pump drive circuit stops working, and its output node is in a high-impedance state.

[0029] Please see Figure 3 In (a) of the diagram, during the first operating phase (CLK1 high, CLK2 low), switches S2, S3, S6, and S7 are on, while S1, S4, S5, and S8 are off. The first storage capacitor CP1 is charged (its lower plate is connected to VSSH via N5 and S3, and its upper plate is grounded via N2 and S6). The second storage capacitor CP2 discharges the bootstrap capacitor (its lower plate is connected to VDDH via N6 and S2, and its upper plate is connected to VDD via N3 and S7). Please refer to [link to relevant documentation]. Figure 3 In (b) of the diagram, during the second operating phase (CLK1 is low, CLK2 is high), switches S1, S4, S5, and S8 are turned on, while S2, S3, S6, and S7 are turned off. The second storage capacitor CP2 is charged (the lower plate is connected to VSSH via N6 and S4, and the upper plate is grounded via N3 and S8). The first storage capacitor CP1 discharges the bootstrap capacitor (the lower plate is connected to VDDH via N5 and S1, and the upper plate is connected to VDD via N2 and S5). The first and second phases operate alternately, causing CP1 and CP2 to alternately charge CBST. During VSW=VL, the voltage across CBST continuously rises; when VSW transitions from VL to VH, VCTRL becomes low, and all drive switches (S5~S8) are turned off, cutting off the current path from VSSH and VDDH to VDD and GND, preventing charge backflow. This mode is suitable for applications where the power converter has a small duty cycle and the switching nodes are at the first voltage level for an ample period. When the power switch is N-type and the mode selection signal SELECT=01 (second state): In this state, the control signal VCTRL is effectively high when the switching node voltage VSW=VH, and the charge pump circuit only charges the bootstrap capacitor CBST during the VSW=VH phase. When VSW transitions to VL, VCTRL goes low, and the charge pump drive circuit stops working. The internal two-phase operation of the charge pump circuit is exactly the same as in the first state described above, except that the charging action occurs during VSW=VH. When VSW transitions from VH to VL, VCTRL goes low, all drive switches (S5~S8) are turned off, cutting off the current path from VSSH and VDDH to VDD and GND, preventing charge backflow. This mode is suitable for applications where the power converter has a large duty cycle and the switching node has ample time at the second voltage level. When the power switch is N-type and the mode selection signal SELECT=10 (third state): In this state, the control signal VCTRL is effectively high when the switching node voltage VSW = VL and VH, and only low at the edges where the switching node voltage transitions from VL to VH or from VH to VL. The charge pump circuit charges the bootstrap capacitor CBST throughout the entire VSW cycle (i.e., the VL and VH phases). The two-phase operation of the charge pump circuit is the same as above, and it continues to alternate throughout the entire switching cycle. When VSW transitions from VL to VH and from VH to VL, VCTRL is low, all drive switches (S5~S8) are turned off, cutting off the current path from VSSH and VDDH to VDD and GND, preventing charge backflow. This mode is suitable for applications with medium duty cycles or requiring maximum charging capacity, ensuring that the voltage across CBST remains at a high level at all times.

[0030] Please see Figure 4 (a) in the diagram corresponds to the waveform of the charge pump circuit when the mode selection signal SELECT=00; please refer to [link / reference]. Figure 4 (b) shows the waveform of the charge pump circuit operating when the mode selection signal SELECT=01; please refer to [the diagram]. Figure 4 (c) shows the waveform of the charge pump circuit when the mode selection signal SELECT=10. Here, VCBST is the voltage across the bootstrap capacitor, VC,manx is the maximum charging voltage of the bootstrap capacitor, and VGS,on is the turn-on voltage of the power switch.

[0031] When the power switch is P-type, the VDDH node is connected to the switching node VSW, the upper plate of the bootstrap capacitor CBST is connected to VDDH, and the lower plate is connected to VSSH. The charge pump circuit needs to pull the VSSH voltage down below VSW to provide a negative gate-source voltage.

[0032] Before the charge pump operates in positive steady state, the first storage capacitor CP1 and the second storage capacitor CP2 need to be pre-charged. During the pre-charge phase, switches S1, S2, S5, and S7 are turned on, and the first storage capacitor CP1 and the second storage capacitor CP2 are charged by the switch node voltage VSW until the voltage across the storage capacitors CP1 and CP2 is the same as the switch node voltage minus the power supply voltage.

[0033] When the power switch is P-type and the mode selection signal SELECT=00 (first state): In this state, the control signal VCTRL is at an effective high level when the switching node voltage VSW=VL, and the charge pump circuit charges the bootstrap capacitor CBST only during the VSW=VL phase; when VSW jumps to VH, VCTRL becomes an ineffective low level, the charge pump drive circuit stops working, and its output node is in a high-impedance state.

[0034] In the first operating phase (CLK1 is high, CLK2 is low), switches S2, S3, S6, and S7 are turned on, while S1, S4, S5, and S8 are turned off. The second storage capacitor CP2 is charged (its lower plate is connected to VDDH (i.e., VSW) via N6 and S2, and its upper plate is connected to VDD via N3 and S7). The first storage capacitor CP1 discharges to the bootstrap capacitor (its lower plate is connected to VSSH via N5 and S3, and its upper plate is grounded via N2 and S6). At this time, CBST gains charge, and the voltage across it (VSW - VSSH) increases. In the second operating phase (CLK1 low, CLK2 high), switches S1, S4, S5, and S8 are turned on, while S2, S3, S6, and S7 are turned off. The first storage capacitor CP1 is charged (its lower plate is connected to VDDH (i.e., VSW) via N5 and S1, and its upper plate is connected to VDD via N2 and S5). The second storage capacitor CP2 discharges the bootstrap capacitor (its lower plate is connected to VSSH via N6 and S4, and its upper plate is grounded via N3 and S8). The two phases operate alternately, causing CP1 and CP2 to alternately charge CBST. During VSW=VL, the voltage across CBST gradually rises; when VSW transitions from VL to VH, VCTRL becomes low, and all drive switches (S5~S8) are turned off, cutting off the current path from VSSH and VDDH to VDD and GND, preventing charge backflow.

[0035] When the power switch is P-type and the mode selection signal SELECT=01 (second state): In this state, the control signal VCTRL is effectively high when the switching node voltage VSW=VH, and the charge pump circuit only charges the bootstrap capacitor CBST during the VSW=VH phase. When VSW transitions to VL, VCTRL goes low, and the charge pump drive circuit stops working. The internal two-phase operation of the charge pump circuit is exactly the same as described above (first state), except that the charging action occurs during VSW=VH. When VSW transitions from VH to VL, VCTRL goes low, all drive switches (S5~S8) are turned off, cutting off the current path from VSSH and VDDH to VDD and GND, preventing charge backflow. This mode is suitable for applications where the power converter has a large duty cycle and the switching node has ample time at the second voltage level. When the power switch is P-type and the mode selection signal SELECT=10 (third state): In this state, the control signal VCTRL is effectively high when the switching node voltage VSW = VL and VH, and only low at the edges where the switching node voltage transitions from VL to VH or from VH to VL. The charge pump circuit charges the bootstrap capacitor CBST throughout the entire VSW cycle (i.e., the VL and VH phases). The two-phase operation of the charge pump circuit is the same as above, and it continues to alternate throughout the entire switching cycle. When VSW transitions from VL to VH and from VH to VL, VCTRL is low, all drive switches (S5~S8) are turned off, cutting off the current path from VSSH and VDDH to VDD and GND, preventing charge backflow. This mode is suitable for applications with medium duty cycles or requiring maximum charging capacity, ensuring that the voltage across CBST remains at a high level at all times.

[0036] In the six operating conditions mentioned above, clock signals CLK1 and CLK2 are always kept non-overlapping to prevent the absence of a current path for charging the bootstrap capacitor when both CLK1 and CLK2 are high simultaneously. The non-overlapping time tnov is typically 1 / 20 to 1 / 100 of the clock signal period. For example, if the clock signal frequency is 10MHz, then the non-overlapping time tnov can be 1 to 5ns.

[0037] When the fourth node (VSSH) transitions from the first voltage level to the second voltage level or from the second voltage level to the first voltage level (for an N-type transistor), and when the first node (VDDH) transitions from the first voltage level to the second voltage level or from the second voltage level to the first voltage level (for a P-type transistor), switches S5, S6, S7, and S8 are all in the off state, cutting off the current path from the high-voltage floating node to the power supply voltage terminal VDD and the ground terminal GND to prevent charge backflow and block the charge loss of the bootstrap capacitor. The transistor-level implementation of the charge pump drive circuit is as follows: Figure 5 As shown: For Figure 5 In (a), the output stage of the drive circuit uses NMOS switches MN1, MN2, and MN3, where MN1 is a low-voltage device, and MN2 and MN3 are high-voltage devices whose withstand voltage values ​​must match the voltage of the switching node VSW. The VCTRL signal serves as enable control: when VCTRL is high, if the input signal IN is high, MN1 and MN2 are turned on, MN3 is turned off, and the output OUT = VDD; if IN is low, MN1 and MN2 are turned off, MN3 is turned on, and the output OUT = GND. When VCTRL is low, MN1, MN2, and MN3 are all turned off, and the output node OUT is in a high-impedance state, thus preventing current from flowing back from the floating voltage domain to the low-voltage power supply domain. Figure 5 In (b), the output stage of the drive circuit uses NMOS switches MN1 and MN3 and diode D2. MN1 is a low-voltage device, while D2 and MN3 are high-voltage devices whose withstand voltage values ​​must match the voltage of the switching node VSW. The VCTRL signal acts as an enable control: when VCTRL is high, if the input signal IN is high, MN1 and D2 are turned on, MN3 is turned off, and the output OUT = VDD - VF, where VF is the forward voltage drop of diode D2; if IN is low, MN1 and D2 are turned off, MN3 is turned on, and the output OUT = GND. When VCTRL is low, MN1, D2, and MN3 are all turned off, and the output node OUT is in a high-impedance state, thus preventing current from flowing back from the floating voltage domain to the low-voltage domain. Additionally, for... Figure 5 (a) and Figure 5 In (b), the MN1 switch can also be implemented using a PMOS switch.

[0038] Preferably, the capacitance values ​​of the first storage capacitor CP1 and the second storage capacitor CP2 are equal. The values ​​need to be determined by comprehensively considering factors such as the clock signal frequency, the size of the power switch input capacitor, and the chip area. The lower the clock signal frequency, the larger the power switch input capacitor, requiring a larger storage capacitor and a larger chip area; conversely, the higher the clock signal frequency, the smaller the power switch input capacitor, requiring a smaller storage capacitor and a smaller chip area. In some applications, such as a clock signal frequency of 10MHz, the power switch input capacitor is 80pF, and the storage capacitor can be 5pF to 30pF. Its withstand voltage is configured to be no less than the switching node voltage VSW. The bootstrap capacitor CBST can be an on-chip integrated capacitor or an off-chip capacitor. When it is an on-chip integrated capacitor, a larger bootstrap capacitor value results in a higher turn-on voltage for the power switch, and a smaller bootstrap capacitor value results in a lower turn-on voltage. Its value can be 10 times the gate input capacitance CG of the power switch. When it is an off-chip capacitor, the bootstrap capacitor is typically a 100nF surface-mount ceramic capacitor.

[0039] Please see Figure 2When switches S1 and S3, and switches S2 and S4 are simultaneously conducting, short-circuit power consumption occurs, reducing the voltage across the bootstrap capacitor. Please refer to [link / reference]. Figure 7 ,exist Figure 2 Based on the existing circuit, switch S5 is added to independently control switch S3, and switch S6 is added to independently control switch S4. Specifically, CLKP1 controls the on / off state of switch S2, CLKP2 controls the on / off state of switch S1, CLKN1 controls the on / off state of switches S3 and S6, and CLKN2 controls the on / off state of switches S4 and S5. Proper timing control can prevent simultaneous conduction of switches S1 and S3, and switches S2 and S4, reducing short-circuit power consumption and avoiding the drop in bootstrap capacitor voltage caused by simultaneous switch conduction.

[0040] Please see Figure 8 In a multilevel converter topology, VIN is a high-voltage DC power supply signal, typically 48V, and the voltages of multiple switching nodes, such as VSW1 and VSW2, are in a floating state. If the power switch is directly driven by a low-voltage power supply VDD (typically 5V), the switching nodes will not be pulled down to ground potential, lacking a path to ground discharge. The diodes will remain in reverse bias, the bootstrap capacitors will not be able to charge, and the high-side drive will fail. If a stacked power supply architecture using cascaded diodes and bootstrap capacitors is adopted, the overall bootstrap capacitor is extremely large and cannot be integrated. Compared with the traditional solution, this invention achieves independent power supply for each power transistor in the floating voltage domain of the converter, which can effectively charge the bootstrap capacitor under any floating voltage, reduce the size of the overall bootstrap capacitor, save chip area, and reduce chip cost.

[0041] Please see Figure 6 , Figure 6 This paper compares the bootstrap capacitor size required in traditional multilevel converter schemes with that required in this invention. In existing technologies, bootstrap capacitors are stacked for power supply, resulting in an exponential change in bootstrap capacitance: CBSTn >> CBSTn-1 >> ... >> CBST2 >> CBST1 ≈ 10·CG (where n is the number of stages). This leads to an extremely large overall bootstrap capacitance, making integration impossible. In this invention, the bootstrap capacitors of each stage are no longer stacked. Storage capacitors alternately discharge the bootstrap capacitors, achieving independent power supply for the bootstrap capacitors. The bootstrap capacitor size required for the floating voltage domain of each power switch is 10·CG (when integrated on-chip) or 100nF (when off-chip). The required bootstrap capacitor sizes for each stage are similar, significantly reducing the overall required bootstrap capacitor area. Here, CG is the gate capacitance of the power switch.

[0042] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0043] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0044] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A bootstrap power supply circuit suitable for multi-level and hybrid power converters, characterized in that, This includes a charge pump circuit, a charge pump drive circuit, and a clock control circuit; The charge pump drive circuit includes a first charge pump drive circuit and a second charge pump drive circuit. The charge pump circuit includes a first switch, a second switch, a third switch, a fourth switch, a first storage capacitor, a second storage capacitor, and a bootstrap capacitor; The first switch is connected between the first node and the fifth node, the second switch is connected between the first node and the sixth node, the third switch is connected between the fourth node and the fifth node, the fourth switch is connected between the fourth node and the sixth node, the first storage capacitor is connected between the second node and the fifth node, and the second storage capacitor is connected between the third node and the sixth node. The bootstrap capacitor is connected between the first node and the fourth node. The first node is used to connect to the high potential end of the floating voltage domain of the power switch in the power converter, and the fourth node is used to connect to the low potential end of the floating voltage domain of the power switch. The output of the first charge pump drive circuit is connected to the second node, and the output of the second charge pump drive circuit is connected to the third node. By controlling the on / off state of each switch, the charge pump circuit can achieve alternating charging and discharging of the first and second storage capacitors to charge the bootstrap capacitor.

2. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 1, characterized in that, The first charge pump drive circuit is equipped with a fifth switch and a sixth switch, and the second charge pump drive circuit is equipped with a seventh switch and an eighth switch; the fifth switch is connected between the power supply voltage terminal of the drive circuit and the second node, and the sixth switch is connected between the second node and the ground terminal. The seventh switch is connected between the power supply voltage terminal and the third node, and the eighth switch is connected between the third node and the ground terminal.

3. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 2, characterized in that, The clock control circuit is used to generate a first clock signal and a second clock signal. The first clock signal and the second clock signal are out of phase and do not overlap. The first clock signal is used to control the on / off state of the second switch, the third switch, the sixth switch, and the seventh switch. The second clock signal is used to control the on / off state of the first, fourth, fifth, and eighth switches.

4. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 3, characterized in that, The power converter is a multi-level buck converter or a hybrid buck-boost converter; the power switch is a high-side power switch, and the power switch is N-type or P-type.

5. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 4, characterized in that, The bootstrap power supply circuit has a low-voltage control domain and a floating voltage domain, specifically: The low-voltage control domain uses ground as a reference, the high level of the low-voltage control domain is the power supply voltage terminal, and the low level of the low-voltage control domain is the ground terminal; the clock control circuit and the charge pump drive circuit operate in the low-voltage control domain. In the floating voltage domain: In the floating voltage domain, the voltage at the first node is at a high potential, and the voltage at the fourth node is at a low potential. When the power switch is N-type, the fourth node is connected to the switching node, the bootstrap capacitor is connected between the first node and the fourth node, and the upper plate of the bootstrap capacitor is connected to the first node and the lower plate is connected to the fourth node. When the power switch is P-type, the first node is connected to the switching node, the bootstrap capacitor is connected between the first node and the fourth node, and the upper plate of the bootstrap capacitor is connected to the first node and the lower plate is connected to the fourth node.

6. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 5, characterized in that, It also includes a mode selection circuit; the mode selection circuit is used to receive an externally input mode selection signal, which is used to select the timing when the charge pump circuit charges the bootstrap capacitor. The mode selection signal is a two-bit binary number. The voltage of the switching node alternates between a first voltage level and a second voltage level, with the second voltage level being higher than the first voltage level. Specifically: When the power switching transistor is N-type: When the mode selection signal is in the first state, the control signal is at an effective level when the switching node voltage is at the first voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level. When the mode selection signal is in the second state, the control signal is active when the switching node voltage is at the second voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the second voltage level. When the mode selection signal is in the third state, the control signal is active when the switching node voltage is at the first voltage level and the second voltage level. The charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level and the second voltage level. When the power switching transistor is P-type: When the mode selection signal is in the first state, the control signal is at an effective level when the switching node voltage is at the first voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level. When the mode selection signal is in the second state, the control signal is active when the switching node voltage is at the second voltage level, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the second voltage level. When the mode selection signal is in the third state, the control signal is active when the switching node voltage is at the first voltage level and the second voltage level. The charge pump circuit charges the bootstrap capacitor when the switching node voltage is at the first voltage level and the second voltage level. When the mode selection signal is in the third state, the control signal is active when the switching node voltage is low or high, and the charge pump circuit charges the bootstrap capacitor when the switching node voltage is low or high.

7. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 6, characterized in that, When the charge pump circuit operates in the first phase, the second, third, sixth, and seventh switches are turned on, while the first, fourth, fifth, and eighth switches are turned off. The first storage capacitor is charged, and the second storage capacitor discharges onto the bootstrap capacitor. When the charge pump circuit operates in the second phase, the first, fourth, fifth, and eighth switches are turned on, while the second, third, sixth, and seventh switches are turned off. The second storage capacitor is charged, and the first storage capacitor discharges onto the bootstrap capacitor. The first and second phases operate alternately, causing the first and second storage capacitors to alternately charge the bootstrap capacitor.

8. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 7, characterized in that, When the voltage at the switching node changes from the first voltage level to the second voltage level, the fifth, sixth, seventh, and eighth switches are all in the off state, cutting off the current path from the fourth node to the power supply voltage terminal and the ground terminal to prevent charge backflow and block the charge loss of the bootstrap capacitor.

9. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 8, characterized in that, The first and second storage capacitors have equal capacitance values, and their withstand voltage values ​​are configured to be no less than the switching node voltage; the bootstrap capacitor is an on-chip integrated capacitor or an off-chip capacitor.

10. The bootstrap power supply circuit for multi-level and hybrid power converters according to claim 9, characterized in that, The first charge pump drive circuit and the second charge pump drive circuit are each provided with an enable terminal for receiving a mode selection signal. When the mode selection signal received by the enable terminal is at an active level, the first charge pump drive circuit and the second charge pump drive circuit operate normally. When the mode selection signal received by the enable terminal is at an inactive level, the first charge pump drive circuit and the second charge pump drive circuit stop working, and the output node is in a high impedance state.

Images