Circuit with dynamic bias and input compensation

Abstract

This disclosure relates to circuitry with dynamic bias and input compensation. A system (100) includes: a load (160A); a circuit (114A) having a switch coupled to the load (160A); and a controller (122A) coupled to the circuit (114A). The controller (122A) is configured to: receive a first current at a third terminal (130A) of a comparator (124A); receive a second current less than the first current at the third terminal (130A) of the comparator (124A) in response to entering a pause mode where the switch is open; receive a first signal at a first terminal (126A) of the comparator (124A) during the pause mode; apply compensation to the first signal to generate a compensated first signal; and receive a second signal at a second terminal (128A) of the comparator (124A).

Description

Technical Field

[0001] This disclosure relates to electronic circuit technology. Background Technology

[0002] A switching converter is used to provide a direct current (DC) output voltage (VOUT) based on an input voltage (VIN). A typical switching converter includes: a power stage with switches and inductors; and a controller for switching the power stage. The controller includes a control loop with a comparator. To reduce power consumption, the comparator uses dynamic bias (e.g., using different quiescent currents). For example, when the controller directs the switches to continuous current mode (CCM), the comparator receives a first quiescent current. When the controller is in paused mode (e.g., a portion of a low-power mode with switching intervals separated by pause intervals), the comparator receives a second quiescent current lower than the first quiescent current. This dynamic bias of the comparator causes some voltage variation at the comparator's input terminals. This voltage variation at the comparator's input terminals affects the control loop and causes switching bursts (overlapping switching cycles without pause intervals). These switching bursts undesirably increase the output voltage ripple. Summary of the Invention

[0003] In this example, the system includes: a load; a circuit having a switch coupled to the load; and a controller coupled to the circuit. The controller is configured to: receive a first current at a third terminal of a comparator; receive a second current at the third terminal of the comparator, the second current being less than the first current, in response to entering a pause mode where the switch is open; receive a first signal at a first terminal of the comparator during the pause mode; apply compensation to the first signal to generate a compensated first signal having a lower amplitude than the first signal; receive a second signal at a second terminal of the comparator; provide a comparison result at a fourth terminal of the comparator in response to the compensated first and second signals; and provide a control signal to the switch in response to the comparison result.

[0004] In another example, a circuit includes: a first transistor; a second transistor; a dynamic bias circuit system; and a compensation circuit. The first transistor has a first terminal, a second terminal, and a control terminal. The second transistor has a first terminal, a second terminal, and a control terminal. The first and second transistors form an input pair. The dynamic bias circuit system includes a third transistor having a first terminal, a second terminal, and a control terminal. The second terminal of the third transistor is coupled to the first terminal of both the first and second transistors. The compensation circuit system is coupled to the control terminal of the first transistor. The compensation circuit system is configured to compensate the signal at the control terminal of the first transistor. The compensation reduces the amplitude of the signal.

[0005] In another example, a circuit includes: an error amplifier; a comparator; a dynamic bias circuit system; and a compensation circuit system. The error amplifier has a first terminal, a second terminal, and a third terminal. The comparator has a first terminal, a second terminal, a third terminal, and a fourth terminal. The second terminal of the comparator is coupled to the third terminal of the error amplifier. The dynamic bias circuit system is coupled to the third terminal of the comparator. The compensation circuit system is coupled to the first terminal of the comparator and configured to compensate the signal at the first terminal of the comparator. Attached Figure Description

[0006] Figure 1 This is an image showing example vehicles.

[0007] Figure 2 This is a diagram showing an example computer rack.

[0008] Figure 3 This is a diagram showing the instance controller.

[0009] Figure 4 This is a diagram showing another instance controller.

[0010] Figure 5 This is a diagram illustrating the circuit system of an example controller.

[0011] Figure 6 It is a timing diagram showing an example waveform of the controller.

[0012] Figure 7 It is a timing diagram showing example waveforms of the power stage and controller. Detailed Implementation

[0013] Use the same reference numerals or other reference designators in the accompanying drawings to designate the same or similar features. Such features may be identical or similar in function and / or structure.

[0014] This article describes circuits with dynamic bias and compensation circuitry. Example circuits include comparators, low-dropout regulators, or other circuits with input-pair transistors. The compensation circuitry takes into account the effect of dynamic bias on one or more input signals of the circuit. In some instances, the effect of dynamic bias on the circuit is due to variations or interference in the input signal caused by local capacitances in the circuit (e.g., the gate-source capacitance of the input-pair transistor). The compensation circuitry is used to apply compensation to reduce interference or variations in the input signal, thereby producing a more accurate comparison result. In some instances, interference or variations in the input signal due to dynamic bias increase the amplitude of the input signal. In such instances, compensation reduces the amplitude of the input signal to account for amplitude variations in the input signal caused by dynamic bias and local capacitances (e.g., the gate-source capacitance of the input-pair transistor). In some instances, the circuit is a comparator that is part of a controller with a control loop, where improved comparator results lead to improved control loop operation. In some instances, the controller provides control signals for the switching of a switching converter based on the comparison results, where improved accuracy of the comparison results reduces output voltage (VOUT) ripple and improves the efficiency of the switching converter.

[0015] In some instances, the switching converters and controllers are components of a battery-powered system, where improved efficiency of the switching converters and controllers extends battery charging time. In other instances, the switching converters and controllers are components of a data storage system, where improved efficiency of the switching converters and controllers reduces power consumption of the data storage system. In some instances, a battery-powered system (e.g., a vehicle) or a data storage system (e.g., a computer rack in a data storage center or artificial intelligence processing center) may contain a plurality of switching converters and corresponding controllers, where improvements in the efficiency of each switching converter and corresponding controller are cumulative.

[0016] Figure 1 This diagram illustrates example vehicle 100. Vehicle 100 can be a car or other vehicle. Figure 1In this example, vehicle 100 includes battery 102, voltage regulation circuitry system 108, power stages 114A to 114N, controllers 122A to 122N, and loads 160A to 160N. Battery 102 has a first terminal 104 and a second terminal 106. Vehicle 100 may also include a battery charging controller (not shown) coupled to the first terminal 104 and the second terminal 106 of battery 102 to regulate charging of battery 102 via an external or internal power source. Voltage regulation circuitry system 108 has a first terminal 110, a second terminal 111, and a set of third terminals 112A to 112N. Each of power stages 114A to 114N has a corresponding first terminal 116A to 116N, a corresponding set of second terminals 118A to 118N, and a corresponding set of third terminals 120A to 120N. Each of controllers 122A to 122N has a corresponding set of terminals 123A to 123N. Each of the loads 160A to 160N has a corresponding terminal 162A to 162N.

[0017] exist Figure 1 In this example, each of the controllers 122A to 122N includes a corresponding comparator 124A to 124N, a corresponding dynamic bias circuit system 134A to 134N, a corresponding compensation circuit system 138A to 138N, a corresponding control logic 142A to 142N, and a corresponding driver circuit system 148A to 148N. Each of the comparators 124A to 124N has a corresponding first terminal 126A to 126N, a corresponding second terminal 128A to 128N, a corresponding third terminal 130A to 130N, and a corresponding fourth terminal 132A to 132N. Each dynamic bias circuit system 134A to 134N has a corresponding terminal 136A to 136N. Each compensation circuit system 138A to 138N has a corresponding terminal 140A to 140N. Each control logic 142A to 142N has a corresponding first terminal 144A to 144N and a corresponding second terminal group 146A to 146N. Each driver circuit system 148A to 148N has a corresponding first terminal group 150A to 150N and a corresponding second terminal group 152A to 152N.

[0018] A first terminal 104 of battery 102 is coupled to a first terminal 110 of voltage regulation circuit system 108. A second terminal 106 of battery 102 is coupled to a second terminal 111 of voltage regulation circuit system 108. Each terminal of the third terminal group 112A to 112N of voltage regulation circuit system 108 is coupled to a corresponding terminal of the first terminal group 116A to 116N of power stages 114A to 114N. A terminal of the second terminal group 118A to 118N of power stages 114A to 114N is coupled to a corresponding terminal of the terminal group 123A to 123N of controller 122A to 122N. Each terminal of the third terminal group 120A to 120N of power stages 114A to 114N is coupled to a corresponding terminal of the terminal group 162A to 162N of load 160A to 160N.

[0019] The first terminal 126A of comparator 124A is coupled to terminal 140A of compensation circuit system 138A and a first signal (IN1_A) source (not shown). The second terminal 128A of comparator 124A is coupled to a second signal (IN2_A) source (not shown). The third terminal 130A of comparator 124A is coupled to terminal 136A of dynamic bias circuit system 134A. The fourth terminal 132A of comparator 124A is coupled to the first terminal 144A of control logic 142A. The second terminal group 146A of control logic 142A is coupled to a corresponding terminal in the first terminal group 150A of driver circuit system 148A. The second terminal group 152A of driver circuit system 148A is coupled to a corresponding terminal in the terminal group 123A of controller 122A. Each of controllers 122B (not shown) to 122N has a similar topology to controller 122N. The first terminal 126N of comparator 124N is coupled to terminal 140N of compensation circuit system 138N and the first signal (IN1_N) source (not shown). The second terminal 128N of comparator 124N is coupled to the second signal (IN2_N) source (not shown). The third terminal 130N of comparator 124N is coupled to terminal 136N of dynamic bias circuit system 134N. The fourth terminal 132N of comparator 124N is coupled to the first terminal 144N of control logic 142N. The second terminal group 146N of control logic 142N is coupled to the corresponding terminal in the first terminal group 150N of driver circuit system 148N. The second terminal group 152N of driver circuit system 148N is coupled to the corresponding terminal in the terminal group 123N of controller 122N.

[0020] Battery 102 is used to convert battery voltage (V) BAT The current is supplied to the voltage regulation circuit system 108. Figure 1 In the example, V BATThe voltages across the first terminal 104 and the second terminal 106 of battery 102, and across the first terminal 110 and the second terminal 111 of voltage regulation circuit system 108, vary depending on the current drawn from battery 102, which is regulated by each of the loads 160A to 160N, power stages 114A to 114N, and corresponding controllers 122A to 122N. Each of controllers 122A to 122N supports different modes for power stages 114A to 114N, including continuous current mode (CCM) and discontinuous current mode (DCM) (or low power mode). During CCM operation, the power stage switches have on / off intervals without pauses between on / off intervals to support the target VOUT and output current for continuous loads. During DCM operation, the power stage switches have on / off intervals with pauses between on / off intervals to support the target VOUT and output current for light or intermittent loads. During DCM operation or related pause intervals, each dynamic bias circuit system 134A to 134N can adjust the current supplied to the corresponding comparator in comparators 124A to 124N. For example, the current is supplied via corresponding terminals 136A to 136N of the dynamic bias circuit systems 134A to 134N and corresponding terminals of the third terminals 130A to 130N of the comparators 124A to 124N. In some instances, during CCM operation, each dynamic bias circuit system 134A to 134N supplies a first current to the corresponding comparator in comparators 124A to 124N. During DCM operation or related pause intervals, each dynamic bias circuit system 134A to 134N supplies a second current to the corresponding comparator in comparators 124A to 124N, wherein the second current is less than the first current.

[0021] Compensation circuit systems 138A to 138N apply compensation to the corresponding signals IN1_A to IN1_N to account for the effects of dynamic bias. In some instances, the effect of dynamic bias is the variation (e.g., an increase in voltage) of signals IN1_A to IN1_N due to local capacitance (e.g., the gate-source capacitance of the input-to-transistor of each corresponding comparator). In some instances, compensation circuit system 138A reduces the variation of signal IN1_A at the first terminal 126A of comparator 124A, compensation circuit system 138B reduces the variation of signal IN1_B at the first terminal 126B of comparator 124B, and so on, until compensation circuit system 138B reduces the variation of signal IN1_N at the first terminal 126N of comparator 124N.

[0022] By utilizing compensation circuit systems 138A to 138N, input signal interference or variation is reduced, and the comparison results at the fourth terminals 132A to 132N of comparators 124A to 124N are more accurate, resulting in improved control loop operation. The corresponding comparison results are provided to the corresponding first terminals 144A to 144N of control logic 142A to 142N. Each control logic 142A to 142N generates a corresponding switch control signal at a corresponding terminal in the second terminal group 146A to 146N in response to the comparison result. Each driver circuit system 148A to 148N receives the corresponding switch control signal (at a corresponding terminal in the first terminal group 150A to 150N) and provides a corresponding switch drive signal (at a corresponding terminal in the second terminal group 152A to 152N). Switching drive signals are output from corresponding terminals in terminal groups 123A to 123N of controllers 122A to 122N and provided to corresponding terminals in the second terminal groups 118A to 118N of power stages 114A to 114N to control the corresponding switches of power stages 114A to 114N. Since each load 160A to 160N is variable, each controller 122A to 122N can control each corresponding power stage 114A to 114N in different ways. The comparison results are adjusted using compensation circuitry systems 138A to 138N to prevent switching bursts (overlapping switching cycles without pause intervals) during DCM operation.

[0023] In a typical switching cycle, there is a ramp-up interval followed by a ramp-down interval. During the ramp-up interval, the high-side switch is on, and the low-side switch is off. During the ramp-down interval, the low-side switch is on, and the high-side switch is off. A switching burst occurs when consecutive switching cycles overlap. In one instance of a switching burst, consecutive ramp-up intervals occur without ramp-down intervals. In another instance of a switching burst, consecutive ramp-up intervals occur without a complete ramp-down interval between them. In yet another instance of a switching burst, consecutive switching cycles occur without a pause interval between them. Such switching bursts are undesirable during DCM and may occur due to control loop problems (e.g., if the comparator input is affected by the comparator's dynamic bias and no compensation is provided).

[0024] The use of dynamic bias circuitry systems 134A to 134N and compensation circuitry systems 138A to 138N, along with corresponding comparators 124A to 124N, reduces power consumption during the corresponding DCM operation, while avoiding switching bursts to reduce VOUT ripple and improve the efficiency of power stages 114A to 114N. The efficiency improvement of power stages 114A to 114N is cumulative, providing benefits such as: reduced power consumption of vehicle 100; extended charging duration and lifespan of vehicle battery 102; reduced unwanted heat emissions from vehicle 100's electronics; and reduced heat sink / cooling overhead for vehicle 100's electronics.

[0025] Figure 2 This diagram illustrates an example computer rack 200. Computer rack 200 can be part of a data storage center or an artificial intelligence processing center. Figure 2 In this example, computer rack 200 includes an AC-to-DC (AC / DC) converter 202, a voltage regulation circuit system 208, power stages 214A to 214N, controllers 222A to 222N, and loads 260A to 260N. The AC / DC converter 202 has a first terminal 203, a second terminal 204, and a third terminal 206. The voltage regulation circuit system 208 has a first terminal 210, a second terminal 211, and a set of third terminals 212A to 212N. Each of the power stages 214A to 214N has a corresponding first terminal 216A to 216N, a corresponding second terminal group 218A to 218N, and a corresponding third terminal 220A to 220N. Each of the controllers 222A to 222N has a corresponding terminal group 223A to 223N. Each of the loads 260A to 260N has a corresponding terminal 262A to 262N.

[0026] exist Figure 2In this example, each of the controllers 222A to 222N includes a corresponding comparator 224A to 224N, a corresponding dynamic biasing circuit system 234A to 234N, a corresponding compensation circuit system 238A to 238N, a corresponding control logic 242A to 242N, and a corresponding driver circuit system 248A to 248N. Each of the comparators 224A to 224N has a corresponding first terminal 226A to 226N, a corresponding second terminal 228A to 228N, a corresponding third terminal 230A to 230N, and a corresponding fourth terminal 232A to 232N. Each dynamic biasing circuit system 234A to 234N has a corresponding terminal 236A to 236N. Each compensation circuit system 238A to 238N has a corresponding terminal 240A to 240N. Each control logic 242A to 242N has a corresponding first terminal 244A to 244N and a corresponding second terminal group 246A to 246N. Each driver circuit system 248A to 248N has a corresponding first terminal group 250A to 250N and a corresponding second terminal group 252A to 252N.

[0027] The second terminal 204 of the AC / DC converter 202 is coupled to the first terminal 210 of the voltage regulation circuit system 208. The third terminal 206 of the AC / DC converter 202 is coupled to the second terminal 211 of the voltage regulation circuit system 208. Each terminal in the third terminal group 212A to 212N of the voltage regulation circuit system 208 is coupled to a corresponding terminal in the first terminals 216A to 216N of the power stages 214A to 214N. Each terminal in the second terminal group 218A to 218N of the power stages 214A to 214N is coupled to a corresponding terminal in the terminal group 223A to 223N of the controllers 222A to 222N. Each terminal in the third terminals 220A to 220N of the power stages 214A to 214N is coupled to a corresponding terminal in the terminals 262A to 262N of the loads 260A to 260N.

[0028] The first terminal 226A of comparator 224A is coupled to terminal 240A of compensation circuit system 238A and a first signal (IN1_A) source (not shown). The second terminal 228A of comparator 224A is coupled to a second signal (IN2_A) source (not shown). The third terminal 230A of comparator 224A is coupled to terminal 236A of dynamic bias circuit system 234A. The fourth terminal 232A of comparator 224A is coupled to the first terminal 244A of control logic 242A. The second terminal group 246A of control logic 242A is coupled to a corresponding terminal in the first terminal group 250A of driver circuit system 248A. The second terminal group 252A of driver circuit system 248A is coupled to a corresponding terminal in the terminal group 223A of controller 222A. Each of controllers 222B (not shown) to 222N has a similar topology to controller 222N. The first terminal 226N of comparator 224N is coupled to terminal 240N of compensation circuit system 238N and the first signal (IN1_N) source (not shown). The second terminal 228N of comparator 224N is coupled to the second signal (IN2_N) source (not shown). The third terminal 230N of comparator 224N is coupled to terminal 236N of dynamic bias circuit system 234N. The fourth terminal 232N of comparator 224N is coupled to the first terminal 244N of control logic 242N. The second terminal group 246N of control logic 242N is coupled to the corresponding terminal in the first terminal group 250N of driver circuit system 248N. The second terminal group 252N of driver circuit system 248N is coupled to the corresponding terminal in the terminal group 223N of controller 222N.

[0029] AC / DC converter 202 is used to: receive AC voltage (V) at the first terminal 203 AC ); and DC voltage (V DC The current is supplied to the voltage regulation circuit system 108. Figure 2 In this example, the voltage across the second terminal 204 and the third terminal 206 of the AC / DC converter 202 is V. DCThe voltage across the first terminal 210 and the second terminal 211 of the voltage regulation circuit system 208 is the same. The current drawn from the AC / DC converter 202 varies depending on the current regulation of each of the loads 260A to 260N, the power stages 214A to 214N, and the corresponding controllers 222A to 222N. Each of the controllers 222A to 222N supports different modes of the power stages 214A to 214N, including CCM and DCM. During DCM operation or associated pause intervals, each dynamic bias circuit system 234A to 234N can adjust the current supplied to the corresponding comparator in the comparators 224A to 224N. For example, current is supplied via the corresponding terminals 236A to 236N of the dynamic bias circuit systems 234A to 234N and the corresponding terminals of the third terminals 230A to 230N of the comparators 224A to 224N. In some instances, during CCM operation, each dynamic bias circuit system 234A to 234N provides a first current to a corresponding comparator in comparators 224A to 224N. During DCM operation or a related pause interval, each dynamic bias circuit system 234A to 234N provides a second current to a corresponding comparator in comparators 224A to 224N, wherein the second current is less than the first current.

[0030] Compensation circuit systems 238A to 238N compensate for the corresponding signals IN1_A to IN1_N to account for the effects of dynamic bias and local capacitance (e.g., the gate-source capacitance of the input to the transistor). In some instances, the effect of dynamic bias is the change in signals IN1_A to IN1_N (e.g., an increase in voltage) due to local capacitance (e.g., the gate-source capacitance of the input to the transistor of each corresponding comparator). In such instances, compensation circuit system 238A compensates for signal IN1_A at the first terminal 226A of comparator 224A, compensation circuit system 238B (shown but not shown) compensates for signal IN1_B at the first terminal 226B (shown but not shown) of comparator 224B (shown but not shown), and so on, until compensation circuit system 238B compensates for signal IN1_N at the first terminal 226N of comparator 224N.

[0031] By utilizing compensation circuit systems 238A to 238N, the comparison results at the fourth terminals 232A to 232N of comparators 224A to 224N are more accurate, resulting in improved control loop operation. The corresponding comparison results are provided to the corresponding terminals in each group of first terminals 244A to 244N of control logics 242A to 242N. Each control logic 242A to 242N generates a corresponding switch control signal at the corresponding terminal in each group of second terminals 246A to 246N in response to the comparison result. Each driver circuit system 248A to 248N receives the corresponding switch control signal (at the corresponding terminal in each group of first terminals 250A to 250N) and provides a corresponding switch drive signal (at the corresponding terminal in each group of second terminals 252A to 252N). Switching drive signals are output from corresponding terminals in terminal groups 223A to 223N and provided to corresponding terminals in each group of second terminals 218A to 218N of power stages 214A to 214N to control the corresponding switches of power stages 214A to 214N. Since each load 260A to 260N is variable, each controller 222A to 222N can control each corresponding power stage 214A to 214N in different ways. Comparison results are adjusted using compensation circuit systems 238A to 238N to avoid switching bursts during DCM operation. The use of dynamic bias circuit systems 234A to 234N, compensation circuit systems 238A to 238N, and corresponding comparators 224A to 224N reduces power consumption during corresponding DCM operation while avoiding switching bursts to reduce VOUT ripple and improve the efficiency of power stages 214A to 214N. The efficiency improvement of power stages 214A to 214N is cumulative, which provides benefits such as: reduced power consumption of computer rack 200; reduced unwanted heat emissions; and reduced heat sink / cooling overhead for the electronic devices in computer rack 200.

[0032] Figure 3 This is a diagram to illustrate instance controller 300. Figure 3 The controller 300 is Figure 1 Each of the corresponding controllers 122A to 122N or Figure 2 Each of the corresponding controllers 222A to 222N is an instance. In Figure 3 In this example, the controller 300 has a set of terminals 301. The set of terminals 301 is... Figure 1 Terminals 123A to 123N or Figure 2 Examples of each of terminals 223A to 223N. Controller 300 includes a ramp generator 302, an error amplifier 308, a comparator 316, a dynamic bias circuitry 324, a compensation circuitry 328, control logic 332, a timer 338, and a driver circuitry 342. Comparator 316 is... Figure 1 An instance of each corresponding comparator in comparators 124A to 124N or comparators 224A to 224N. The dynamic bias circuit system 324 is... Figure 1 Each of the corresponding dynamic bias circuit systems in the 134A to 134N or Figure 2 Examples of each corresponding dynamic bias circuit system 234A to 234N are provided. The compensation circuit system 328 is... Figure 1 Each of the corresponding compensation circuit systems in the 138A to 138N or Figure 2 Examples of each corresponding compensation circuit system 238A to 238N. Control logic 332 is... Figure 1 Each of the corresponding control logic 142A to 142N or Figure 2 Examples of each corresponding control logic 242A to 242N. The driver circuit system 342 is... Figure 1 Each of the corresponding driver circuit systems in the series 148A to 148N or Figure 2 Examples of each of the corresponding driver circuit systems 248A to 248N.

[0033] The ramp generator 302 has a first terminal 304 and a second terminal 306. The error amplifier 308 has a first terminal 310, a second terminal 312, and a third terminal 314. The comparator 316 has a first terminal 318, a second terminal 320, a third terminal 321, and a fourth terminal 322. The first terminal 318 is... Figure 1 Each of the corresponding first terminals 126A to 126N or Figure 2 Examples of each corresponding first terminal 226A to 226N. The second terminal 320 is... Figure 1 Each of the corresponding second terminals 128A to 128N or Figure 2 Examples of each corresponding second terminal 228A to 228N. The third terminal 321 is... Figure 1 Each of the corresponding third terminals 130A to 130N or Figure 2 Examples of each corresponding third terminal 230A to 230N. The fourth terminal 322 is... Figure 1 Examples of each corresponding fourth terminal 132A to 132N or each corresponding fourth terminal 223A to 223N. The dynamic bias circuit system 324 has terminal 326. Terminal 326 is... Figure 1 Each corresponding terminal 136A to 136N or Figure 2 Examples of each corresponding terminal 236A to 236N. The compensation circuit system 328 has terminal 330. Terminal 330 is... Figure 1 Each corresponding terminal in the middle is 140A to 140N or Figure 2Examples of each corresponding terminal 240A to 240N. Control logic 332 has a first terminal 334, a second terminal 336, and a set of third terminals 337. The first terminal 334 is... Figure 1 Each of the corresponding first terminals 144A to 144N or Figure 2 Examples of each corresponding first terminal 244A to 244N. The third terminal group 337 is... Figure 1 Each of the corresponding second terminal groups 146A to 146N or Figure 2 Examples of each corresponding second terminal group 246A to 246N. Timer 338 has terminal 340. Driver circuit system 342 has a first terminal group 344 and a second terminal group 346. The first terminal group 344 is... Figure 1 Each corresponding first terminal group in the 150A to 150N or Figure 2 Examples of each corresponding first terminal group 250A to 250N. The second terminal group 346 is... Figure 1 Each of the corresponding second terminal groups 152A to 152N or Figure 2 Examples of each corresponding second terminal group 252A to 252N.

[0034] exist Figure 3 In this example, the third terminal 314 of the error amplifier 308 is coupled to the first terminal 318 of the comparator 316 and the terminal 330 of the compensation circuit system 328. The second terminal 306 of the ramp generator 302 is coupled to the second terminal 320 of the comparator 316. The third terminal 321 of the comparator 316 is coupled to the terminal 326 of the dynamic bias circuit system 324. The fourth terminal 322 of the comparator 316 is coupled to the first terminal 334 of the control logic 332. The second terminal 336 of the control logic 332 is coupled to the terminal 340 of the timer 338. The third terminal group 337 of the control logic 332 is coupled to a corresponding terminal in the first terminal group 344 of the driver circuit system 342. The second terminal group 346 of the driver circuit system 342 is coupled to a corresponding terminal in the terminal group 301 of the controller 300.

[0035] In some instances, ramp generator 302 is used to: receive an offset voltage (VOS) at a first terminal 304; and, in response to VOS, provide a ramp signal at a second terminal 306. The ramp signal from the ramp generator represents the behavior of the inductor current of the corresponding power stage. Error amplifier 308 is used to: receive a feedback voltage (VFB, where VFB is equal to the corresponding VOUT or a scaled version of the corresponding VOUT) at a first terminal 310; receive a reference voltage (VREF, where VREF is equal to the target VOUT) at a second terminal 312; and, in response to VFB and VREF, provide an error amplifier result at a third terminal 314. In some instances, the first terminal 310 is an inverting (-) terminal, and the second terminal 312 is a non-inverting (+) terminal. Comparator 316 is used to: receive the error amplifier result at the first terminal 318 as a first signal (IN1); receive a ramp signal at the second terminal 320 as a second signal (IN2); receive a bias current from the dynamic bias circuit system 324 at the third terminal 321; and provide a comparison result at the fourth terminal 322 in response to signals IN1, IN2, and the bias current. Figure 3 In one example, the compensation circuitry 328 is used to compensate for signal IN1 to account for variations or interference in the value of signal IN1 caused by different bias currents applied at the third terminal 321 and local capacitances (e.g., the gate-source capacitance of the input to the transistor of comparator 316). In some instances, the compensation applied by the compensation circuitry 328 reduces the amplitude of signal IN1 to account for variations in the amplitude of signal IN1 caused by the use of different bias currents and local capacitances.

[0036] Timer 338 is used to provide a timer result as terminal 340 based on a predetermined on-time interval. Control logic 332 is used to: receive a comparison result from comparator 316 at a first terminal 334; receive a timer result at a second terminal 336; and provide a switch control signal at a third terminal group 337 in response to the comparison result and the timer result. Driver circuitry 342 is used to: receive the switch control signal at the first terminal group 344; and provide a switch drive signal at the second terminal group 346 in response to the switch control signal. The switch drive signal is provided to terminal group 301 to control the power stage (e.g., ...). Figure 1 One of the power stages 114A to 114N or Figure 2 The switch of the power stage (one of 214A to 214N).

[0037] The compensation circuit system 328 is used to adjust the comparison result, thereby avoiding switching bursts during DCM operation. The use of the dynamic bias circuit system 324, the compensation circuit system 328, and the comparator 316 reduces power consumption during the corresponding DCM operation, while avoiding switching bursts to reduce VOUT ripple and improve the efficiency of the power stage controlled by the controller. When multiple controllers, such as controller 300, are used, the efficiency improvement of the corresponding power stage is cumulative, which provides benefits such as reducing vehicle (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 The power consumption of the computer rack 200 in the middle; extending the battery life (e.g., Figure 1 The charging duration and lifespan of the battery 102 in the vehicle; reducing the vehicle's (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 Undesirable heat emissions from electronic devices in the computer rack 200; and reducing vehicle (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 The heat sink / cooling overhead of electronic devices in the computer rack 200.

[0038] Figure 4 This diagram illustrates another instance of controller 400. Controller 400 is... Figure 1 Each of the corresponding controllers 122A to 122N or Figure 2 Each of the corresponding controllers 222A to 222N is an instance. In Figure 4 In this example, controller 400 has terminal 402. Terminal 402 is... Figure 1 Terminals 123A to 123N or Figure 2 Examples of each of terminals 223A to 223N. Controller 400 includes an error amplifier 408, a comparator 416, a dynamic bias circuitry 424, a compensation circuitry 428, a control logic / driver circuitry / switch 442, resistors R1 and R2, capacitors C1, C2 and C3, and an inductor L1. Comparator 416 is... Figure 1 An instance of each corresponding comparator in comparators 124A to 124N or comparators 224A to 224N. The dynamic bias circuit system 424 is... Figure 1 Each of the corresponding dynamic bias circuit systems in the 134A to 134N or Figure 2 Examples of each corresponding dynamic bias circuit system 234A to 234N are shown. The compensation circuit system 428 is... Figure 1 Each of the corresponding compensation circuit systems in the 138A to 138N or Figure 2Examples of each corresponding compensation circuit system 238A to 238N. Control logic / driver circuit system / switch 442 is... Figure 1 Each of the corresponding control logics 142A to 142N, driver circuit systems 148A to 148N, and Figure 1 The corresponding power stage switches from 114A to 114N in the power stage or Figure 2 Each of the corresponding control logics 242A to 242N, driver circuit systems 248A to 248N, and Figure 2 Examples of corresponding power stage switches for power stages 214A to 214N.

[0039] Error amplifier 408 has a first terminal 410, a second terminal 412, and a third terminal 314. Comparator 416 has a first terminal 418, a second terminal 420, a third terminal 421, and a fourth terminal 422. The first terminal 418 is... Figure 1 Each of the corresponding first terminals 126A to 126N or Figure 2 Examples of each corresponding first terminal 226A to 226N. The second terminal 420 is... Figure 1 Each of the corresponding second terminals 128A to 128N or Figure 2 Examples of each corresponding second terminal 228A to 228N. The third terminal 421 is... Figure 1 Each of the corresponding third terminals 130A to 130N or Figure 2 Examples of each corresponding third terminal 230A to 230N. The fourth terminal 422 is... Figure 1 Examples of each corresponding fourth terminal 132A to 132N or each corresponding fourth terminal 223A to 223N. The dynamic bias circuit system 424 has a terminal 426. Terminal 426 is... Figure 1 Each corresponding terminal 136A to 136N or Figure 2 Examples of each corresponding terminal 236A to 236N. The compensation circuit system 428 has terminal 430. Terminal 430 is... Figure 1 Each corresponding terminal in the middle is 140A to 140N or Figure 2 Examples of each corresponding terminal 240A to 240N. The control logic / driver circuit system / switch 442 has a first terminal 444 and a second terminal 446. The first terminal 444 is... Figure 1 Each of the corresponding first terminals 144A to 144N or Figure 2 Examples of each corresponding first terminal 244A to 244N. The second terminal 446 is... Figure 1 The switching nodes between the corresponding power level switches of power stages 114A to 114N in the middle or Figure 2Examples of switching nodes between the corresponding power stage switches of power stages 214A to 214N. Figure 4 In the example, each of resistors R1 and R2, each of capacitors C1, C2 and C3, and inductor L1 have a corresponding first terminal and a corresponding second terminal.

[0040] exist Figure 4 In this example, the first terminal 410 of the error amplifier 408 is coupled to terminal 402 of the controller 400, the first terminal of capacitor C3, and the second terminal of inductor L1. The second terminal 412 of the error amplifier 408 is coupled to the VREF source (not shown). The third terminal 414 of the error amplifier 408 is coupled to the first terminal 418 of the comparator 416, the terminal 430 of the compensation circuit system 428, and the first terminal of resistor R1. The second terminal of resistor R1 is coupled to the first terminal of capacitor C1. The second terminal of capacitor C1 is coupled to ground or a ground terminal. The third terminal 421 of the comparator 416 is coupled to terminal 426 of the dynamic bias circuit system 424. The fourth terminal 422 of the comparator 416 is coupled to the first terminal 444 of the control logic / driver circuit system / switch 442. The second terminal 446 of the control logic / driver circuit system / switch 442 is coupled to the first terminal of resistor R2 and the first terminal of inductor L1. The second terminal of resistor R2 is coupled to the first terminal of capacitor C2 and the second terminal 420 of comparator 416. The second terminal of capacitor C2 is coupled to ground or a ground terminal. Figure 4 In this example, resistor R2 and capacitor C2 form components of a slow control loop between the second terminal 446 of the control logic / driver circuitry / switch 442 and the second terminal 420 of the comparator 416. Inductor L1 forms components of a fast control loop between the second terminal 446 of the control logic / driver circuitry / switch 442 and the first terminal 410 of the error amplifier 408.

[0041] In some instances, error amplifier 408 is used to: receive a fast control loop result (e.g., VFB) at a first terminal 410; receive VREF at a second terminal 412; and provide an error amplifier result at a third terminal 414 in response to VFB and VREF. In some instances, the first terminal 410 is an inverting (-) terminal, and the second terminal 412 is a non-inverting (+) terminal. Comparator 416 is used to: receive an error amplifier result as a first signal at a first terminal 418; receive a slow control loop result as a second signal at a second terminal 420; receive a bias current from dynamic bias circuitry 424 at a third terminal 421; and provide a comparison result at a fourth terminal 422 in response to the first signal (e.g., error amplifier result), the second signal (e.g., slow control loop result), and the bias current. Figure 4 In one example, compensation circuitry 428 is used to compensate the error amplifier result to account for the effects of different bias currents and local capacitances (e.g., the gate-source capacitance of the transistor at the input of comparator 416) applied at the third terminal 421. In some examples, compensation circuitry 328 reduces the amplitude of the error amplifier result by providing a reverse current or charge, wherein the reverse current or charge accounts for amplitude variations in the error amplifier result due to dynamic bias and local capacitance.

[0042] The control logic / driver circuitry / switch 442 is used to: receive a comparison result from the comparator 416 at the first terminal 444; control the power stage switch in response to the comparison result; and provide a switch node voltage (VSW) at the second terminal 446 in response to the comparison result, driver circuitry operation, and power stage switch operation.

[0043] The compensation circuit system 428 is used to adjust the comparison result, thereby preventing switching bursts during DCM operation. The use of the dynamic bias circuit system 424, the compensation circuit system 428, and the comparator 416 reduces power consumption during the corresponding DCM operation, while avoiding switching bursts to reduce VOUT ripple and improve the efficiency of the power stage controlled by the controller. When multiple controllers, such as controller 400, are used, the efficiency improvement of the corresponding power stage is cumulative, which provides benefits such as reducing vehicle (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 The power consumption of the computer rack 200 in the middle; extending the battery life (e.g., Figure 1 The charging duration and lifespan of the battery 102 in the vehicle; reducing the vehicle's (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 Undesirable heat emissions from electronic devices in the computer rack 200; and reducing vehicle (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 The heat sink / cooling overhead of electronic devices in the computer rack 200.

[0044] Figure 5 The diagram illustrates an example controller circuit system 500. The controller circuit system 500 includes... Figure 1 Each of the corresponding controllers 122A to 122N in the series Figure 2 Each of the corresponding controllers 222A to 222N in the series Figure 3 Controller 300 or Figure 4 The instance component of controller 400. Figure 5In this example, the controller circuit system 500 includes an error amplifier 508, a resistor R1, a capacitor C1, a comparator circuit system 516, a dynamic bias circuit system 524, and a compensation circuit system 528. The error amplifier 508 is... Figure 3 Error amplifier 308 or Figure 4 An example of error amplifier 408 in the example. Dynamic bias circuitry system 524 includes... Figure 1 Each of the corresponding dynamic bias circuit systems 134A to 134N in the series Figure 2 Each of the corresponding dynamic bias circuit systems 234A to 234N in the series Figure 3 The dynamic bias circuit system 324 or Figure 4 An example component of the dynamic bias circuitry system 424. The comparator circuitry system 516 includes... Figure 1 Each of the corresponding comparators 124A to 124N in the series Figure 2 Each of the corresponding comparators 224A to 224N in the series Figure 3 The comparator 316 or Figure 4 The comparator 416 is an example component. The compensation circuit system 528 includes... Figure 1 Each of the corresponding compensation circuit systems 138A to 138N, Figure 2 Each of the corresponding compensation circuit systems 238A to 238N, Figure 3 The compensation circuit system 328 or Figure 4 Example components of the compensation circuit system 428 in the example.

[0045] exist Figure 5 In this example, the dynamic bias circuit system 524 includes transistor M1. The comparator circuit system 516 includes transistors M2 and M3. The compensation circuit system 528 includes transistors M4 through M7. The error amplifier 508 has a first terminal 510, a second terminal 512, and a third terminal 514. Each of transistors M1 through M7 has a first terminal, a second terminal, and a control terminal. Figure 1 In one example, transistors M1 to M4 are n-channel field-effect transistors (NFETs), and transistors M5 to M7 are p-channel field-effect transistors (PFETs). In other examples, transistors M1 to M4 are PFETs and transistors M5 to M7 are NFETs. The controller circuit system 500 also shows a capacitor C. SG and C GS C SG C is the source-gate capacitance of transistor M2, and C GS This is the gate-source capacitance of transistor M6.

[0046] exist Figure 5In one example, the first terminal 510 of the error amplifier 508 is coupled to a VOUT source (e.g., the output terminal of the power stage). In other examples, the first terminal 510 of the error amplifier 508 is coupled to a VFB source (e.g., a voltage divider terminal between the output terminal of the power stage and the first terminal 510). The second terminal 512 of the error amplifier 508 is coupled to a VREF (or target VOUT) source. The third terminal 514 of the error amplifier 508 is coupled to the first terminal of resistor R1 and the control terminals of transistors M2 and M6. The second terminal of resistor R1 is coupled to the first terminal of capacitor C1. The second terminal of capacitor C1 is coupled to ground or a ground terminal. The first terminals of transistors M1 and M4 are coupled to voltage supply terminal 502. The second terminal of transistor M1 is coupled to the first terminals of transistors M2 and M3 and applies bias current (I0). TAIL The second terminals of transistors M2 and M3 are coupled to other circuitry of comparator 516. The control terminal of transistor M3 is coupled to a ramp generator (e.g., Figure 3 (in the slope generator 302) or Figure 4 The slow loop result is as follows. The control terminals of transistors M1 and M4 are coupled to the dynamic bias circuit system, which provides: lower current during the pause interval of DCM operation; and higher current during CCM operation. The second terminal of transistor M4 is coupled to the first terminal of transistor M5 and the control terminals of transistors M5 and M7. The second terminals of transistors M5 and M7 are coupled to ground or a ground terminal. The first terminal of transistor M7 is coupled to the second terminal of transistor M6.

[0047] exist Figure 5 In this example, error amplifier 508 is used to: receive VOUT (or VFB) at a first terminal 510; receive VREF at a second terminal 512; and provide the error amplifier result (GM_OUT) at a third terminal in response to VOUT (or VFB) and VREF. Compensation circuitry 528 is used to adjust GM_OUT (e.g., reduce the amplitude of GM_OUT) to account for the amplitude loss due to the capacitance C. SG and C GS The change in GM_OUT caused by charge transfer from the dynamic bias circuit system 524 (e.g., an increase in the amplitude of GM_OUT). In some instances, the compensation circuit system 528 reduces GM_OUT below a threshold or maintains GM_OUT within the target voltage range.

[0048] In some instances, the compensation circuit system 528 generates a value relative to I. TAIL The opposite current / charge. If the comparator circuit system 516 includes Figure 5In the PMOS input pair (transistors M2 and M3), current flows out of the input pair transistors (e.g., transistor M2) and the corresponding source-to-gate voltage (V) SG The current increases if the comparator circuit system 516 includes an NMOS input pair (replacing transistors M2 and M3 with NMOS transistors), then current flows into the input pair transistors (e.g., transistor M2 is replaced) and the corresponding V... GS Increase. Using compensation circuitry 528, zero net current entering or leaving the comparator input is possible (where comparator circuitry 516 uses NMOS or PMOS input-pair transistors). In some instances, input-pair transistors M2 and M3, and transistor M6, have matched areas and gate-to-source capacitances, such that V GS The response to dynamic bias is approximately the same. In some instances, the compensation circuitry system 528 is insensitive to first-order processes. Despite the use of different transistor types (NMOS and PMOS), V GS Changes and C GS Similarly. In some instances, transistors M2, M3, and M6 have the same gate oxide thickness.

[0049] The compensation circuit system 528 is used to adjust the comparison result, thereby avoiding switching bursts during DCM operation. The use of the dynamic bias circuit system 524, the compensation circuit system 528, and the comparator 516 reduces power consumption during the corresponding DCM operation, while avoiding switching bursts to reduce VOUT ripple and improve the efficiency of the power stage controlled by the controller. When multiple controllers, such as controller circuit system 500, are used, the efficiency improvement of the corresponding power stage is cumulative, which provides benefits such as reducing vehicle (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 The power consumption of the computer rack 200 in the middle; extending the battery life (e.g., Figure 1 The charging duration and lifespan of the battery 102 in the vehicle; reducing the vehicle's (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 Undesirable heat emissions from electronic devices in the computer rack 200; and reducing vehicle (e.g., Figure 1 Vehicle 100) or computer rack (e.g., Figure 2 The heat sink / cooling overhead of electronic devices in the computer rack 200.

[0050] Figure 6 To demonstrate the controller (e.g., Figure 1 Each of the corresponding controllers 122A to 122N in the series Figure 2 Each of the corresponding controllers 222A to 222N in the series Figure 3Controller 300 in Figure 4 Controller 400 or Figure 5 Timing diagram 600 shows an example waveform of the controller circuit system 500 in the document. More specifically, timing diagram 600 contains example waveforms during the pause interval of the DCM operation described herein. The example waveforms include I... TAIL 602, ramp 604, first GM_OUT 606 (no compensation), second GM_OUT 608 (compensated), first comparator result 610 (no compensation), and second comparator result 612 (compensated).

[0051] like Figure 6 As shown, I TAIL Before time T1, it has a first value (e.g., 1.3 μA) (e.g., due to the low quiescent current provided by the dynamic bias circuitry system during the DCM pause interval). At time T1, the first comparator result 610 and the second comparator result 612 are asserted to indicate that VOUT or VFB has dropped below VREF or the target VOUT. In response, I TAIL The current begins to increase (e.g., due to the dynamic bias circuitry system increasing from a low quiescent current to a higher current when a DCM pulse is needed or when transitioning to CCM). Without compensation, the first GM_OUT 606 increases due to dynamic bias (after time T1). TAIL The increase is due to the increase in I (and local capacitance), as described herein. Using the first GM_OUT 606, the first comparator result 610 is asserted until time T3, and a switching burst occurs, specifically manifested as a continuous positive slope in ramp 604. Using compensation, the second GM_OUT 608 is unaffected by I after time T1. TAIL The increased impact. By utilizing the second GM_OUT 608, the second comparator result 612 is deasserted at time T2, and switching bursts of the power stage switches are avoided.

[0052] Figure 7 To demonstrate the power stage and controller (e.g., Figure 1 Each of the corresponding controllers 122A to 122N in the series Figure 2 Each of the corresponding controllers 222A to 222N in the series Figure 3 Controller 300 in Figure 4 Controller 400 or Figure 5Timing diagram 700 shows example waveforms of the controller circuit system 500 in the document. More specifically, timing diagram 700 contains example waveforms during the pause interval of the DCM operation described herein. The example waveforms include first inductor current 702 (compensated), second inductor current 704 (uncompensated), first VOUT 706 (compensated), second VOUT 708 (uncompensated), first GM_OUT 710 (compensated), second GM_OUT 712 (uncompensated), first ramp 714 (compensated), second ramp 716 (uncompensated), first comparator result 718 (compensated), and second comparator result 720 (uncompensated).

[0053] At time T1, the first comparator result 718 and the second comparator result 720 are asserted to indicate that VOUT or VFB has fallen below VREF or the target VOUT. In response, I TAIL (See example) Figure 6 I in TAIL The current begins to increase (e.g., due to the dynamic bias circuitry system increasing from a low quiescent current to a higher current when a DCM pulse is needed or when transitioning to CCM). Without compensation, the first GM_OUT 712 increases due to dynamic bias (after time T1). TAIL The increase is due to the increase in the second comparator result 720. Using the first GM_OUT 712, the second comparator result 720 holds the assertion until time T3, and a switching burst occurs, specifically manifested as a multi-stage change in the second inductor current 704 and the second ramp 716 (first rising-falling, then rising-falling, and then stabilizing). With compensation, the first GM_OUT 710 is unaffected by the increase in the second comparator result 720 after time T1. TAIL The increased impact. Using the first GM_OUT 710, the first comparator result 718 is deasserted at time T2, and the switching burst of the power stage switch is avoided. Specifically, the first inductor current 702 and the first ramp 714 change in a single stage (first rise-fall, then tend to stabilize).

[0054] In some instances, a system (e.g., Figure 1 Vehicle 100 Figure 2 The computer rack 200 or other system in the system contains: a load (e.g., Figure 1 The load is one of 160A to 160N or Figure 2 The load in the circuit is one of 260A to 260N; a circuit with a switch (e.g., Figure 1 One of the power stages 114A to 114N or Figure 2 The power stage is one of 214A to 214N, coupled to a load; and a controller coupled to a circuit (e.g., Figure 1 One of the controllers 122A to 122N in the middle Figure 2 One of the controllers 222A to 222N in the middle Figure 3 Controller 300 in Figure 4 Controller 400 or Figure 5 The controller circuit system 500 in the example. In such instances, the controller includes a comparator (e.g., Figure 1 One of the comparators 124A to 124N in the middle Figure 2 One of the comparators 224A to 224N in the middle Figure 3 Comparator 316 in Figure 4 The comparator 416 in the middle has a first terminal (e.g., Figure 1 One of the first terminals 126A to 126N, Figure 2 One of the first terminals 226A to 226N, Figure 3 The first terminal 318 or Figure 4 The first terminal 418), the second terminal (e.g., Figure 1 One of the second terminals 128A to 128N, Figure 2 One of the second terminals 228A to 228N, Figure 3 The second terminal 320 or Figure 4 The second terminal 420), the third terminal (e.g., one of the third terminals 130A to 130N, one of the third terminals 230A to 230N), Figure 3 The third terminal 321 or Figure 4 The third terminal 421), and the fourth terminal (e.g., Figure 1 One of the fourth terminals 132A to 132N, Figure 2 One of the fourth terminals 232A to 232N, Figure 3 The fourth terminal 322 or Figure 4 The fourth terminal 422 in the middle.

[0055] In such instances, the controller is configured such that: at the third terminal of the comparator (e.g., Figure 1 The third terminal 130A to 130N in Figure 2 The third terminal 230A to 230N in Figure 3 The third terminal 321 in Figure 4 The third terminal 421 or Figure 5 The first current (or first bias current, or IT) is received at the first terminal of transistors M2 and M3 in this document. TAIL (value); in response to entering the pause mode where the switch is open, a second current (e.g., the second bias current or I in this document) is received at the third terminal of the comparator. TAILThe second current is less than the first current; during the pause mode, at the first terminal of the comparator (e.g., Figure 1 One of the first terminals 126A to 126N, Figure 2 One of the first terminals 226A to 226N, Figure 3 The first terminal 318 in Figure 4 The first terminal 418 or Figure 5 The first signal (e.g.,) is received at the control terminal of transistor M2. Figure 1 Or one of the signals IN1_A to IN1_N in step 2 Figure 3 The signal IN1 in the first signal is compensated to generate a compensated first signal (e.g., Figure 6 The second GM_OUT or Figure 7 The first GM_OUT 710 in the comparator, after compensation, has a lower amplitude than the first signal; at the second terminal of the comparator (e.g., Figure 1 One of the second terminals 128A to 128N, Figure 2 One of the second terminals 228A to 228N, Figure 3 The second terminal 320 in Figure 4 The second terminal 420 or Figure 5 The second signal (e.g., at the control terminal of transistor M3) is received. Figure 1 Or one of the signals IN2_A to IN2_N in 2 or Figure 3 The signal IN2); in response to the compensated first and second signals, at the fourth terminal of the comparator (e.g., Figure 1 One of the fourth terminals 132A to 132N, Figure 2 One of the fourth terminals 232A to 232N, Figure 3 The fourth terminal 322 or Figure 4 The comparator result is provided at the fourth terminal 422; and a control signal is provided to the switch in response to the comparator result. In some instances, the control signal for the switch results in high-side conduction intervals separated by pause intervals. By utilizing the compensated first signal and the associated comparator result, the control signal for the switch avoids switch bursts that occur with consecutive high-side conduction intervals without pause intervals.

[0056] In some instances, the load is a first load, the circuit is a first circuit, the controller is a first controller, the switch is a first switch, the comparator is a first comparator, the compensation is a first compensation, the comparator result is a first comparator result, and the system further includes: a second load; a second circuit having a second switch (e.g., a second power stage in this document), the second circuit being coupled to the second load; and a second controller coupled to the second circuit. The second controller (e.g., Figure 1 The other of the controllers 122A to 122N in the middle, Figure 2 The other of the controllers 222A to 222N, Figure 3 Another controller 300 in the middle, Figure 4 Another controller 400 or Figure 5 Another controller circuit system 500 in the system includes a second comparator having a first terminal, a second terminal, a third terminal, and a fourth terminal.

[0057] In some instances, the second controller is configured to: at the third terminal of the second comparator (e.g., Figure 1 The other third terminal in the middle is 130A to 130N. Figure 2 The other third terminal 230A to 230N, Figure 3 The other third terminal 321 in Figure 4 Another third terminal 421 or Figure 5 A third current (e.g., the first bias current for the second comparator or I) is received at another first terminal of transistors M2 and M3. TAIL (value); in response to entering the pause mode where the second switch is open, a fourth current (e.g., the second bias current or I for the second comparator) is received at the third terminal of the second comparator. TAIL The fourth current is less than the third current; during the pause mode, at the first terminal of the second comparator (e.g., Figure 1 The other of the first terminals 126A to 126N, Figure 2 The other of the first terminals 226A to 226N, Figure 3 The other first terminal 318 in Figure 4 Another first terminal 418 or Figure 5 The third signal (e.g., at the control terminal of another transistor M2 in the middle) is received at the control terminal. Figure 1 Or, the signal from IN1_A in step 2 to the other signal in IN1_N. Figure 3 Another signal IN1 in the signal; apply a second compensation to the third voltage to generate a compensated third signal (e.g., Figure 6 Another second GM_OUT or Figure 7 Another first GM_OUT 710 in the second comparator), the compensated third signal has a lower amplitude than the third signal; at the second terminal of the second comparator (e.g., Figure 1 The other of the second terminals 128A to 128N, Figure 2 The other of the second terminals 228A to 228N, Figure 3 The other second terminal 320 in Figure 4 Another second terminal 420 or Figure 5The fourth signal (e.g., at the control terminal of another transistor M3) is received. Figure 1 Or one of the signals IN2_A to IN2_N in 2 or Figure 3 The signal IN2 in the second comparator is used to provide a second comparator result in response to the compensated third and fourth signals; and a control signal is provided for the second switch in response to the second comparator result. In some instances, the control signal for the second switch results in high-side conduction intervals separated by pause intervals. By utilizing the compensated third signal and the associated second comparator result, the control signal for the second switch avoids switch bursts that occur with consecutive high-side conduction intervals without pause intervals.

[0058] In some instances, the system is a computer rack (e.g., Figure 2 The system is a computer rack 200, and the first and second loads are processors. In some instances, the system is a vehicle (e.g., Figure 1 The vehicle 100 in the middle, and the first load and the second load are the processor.

[0059] In some instances, the controller includes a first control loop (e.g., error amplifier 408, first terminal 418 of comparator 416, and inductor L1) and a second control loop (e.g., Figure 4 The second control loop is slower than the first control loop. The first terminal of the comparator (e.g., first terminal 418) is coupled to the first control loop, and the second terminal of the comparator (e.g., second terminal 420) is coupled to the second control loop.

[0060] In some instances, the controller is configured to apply compensation by generating a negative current or charge to counteract the increase in amplitude of the first signal due to dynamic bias. In some instances, the comparator comprises NMOS input pair transistors (e.g., replacing transistors M2 and M3 with NMOS transistors), and compensation is performed by a compensation circuit system comprising PMOS transistors (replacing transistor M6 with PMOS transistors). The NMOS input pair transistors and PMOS transistors in the compensation circuit system have approximately the same gate-source capacitance and gate oxide thickness.

[0061] In some instances, the comparator includes a PMOS input pair transistor (e.g., Figure 5 Transistors M2 and M3 in the transistors), and consisting of NMOS transistors (e.g., Figure 5 The compensation circuit system (using transistor M6 in the transistor) performs the compensation. In some instances, the PMOS input of the compensation circuit system is paired with the transistor (e.g., Figure 5 Transistors M2 and M3) and NMOS transistors (e.g., Figure 5The transistor M6 in the middle has approximately the same gate-source capacitance and gate oxide thickness.

[0062] In some instances, a circuit (e.g., a comparator, LDO, or other circuit with input-pair transistors and high / low power mode options) includes: a first transistor (e.g., Figure 5 The transistor M2 has a first terminal, a second terminal, and a control terminal; the second transistor (e.g., Figure 5 Transistor M3 in the circuit has a first terminal, a second terminal, and a control terminal, wherein the first transistor and the second transistor form an input pair; a dynamic bias circuit system (e.g., Figure 5 The dynamic bias circuit system 524 includes a third transistor having a first terminal, a second terminal, and a control terminal (e.g., Figure 5 In the transistor M1), the second terminal of the third transistor is coupled to the first terminal of the first transistor and the second transistor; and the compensation circuit system (e.g., Figure 5 The compensation circuit system 528 is coupled to the control terminal of the first transistor. The compensation circuit system is configured to compensate the signal at the control terminal of the first transistor. The compensation reduces the amplitude of the signal.

[0063] In some instances, the compensation circuit system includes: a fourth transistor (e.g., Figure 5 The transistor M6 in the fourth transistor has a first terminal, a second terminal, and a control terminal, and the control terminal of the fourth transistor is coupled to the control terminal of the first transistor; the fifth transistor (e.g., Figure 5 The fifth transistor (M7) has a first terminal, a second terminal, and a control terminal; the first terminal of the fifth transistor is coupled to the second terminal of the fourth transistor; the sixth transistor (e.g., Figure 5 The transistor M5 in the middle has a first terminal, a second terminal and a control terminal, the second terminal of the sixth transistor is coupled to the second terminal of the fifth transistor; and the seventh transistor (e.g., Figure 5 The transistor M4 in the middle has a first terminal, a second terminal and a control terminal. The first terminal of the seventh transistor is coupled to the first terminal of the fourth transistor and the first terminal of the third transistor. The second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor and the control terminals of the fourth transistor and the fifth transistor.

[0064] In some instances, the first, second, and seventh transistors are NMOS transistors, and the fourth, fifth, and sixth transistors are PMOS transistors. In some instances, the first, second, and seventh transistors are PMOS transistors, and the fourth, fifth, and sixth transistors are NMOS transistors. In some instances, the first, second, and fourth transistors have substantially the same gate-source capacitance and gate oxide thickness.

[0065] In some instances, a circuit (e.g., Figure 1 One of the controllers 122A to 122N in the middle Figure 2 One of the controllers 222A to 222N in the middle Figure 3 Controller 300 in Figure 4 Controller 400 or Figure 5 The controller circuit system 500 in the middle includes: an error amplifier (e.g., Figure 3 Error amplifier 308 in Figure 4 Error amplifier 408 or Figure 5 The error amplifier 508 in the middle has a first terminal, a second terminal and a third terminal; the comparator (e.g., Figure 1 One of the comparators 124A to 124N in the middle Figure 2 One of the comparators 224A to 224N in the middle Figure 3 The comparator 316 or Figure 4 The comparator 416 has a first terminal, a second terminal, a third terminal, and a fourth terminal, the second terminal of the comparator being coupled to the third terminal of the error amplifier; a dynamic bias circuit system (e.g., Figure 1 One of the dynamic bias circuit systems 134A to 134N in the system. Figure 2 One of the dynamic bias circuit systems 234A to 234N in the system. Figure 3 The dynamic bias circuit system 324 or Figure 4 The dynamic bias circuit system 424 in the comparator is coupled to the third terminal of the comparator; and the compensation circuit system (e.g., Figure 1 One of the compensation circuit systems 138A to 138N in the system. Figure 2 One of the compensation circuit systems 238A to 238N in the system. Figure 3 The compensation circuit system 328 or Figure 4 The compensation circuit system 428 in the first transistor is coupled to the first terminal of the comparator and can be configured to apply compensation to the signal at the control terminal of the first transistor.

[0066] In some instances, the signal is a first signal, and the comparator is configured to: receive a first current from a dynamic bias circuit system at a third terminal of the comparator; receive a second current from the dynamic bias circuit system at the third terminal of the comparator in response to a pause mode, the second current being less than the first current; receive the first signal at a first terminal of the comparator during the pause mode; apply compensation to the first signal using a compensation circuit system, the compensation producing a compensated first signal having a lower amplitude than the first signal; receive the second signal at a second terminal of the comparator; and provide a comparator result at a fourth terminal of the comparator in response to the compensated first and second signals.

[0067] In some instances, the circuit also includes control logic and driver circuitry with first and second terminals (e.g., Figures 1 to 4 The control logic and driver circuitry options), the first terminal of the control logic and driver circuitry is coupled to the fourth terminal of the comparator; an inductor having a first terminal and a second terminal (e.g., Figure 5 Inductor L1 or Figure 1 and 2 (The corresponding inductor in the power stage), the first terminal of the inductor is coupled to the second terminal of the control logic and driver circuit system, and the second terminal of the inductor is coupled to the third terminal of the comparator.

[0068] In some instances, the comparator includes: a first transistor (e.g., Figure 5 The transistor M2 has a first terminal, a second terminal, and a control terminal; and a second transistor (e.g., Figure 5 The transistor MM in the circuit has a first terminal, a second terminal, and a control terminal, and the first transistor and the second transistor form an input pair. The dynamic bias circuit system includes a third transistor (e.g., Figure 5 The third transistor (M1) has a first terminal, a second terminal, and a control terminal. The second terminal of the third transistor is coupled to the first terminal of the first transistor and the first terminal of the second transistor. The compensation circuit system includes: a fourth transistor (e.g., Figure 5 Transistor M6 in the middle); the fifth transistor (for example, Figure 6 Transistor M7 in the middle); the sixth transistor (e.g., Figure 5 Transistor M5); and the seventh transistor (e.g., Figure 5Transistor M4 in the example. The fourth transistor has a first terminal, a second terminal, and a control terminal. The control terminal of the fourth transistor is coupled to the control terminal of the first transistor. The fifth transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the fifth transistor is coupled to the second terminal of the fourth transistor. The sixth transistor has a first terminal, a second terminal, and a control terminal. The second terminal of the sixth transistor is coupled to the second terminal of the fifth transistor. The seventh transistor has a first terminal, a second terminal, and a control terminal. The first terminal of the seventh transistor is coupled to the first terminal of the fourth transistor and the first terminal of the third transistor. The second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor and the control terminals of the fourth and fifth transistors. In some examples, the first, second, and fourth transistors have approximately the same gate-source capacitance and gate oxide thickness.

[0069] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0070] Furthermore, in this specification, the term "based on" means "at least partially based on". Therefore, if X is based on Y, then X can depend on Y and any number of other factors.

[0071] A device “configured to” or “configurable to” perform a task or function may be configured by the manufacturer at the time of manufacture (e.g., programmed and / or hardwired) to perform the function and / or may be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. Such configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components and the interconnection of the device, or a combination thereof.

[0072] As used herein, the terms “terminal,” “node,” “interconnect,” “lead,” and “pin” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components and / or conductors.

[0073] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacture by an end user and / or a third party.

[0074] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the rest of the circuit system. For example, field-effect transistors (“FETs”) (e.g., NFETs or PFETs), bipolar junction transistors (BJTs – e.g., NPN or PNP transistors), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices described herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in or on a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0075] Reference may be made to the control terminal of the transistor, as well as its first and second terminals, in the claims. In the context of a FET, the control terminal is the gate, and the first and second terminals are the drain and source, respectively. In the context of a BJT, the control terminal is the base, and the first and second terminals are the collector and emitter, respectively.

[0076] In this article, "FET on" means that a conductive channel exists in the FET and drain current can flow through it. "FET off" means that no conductive channel exists, and therefore drain current does not flow through the FET. However, a "off" FET can still have current flowing through the body diode of a transistor.

[0077] The circuits described herein can be reconfigured to include additional or different components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0078] While some elements of the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all features shown as external to the integrated circuit may be contained within the integrated circuit, and / or some features shown as internal to the integrated circuit may be external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0079] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings herein. In this specification, unless otherwise stated, "about," "approximately," or "substantially" preceding a parameter means within + / - 10% of the parameter, or, if the parameter is zero, within a reasonable range of approximately zero.

[0080] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. A system comprising: load; A circuit having a switch, the circuit being coupled to the load; as well as A controller, coupled to the circuit, includes a comparator having a first terminal, a second terminal, a third terminal, and a fourth terminal, and the controller is configurable to: The first current is received at the third terminal of the comparator; In response to entering the pause mode where the switch is open, a second current is received at the third terminal of the comparator, the second current being less than the first current; During the pause mode, a first signal is received at the first terminal of the comparator; Compensation is applied to the first signal to generate a compensated first signal, which has a lower amplitude than the first signal; A second signal is received at the second terminal of the comparator; In response to the compensated first signal and the second signal, a comparison result is provided at the fourth terminal of the comparator; as well as In response to the comparator result, a control signal is provided to the switch.

2. The system according to claim 1, wherein the load is a first load, the circuit is a first circuit, the controller is a first controller, the switch is a first switch, the comparator is a first comparator, the compensation is a first compensation, the comparison result is a first comparison result, and the system further comprises: Second load; A second circuit having a second switch, the second circuit being coupled to the second load; as well as A second controller, coupled to the second circuit, includes a second comparator having a first terminal, a second terminal, a third terminal, and a fourth terminal, and the second controller can be configured to: A third current is received at the third terminal of the second comparator; In response to entering a pause mode where the second switch is open, a fourth current is received at the third terminal of the second comparator, the fourth current being less than the third current; During the pause mode, a third signal is received at the first terminal of the second comparator; A second compensation is applied to the third signal to generate a compensated third signal, which has a lower amplitude than the third signal. The fourth signal is received at the second terminal of the second comparator; In response to the compensated third signal and the fourth signal, a second comparison result is provided at the fourth terminal of the comparator; as well as In response to the second comparison result, a control signal is provided to the second switch.

3. The system of claim 2, wherein the system is a computer rack, and the first load and the second load are processors.

4. The system of claim 2, wherein the system is a vehicle, and the first load and the second load are processors.

5. The system of claim 1, wherein the controller includes a first control loop and a second control loop, the second control loop being slower than the first control loop, the first terminal of the comparator being coupled to the first control loop, and the second terminal of the comparator being coupled to the second control loop.

6. The system of claim 1, wherein the controller is configured to apply the compensation by generating a negative current or charge to counteract the increase in amplitude of the first signal due to dynamic bias.

7. The system of claim 1, wherein the comparator comprises an n-channel metal-oxide-semiconductor (NMOS) input pair transistor, and the compensation is performed by a compensation circuit system comprising a p-channel metal-oxide-semiconductor (PMOS) transistor.

8. The system of claim 7, wherein the NMOS input pair transistor of the comparator and the PMOS transistor of the compensation circuit system have substantially the same gate-source capacitance and gate oxide thickness.

9. The system of claim 1, wherein the comparator comprises a p-channel metal-oxide-semiconductor (PMOS) input pair transistor, and the compensation is performed by a compensation circuit system comprising an n-channel metal-oxide-semiconductor (NMOS) transistor.

10. The system of claim 9, wherein the PMOS input pair transistor of the comparator and the NMOS transistor of the compensation circuit system have substantially the same gate-source capacitance and gate oxide thickness.

11. A circuit comprising: The first transistor has a first terminal, a second terminal, and a control terminal; The second transistor has a first terminal, a second terminal and a control terminal, and the first transistor and the second transistor form an input pair transistor; A dynamic bias circuit system comprising a third transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the third transistor is coupled to the first terminal of the first transistor and the first terminal of the second transistor; as well as A compensation circuit system coupled to the control terminal of the first transistor, the compensation circuit system being configurable to apply compensation to the signal at the control terminal of the first transistor, the compensation reducing the amplitude of the signal.

12. The circuit of claim 11, wherein the compensation circuit system comprises: A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the fourth transistor is coupled to the control terminal of the first transistor; A fifth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is coupled to the second terminal of the fourth transistor; A sixth transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the sixth transistor is coupled to the second terminal of the fifth transistor; as well as A seventh transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is coupled to the first terminal of the fourth transistor and the first terminal of the third transistor, and the second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor and the control terminal of the fourth transistor and the fifth transistor.

13. The circuit of claim 12, wherein the first transistor, the second transistor, and the seventh transistor are n-channel metal-oxide-semiconductor (NMOS) transistors, and the fourth transistor, the fifth transistor, and the sixth transistor are p-channel metal-oxide-semiconductor (PMOS) transistors.

14. The circuit of claim 12, wherein the first transistor, the second transistor, and the seventh transistor are p-channel metal-oxide-semiconductor (PMOS) transistors, and the fourth transistor, the fifth transistor, and the sixth transistor are n-channel metal-oxide-semiconductor (NMOS) transistors.

15. The circuit of claim 12, wherein the first transistor, the second transistor, and the fourth transistor have substantially the same gate-source capacitance and gate oxide thickness.

16. A circuit comprising: An error amplifier having a first terminal, a second terminal, and a third terminal; A comparator having a first terminal, a second terminal, a third terminal, and a fourth terminal, wherein the second terminal of the comparator is coupled to the third terminal of the error amplifier; A dynamic bias circuit system coupled to the third terminal of the comparator; as well as A compensation circuit system coupled to the first terminal of the comparator and configured to apply compensation to the signal at the first terminal of the comparator.

17. The circuit of claim 16, wherein the signal is a first signal, and the comparator is configured to: A first current is received from the dynamic bias circuit system at the third terminal of the comparator; In response to the pause mode, a second current is received from the dynamic bias circuit system at the third terminal of the comparator, the second current being less than the first current; During the pause mode, the first signal is received at the first terminal of the comparator; The compensation circuit system is used to compensate the first signal, and the compensation generates a compensated first signal having a lower amplitude than the first signal. A second signal is received at the second terminal of the comparator; as well as In response to the compensated first signal and the second signal, a comparison result is provided at the fourth terminal of the comparator.

18. The circuit of claim 16, further comprising: A control logic and driver circuit system having a first terminal and a second terminal, wherein the first terminal of the control logic and driver circuit system is coupled to the fourth terminal of the comparator; as well as An inductor having a first terminal and a second terminal, the first terminal of the inductor being coupled to the second terminal of the control logic and driver circuitry, and the second terminal of the inductor being coupled to the third terminal of the comparator.

19. The circuit according to claim 16, The comparator includes: A first transistor having a first terminal, a second terminal, and a control terminal; and The second transistor has a first terminal, a second terminal, and a control terminal, and the first transistor and the second transistor form an input pair transistor. The dynamic bias circuit system includes a third transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the third transistor is coupled to the first terminal of the first transistor and the first terminal of the second transistor, and The compensation circuit system includes: A fourth transistor having a first terminal, a second terminal, and a control terminal, wherein the control terminal of the fourth transistor is coupled to the control terminal of the first transistor; A fifth transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the fifth transistor is coupled to the second terminal of the fourth transistor; A sixth transistor having a first terminal, a second terminal, and a control terminal, wherein the second terminal of the sixth transistor is coupled to the second terminal of the fifth transistor; as well as A seventh transistor having a first terminal, a second terminal, and a control terminal, wherein the first terminal of the seventh transistor is coupled to the first terminal of the fourth transistor and the first terminal of the third transistor, and the second terminal of the seventh transistor is coupled to the first terminal of the sixth transistor and the control terminal of the fourth transistor and the fifth transistor.

20. The circuit of claim 19, wherein the first transistor, the second transistor, and the fourth transistor have substantially the same gate-source capacitance and gate oxide thickness.

Images