Drive circuit arrangement, control method, device, medium and product

Abstract

Embodiments of the present application provide a driving circuit device, which can be applied to the technical field of integrated circuits. The driving circuit device is applied to load driving, which comprises a segmented regulation module, a logic control module and a symmetric charge pump module. The segmented regulation module is configured to output at least one regulation electric signal in stages according to a complete signal period of a target load signal; the logic control module is connected with the segmented regulation module and is configured to output at least two control logic signals according to each regulation electric signal in the at least one regulation electric signal; and the symmetric charge pump module is connected with the logic control module and is configured to output the target load signal to the load according to each control logic signal in the at least two control logic signals. Embodiments of the present application also provide a driving circuit device, a method, equipment, a storage medium and a program product.

Description

Technical Field

[0001] This invention relates to the field of circuit technology, specifically to the field of drive circuit technology, and more specifically to a drive circuit device, control method, equipment, medium, and product. Background Technology

[0002] Existing drive circuits for generating sinusoidal output voltages convert DC (Direct Current) voltage into a periodic sinusoidal output voltage through Boost-Buck, LC oscillation, or other methods to drive resistive, capacitive, or mixed resistive-capacitive loads. There are various architectures for existing drive circuits capable of generating sinusoidal output voltages, offering different solutions for different application scenarios. Boost-Buck converters are frequently used to generate the desired waveform. Boost (boost) and Buck (buck) converters serve as the core topology of inductive DC-DC converters, achieving voltage conversion through the coordinated operation of switching transistors, inductors, diodes, and output capacitors. Essentially, they control the inductor's energy storage and release through Pulse Width Modulation (PWM) or Pulse Frequency Modulation (PFM), outputting a DC or low-frequency pulse waveform. However, existing sinusoidal drive circuits typically suffer from problems such as susceptibility to waveform distortion, higher energy consumption and heat generation, complex and costly design and manufacturing, and larger size. Summary of the Invention

[0003] In view of at least one of the above-mentioned technical problems existing in the prior art, embodiments of the present invention provide a driving circuit device, control method, equipment, medium and product, in order to realize a new structure of multi-phase LC resonant driving circuit with high frequency sine wave, high efficiency, low cost and small area.

[0004] One aspect of the present invention provides a driving circuit device for load driving, including a segmented control module, a logic control module, and a symmetrical charge pump module. The segmented control module is configured to output at least one control electrical signal in stages according to the complete signal cycle of the target load signal; the logic control module is connected to the segmented control module and configured to output at least two control logic signals according to each of the at least one control electrical signal; and the symmetrical charge pump module is connected to the logic control module and configured to output the target load signal to the load according to each of the at least two control logic signals.

[0005] According to an embodiment of the present invention, the segmented control module includes a main control unit and at least one sub-control unit. One end of the main control unit is connected to a preset power supply level, and the other end is grounded. It is configured to control the segmented control module to achieve current bias. Each of the at least one sub-control unit is connected in parallel with the main control unit, and one end of the sub-control unit is connected to a preset power supply level, and the other end is grounded. It is configured to output one of the at least one control signal.

[0006] According to one embodiment of the present invention, the main control unit includes a reference current source and a reference current mirror. The input terminal of the reference current source is connected to a preset power supply level; the drain terminal of the reference current mirror is connected to the output terminal of the reference current source, and its source terminal is grounded; wherein, the drain terminal of the reference current mirror is connected to its gate terminal.

[0007] According to an embodiment of the present invention, each sub-control unit in at least one sub-control unit includes a control current source, a control capacitor, a control switch, and a control current mirror. The input terminal of the control current source is connected to a preset power supply level; one end of the control capacitor is connected to the output terminal of the control current source, and the other end is grounded; the control switch is connected in parallel with the control capacitor, and one end of the control switch is connected to the output terminal of the control current source; the control current mirror is connected in series with the control switch, and the drain terminal of the control current mirror is connected to the other end of the control switch, while its source terminal is grounded.

[0008] According to one embodiment of the present invention, the gate terminal of the reference current mirror is connected to the gate terminal of the control current mirror of each sub-control unit; the output terminal of the control current source of each sub-control unit is connected to the logic control module, and each sub-control unit, under the control of the parent control unit, outputs at least one control electrical signal corresponding to the stage of the control electrical signal to the logic control module.

[0009] According to an embodiment of the present invention, the logic control module includes a selector, a reference source unit, a comparator, and a charge pump logic unit. The selector provides multiple input terminals, each connected to at least one sub-control unit of the segmented control module, for receiving at least one control electrical signal. The reference source unit provides a reference signal. The comparator is connected to the output terminals of the selector and the reference source unit, respectively, and receives at least one control electrical signal output by the selector in stages. Based on the comparison result of each control electrical signal with the reference reference signal, it outputs a comparison logic signal for the corresponding stage. The charge pump logic unit is connected to the output terminal of the comparator and generates a logic combination signal for the corresponding stage based on the comparison logic signal. The logic combination signal is configured to generate a control logic signal for the corresponding stage of at least two control logic signals that conform to a preset state logic expression rule.

[0010] According to one embodiment of the present invention, a symmetrical charge pump module includes at least two charge pump structures that satisfy a preset circuit symmetry relationship. Each of the at least two charge pump structures includes at least one capacitor control subunit and a plurality of control switches. One end of each capacitor control subunit is connected to a preset power supply level, and the other end is grounded. The at least one capacitor control subunit is connected in parallel with each other. The plurality of control switches are connected in an array structure of the at least one capacitor control subunit and are configured to control the at least one capacitor control subunit according to the corresponding control logic signal of at least two received control logic signals.

[0011] According to one embodiment of the present invention, each capacitor control subunit includes a power switch, a control capacitor, and a grounding switch. One end of the power switch is connected to a preset power level; one end of the control capacitor is connected to the other end of the power switch; one end of the grounding switch is connected to the other end of the control capacitor, and its other end is grounded.

[0012] According to one embodiment of the present invention, the driving circuit device further includes an inductor. One end of the inductor is connected to the output terminal of one of the at least two charge pump structures of the symmetrical charge pump module, and the other end is connected to a load.

[0013] Another aspect of the present invention provides a control method for a drive circuit device of the above kind, applied to load drive, comprising: outputting at least one regulating electrical signal in stages according to the complete signal period of the target load signal; outputting at least two control logic signals according to each of the at least one regulating electrical signal; and outputting the target load signal to the load according to each of the at least two control logic signals.

[0014] Another aspect of the present invention provides an electronic device including one or more processors and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to perform the control method of the driving circuit device described above.

[0015] Another aspect of the present invention provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the control method of the aforementioned driving circuit device.

[0016] Another aspect of the present invention provides a computer program product, including a computer program that, when executed by a processor, implements the control method of the above-described drive circuit device.

[0017] The driving circuit device provided in this embodiment of the invention can at least partially solve the technical problems existing in related technologies, such as sine wave distortion, complex design, and large area size, and thus can achieve at least one of the following technical effects:

[0018] Therefore, based on the above-described driving circuit device of this invention, a driving waveform output architecture based on a charge pump architecture can be constructed, which can generate higher output waveforms without multi-stage cascading, and the circuit structure is simpler. Furthermore, by employing a symmetrical charge pump module, a target load signal (such as a sine wave) with an amplitude greater than the power rail can be generated even under low-voltage power rail conditions, thus avoiding the need for a boost circuit in the previous stage for voltage boosting in some higher-voltage application scenarios. In addition, with the help of the above-described segmented control module and logic control module, a more accurate target load signal can be generated, enabling flexible adjustment of the duration of each step (time stage) in a single waveform cycle. This makes the transition points between each stage and the overall waveform smoother and more aesthetically pleasing, improving performance indicators such as THD and expanding the application range in high-fidelity applications. Finally, compared with the traditional switching mode drive circuit architecture, the drive circuit device described in the embodiments of the present invention significantly reduces the switching frequency, has higher circuit control efficiency, and less loss. For example, it can further reduce the proportion of losses of the switch itself (including the charging and discharging losses of the switch junction capacitance and the conduction losses), and the efficiency can reach more than 90%. Furthermore, it can also reduce the strong electromagnetic radiation generated by high-frequency switches (MHz level), save on off-chip structures such as shielding and filtering, reduce the difficulty of PCB layout, simplify the overall structure, and make the actual circuit area smaller.

[0019] Therefore, the driving circuit device of this invention provides a novel structure for a multi-phase LC resonant driving circuit that can realize high-frequency sine waves, high efficiency, low cost, and small area. It can be used in various application scenarios that require strict area control while realizing boost and high-frequency (such as tens of kHz) sine wave driving signals (such as air pumps). It can be widely used in the fields of analog integrated circuits and power management, and has extremely high scientific research value and commercial application value.

[0020] It should be understood that the above general description and the following specific embodiments are merely exemplary and illustrative, and do not limit the scope of the invention. Attached Figure Description

[0021] The above-described features, other objects, and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0022] Figure 1 A schematic diagram illustrating the structural composition of a drive circuit device according to an embodiment of the present invention is shown.

[0023] Figure 2 A schematic diagram of a sinusoidal segmentation of a target load signal according to an embodiment of the present invention is shown.

[0024] Figure 3A This schematic diagram illustrates the structural composition of an eight-divider in the logic control module of a drive circuit device according to an embodiment of the present invention.

[0025] Figure 3B A schematic diagram illustrating the circuit implementation of the switching state logic expression of the driving circuit device according to an embodiment of the present invention is shown.

[0026] Figure 4 The illustration shows an embodiment of the present invention as follows. Figure 1 The inductor L to the left of point C and the load capacitor C of the drive circuit device shown LOAD Level change diagram between points B on the right;

[0027] Figure 5 A flowchart illustrating a control method for a drive circuit device according to an embodiment of the present invention is shown schematically; and

[0028] Figure 6 A block diagram of an electronic device suitable for implementing a control method for a drive circuit device according to an embodiment of the present invention is shown schematically.

[0029] The accompanying drawings mentioned above are part of the specification of embodiments of the present invention, illustrating exemplary embodiments of the invention. The drawings, together with the description in the specification, serve to illustrate the principles of the embodiments of the present invention. It should be understood that the above general description with reference to the drawings and the following detailed description are merely exemplary and illustrative, and do not limit the scope of the invention. Detailed Implementation

[0030] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the spirit of the contents disclosed in the present invention will be clearly explained below with reference to the accompanying drawings and detailed description. After understanding the embodiments of the present invention, any person skilled in the art can make changes and modifications based on the technology taught in the present invention without departing from the spirit and scope of the present invention.

[0031] The illustrative embodiments and descriptions of the present invention are used to explain the invention, but are not intended to limit the invention. Furthermore, elements / components using the same or similar reference numerals in the drawings and embodiments are used to represent the same or similar parts.

[0032] The terms "first," "second," etc., used in this invention do not specifically refer to any order or sequence, nor are they intended to limit the invention; they are merely used to distinguish elements or operations described using the same technical terms.

[0033] The directional terms used in this invention, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the scope of this invention.

[0034] The terms “comprising,” “including,” “having,” “containing,” etc., used in this invention are all open-ended terms, meaning that they include but are not limited to.

[0035] The term "and / or" as used in this invention includes any or all combinations of the things mentioned.

[0036] In this invention, "multiple" includes "two" and "more than two"; in this invention, "multiple groups" includes "two groups" and "more than two groups".

[0037] The terms "approximately," "about," etc., used in this invention are intended to modify any quantity or error that may vary slightly, but these slight variations or errors do not change the essence of the quantity or error. Generally, the range of slight variations or errors modified by such terms may be 20% in some embodiments, 10% in some embodiments, 5% in some embodiments, or other values. Those skilled in the art should understand that the aforementioned values ​​can be adjusted according to actual needs and are not limited thereto.

[0038] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0039] When expressions such as "at least one of A, B, and C" are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When expressions such as "at least one of A, B, or C" are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). Those skilled in the art should also understand that any conjunction and / or phrase that substantially arbitrarily indicates two or more optional items, whether in the specification, claims, or drawings, should be understood to indicate the possibility of including one of these items, either of these items, or both items. For example, the phrase “A or B” should be understood as including the possibility of “A” or “B”, or “A and B”.

[0040] In addition to the above-mentioned technical solutions that combine Boost-Buck converters to achieve voltage conversion through the coordinated use of switching transistors, inductors, diodes and output capacitors, existing technologies typically include: (1) linear amplifier solutions, such as Class A amplifiers and Class B amplifiers; (2) switch-mode amplifier solutions, such as Class D amplifiers and Class E amplifiers; and (3) resonant drive solutions, such as LLC resonant converters and series resonant inverters.

[0041] The three main implementation schemes based on the Boost-Buck architecture in the above-mentioned existing technologies are briefly described below:

[0042] (1) Pulse Width Modulation (PWM) Adjustment + LC Filtering: The target sine wave signal is compared with a high-frequency triangular wave to generate a PWM control signal, which drives the boost or buck switch, and the output pulse voltage is then filtered by LC low-pass to extract the fundamental component.

[0043] (2) Resonant DC-DC converter: In the buck topology, a series LC resonant network is introduced to generate a sinusoidal current by utilizing the resonant characteristics, and the sinusoidal voltage is extracted by synchronous rectification.

[0044] (3) Multiphase parallel synthesis: Multi-phase interleaved boost or buck units are used, and each unit outputs a sine segment signal, which is then superimposed to synthesize a complete sine wave.

[0045] Class A amplifiers operate based on the linear amplification characteristics of transistors. In a Class A amplifier, the transistor remains on throughout the entire signal cycle; that is, regardless of the magnitude of the input signal, the base current of the transistor is always present and it is never completely cut off. This operating principle ensures that Class A amplifiers provide very linear amplification characteristics, meaning that the output signal maintains a strictly linear relationship with the input signal, resulting in extremely low distortion. Therefore, Class A amplifiers are commonly used in high-end speaker systems, professional audio equipment, and precision measuring instruments.

[0046] Unlike traditional Class A, Class B, and Class AB amplifiers, Class D amplifiers operate in a switching mode, with modulation and demodulation being their core processes. Modulation converts the analog audio signal into a PWM signal, while demodulation restores the PWM signal back to the analog audio signal. The modulator uses a triangular wave as the carrier and the audio signal as the modulation signal. When the amplitude of the audio signal is higher than the amplitude of the triangular wave, the PWM signal is high; when the amplitude is lower, the PWM signal is low. In this way, the amplitude information of the audio signal is converted into the duty cycle of the PWM signal. The switching element operates according to the high and low levels of the PWM signal. When the PWM signal is high, the switching element is on, and current is output; when the PWM signal is low, the switching element is off, and the output current is zero. The output filter filters the pulse current output by the switching element to recover the analog audio signal. Class D amplifiers are commonly used in portable audio devices, home theater systems, and professional audio equipment.

[0047] An LLC resonant converter is a power converter based on the principle of resonant oscillation. It is widely used in power electronics due to its high efficiency, low electromagnetic interference, and wide input / output range. During operation, the LLC resonant converter controls the switching time and frequency of the switching transistors to induce resonant oscillation between the primary and secondary coils. In this resonant state, electrical energy can be efficiently converted between the primary and secondary coils and ultimately output to the load. The control circuit monitors load demand and input voltage fluctuations in real time, adjusting the switching time and frequency of the switching transistors to maintain the resonant state and achieve stable power conversion.

[0048] The existing solutions for sine wave drive circuits have the following shortcomings:

[0049] (1) For the traditional boost-buck architecture, the switching frequency may reach the megahertz (MHz) level under high amplitude and high frequency conditions. This leads to a significant increase in energy loss caused by frequent switching of the on state. Furthermore, due to the limitation of the inductor peak current, the generated drive waveform may not achieve the expected effect and may be distorted.

[0050] (2) For linear amplifiers, such as Class A amplifiers, since Class A amplifiers remain in the conducting state throughout the entire signal cycle, their static power consumption is relatively large, and their energy efficiency is not high due to the voltage difference of linear devices. This means that a lot of heat and power consumption will be generated during long-term operation.

[0051] (3) For switch-mode amplifier solutions, such as Class D amplifiers, the high-frequency switches (MHz level) generate strong electromagnetic radiation, requiring shielding and filtering. This increases the difficulty of printed circuit board (PCB) layout. Furthermore, when operating at the MHz level, the charging and discharging losses of the switching transistor junction capacitance account for over 30% (e.g., C). oss =100pF, loss reaches 0.5W at f=10MHz), and the output LC filter is bulky. Furthermore, the PWM signal output by the Class D amplifier needs to be converted back to an analog signal via a low-pass filter. However, the design and fabrication of a low-pass filter is relatively complex, requiring consideration of factors such as the filter's cutoff frequency, bandwidth, and impedance matching. When nonlinear distortion is introduced into the H-bridge switching dead time, especially at low amplitude outputs, the total harmonic distortion (THD) deteriorates (>2%).

[0052] (4) For resonant conversion schemes (such as LLC resonant converters), the dynamic response is usually slow, and the closed-loop control bandwidth is typically <10kHz, thus making it unable to quickly track sinusoidal modulation (e.g., waveform distortion is significant at >50kHz). Furthermore, LLC resonant converters have poor capacitive load adaptability, requiring the load capacitance to be much smaller than the resonant capacitance (C). load <0.1C r Otherwise, a resonant frequency shift will lead to efficiency failure. Furthermore, LLC converters are relatively complex to control, requiring precise frequency control to maintain stable output voltage, which may necessitate more complex control circuitry. Additionally, LLC resonant circuits require mutual inductance coils with very high inductance values, reaching tens of μH, resulting in large size, inconvenient integration, and unsuitability for portable devices.

[0053] In view of at least one of the above-mentioned technical problems existing in the prior art, embodiments of the present invention provide a driving circuit device, control method, equipment, medium and product, in order to realize a new structure of multi-phase LC resonant driving circuit with high frequency sine wave, high efficiency, low cost and small area.

[0054] To enable those skilled in the art to have a clearer understanding of the driving circuit device described in the embodiments of the present invention, the following further provisions are provided. Figures 1-6 Explanation.

[0055] like Figures 1-6 As shown, one aspect of an embodiment of the present invention provides a driving circuit device for load driving, including a segmented control module 101, a logic control module, and a symmetrical charge pump module.

[0056] The segmented control module 101 is configured to output at least one control electrical signal in stages according to the complete signal cycle of the target load signal;

[0057] The logic control module is connected to the segmented control module 101 and is configured to output at least two control logic signals according to each of the at least one control electrical signal; and

[0058] The symmetrical charge pump module is connected to the logic control module and is configured to output a target load signal to the load according to each of at least two control logic signals.

[0059] The target load signal is the target output waveform of the drive circuit device, and is usually also the optimal drive waveform for the target load driven by the drive circuit device. For example... Figure 2 As shown, the complete signal period of the target load signal can be the time period of a single complete signal waveform (t = Δt1 + Δt2 + ... + Δt8), corresponding to a complete sine wave waveform. The complete signal period can be divided into stages according to actual needs, such as... Figure 2 As shown, it can be divided into 8 time stages from Δt1 to Δt8. Each stage corresponds to a fixed time interval. The time intervals can be the same or different, and can be set according to the actual scenario.

[0060] The control signal can be the control signal output by the segmented control module 101 according to the stage corresponding to the complete signal cycle, used as the logic control processing of the logic control module. Specifically, within a time interval (i.e., stage) of the complete signal cycle, the segmented control module 101 can output one control signal; in multiple consecutive stages, one control signal can be output in each stage. This control signal can be a voltage signal or a current signal, and in some cases, it can be a specific signal code or encoding.

[0061] For example, within time interval Δt1, the segmented control module 101 can output the first control signal; then, entering time interval Δt2, the segmented control module 101 can output the second control signal within this time, and so on, sequentially traversing all stages within the complete signal cycle, outputting at least 8 control signals. The order in which the control signals are output can also be performed at different time stages. For example, the segmented control module 101 can first output the first control signal for time interval Δt8, and then output the second control signal within time interval Δt5, until all at least 8 control signals for the entire complete signal cycle are output; there is no specific limitation.

[0062] The signal input terminal of the logic control module is connected to the signal output terminal of the segmented control module 101. The logic control module can convert the input electrical signal according to preset logic circuit control rules. These logic circuit control rules can be signal conversion processing rules determined by preset circuit elements or circuit control units of the logic control module through specific connections. Specifically, for the control electrical signals output by the segmented control module 101 within different time intervals Δt, the logic control module can complete the processing and conversion of the corresponding control electrical signal within that time interval Δt, thereby outputting the corresponding control logic signal. This processing and conversion can be a process of generating a control logic signal in response to the processing of the control electrical signal, or it can be a process of directly processing the control electrical signal (such as amplitude amplification) to generate the control logic signal.

[0063] A symmetrical charge pump module can be a control circuit structure consisting of at least two charge pump structures. The module can have an even number of charge pump structures, arranged symmetrically (i.e., symmetrically connected to different ends of the load). Each charge pump structure is connected to a corresponding output terminal of the logic control module. For example, the output terminal of one charge pump structure can be connected to the left input terminal of the load, while the output terminal of the other symmetrical charge pump structure can be connected to the right input terminal of the load. Typically, the waveform output from one charge pump structure has a 180° phase difference with the waveform output from the other charge pump structure, allowing opposite polarity level changes to be generated on both sides of the load as driving signals (i.e., target load signals).

[0064] The logic control module can output corresponding control logic signals to the corresponding charge pump structures. These control logic signals can be electrical signals that control a single charge pump structure to output a specific waveform. Within a corresponding time interval Δt, all charge pump structures of the symmetrical charge pump module can output their respective waveforms based on the received control logic signals. These waveforms, when applied to the load, will exhibit the waveform characteristics of the target load signal, i.e., the output target load signal.

[0065] Therefore, based on the above-described driving circuit device of this invention, a driving waveform output architecture based on a charge pump architecture can be constructed, which can generate higher output waveforms without multi-stage cascading, and the circuit structure is simpler. Furthermore, by employing a symmetrical charge pump module, a target load signal (such as a sine wave) with an amplitude greater than the power rail can be generated even under low-voltage power rail conditions, thus avoiding the need for a boost circuit in the previous stage for voltage boosting in some higher-voltage application scenarios. In addition, with the help of the above-described segmented control module and logic control module, a more accurate target load signal can be generated, enabling flexible adjustment of the duration of each step (time stage) in a single waveform cycle. This makes the transition points between each stage and the overall waveform smoother and more aesthetically pleasing, improving performance indicators such as THD and expanding the application range in high-fidelity applications. Finally, compared to the traditional switching mode drive circuit architecture, the drive circuit device described in this embodiment of the invention significantly reduces the switching frequency, resulting in higher circuit control efficiency and less loss. For example, it can further reduce the proportion of losses inherent in the switch itself (including charging and discharging losses of the switch junction capacitance and conduction losses), achieving an efficiency of over 90%. Furthermore, it can reduce the strong electromagnetic radiation generated by high-frequency switching (MHz level), saving on off-chip structures such as shielding and filtering, reducing PCB layout difficulty, simplifying the overall structure, and requiring only a single inductor component, resulting in a smaller actual circuit area. The functional block diagram of the drive circuit device in this embodiment of the invention is as follows: Figure 1 As shown (taking a multi-phase LC resonant circuit structure as an example), the overall circuit is divided into three modules: segmented control module 101, logic control module, and symmetric charge pump module.

[0066] like Figures 1-6 As shown, according to an embodiment of the present invention, the segmented control module 101 includes a mother control unit 111 and at least one sub-control unit 112.

[0067] One end of the mother control unit 111 is connected to a preset power supply level V. SUP Its other end is grounded to GND and is configured to control the segmented regulation module 101 to achieve current bias;

[0068] At least one sub-control unit 112 is connected in parallel with the parent control unit 111, and one end of each sub-control unit 112 is connected to a preset power supply level V. SUP Its other end is grounded and is configured to output one of at least one control signal.

[0069] The main control unit 111 and each sub-control unit 112 are connected in parallel to the ground wire GND and the preset power supply level V. SUP In the circuit between the corresponding power rails, the main control unit can perform separate or simultaneous current bias control on different sub-control units within the corresponding time interval Δt, thereby enabling the segmented control module 101 to output corresponding control electrical signals to the logic control module at different stages.

[0070] like Figures 1-6 As shown, according to an embodiment of the present invention, the mother control unit 111 includes a reference current source I. REF and reference current mirror M REF .

[0071] Reference current source I REF The input terminal is connected to a preset power supply level V. SUP ;

[0072] Reference current mirror M REF The drain terminal is connected to the reference current source I. REF The output terminal of the device is grounded to GND.

[0073] Among them, the reference current mirror M REF The drain terminal is connected to its gate terminal to facilitate current biasing.

[0074] Reference current mirror M REF It can be a metal-oxide-semiconductor transistor (MOS transistor), such as an N-type MOS transistor, which has a three-electrode structure with source, drain, and gate.

[0075] like Figures 1-6 As shown, according to an embodiment of the present invention, each sub-control unit 112 in at least one sub-control unit 112 includes a control current source I. k , regulating capacitor C k Control switch S k and the regulating current mirror M k :

[0076] Regulating current source I k The input terminal is connected to a preset power supply level V. SUP ;

[0077] Regulating capacitor C k One end is connected to the regulating current source I k The output terminal is connected to ground (GND) at the other end.

[0078] Control switch S k With the regulating capacitor C k Parallel setup, control switch S k One end is connected to the regulating current source I k The output terminal;

[0079] Adjustable current mirror M k With control switch S k Series setting, regulating current mirror M k The drain terminal is connected to the regulating switch S k At the other end, its source is grounded to GND.

[0080] Therefore, at the preset power supply level V SUP Between the corresponding power rail and ground line GND, regulate the current source I. k and regulating capacitor C k They are connected in series and simultaneously control the switch S. k and the regulating current mirror M k They are connected in series and connected to the regulating capacitor C k They are connected in parallel.

[0081] Furthermore, while the mother control unit 111 is typically configured with only one unit, k sub-control units can be configured simultaneously, where k is a positive integer greater than or equal to 1. The value of k is typically related to the number of time segments in the complete signal cycle, x (e.g., ...). Figure 2 As shown, x = 8, and a complete signal cycle is divided into 8 time stages, satisfying: x = k + 1. Therefore, all sub-control units can simultaneously have k control current sources I1 to I2. k k regulating capacitors C1 to C k k control switches S1 to S k and k adjustable current mirrors M1 to M k Each sub-control unit can output a control signal corresponding to a single time interval Δt. For example, the sub-control units of the control current source I2, control capacitor C2, control switch S2, and control current mirror M2 can output a second control signal in the corresponding time interval Δt.

[0082] k controllable current sources I1~I k These can be current sources of the same size. In contrast, the reference current source I... REF It can be a reference current source, and its current magnitude can remain constant.

[0083] Each regulating current mirror M kIt can be a metal-oxide-semiconductor transistor (MOS transistor), such as an N-type MOS transistor, which has a three-electrode structure with source, drain, and gate. Furthermore, each control switch S... k It can also be a metal-oxide-semiconductor field-effect transistor (MOSFET), such as a power MOSFET, where the corresponding switching S can be controlled by adjusting its gate-source voltage. k The on / off state.

[0084] like Figures 1-6 As shown, according to an embodiment of the present invention, the reference current mirror M REF The gate terminal and the control current mirror M of each sub-control unit 112 k The gate terminal connection; the control current source I of each sub-control unit 112 k The output terminal is connected to the logic control module. Under the control of the parent control unit 111, each sub-control unit 112 outputs at least one control electrical signal corresponding to the stage of the control electrical signal to the logic control module.

[0085] like Figure 1 As shown, the segmented regulation module 101 of this embodiment constructs a segmented regulation array of capacitor charging and discharging architecture. For example... Figure 1 The multi-phase LC resonant drive circuit architecture shown includes a single reference current source I in the mother control unit. REF and reference current mirror M REF In addition, it can specifically consist of k = 7 controllable current sources I1~I7, 7 controllable capacitors C1~C7, 7 controllable switches S1~S7, and 7 controllable current mirrors M1~M7. Among them, the controllable capacitors C1~C7 can be capacitors of different capacitance values ​​depending on the actual situation. Specifically, they can be determined by the waveform (such as a sine wave) corresponding to each time interval Δt. This waveform depends on factors such as the actual load and inductance. Different application scenarios require different waveform amplitudes and frequencies, so the discharge currents of these capacitors can also be different or some can be the same.

[0086] Figure 2A simulation diagram of a target load signal (sine wave) generated based on an ideal model architecture is shown. A complete sine wave period (i.e., a complete signal period) can be divided into 8 parts, represented by Δt1 to Δt8. During the control process of the aforementioned segmented control module 101, arbitrarily taking the above... Figure 2 The duration of one step (time interval) of the differential sine wave shown is used as a reference time base (e.g., Δt4). Within this reference time base, k (e.g., ...) is adjusted. Figure 1 The control capacitors C1 to C7 (k=7) are charged with the same current, and then other time stages (such as Δt1 to Δt3 and Δt5 to Δt8) are selected in sequence to control the control capacitors of the corresponding sub-control unit 112 to discharge in stages.

[0087] For example, after charging all the control capacitors in time phase Δt4, the system switches to time phase Δt1. First, the control capacitor C1 of the first sub-control unit is discharged. Specifically, this can be achieved by controlling the control switch S1 to turn on, so that the reference current mirror M... REF The control current mirror M1 is turned on, thereby discharging the control capacitor C1. During this time period, the corresponding control signal for this stage is output to the logic control module. Then, the control signals for each stage are output one by one, completing the stage-by-stage output of the control signal for a complete signal cycle. The details are not elaborated here.

[0088] Among them, such as Figure 2 As shown, during the control process of the segmented control module 101, the duration of one step of the target load signal (differential sine wave) is arbitrarily selected as the reference time base, that is, the duration of one step of the target load signal (differential sine wave) is selected as the reference time base. Figure 2 During a certain phase, such as the duration of phase Δt4, the seven control capacitors in the segmented control module 101 are simultaneously charged, and then the remaining seven control capacitors are discharged sequentially. Figure 2 The durations of the Δt1 to Δt3 and Δt5 to Δt8 stages are not detailed here.

[0089] Specifically, such as Figure 1 and Figure 2 As shown, the current sources I1 to I2 are regulated. k Assuming current sources of the same size, with reference current source I. REF As a reference current source, the current magnitude remains constant, and the regulating capacitors C1 to C2 are used. k The capacitance values ​​are not the same (they can be all different, or there can be several identical values). In the eight stages constituting a complete signal cycle (sine wave), which can correspond to... Figure 1The charge pump structure of the symmetrical charge pump module shown has eight connection methods for the four flying capacitors (see below for details). One stage (time interval Δt4) is selected as the reference time. Within this complete stage time Δt4, the control and regulation current sources I1 to I2 are... k The same current is applied to the regulating capacitors C1 to C2. k Charging is performed, where k satisfies: k = 7. During this stage, the amount of charge stored in each regulating capacitor is the same, all satisfying the following formula 1:

[0090] Q = I k ·t (1)

[0091] Furthermore, the voltage difference between the upper and lower plates of each regulating capacitor satisfies the following formula 2:

[0092]

[0093] Among them, as mentioned above, the reference current mirror M of the mother control unit 111 REF (such as NMOS transistor), regulating current mirrors M1 to M k The gates are connected to the same line (such as the word line, or WL) to form a current mirror structure. The reference current mirror M is used in this structure. REF As a mother current mirror, the current mirrors M1 to M2 are adjusted. k As a sub-current mirror, and as a reference current mirror M REF With the adjustment of current mirrors M1 to M k The ratio of the number of MOSFETs connected in parallel (Multiplier, which is the number of MOSFETs connected in parallel; for current mirrors, the ratio of the number of MOSFETs connected in parallel in the mother current mirror to the number of MOSFETs connected in parallel in the daughter current mirror is the ratio of the current magnitudes) is 1:n1:n2:…:n k That is, the current replication ratio is 1:n1:n2:…:n k Therefore, the current source I1~I is regulated. k It can be used as a reference current source I REF The image is generated by mirroring the current replication ratio described above.

[0094] like Figure 1 and Figure 2 As shown, in the initial stage, all k control capacitors in the control capacitor array are initialized to a zero-voltage state with no stored charge. Then, the duration Δt4 of one step of a complete signal period (differential sine wave) is arbitrarily chosen as the reference time base. Within this reference time base Δt4, the seven control capacitors C1 to C7 are charged with the same current, at which point all control capacitors C1 to C7 have the same amount of stored charge. Then, the charge is increased from control capacitors C1 to C7... kDischarges are performed sequentially with different current magnitudes, correspondingly adjusting the voltage difference between the upper and lower plates of the capacitor (the lower plate is grounded to GND, i.e., the voltage V of the upper plate is...). cap1 ~V capk This can be used as a control signal to output to the logic control module; specifically, when the duration Δt4 ends, the control switch S1 of the sub-control unit will be turned on immediately within the reference time period Δt1. At this time, the corresponding control capacitor C1 will be in the reference current mirror M of the mother control unit. REF Discharge is performed under the control of the capacitor, and the upper plate voltage V of the regulating capacitor C1 is output within the reference time period Δt1. cap1 The output signal is used as a control signal. Following the control process described above, time periods Δt2, Δt3, Δt5, Δt6, Δt7, and Δt8 are selected sequentially to output the upper plate voltage V of the corresponding control capacitors C2, C3, C4, C5, C6, and C7 within their respective time periods. cap2 V cap3 V cap4 V cap5 V cap6 V cap7 As a control electrical signal.

[0095] In other words, the driving circuit device of this invention can use a symmetrical charge pump structure with at least two parts to charge capacitors of different sizes in the capacitor charging and discharging array with the same current within a certain time reference, and then discharge them to a set reference voltage with different currents in sequence. By controlling the duration of each stage of the charge pump structure of the symmetrical charge pump module in different discharge time segments, two waveforms with multiple steps (differential sine waves) in opposite phase are generated. At the same time, the waveform is filtered by a small inductor L to realize the required high-frequency sine wave, i.e. the target load signal.

[0096] In summary, this invention constructs a segmented control array architecture for capacitor charging and discharging through the segmented control module 101. This architecture controls the duration of each step in generating the target load signal (differential sine wave). The duration of one step is arbitrarily selected as a reference. After charging the capacitor array at this reference time, the capacitor discharge is controlled according to the duration of the remaining steps, thereby achieving waveform smoothing. This allows the circuit to flexibly adjust and optimize the waveform when generating waveforms (sine waves) of different frequencies, and reduces the total harmonic distortion (THD) of the generated waveform (sine wave).

[0097] like Figures 1-6As shown, according to an embodiment of the present invention, the logic control module includes a selector MUX, a reference source unit BGR, a comparator CMP, and a charge pump logic unit 121.

[0098] The selector MUX provides multiple input terminals, which are connected one-to-one with at least one sub-control unit 112 of the segmented control module 101 to receive at least one control electrical signal V. cap ;

[0099] The reference source unit BGR provides the reference signal V. REF ;

[0100] The comparator CMP is connected to the output of the selector MUX and the output of the reference source unit BGR, respectively, and receives at least one control electrical signal V from the selector MUX in stages. cap And based on at least one regulating electrical signal V cap Each regulating electrical signal V cap With reference signal V REF The comparison result is used to output the comparison logic signal for the corresponding stage;

[0101] The charge pump logic unit 121 is connected to the output of the comparator MUX and generates a logic combination signal for the corresponding stage based on the comparison logic signal. The logic combination signal is configured to generate a control logic signal for the corresponding stage of at least two control logic signals that conform to the preset state logic expression rules.

[0102] The selector MUX can be a multiplexer composed of multiple switching structural elements. Specifically, for the internal selection of the control signal, the selector MUX can be configured according to the corresponding control switches S1 to S2 on different sub-control units 112. k The state is used as the judgment criterion. For example, when the control switch S1 is turned on, the control capacitor C1 can be discharged. The switch corresponding to the control switch S1 inside the selector MUX is turned on, and the voltage V on the upper plate of the control capacitor C1 is reduced. cap1 The input to comparator CMP completes the corresponding control electrical signal V at the corresponding time stage Δt. cap1 The output of the first control signal is the same as the output of the second control signal. It is important to note that the output of each control signal is the output of the capacitor voltage of the control capacitor at the corresponding time stage Δt, until the control signals for all control capacitors have been output for all time stages (i.e., the complete signal cycle).

[0103] The reference source unit BGR can be a bandgap reference (BGR). Specifically, the selector MUX output from the segmented control module 101 to the logic control module has only the corresponding control capacitor C within the duration Δt of each step of the differential sine wave. k The voltage of the upper plate is selected by the selector MUX and input into the comparator CMP to compare with the reference signal V generated by the reference source unit BGR. REF The comparison is performed. The reference signal V is used for this comparison. REF It can be the reference voltage for the aforementioned control electrical signal, specifically a relatively small voltage threshold, such as V. REF =100mV.

[0104] A comparator (CMP) is a signal comparison unit that outputs high or low levels based on a reference input. For example... Figure 1 As shown, when following the control capacitors C1 to C k The control switches S1 to S2 are controlled sequentially. k When one of the control switches is turned on, the control switch S k The corresponding regulating current mirror M k With size n k ·I REF The regulating current affects the regulating capacitor C k Discharge occurs, and simultaneously the selector MUX adjusts the regulating capacitor C. k Upper plate voltage V capk The selected signal is used as the control signal and fed to the comparator CMP. The comparator CMP then selects the control signal V. capk Reference voltage V of the reference signal REF A comparison is made. Because of the corresponding regulating capacitor C... k During the discharge time phase Δt, the comparator CMP receives the control electrical signal V. capk It decreases gradually, therefore, as the regulating capacitor C... k The discharge occurs when the regulating electrical signal V capk Drop to below the reference voltage V REF At this time, the comparator CMP is thus triggered to flip.

[0105] The flip of comparator CMP marks the end of the duration of the waveform output state of the charge pump structure in the symmetrical charge pump module during the previous time period, corresponding to the end of a segment of the complete sine wave and the beginning of the next segment. In other words, the flip of comparator CMP generates a flip signal, and the rising edge of this signal triggers the octet of the charge pump logic unit 121 to complete subsequent logic control. Afterwards, the previous operation is repeated to adjust the current mirror M. k+1 With size n k+1 ·IREF The regulating current affects the regulating capacitor C k+1 Discharge is performed, sequentially traversing all regulating capacitors C1 to C2. k Ultimately, the waveform (sine wave) of the complete target load signal within a single complete signal cycle is generated.

[0106] Based on the above-described segmented control module 101 control process, arbitrarily taking the above... Figure 2 The duration Δt of a step (time interval) of the differential sine wave (target load signal) shown is used as a reference time base. Within this reference time base, k (such as...) Figure 1 The following are k=7) regulating capacitors C1 to C2. k The system is charged with the same current and then discharged sequentially with different currents until it reaches the reference signal V generated by the reference source cell BGR. REF Similarly, depending on the discharge time, the duration of the remaining k-1 steps within a single sine wave cycle can be simulated, and the signal is transmitted to the selector MUX to select the correct control electrical signal V. Cap Then, with reference signal V REF The comparison is then performed, and the comparison result is transmitted to the logic control module corresponding to the symmetrical charge pump module to control the connection of the charge pump across the capacitor.

[0107] Therefore, to achieve logic control of the symmetrical charge pump module, the logic control module constructs a charge pump control logic architecture, utilizing the flip-flops and logic gates of the charge pump logic unit 121 to comprehensively process the comparison result signal output by the comparator CMP. This comparison result signal can be an output with a rising edge from low to high, for example, when the comparator CMP performs a modulation signal V. cap and reference signal V REF During comparison, when the regulating electrical signal V cap Less than or equal to the reference signal V REF When the comparator CMP flips, it outputs a rising edge from low to high as a comparison result signal to the charge pump logic unit 121. This comparison result signal can be used as the comparison logic signal in this embodiment of the invention.

[0108] The comparison result generated by the comparator CMP is input to the charge pump logic unit 121 of the logic control module. The charge pump logic unit 121 can be a combinational circuit structure composed of an eight-divider and logic gates.

[0109] like Figure 3AThe octet structure shown can be constructed by connecting three D flip-flops (DFF1, DFF2, and DFF3) in series. The clock interface CK1 of D flip-flop DFF1 is connected to the output of comparator CMP, and the comparison result (ComparatorResult) is input to D flip-flop DFF1. The segmented control module 101 has a corresponding control capacitor C in the corresponding time period Δt. k The voltage of the upper plate output during the discharge process is used as the control signal V. cap The regulating electrical signal V cap The current discharge drops to the level of the reference signal V. REF When the reference voltage values ​​are equal, the output level of the comparator CMP can transition from low to high. At this time, the clock interface CK1 of the D flip-flop DFF1 receives the rising edge of the comparison result signal, triggering the D flip-flop DFF1, which can output the signal from port D1 to port Q1. Referring to the above process, since a complete signal cycle of the sine wave is divided into k+1 stages, or k+1 phases, each time a stage is switched, corresponding to the waveform of one phase, the output level of the comparator CMP in the corresponding stage can generate a rising edge, which is input to the D flip-flop DFF1 of the charge pump logic unit 121.

[0110] like Figure 2 As shown, the output level signals of ports Q1, Q2, and Q3 of the three flip-flops DFF1, DFF2, and DFF3 are extracted and labeled A, B, and C respectively, with "1" representing a high level and "0" representing a low level. Then, within one complete sine wave cycle, the logic combination signal ABC can be different logic combination signals that change continuously corresponding to k+1 time stages, such as those described above. Figure 2 The time stages Δt4, Δt1, Δt2, Δt3, Δt5, Δt6, Δt7, and Δt8 shown correspond to a preset sequence of 111, 011, 101, 001, 110, 010, 100, and 000, respectively. For example, in the charging state corresponding to time stage Δt4, the charge pump logic unit 121 can generate a flip-flop output with the logic combination signal ABC = 111. The logic combination signal can be a combination of the level of the Q-terminal signals of multiple flip-flops in the aforementioned divider.

[0111] In the charge pump structure of the symmetrical charge pump module, different control switches of the charge pump structure correspond to different logic combination signals to achieve switch control. The preset state logic expression rules can be mapping rules between logic combination signals and control logic signals based on Karnaugh maps. Among them, the control logic signals are switch state logic expression signals designed for the timing control of the charge pump structure, which can be generated based on the switch state logic expressions generated by Karnaugh maps, as shown in Table 1 below.

[0112] like Figures 1-6 As shown, according to one embodiment of the present invention, the symmetrical charge pump module includes at least two charge pump structures (such as...) that satisfy a preset circuit symmetry relationship. Figure 1 As shown in 131 or 132), each of the at least two charge pump structures includes at least one capacitor control subunit 301 and a plurality of control switches S. L5 S L6 S L7 S L8 or S R5 S R6 S R7 S R8 .

[0113] At least one capacitor control subunit 301, each capacitor control subunit 301, is connected at one end to a preset power supply level V. SUP The other end is grounded to GND, and at least one capacitor control subunit 301 is connected in parallel with each other;

[0114] Multiple control switches S L5 S L6 S L7 S L8 or S R5 S R6 S R7 S R8 Connected in an array structure of at least one capacitor control subunit 301, it is configured to control at least one capacitor control subunit 301 according to the corresponding control logic signal of at least two received control logic signals.

[0115] like Figures 1-6 As shown, according to an embodiment of the present invention, each capacitor control subunit 301 includes a power switch S. L1 / S L2 / S R1 / S R2 Control capacitor C L1 / C L2 / C R1 / C R2 and grounding switch S L3 / S L4 / S R4 / S R3 .

[0116] Power switch S L1 / S L2 / S R1 / S R2 One end is connected to a preset power supply level;

[0117] Control capacitor C L1 / CL2 / C R1 / C R2 One end is connected to the power switch S L1 / S L2 / S R1 / S R2 The other end is connected;

[0118] Grounding switch S L3 / S L4 / S R4 / S R3 One end is connected to the control capacitor C L1 / C L2 / C R1 / C R2 The other end is connected to ground (GND).

[0119] The preset circuit symmetry relationship is used to define the circuit connection relationship between each charge pump structure in the symmetrical charge pump module, such as the structural symmetry relationship of the circuit connection, where the mutually symmetrical charge pump structures are respectively connected to different input terminals A and B of the load.

[0120] like Figure 1 As shown, in a single charge pump structure, a single capacitor control subunit 301 can be controlled by a power switch S. L1 Control capacitor C L1 and grounding switch S L3 Composition. Specifically, in the single-sided charge pump structure 131, the control switch S... L5 Connect control capacitor C L1 The upper plate and control capacitor C L2 The lower electrode plate is controlled by switch S. L6 Connect the inductor L and control capacitor C corresponding to the load input terminal A. L2 The upper electrode plate is controlled by switch S. L7 Connect the inductor L and control capacitor C corresponding to the load input terminal A. L1 The lower electrode plate is controlled by switch S. L8 Control capacitor C L2 The upper electrode is grounded to GND. Correspondingly, based on the aforementioned pre-defined circuit symmetry, in another single-sided charge pump structure 132, the control switch S... R5 Connect control capacitor C R1 The upper plate and control capacitor C R2 The lower electrode plate is controlled by switch S. R6 Connect the load input terminal B and the control capacitor C. R2 The upper electrode plate is controlled by switch S. R7 Connect the load input terminal B and the control capacitor C. R1 The lower electrode plate is controlled by switch S. R8 Control capacitor CR2 The upper electrode plate is grounded to GND.

[0121] The power switch, grounding switch, and control switch mentioned above can all be control logic switching elements in the form of MOSFETs with the same structure and specifications. These MOSFETs can be turned on and off by controlling their gate-source voltage, thereby controlling their switching logic state. The control capacitor can be a flying capacitor.

[0122] Specifically, using the level combinations of the three signals A, B, and C, based on the aforementioned preset state logic expression rules, the Karnaugh map can be used to obtain the following... Figure 1 The symmetrical charge pump module shown has 8 control logic switches S in each side of the charge pump structure (131 / 132). L1 To S L8 (or S) R1 To S R8 The logical expressions corresponding to the state in one sine wave cycle are shown in Table 1 below.

[0123]

[0124] Table 1 Switch State Logic Combination Table

[0125] Table 1 is as follows: Figure 1 The control logic switch of the charge pump structure 131 on the left side is used as an example for explanation: The overline in the text represents the inversion of the state of A. For example, if A = 0, then... When the switch state logic expression is 1, it means the corresponding control logic switch is on; when the switch logic expression is 0, it means the control logic switch is off. Specifically, taking power switch S... L1 For example, when the logic combination signal ABC level combination is 001, the power switch S L1 The corresponding switch state logic expression shows that it is 1 at this time, which means that the power switch S is in the stage corresponding to ABC=001 in the sine wave. L1 In the ON state, the control logic signal output by the charge pump logic unit to the charge pump structure 131 will control the power switch SL1 to turn on. Similarly, the states of the other seven control logic switches within the ABC=001 phase of the sine wave can be obtained, and the operation of controlling their switching states is the same, ultimately realizing the left-side timing control of the charge pump structure 131. Likewise, right-side timing control of the right-side charge pump structure 132 can be implemented, details of which will not be elaborated upon.

[0126] Among them, such as Figure 3B The circuit shown is a switch state logic expression to control logic switch S.L4 The logic expression corresponding to the control logic signal For example, the flip-flop signal A is inverted using an inverter INV, flip-flop signals A and B are ANDed using an AND gate, and finally ORed using an OR gate. The output result is the desired result. The logical expression can be used as the control logic signal output by the charge pump logic unit received by the corresponding charge pump structure 131.

[0127] In summary, the on / off switching of the 16 MOS control logic switches in the symmetrical charge pump module can be achieved according to the above-mentioned preset signal logic. Prior to this, it could be done through methods such as... Figure 3A and Figure 3B The circuit shown, comprising an octet and the logic expression for the switch states, processes the comparator output signal. An octet can be constructed using three D flip-flops connected in series. The three output signals of each D flip-flop are taken, and these three signals can form eight permutations within a complete sine wave cycle, corresponding to eight step states. Eight logic combination circuits are then used to obtain the state of the eight control logic switches in the single-sided charge pump for each step state. The other-sided charge pump structure is similar, except that the phase difference between the two is half a cycle.

[0128] like Figure 1 As shown, control logic switch S L1 ~S L8 Control capacitor C L1 and C L2 This forms the charge pump structure 131 on the left side, and correspondingly, the control logic switch S... R1 ~S R8 Control capacitor C R1 and C R2 This constitutes the right-side charge pump structure 132. The connection state and generated level of the charge pump flying capacitor corresponding to each stage in a single complete sine wave cycle are described below (taking the left-side charge pump structure 131 as an example):

[0129] Phase 1: Control logic switch S L1 S L2 S L3 S L4 S L7 Turn on, control logic switch S L5 S L6 S L8 When disconnected, the voltage level on the left side of inductor L is 0V;

[0130] Phase Two: Control Logic Switch S L1 S L2 S L3 S L4 SL6 Turn on, control logic switch S L5 S L7 S L8 When disconnected, the voltage level on the left side of inductor L is V. SUP ;

[0131] Phase 3: Control logic switch S L1 S L3 S L5 S L6 Turn on, control logic switch S L2 S L4 S L7 S L8 When disconnected, the voltage level on the left side of inductor L is 2V. SUP ;

[0132] Phase 4: Control logic switch S L1 S L2 S L3 S L4 S L6 Turn on, control logic switch S L5 S L7 S L8 When disconnected, the voltage level on the left side of inductor L is V. SUP ;

[0133] Fifth stage: Control logic switch S L1 S L2 S L3 S L4 S L7 Turn on, control logic switch S L5 S L6 S L8 When disconnected, the voltage level on the left side of inductor L is 0V;

[0134] Phase 6: Control logic switch S L2 S L4 S L5 S L7 Turn on, control logic switch S L1 S L3 S L6 S L8 When disconnected, the voltage level on the left side of inductor L is -V. SUP ;

[0135] Phase 7: Control logic switch S L5 S L7 S L8 Turn on, control logic switch S L1 S L2 S L3 S L4 SL6 When disconnected, the voltage level on the left side of inductor L is -2V. SUP ;

[0136] Phase 8: Control Logic Switch S L2 S L4 S L5 S L7 Turn on, control logic switch S L1 S L3 S L6 S L8 When disconnected, the voltage level on the left side of inductor L is -V. SUP .

[0137] As the eight stages are completed sequentially, the voltage level on the left side of inductor L changes from 0 to V. SUP →2V SUP →V SUP →0→-V SUP →-2V SUP →-V SUP The sequence of changes →0, while simultaneously causing the symmetrical right-side charge pump to repeat the above stages with a 180° phase difference, allows for changes on the left side of the inductor L and the load capacitor C. LOAD The right side of the inductor L produces a voltage level change of opposite polarity; specifically, the voltage level on the right side of the inductor L changes from 0 to -V. SUP →-2V SUP →-V SUP →0→V SUP →2V SUP →V SUP →0. This level change is ultimately reflected in the inductor L and the load capacitance C. LOAD Above, this represents the LC resonance effect. Overall, the charge pump structures on both sides generate two differential sine waves of opposite phase with multiple steps, such as... Figure 4 As shown. The final output waveform signal of the charge pump structure on the left side of the drive circuit device is as follows. Figure 4 The C-point level shown (corresponding to...) Figure 1 The waveform signal output by the charge pump structure on the right side of the inductor L (point C to the left of the inductor L) is shown below. Figure 4 The level at point B shown (corresponding to...) Figure 1 The load capacitor C shown LOAD Point B on the right). Among them, such as... Figure 1 Point A on the right side of the inductor L and the load capacitor C are shown. LOAD The level difference between point B on the right side is the sine wave V output by the driving circuit device. OUT (i.e., the target load signal).

[0138] like Figures 1-6 As shown, according to an embodiment of the present invention, the driving circuit device further includes an inductor L.

[0139] One end of the inductor L is connected to the output of one of the charge pump structures of at least two charge pump structures of the symmetrical charge pump module, and the other end is connected to the load.

[0140] Typically, to drive the same load to achieve the same sinusoidal amplitude and frequency, most existing drive circuit structures require large inductors, such as hundreds of μH, or multiple inductors. However, the drive circuit device described in this embodiment of the invention, thanks to its circuit structure, actually only requires one inductor L, which is only 100 μH, thus further reducing the area significantly. In addition, the circuit does not require complex logic control circuitry, therefore the circuit area itself, excluding external components, is also smaller.

[0141] like Figure 1 As shown, the symmetrical charge pump module can be composed of 4 flying capacitors and 16 MOS switches, forming a charge pump structure with left and right symmetrical parts. It receives the switch control logic signals of the charge pump structure generated by the segmented control module 101 (capacitor charge / discharge segmented control array) after processing by the logic control module, and controls the connection of the flying capacitors of the charge pump structure according to a predetermined method to complete the load driving. Wherein, as... Figure 1 The A and B terminals shown represent the equivalent model of the load, which can be represented as a resistor and capacitor connected in series. In practical applications, terminals A and B can be understood as two pins of the chip connected in series with the load. It should be noted that the number of charge pump structures described above can be even, such as 4, 6, or 8, as long as the corresponding preset circuit symmetry is satisfied. The corresponding switching elements, capacitors, and the connection methods between these elements can all be specified in the following diagram. Figure 1 The circuit structure shown is adapted to meet actual needs, but details are not elaborated here.

[0142] In summary, by employing a symmetrical charge pump module structure, with each charge pump using multiple MOS switches, a complete sine wave cycle is divided into k+1 stages. Compared to the traditional boost-buck DC-DC architecture, this significantly reduces the switching frequency of each switch, greatly reducing losses generated by switching at high frequencies in traditional switch-mode amplifier schemes (such as junction capacitance charging and discharging losses). Furthermore, the drive circuit based on this charge pump structure has no static power consumption. Combining these improvements, the drive circuit device of this embodiment significantly reduces power loss, achieving an efficiency of over 90%. Simultaneously, it avoids strong electromagnetic radiation generated by high-frequency switching, greatly improving efficiency, reducing the need for external shielding and filtering components, and significantly reducing circuit area or size.

[0143] Specifically, based on simulation data from an ideal simulation model, at a 40kHz sine wave frequency and an amplitude of 60V, the present invention implements, for example... Figure 1 The aforementioned drive circuit device can achieve an efficiency of 90% or higher. The unoptimized total harmonic distortion (THD) of the sine wave is approximately 7%. After segmented control using the capacitor array of the segmented control module 101, the THD can be significantly reduced, and the overall area is greatly reduced (less than 6×6mm even including external components). 2 ).

[0144] In summary, the driving circuit device described in the embodiments of the present invention can achieve at least the following technical effects:

[0145] (1) A symmetrical charge pump structure is adopted, which uses multiple control logic switches to divide a complete sine wave cycle into k+1 stages. Compared with the traditional Boost-Buck DC-DC architecture, the switching frequency of each logic switch can be significantly reduced, greatly reducing the losses generated by switching in traditional switch-mode amplifier schemes at high frequencies (such as the charging and discharging losses of the junction capacitance of the switching transistors). In addition, the drive circuit device has no static power consumption. With comprehensive improvements, the drive circuit device further reduces a large amount of power loss, and the efficiency can reach more than 90%. At the same time, it avoids the strong electromagnetic radiation generated by high-frequency switching, which greatly improves the efficiency and reduces the number of external shielding and filtering components, further reducing the circuit area or size.

[0146] (2) A segmented control module of capacitor charging and discharging segmented control array is used to control the duration of each step of the differential waveform (differential sine wave) used to generate the target load signal (sine wave). The duration of one time interval step is arbitrarily selected as a reference. By charging the capacitor array with this reference time and then discharging it in sequence, the duration of the remaining steps is adjusted to achieve the purpose of smoothing the waveform. This allows the drive circuit device to flexibly adjust and optimize the waveform when generating waveforms of different frequencies, and reduces the total harmonic distortion (THD) of the generated target load signal (sine wave).

[0147] (3) Compared with the traditional LC resonant scheme, the driving circuit device of the present invention can further reduce the inductance value, require smaller off-chip components, and has lower cost, simpler structure, and is easier to lay out on the PCB. Therefore, compared with the traditional LC resonant structure, a lower frequency sine wave can be generated without requiring a very high inductance value and capacitance value.

[0148] (4) It can generate a wide range of waveforms (sine waves) and has strong load adaptability. It can drive resistive loads, capacitive loads, or mixed capacitive and resistive loads, making its application range wider. The overall circuit structure is simpler and no longer requires complex logic control circuits.

[0149] Secondly, the multi-phase LC resonant circuit based on a charge pump architecture, constructed using the driving circuit device according to embodiments of the present invention, can have the following technical effects:

[0150] (1) The circuit structure is simple and can generate higher output voltage without multi-stage cascading. It adopts a symmetrical charge pump architecture and can generate a sine wave with an amplitude greater than that of the power rail under low voltage power rail conditions, thus avoiding the need to use a boost circuit in the previous stage to raise the voltage in some higher voltage application scenarios.

[0151] (2) It generates sine waves with higher precision and can flexibly adjust the duration of each step in a single sine wave cycle, making the connection points between each segment and the overall waveform smoother and more beautiful, improving the performance of indicators such as THD, and expanding the application range in high fidelity.

[0152] (3) Higher efficiency and less loss: Compared with the traditional switching mode, the switching frequency is significantly reduced, which further reduces the proportion of losses of the switch itself—including the charging and discharging loss of the junction capacitance of the switching transistor and the conduction loss, with an efficiency of over 90%. It reduces the strong electromagnetic radiation generated by high-frequency switching (MHz level), saves on off-chip structures such as shielding and filtering, reduces the difficulty of PCB layout, and simplifies the overall structure.

[0153] (4) The overall circuit area is small and the application scenarios are wide. It can drive various types of loads, such as capacitive loads or resistive-capacitive mixed loads. Compared with traditional LC resonant circuits, the inductance value does not need to be very high, the off-chip components are small, saving area and reducing costs.

[0154] According to embodiments of the present invention, any plurality of modules among the segmented control module, logic control module, and symmetric charge pump module can be combined into one module, or any one of these modules can be split into multiple modules. Alternatively, at least a portion of the functionality of one or more of these modules can be combined with at least a portion of the functionality of other modules and implemented in one module. According to embodiments of the present invention, at least one of the segmented control module, logic control module, and symmetric charge pump module can be at least partially implemented as hardware circuitry, such as field-programmable gate arrays (FPGAs), programmable logic arrays (PLAs), systems-on-a-chip, systems-on-a-substrate, systems-on-package, application-specific integrated circuits (ASICs), or implemented in hardware or firmware by any other reasonable means of integrating or packaging circuitry, or implemented in software, hardware, and firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the segmented control module, logic control module, and symmetric charge pump module can be at least partially implemented as a computer program module, which, when run, can perform corresponding functions.

[0155] Based on the above-described driving circuit device, the present invention also provides a control method for the above-described driving circuit device. The following will be combined with... Figure 5 The method is described in detail.

[0156] like Figure 5 As shown, one aspect of an embodiment of the present invention provides a control method for a drive circuit device applied to a load drive, including operations S501 to S503.

[0157] In operation S501, at least one control electrical signal is output in stages according to the complete signal cycle of the target load signal.

[0158] In operation S502, at least two control logic signals are output according to each of the at least one control electrical signal; and

[0159] In operation S503, a target load signal is output to the load according to each of at least two control logic signals.

[0160] The control method of the driving circuit device described in the embodiments of the present invention is based on the foregoing Figures 1-4 The driving circuit device shown is used to achieve more efficient, lower cost, lower loss and higher accuracy output control of the target load signal, which will not be elaborated in detail.

[0161] Figure 6 A block diagram of an electronic device suitable for implementing a control method for a drive circuit device according to an embodiment of the present invention is shown schematically.

[0162] The electronic device provided in the embodiments of the present invention includes one or more processors and a memory, wherein the memory is used to store one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors cause the one or more processors to execute the control method of the driving circuit device.

[0163] like Figure 6 As shown, an electronic device 600 according to an embodiment of the present invention includes a processor 601, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. The processor 601 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or an associated chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 601 may also include onboard memory for caching purposes. The processor 601 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present invention.

[0164] RAM 603 stores various programs and data required for the operation of electronic device 600. Processor 601, ROM 602, and RAM 603 are interconnected via bus 604. Processor 601 executes various operations of the method flow according to embodiments of the present invention by executing programs in ROM 602 and / or RAM 603. It should be noted that the programs may also be stored in one or more memories other than ROM 602 and RAM 603. Processor 601 may also execute various operations of the method flow according to embodiments of the present invention by executing programs stored in said one or more memories.

[0165] According to an embodiment of the present invention, the electronic device 600 may further include an input / output (I / O) interface 605, which is also connected to a bus 604. The electronic device 600 may also include one or more of the following components connected to the I / O interface 605: an input section 606 including a keyboard, mouse, etc.; an output section 607 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed on the drive 610 as needed so that computer programs read from it can be installed into the storage section 608 as needed.

[0166] The present invention also provides a computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the control method of the aforementioned drive circuit device.

[0167] The computer-readable storage medium may be included in the device / apparatus / system described in the above embodiments; or it may exist independently and not assembled into the device / apparatus / system. The computer-readable storage medium carries one or more programs, which, when executed, implement the method according to the embodiments of the present invention.

[0168] According to embodiments of the present invention, a computer-readable storage medium may be a non-volatile computer-readable storage medium, such as including, but not limited to: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In the present invention, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to embodiments of the present invention, a computer-readable storage medium may include ROM 602 and / or RAM 603 and / or one or more memories other than ROM 602 and RAM 603 described above.

[0169] Embodiments of the present invention also include a computer program product comprising a computer program that, when executed by a processor, implements the control method of the aforementioned drive circuit device.

[0170] The computer program includes program code for performing the methods shown in the flowchart. When the computer program product is run on a computer system, the program code is used to enable the computer system to implement the methods provided in the embodiments of the present invention.

[0171] When the computer program is executed by the processor 601, it performs the functions defined in the system / apparatus of this invention. According to embodiments of the invention, the systems, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0172] In one embodiment, the computer program may rely on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may also be transmitted and distributed in the form of signals over a network medium, and downloaded and installed via the communication section 609, and / or installed from the removable medium 611. The program code contained in the computer program can be transmitted using any suitable network medium, including but not limited to: wireless, wired, etc., or any suitable combination thereof.

[0173] In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 609, and / or installed from the removable medium 611. When the computer program is executed by the processor 601, it performs the functions defined in the system of this embodiment of the invention. According to embodiments of the invention, the systems, devices, apparatuses, modules, units, etc., described above can be implemented by computer program modules.

[0174] According to embodiments of the present invention, program code for executing the computer programs provided in the embodiments of the present invention can be written in any combination of one or more programming languages. Specifically, these computational programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, languages ​​such as Java, C++, Python, "C", or similar programming languages. The program code can be executed entirely on the user's computing device, partially on the user's device, partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0175] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0176] Furthermore, all actions involving the acquisition of information, signals, or data in this invention are carried out in compliance with the relevant data protection laws, regulations, and policies of the country where the invention is located, and with the authorization granted by the owner of the corresponding device.

[0177] Those skilled in the art will understand that the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present invention. In particular, the features described in the various embodiments and / or claims of the present invention can be combined or combined in various ways without departing from the spirit and teachings of the present invention. All such combinations and / or combinations fall within the scope of the present invention.

[0178] The embodiments of the present invention have been described above. However, these embodiments are merely illustrative and not intended to limit the scope of the invention. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of the invention is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of the invention, and all such substitutions and modifications should fall within the scope of the invention.

Claims

1. A driving circuit device for load driving, characterized in that, include: The segmented control module is configured to output at least one control electrical signal in stages according to the complete signal cycle of the target load signal. A logic control module, connected to the segmented control module, is configured to output at least two control logic signals according to each of the at least one control electrical signal. as well as A symmetrical charge pump module, connected to the logic control module, is configured to output the target load signal to the load according to each of the at least two control logic signals.

2. The driving circuit device according to claim 1, characterized in that, The segmented control module includes: A main control unit, one end of which is connected to a preset power supply level and the other end is grounded, is configured to control the segmented control module to achieve current bias. At least one sub-control unit, wherein each sub-control unit is connected in parallel with the parent control unit, and one end of the sub-control unit is connected to a preset power supply level, and the other end is grounded, and is configured to output one of at least one control signal.

3. The driving circuit device according to claim 2, characterized in that, The parent control unit includes: A reference current source, the input of which is connected to a preset power supply level; A reference current mirror, the drain of which is connected to the output of the reference current source, and the source of which is grounded; The drain terminal of the reference current mirror is connected to its gate terminal.

4. The driving circuit device according to claim 3, characterized in that, Each of the at least one sub-control unit includes: A current source is regulated, wherein the input terminal of the current source is connected to a preset power supply level; A regulating capacitor, one end of which is connected to the output terminal of the regulating current source, and the other end of which is grounded; A control switch is connected in parallel with the control capacitor, and one end of the control switch is connected to the output terminal of the control current source; A regulating current mirror is connected in series with the regulating switch. The drain of the regulating current mirror is connected to the other end of the regulating switch, and its source is grounded.

5. The driving circuit device according to claim 4, characterized in that, The gate terminal of the reference current mirror is connected to the gate terminal of the control current mirror of each sub-control unit; the output terminal of the control current source of each sub-control unit is connected to the logic control module; under the control of the main control unit, each sub-control unit outputs the control signal of the corresponding stage of the at least one control signal to the logic control module.

6. The driving circuit device according to claim 1, characterized in that, The logic control module includes: The selector provides multiple input terminals, which are connected one-to-one with at least one sub-control unit of the segmented control module to receive the at least one control electrical signal. The reference source unit provides a reference signal; The comparator is connected to the output of the selector and the output of the reference source unit, respectively. It receives at least one control electrical signal output by the selector in stages, and outputs a comparison logic signal for the corresponding stage according to the comparison result of each control electrical signal with the reference signal. A charge pump logic unit, connected to the output of the comparator, generates a logic combination signal for a corresponding stage based on the comparison logic signal. The logic combination signal is configured to generate a control logic signal for a corresponding stage of the at least two control logic signals that conform to a preset state logic expression rule.

7. The driving circuit device according to claim 1, characterized in that, The symmetrical charge pump module includes at least two charge pump structures that satisfy a preset circuit symmetry relationship, and each of the at least two charge pump structures includes: At least one capacitor control subunit, wherein one end of each capacitor control subunit is connected to a preset power supply level and the other end is grounded, and the at least one capacitor control subunit is connected in parallel with each other. Multiple control switches are connected in an array structure of the at least one capacitor control subunit and are configured to control the at least one capacitor control subunit according to the corresponding control logic signals of at least two received control logic signals.

8. The driving circuit device according to claim 7, characterized in that, Each capacitor control subunit includes: A power switch, one end of which is connected to a preset power level; A control capacitor, one end of which is connected to the other end of the power switch; A grounding switch, one end of which is connected to the other end of the control capacitor, and the other end of which is grounded.

9. The driving circuit device according to claim 1, characterized in that, Also includes: An inductor, one end of which is connected to the output of one of the at least two charge pump structures of the symmetrical charge pump module, and the other end of which is connected to a load.

10. A control method for a drive circuit device according to any one of claims 1-9, applied to load driving, characterized in that, include: At least one control electrical signal is output in stages according to the complete signal cycle of the target load signal; At least two control logic signals are output according to each of the at least one control electrical signal; as well as The target load signal is output to the load according to each of the at least two control logic signals.

11. An electronic device, comprising: One or more processors; Memory, used to store one or more programs. Wherein, when the one or more programs are executed by the one or more processors, the one or more processors perform the method of claim 10.

12. A computer-readable storage medium having executable instructions stored thereon, which, when executed by a processor, cause the processor to perform the method of claim 10.

13. A computer program product comprising a computer program that, when executed by a processor, implements the method of claim 10.

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