An inverter control method, an inverter and an electronic device

Abstract

Embodiments of the present application provide an inverter control method, an inverter and an electronic device. The method comprises: obtaining a bus voltage of an inverter; performing a process of eliminating a fundamental component on the bus voltage to obtain a bus feedforward voltage, the bus feedforward voltage retaining a direct current component and a second harmonic component in the bus voltage; obtaining a modulation voltage used to represent a target waveform of an alternating voltage output by the inverter; determining a duty cycle according to a ratio of the modulation voltage to the bus feedforward voltage; and generating a driving signal according to the duty cycle to drive a switch tube of the inverter. In this way, the embodiments of the present application eliminate the fundamental component in the bus feedforward voltage, avoid a direct current component in the duty cycle due to the fundamental component, and can suppress the direct current component in the alternating voltage output by the inverter. Moreover, the change of the bus voltage can still be compensated by feedforward, and the improvement effect of the bus voltage feedforward on dynamic performance is retained.

Description

Technical Field

[0001] This application relates to the field of inverter technology, and in particular to an inverter control method, an inverter, and electronic equipment. Background Technology

[0002] Inverters are used to convert direct current (DC) to alternating current (AC) and are widely used in photovoltaic power generation, energy storage systems, uninterruptible power supplies (UPS), and other applications. In inverter control, the bus voltage fluctuates with changes in the upstream power supply status and load power. To compensate for the disturbances caused by bus voltage variations to the output, related technologies typically introduce bus voltage feedforward, which incorporates the bus voltage into the duty cycle calculation. This allows changes in the bus voltage to be reflected in the duty cycle in a timely manner and thus canceled out, thereby improving the inverter's dynamic performance.

[0003] However, in addition to the components that change with the operating state, the bus voltage also contains AC ripple components. If the bus voltage is used directly as a feedforward quantity, the AC ripple components will be included in the duty cycle calculation along with the feedforward, which will have an adverse effect on the quality of the AC voltage output by the inverter. Summary of the Invention

[0004] This application aims to solve the problem that AC ripple components affect the quality of AC voltage in inverters using bus voltage feedforward.

[0005] In a first aspect, this application provides an inverter control method, including: Obtain the inverter's bus voltage; The bus voltage is processed to eliminate the fundamental component, thus obtaining the bus feedforward voltage; Obtain the modulation voltage, which is used to characterize the target waveform of the AC voltage output by the inverter; The duty cycle is determined based on the ratio of the modulation voltage to the bus feedforward voltage; A drive signal is generated based on the duty cycle to drive the switching transistors of the inverter, thereby suppressing the DC component in the AC voltage output by the inverter. Wherein, the fundamental component is the AC component of the bus voltage with a frequency equal to the fundamental frequency, and the fundamental frequency is the frequency of the fundamental wave in the AC voltage output by the inverter; the bus feedforward voltage retains the DC component and the second harmonic component in the bus voltage, and the second harmonic component is the AC component of the bus voltage with a frequency equal to twice the fundamental frequency.

[0006] Secondly, this application also provides an inverter, including a power circuit and a controller, wherein the power circuit includes a switching transistor; The controller is used to execute the inverter control method as described in the first aspect to generate a drive signal to drive the switching transistor.

[0007] Thirdly, this application also provides an electronic device, including: At least one processor; At least one network interface, which is communicatively connected to a corresponding processor, and the network interface is used to establish a communication connection between the processor and other external devices; A memory that is communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, which, when executed, enable the at least one processor to perform the inverter control method as described in the first aspect.

[0008] Fourthly, this application also provides a non-volatile computer storage medium storing computer-executable instructions; The computer-executable instructions are executed by one or more processors, which may cause the one or more processors to perform the inverter control method as described in the first aspect.

[0009] At least one advantage of the inverter control method provided in this application embodiment is that: by processing the bus voltage to eliminate the fundamental component, the bus feedforward voltage is obtained, which eliminates the fundamental component in the bus feedforward voltage that would cause the duty cycle to generate a DC component through ratio calculation, thereby suppressing the DC component in the AC voltage output by the inverter; at the same time, the bus feedforward voltage retains the DC component and the second harmonic component that are the main components of the bus voltage, and changes in the bus voltage can still be compensated in a timely manner through feedforward, thus retaining the improvement effect of bus voltage feedforward on dynamic performance, and taking into account both the suppression of DC component and dynamic performance. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0011] Figure 1 A schematic diagram of the structure of an inverter provided for an embodiment of this application; Figure 2 A flowchart illustrating an inverter control method provided for an embodiment of this application; Figure 3 A schematic block diagram of the controller provided for an embodiment of this application; Figure 4 A flowchart illustrating the process of obtaining sampled values ​​half a fundamental cycle in the inverter control method provided in this application; Figure 5A schematic diagram of the read / write process of the ring buffer in the inverter control method provided in the embodiments of this application; Figure 6 A flowchart illustrating the process of adjusting the storage depth of a cache unit in the inverter control method provided in this application embodiment; Figure 7 A schematic diagram of the process for obtaining the modulation voltage in the inverter control method provided in the embodiments of this application; Figure 8 A schematic diagram of the process for obtaining the bus feedforward voltage based on the fundamental component extraction in the inverter control method provided in the embodiments of this application; Figure 9 A schematic diagram of the amplitude-frequency response of a bandpass filter provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of an electronic device provided for an embodiment of this application. Detailed Implementation

[0012] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as being "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as being "connected" to another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "upper," "lower," "inner," "outer," "bottom," etc., used in this specification indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0013] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0014] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0015] Please see Figure 1 , Figure 1This is a schematic diagram of an inverter provided in an embodiment of this application. The inverter 100 is used to convert DC power into AC power and can be applied to photovoltaic power generation systems, energy storage systems, uninterruptible power supplies and other occasions that require DC-AC conversion.

[0016] Inverter 100 includes power circuit 10 and controller 20. The input terminal of power circuit 10 receives bus voltage Ubus, and the output terminal of power circuit 10 outputs AC voltage Uac; controller 20 is connected to power circuit 10, and controller 20 outputs drive signal to power circuit 10.

[0017] Bus voltage refers to the voltage on the DC input side of inverter 100, that is, the DC side voltage on which power circuit 10 performs DC-AC conversion. Bus voltage is provided by the preceding DC power supply, such as by photovoltaic modules, battery packs or preceding DC-AC conversion circuits.

[0018] The power circuit 10 includes a switching transistor 11, which is turned on or off under the control of a drive signal to modulate the bus voltage Ubus into an AC voltage, thereby obtaining an AC voltage Uac at the output of the power circuit 10.

[0019] In some embodiments, the switching transistor 11 may be a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), or other power semiconductor devices with controllable switching capabilities. The specific device type of the switching transistor is not limited in the embodiments of this application.

[0020] For example, the power circuit 10 adopts a single-phase full-bridge topology. In the single-phase full-bridge topology, the switching transistors 11 include a first switching transistor Q1, a second switching transistor Q2, a third switching transistor Q3, and a fourth switching transistor Q4. The first switching transistor Q1 and the second switching transistor Q2 are connected in series between the positive and negative terminals of the bus voltage Ubus to form a first bridge arm, and the connection point of the first switching transistor Q1 and the second switching transistor Q2 is the midpoint of the first bridge arm. The third switching transistor Q3 and the fourth switching transistor Q4 are connected in series between the positive and negative terminals of the bus voltage Ubus to form a second bridge arm, and the connection point of the third switching transistor Q3 and the fourth switching transistor Q4 is the midpoint of the second bridge arm.

[0021] The midpoints of the first and second bridge arms serve as the output terminals of the power circuit 10, outputting an AC voltage Uac to the load. The drive signals include a first drive signal PWM1, a second drive signal PWM2, a third drive signal PWM3, and a fourth drive signal PWM4, which respectively drive the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4.

[0022] Furthermore, the power circuit 10 may also include an output filter, which includes a filter inductor Lf and a filter capacitor Cf. One end of the filter inductor Lf is connected to the midpoint of the second bridge arm, and the other end of the filter inductor Lf is connected to one end of the filter capacitor Cf. The other end of the filter capacitor Cf is connected to the midpoint of the first bridge arm, and the two ends of the filter capacitor Cf serve as the filtered output terminals connected to the load. The output filter is used to filter out the switching frequency ripple generated during the switching process of the switching transistor 11, making the AC voltage Uac output to the load close to a sine wave.

[0023] It is understood that the power circuit 10 can also adopt other circuit topologies that can convert DC to AC, such as half-bridge topology and three-level topology, and the output filter can also adopt other filtering structures such as LCL filter. The embodiments of this application do not limit the specific topology of the power circuit.

[0024] The controller 20 is used to execute the inverter control method provided in the embodiments of this application, and generates a drive signal to drive the switching transistor 11. The controller 20 can be implemented using a control chip with sampling and computing capabilities, such as a digital signal processor (DSP), a microcontroller unit (MCU), or a field-programmable gate array (FPGA). The controller 20 acquires the bus voltage Ubus and the AC voltage Uac, and outputs the drive signal after processing.

[0025] The AC voltage Uac output by inverter 100 contains a fundamental component. The fundamental component is a sinusoidal component in the AC voltage Uac with a frequency equal to the target output frequency. For example, in the case where inverter 100 supplies power to a power frequency load or power grid, the frequency of the fundamental component is 50Hz or 60Hz. The fundamental period is the period of the fundamental component in the AC voltage output by inverter 100, denoted as T, where T = 2π / ω, and ω is the angular frequency of the fundamental component. Taking a fundamental component frequency of 50Hz as an example, the fundamental period T is 20ms. This example will be used in subsequent embodiments of this specification.

[0026] Bus voltage feedforward refers to a control method that incorporates the bus voltage into the control calculation to compensate for the output disturbance caused by changes in bus voltage. In actual operation, the bus voltage fluctuates with changes in the upstream power supply status and load power. By using the bus voltage as a feedforward quantity in the duty cycle calculation, changes in the bus voltage can be reflected in the duty cycle in a timely manner and thus offset, thereby improving the dynamic performance of the inverter.

[0027] In related technologies, the bus voltage is usually directly used as the feedforward voltage, and the duty cycle is obtained by dividing the modulation voltage by the feedforward voltage. The AC voltage output by the inverter often contains a DC component. This DC component can cause magnetic saturation, overcurrent, and overheating in magnetic components such as transformers and inductors, and accelerate the electrochemical corrosion of batteries and loads, directly threatening the safe operation of the transformer, inverter, battery, and load. Furthermore, when the bus voltage is directly used as the feedforward voltage, the DC component in the output AC voltage is introduced and amplified. This application analyzes the underlying causes of this phenomenon, as follows: The modulation voltage, denoted as Uc, is the voltage used to characterize the target waveform of the AC output voltage of the inverter. The modulation voltage is typically approximately equal to the fundamental frequency, and can be expressed as: (1) Where Xc is the amplitude of the modulation voltage, ω is the angular frequency of the fundamental component, and t is time.

[0028] The following analysis examines the frequency components of the bus voltage when a DC component exists in the output AC voltage. When both the inverter's output AC voltage and output current contain DC components, the AC voltage Vac and AC current Iac can be expressed as follows: (2) (3) Where X1 is the fundamental amplitude of the AC voltage, Y1 is the DC component of the AC voltage, X2 is the fundamental amplitude of the AC current, and Y2 is the DC component of the AC current. When the DC component exists, Y1 and Y2 are not equal to 0. From equations (2) and (3), the AC power Pac is the product of Vac and Iac, using the trigonometric identities Expanding and merging by frequency, we get: (4) As can be seen from equation (4), AC power consists of a constant component and a component with a frequency equal to the fundamental frequency. and components with frequencies equal to twice the fundamental frequency. It consists of three parts. The power component at twice the fundamental frequency originates from the product of the fundamental voltage and the fundamental current, and it exists objectively regardless of whether there is a DC component in the output. The power component at the fundamental frequency is generated by the cross-multiplication of the DC component and the fundamental component, and it only appears when Y1 and Y2 are not zero, that is, when there is a DC component in the output AC voltage.

[0029] According to the law of conservation of energy, the power Pdc supplied by the DC side is equal to the AC power Pac. The AC frequency components of the AC power exhibit the same frequency fluctuations as the DC power. Inverters typically have a bus capacitor on the DC side. Fluctuations in the DC power cause charging and discharging on the bus capacitor, resulting in a superposition of voltage fluctuations of the same frequency on the bus voltage above the DC input: a power component at twice the fundamental frequency causes a voltage fluctuation at twice the fundamental frequency, and a power component at the fundamental frequency causes a voltage fluctuation at the fundamental frequency. Therefore, the bus voltage Ubus can be expressed as: (5) Wherein, A0 is the DC component of the bus voltage, A1 is the amplitude of the fundamental frequency AC component of the bus voltage (hereinafter referred to as the fundamental component), A1 is not zero only when there is a DC component in the output AC voltage, and A2 is the amplitude of the second harmonic component of the bus voltage (hereinafter referred to as the second harmonic component).

[0030] When the bus voltage is directly used as the feedforward voltage, the feedforward voltage... The duty cycle D is: (6) The following proves that the duty cycle of the form (6) contains a DC component.

[0031] make Construction operation This refers to a fractional operation where the numerator is a signal in fundamental frequency form and the denominator is a signal containing DC, fundamental, and second harmonic components. The result of this fractional operation will produce DC, fundamental, and second, third, and fourth harmonics, theoretically including all integer harmonic components. The proof is as follows: The first step is to expand the fraction into a power series. Given that the DC component dominates in the denominator, the following conditions must be met: ,at this time Series formulas can be used Expand (n ranges from 0 to infinity), where After unfolding, It is represented as the superposition of powers of u.

[0032] The second step is to use trigonometric identities to convert products to sums. Since each power of u contains the product of trigonometric functions and higher powers, the product-to-sum formula applies: (7) Each multiplication generates harmonic components of the sum frequency and difference frequency. Specifically, multiplying the fundamental frequency with the fundamental frequency produces DC and the second harmonic, multiplying the fundamental frequency with the second harmonic produces the first and third harmonics, and cross-multiplying higher-order terms successively generates the fourth, fifth, and other integer harmonics.

[0033] The third step is to multiply the expansion result by the fundamental term of the molecule, and then multiply by A1·cos(ωt). The frequency components continue to couple in pairs to generate new frequencies: the DC and the fundamental term are multiplied to obtain the fundamental term, the fundamental term is multiplied by the fundamental term to obtain the DC and the second harmonic, the fundamental term is multiplied by the second harmonic to obtain the first and third harmonics, and the higher-order terms are cross-multiplied to generate all integer harmonics in sequence.

[0034] Furthermore, from the perspective of periodic functions, the function of superimposed finite harmonics is a periodic function with a period of the fundamental period T = 2π / ω. The reciprocal of the periodic function is still a periodic function of the same period, and multiplying it by the harmonics of the same period results in another periodic function of the same period. According to the uniqueness of Fourier series, any periodic signal can be decomposed into the sum of the DC component and all integer harmonic components. Therefore, the result of the above fractional operation includes all integer harmonic components, including the DC component.

[0035] The duty cycle D in equation (6) has the same fractional structure as the above construction operation. The only difference is that the amplitude of the numerator is Xc. Therefore, as can be seen from the above proof, when the bus voltage feedforward contains the fundamental component A1·cos(ωt), the duty cycle D contains a DC component.

[0036] After the duty cycle containing the DC component is pulse width modulated to generate a driving signal and drive the switching transistor, the DC component in the output AC voltage is further increased. As can be seen from the analysis of equations (2) to (5), the increase in the output DC component will increase the fundamental component A1 in the bus voltage, and the DC component in the duty cycle will further increase, thus forming a mutually reinforcing cycle.

[0037] The above analysis shows that the root cause of directly introducing DC components using bus voltage feedforward lies in the presence of a fundamental component in the feedforward voltage. Furthermore, the fundamental component only appears when a DC component is present in the output, while the DC component and second harmonic component in the bus voltage are the components that the feedforward should retain to compensate for DC components. Therefore, if the fundamental component can be selectively eliminated from the bus voltage while retaining the remaining components, the path to DC component generation can be cut off while preserving the dynamic performance improvement effect of bus voltage feedforward.

[0038] Based on the above findings, this application proposes an inverter control method, which is executed by the controller 20, and its flowchart is shown below. Figure 2 As shown, it includes the following steps. Step S101: Obtain the inverter bus voltage.

[0039] The controller 20 samples the bus voltage Ubus to obtain the sampled value of the bus voltage. The sampling of the bus voltage is performed periodically according to the control cycle of the controller 20, and is used for calculation in subsequent steps.

[0040] Step S102: The bus voltage is processed to eliminate the fundamental component, and the bus feedforward voltage is obtained.

[0041] The process of eliminating the fundamental component refers to selectively eliminating the fundamental component from the bus voltage while retaining the DC component and the second harmonic component. From equation (5) in the aforementioned analysis, the bus voltage... After eliminating the fundamental component, the bus feedforward voltage Uf is: (8) In other words, the bus feedforward voltage does not contain the fundamental component, but retains the DC component A0 and the second harmonic component A2·cos(2ωt). Since the DC component A0 is the main component of the bus voltage, and changes in the bus voltage such as drops and rises are mainly reflected in changes in the DC component, retaining A0 in the bus feedforward voltage means that changes in the bus voltage can still be compensated in a timely manner through feedforward, and the improvement effect of bus voltage feedforward on dynamic performance is retained; while the fundamental component, which causes the duty cycle to generate a DC component as pointed out in the previous analysis, is eliminated. The process of eliminating the fundamental component only targets the fundamental component and does not affect the other components in the bus voltage. This is the key to the embodiment of this application being able to balance DC component suppression and dynamic performance.

[0042] In some embodiments, the process of eliminating the fundamental component is achieved by averaging two sampled values ​​of the bus voltage that are half a fundamental cycle apart; in other embodiments, the process of eliminating the fundamental component is achieved by extracting the fundamental component of the bus voltage and then subtracting the extracted signal from the bus voltage.

[0043] Step S103: Obtain the modulation voltage, which is used to characterize the target waveform of the AC voltage output by the inverter.

[0044] As mentioned earlier, the modulation voltage Uc is usually approximately equal to the fundamental frequency, i.e. The modulation voltage can be obtained by closed-loop regulation of the AC voltage output by the inverter; alternatively, it can be obtained by open-loop input, i.e., by directly inputting the modulation voltage according to the target waveform.

[0045] Step S104: Determine the duty cycle based on the ratio of the modulation voltage to the bus feedforward voltage.

[0046] The duty cycle D is calculated using the following formula: (9) The following proves that the duty cycle in equation (9) does not contain a DC component. The denominator of equation (9) contains only the DC component A0 and the second harmonic component A2·cos(2ωt), where A0 is the DC amplitude and A2 is the second harmonic amplitude. The proof is as follows: The first step is to expand the denominator of the fraction into a power series. This assumes the small-signal condition is met. In this case, split the denominator and apply the power series formula. Expand (n ranges from 0 to infinity), where When expanded, 1 / Uf represents the superposition of powers of cos(2ωt).

[0047] The second step is to analyze the frequency components of each power using the product-to-sum formula of equation (7). Each power of cos(2ωt) is expanded by product-to-sum. Multiplying the second harmonic with the second harmonic produces DC and the fourth harmonic. Multiplying the second harmonic with the fourth harmonic produces the second and sixth harmonics, and so on. The resulting components are all DC and even harmonics, without any odd harmonics.

[0048] The third step is to multiply the entire expansion result by the fundamental component of the molecule. Multiplying the DC term by the fundamental frequency yields the first fundamental frequency; multiplying the second harmonic by the fundamental frequency yields the first and third harmonics; multiplying higher even-order harmonics by powers of the fundamental frequency continuously generates higher odd-order harmonics such as the 5th and 7th harmonics. Multiplying even-order harmonics by the fundamental frequency only produces odd-frequency components, without generating DC components or even-order harmonic components.

[0049] Therefore, the duty cycle in the form of equation (9) contains only all odd-order harmonic components and no DC component. A comparison with the analysis of equation (6) shows that the only difference between the two is whether there is a fundamental component A1·cos(ωt) in the denominator. This difference determines whether there is a DC component in the duty cycle. After eliminating the fundamental component in the bus feedforward voltage, the division operation no longer produces a DC component.

[0050] Step S105: Generate a drive signal based on the duty cycle to drive the inverter's switching transistors and suppress the DC component in the AC voltage output by the inverter.

[0051] The duty cycle D is used to generate drive signals via pulse width modulation (PWM). Specifically, the duty cycle D is input to a PWM generator, which generates four drive signals: PWM1, PWM2, PWM3, and PWM4. These signals drive the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4, respectively. Since the duty cycle does not contain a DC component, the AC voltage modulated by the switching transistors will not introduce a DC component through the feedforward path, thus suppressing the DC component in the inverter's output AC voltage.

[0052] Pulse width modulation can be performed using bipolar modulation or unipolar modulation. This application does not limit the specific modulation method.

[0053] Based on the analysis of the aforementioned embodiments, it can be seen that the embodiments of this application eliminate the fundamental component in the bus feedforward voltage, thereby cutting off the cycle of mutual reinforcement between the "output DC component, the bus fundamental component, and the duty cycle DC component": even if the output AC voltage has an initial DC component due to other factors and causes a fundamental component in the bus voltage, the fundamental component will be eliminated in step S102 and will not be able to enter the duty cycle. The DC component loses the path to be amplified through the feedforward path and gradually decays with feedback adjustment, thus suppressing the DC component in the output AC voltage.

[0054] In some embodiments, the elimination of the fundamental component is achieved by averaging two sampled values ​​separated by half a fundamental cycle. Specifically, the sampled value Ubus(t) of the bus voltage at the current moment and the sampled value Ubus(t) of the bus voltage at a moment half a fundamental cycle prior to the current moment are obtained. T / 2), where t is the current time, T is the fundamental frequency period, and the fundamental frequency period is the period corresponding to the fundamental frequency; the sampled value before half a fundamental frequency period is obtained from the pre-cached historical sampled value, that is, the controller 20 writes the sampled value at each time to the cache unit, so that the value sampled before half a fundamental frequency period can be read at the current time.

[0055] The cache unit refers to the storage space used to temporarily store historical sampled values ​​of the bus voltage, which can be implemented by the memory inside the controller 20.

[0056] The bus feedforward voltage is calculated using the following formula: (10) The following explains the effect of equation (10) on the frequency components of the bus voltage. For the fundamental component, by the properties of trigonometric functions: (11) That is, at two moments separated by half a fundamental cycle, the amplitudes of the fundamental components are equal but their signs are opposite, and after averaging, they cancel each other out. The validity of equation (11) is independent of the amplitude A1 and initial phase of the fundamental component, meaning that regardless of the magnitude and phase of the fundamental component in the bus voltage, the averaging operation can eliminate it. For the DC component, its value does not change with time, and the value at both moments is A0, which remains A0 after averaging, thus preserving it completely. For the second harmonic component, That is, the values ​​of the second harmonic components at two moments separated by half a fundamental period are the same, and the average value is retained intact. Substituting equation (5) into equation (10), we get: (12) This means that the fundamental component is eliminated from the bus feedforward voltage, while the DC component and the second harmonic component are retained. For example, suppose A0 is 400V, A1 is 10V, A2 is 20V, and the fundamental component at a certain time t is 10cos(ωt), then t The fundamental component at time T / 2 is taken as: The average of 10cos(ωt) is 0; the DC component at both times is 400V, and the average remains 400V; the second harmonic component at both times is 20cos(2ωt), and the average remains unchanged.

[0057] It is understandable that for any odd-order harmonic components such as the 3rd and 5th harmonics that may exist in the bus voltage, the values ​​at two moments separated by half a fundamental cycle are also opposite in sign. Therefore, the averaging operation of equation (10) can actually eliminate all odd-order harmonic components in the bus voltage and retain the DC component and all even-order harmonic components.

[0058] Since the DC component A0 is the main component of the bus voltage, and the changes in bus voltage such as drops and rises are mainly reflected in the changes in the DC component A0, retaining A0 in the bus feedforward voltage means that the changes in bus voltage can still be compensated by feedforward, and the improvement effect of bus voltage feedforward on dynamic performance is retained. As pointed out in the previous analysis, the fundamental component that causes the duty cycle to generate a DC component is eliminated. This is the key difference between the embodiments of this application and the method of directly using the bus voltage as the feedforward voltage.

[0059] In other embodiments, the elimination of the fundamental component is achieved by extracting the fundamental component from the bus voltage and then subtracting the extracted signal from the bus voltage. Please refer to [link to relevant documentation]. Figure 8 , Figure 8 The inverter control method provided in this application includes a flowchart illustrating the process of obtaining the bus feedforward voltage based on the fundamental component extraction, comprising the following steps.

[0060] Step S501: Extract the fundamental component of the bus voltage to obtain the fundamental extracted signal.

[0061] Fundamental component extraction refers to the process of separating the signal corresponding to the fundamental component from the bus voltage. The extracted signal is called the fundamental extracted signal, denoted as U1.

[0062] In one implementation, the bus voltage is input to a bandpass filter, and the output of the bandpass filter is used as the fundamental frequency extraction signal. A bandpass filter is a linear filtering element whose filtering characteristics are described by a transfer function. The transfer function is the ratio of the frequency domain representation of the output signal to the frequency domain representation of the input signal, reflecting the gain and phase shift of the element for signal components of different frequencies. The bus voltage Ubus is used as the input signal to the bandpass filter, and its frequency domain representation is denoted as Ubus(s); the output of the bandpass filter is the fundamental frequency extraction signal U1, and its frequency domain representation is denoted as U1(s); the transfer function of the bandpass filter is denoted as G1(s). According to the above meaning of the transfer function, the input signal, output signal, and transfer function satisfy the following relationship: (13) That is, the fundamental frequency signal is obtained by applying the transfer characteristics of a bandpass filter to the bus voltage. The transfer function G1(s) of the bandpass filter satisfies: (14) Where U1(s) is the frequency domain representation of the fundamental extracted signal, Ubus(s) is the frequency domain representation of the bus voltage, G1(s) is the transfer function of the bandpass filter, H0 is the center frequency gain, ω is the center angular frequency (ω=2πf), f is the fundamental frequency, Q is the quality factor, s is the Laplace operator, and ω / Q is the angular bandwidth of the bandpass filter. Please refer to [link to relevant documentation]. Figure 9 , Figure 9 A schematic diagram of the amplitude-frequency characteristics of the bandpass filter provided in the embodiments of this application is shown. The amplitude-frequency characteristics of the bandpass filter shown in Equation (14) have the fundamental frequency f as the center frequency, and the peak gain is obtained at the center frequency, and it decreases to both sides as the frequency moves away.

[0063] The bandpass filter is a linear element. According to the superposition principle, each frequency component of the bus voltage is transmitted independently through the bandpass filter, and the output signal is the sum of the transmission results of each frequency component. From equation (5), the bus voltage Ubus consists of the DC component A0 and the fundamental component. and second harmonic components It consists of three parts, and the transmission results of each part after passing through the bandpass filter are analyzed below: For the DC component, its frequency is zero. Substituting s=0 into equation (14), the numerator of equation (14) contains the factor s. At this time, the numerator is zero, that is, G1(0)=0, and the gain of the bandpass filter on the DC component is zero. Therefore, the DC component A0 in the bus voltage is completely blocked by the bandpass filter and does not appear in the output signal.

[0064] For the fundamental component, its angular frequency is equal to the center angular frequency ω of the bandpass filter. Taking the center frequency gain H0 as 1, ... Substituting into equation (14), we obtain the frequency response of the bandpass filter at the center frequency: (15) That is, at the center frequency, the gain is 1 and the phase shift is 0. The fundamental component's amplitude and phase remain unchanged after passing through the bandpass filter. Therefore, the output of the bandpass filter is... That is, the fundamental frequency extracted signal is equal to the fundamental frequency component in the bus voltage.

[0065] For the second harmonic component, its angular frequency is 2ω, which deviates from the center angular frequency of the bandpass filter. Substituting s=j2ω into equation (14), we obtain the amplitude of the frequency response of the bandpass filter at twice the fundamental frequency. When the quality factor Q is large, the amplitude is about 2 / (3Q), that is, the second harmonic component in the bus voltage is attenuated to about 2 / (3Q) of the original amplitude after passing through the bandpass filter.

[0066] The above analysis shows that the DC component is completely blocked, the second harmonic component and higher frequency components are significantly attenuated, and only the fundamental component passes through unaffected. Therefore, when the bus voltage Ubus is input to a bandpass filter, the output of the bandpass filter is the fundamental component of the bus voltage, which can be considered as... That is, the output of the bandpass filter is the fundamental frequency extraction signal.

[0067] The quality factor Q determines the bandwidth of the bandpass filter. A larger Q value results in better selectivity for the fundamental frequency and stronger suppression of adjacent frequency components, but also a slower response speed. The value of Q can be determined based on the requirements for selectivity and response speed. The bandpass filter can be implemented as a digital filter by the controller 20; fundamental component extraction can also be achieved using other filter structures capable of separating the fundamental frequency component from the bus voltage, and this application embodiment does not impose any limitations on this. When the fundamental frequency changes, the center angular frequency ω of the bandpass filter is set accordingly with the fundamental frequency f according to ω=2πf, ensuring that the extraction target is always aligned with the fundamental component in the bus voltage.

[0068] Step S502: Subtract the fundamental extracted signal from the bus voltage to obtain the bus feedforward voltage.

[0069] The bus feedforward voltage is calculated using the following formula: (16) Equation (5) and Substituting into equation (16), we get This is consistent with equation (8), meaning that the fundamental component is eliminated from the bus feedforward voltage, while the DC component and the second harmonic component are retained. This implementation method only eliminates the fundamental component and does not affect the DC component, the second harmonic component, or other frequency components in the bus voltage. Changes in the bus voltage can still be compensated in a timely manner through feedforward, and the dynamic performance of the system will not be affected.

[0070] It should be noted that the filtering accuracy requirements of the bandpass filter are concentrated in two places. First, the gain for the DC component is zero. This is guaranteed by the factor s in the numerator of equation (14) and is independent of the value of the quality factor Q. Therefore, the DC component A0, which is the main body of the bus voltage, will not be extracted and will enter the fundamental extraction signal. A0 in the bus feedforward voltage is completely preserved. Second, the gain is 1 and the phase shift is 0 at the center frequency, which ensures that the fundamental component is accurately extracted and completely canceled in equation (16). As for the case where the second harmonic component is not completely attenuated and enters the fundamental extraction signal in a small amount, its effect is only to slightly reduce the amplitude of the second harmonic component in the bus feedforward voltage obtained by equation (16). The bus feedforward voltage is still a combination of the DC component and the second harmonic component. The duty cycle still does not contain the DC component, and the suppression effect on the DC component is not affected.

[0071] Furthermore, from the relationship between equations (2) to (5) in the aforementioned analysis, it can be seen that the fundamental component in the bus voltage originates from the DC component in the output AC voltage. As the DC component in the duty cycle is eliminated and the DC component in the output AC voltage is suppressed, the fundamental component in the bus voltage decreases accordingly. When the output AC voltage does not contain a DC component in steady state, the bus voltage contains only a DC component and a second harmonic component. At this time, the fundamental extraction signal U1 = 0, and the bus feedforward voltage is equal to the bus voltage itself. That is to say, the process of eliminating the fundamental component only works when there is a DC component. In steady state, the feedforward channel is completely consistent with the direct use of the bus voltage feedforward, without introducing any additional effects. It can be understood that for the aforementioned averaging implementation method, when the bus voltage does not contain a fundamental component in steady state, the averaging operation does not change the DC component and the second harmonic component, and the bus feedforward voltage also tends to the bus voltage itself. The above steady-state characteristics also hold true.

[0072] Please see Figure 4 , Figure 4 The inverter control method provided in this application includes a flowchart of step S101, which obtains the sampled value before half a fundamental cycle. The specific steps are as follows.

[0073] Step S201: Sample the bus voltage according to the preset sampling period Ts.

[0074] The preset sampling period refers to the time interval between two adjacent samples, denoted as Ts. The preset sampling period can be consistent with the control period of controller 20, that is, controller 20 completes one sampling of the bus voltage and subsequent control calculations within each control period. Continuing with the previous example, the fundamental frequency is 50Hz, the fundamental period T is 20ms, and the sampling frequency is 20kHz, then the preset sampling period Ts is 50μs.

[0075] Step S202: Write the sampled values ​​obtained from each sampling into the cache unit sequentially, where the storage depth N of the cache unit satisfies... .

[0076] Storage depth, denoted by N, refers to the number of sampled values ​​that a cache unit can hold. Storage depth is determined by the following formula: (17) In other words, the buffer unit can hold all the sampled values ​​within half a fundamental frequency period. The sampled values ​​obtained from each sampling are written to the buffer unit sequentially according to the sampling time. When the buffer unit is full, it stores N sampled values ​​from the current time back half a fundamental frequency period, where the earliest written sampled value is exactly half a fundamental frequency period away from the current time. Continuing with the previous example, when T is 20ms and Ts is 50μs, N = 20ms / (2×50μs) = 200, meaning the buffer unit holds 200 sampled values. When the 200th sampled value is written, the first sampled value is exactly the value sampled 10ms (i.e., half a fundamental frequency period) ago.

[0077] When T / (2·Ts) is not an integer, N is taken as a positive integer obtained by rounding T / (2·Ts). The resulting time deviation does not exceed half a preset sampling period, which can be ignored relative to half a fundamental period and has no substantial impact on the cancellation effect of the fundamental component.

[0078] In the initial stage after the inverter starts up, the cache unit is not yet full, and there is no sampled value from half a fundamental cycle ago. In some embodiments, before the cache unit is full, the sampled value at the current moment can be used instead of the sampled value from half a fundamental cycle ago to participate in the averaging calculation in step S102, that is, the bus feedforward voltage is equal to the sampled value at the current moment in this stage; after the cache unit is full, the normal calculation is performed according to equation (10). Since this initial stage only lasts for half a fundamental cycle, and the startup stage is usually accompanied by transition control such as soft start, using the current sampled value for transition does not affect the normal operation of the inverter.

[0079] Step S203: Read the earliest sampled value written from the cache unit as the sampled value half a fundamental cycle ago.

[0080] As analyzed in step S202, after the cache unit is full, the earliest written sample value is half a fundamental frequency period away from the current time. Therefore, in each control cycle, the earliest written sample value is read out, thus obtaining... This is used for the averaging operation in step S102.

[0081] Step S204: Write the current sampled value to the target storage location where the read sampled value is located.

[0082] The target storage location refers to the storage location in the cache unit where a read operation is performed within the current control cycle, i.e., the storage location of the earliest written sample value. After reading the earliest written sample value, that sample value has completed its purpose and is no longer used in subsequent calculations. Its storage location is then overwritten by the current sample value. After this read and write operation, the cache unit still stores N sample values ​​from the most recent half-fundamental cycle, and the earliest written sample value is updated to the sample value in the next storage location for reading in the next control cycle.

[0083] Please see Figure 5 , Figure 5 A schematic diagram of the read / write process of the ring buffer in the inverter control method provided in the embodiments of this application.

[0084] In some embodiments, the cache unit is a circular cache. A circular cache refers to a cache structure in which the read and write positions move sequentially along the index direction of the storage unit, and return to the starting position after reaching the end, for cyclical use. For example... Figure 5 As shown, the circular cache includes N storage units numbered from 1 to N. The storage unit pointed to by the read / write position is the target storage location: within the current control cycle, the process starts from the target storage location ( Figure 5 Read the earliest sampled value Ubus(t) from the memory cell with index k. T / 2), then write the current sampled value Ubus(t) to the target storage location, and then move the read / write position to the next storage unit along the sequence number direction; after the read / write position reaches the storage unit with sequence number N and completes the read / write, it returns to the storage unit with sequence number 1, and so on.

[0085] By using a circular buffer and operating the target storage location in the order of reading first and writing later, only one read operation and one write operation are required in each control cycle. Moreover, the storage depth of the buffer unit only needs N storage units to continuously maintain all sampled values ​​in the most recent half-fundamental cycle. There is no need to set up separate storage space for new and old data, which saves the storage resources of the controller 20.

[0086] Please see Figure 6 , Figure 6The flowchart illustrating the adjustment of the cache unit storage depth in the inverter control method provided in this application is shown. Analysis of equation (11) reveals that the cancellation of the fundamental component depends on the two sampled values ​​being exactly half a fundamental cycle apart. However, in some applications, the fundamental cycle is not fixed. For example, when the inverter is connected to the grid, the grid frequency fluctuates around the rated value, and the fundamental cycle changes accordingly. If the storage depth N is always determined according to the rated fundamental cycle, when the fundamental cycle shifts, the earliest sampled value written to the cache unit will deviate from the actual interval of the current time by half a fundamental cycle, and the cancellation of the fundamental component will no longer be complete.

[0087] Therefore, in some embodiments, the inverter control method further includes the following steps.

[0088] Step S301: Determine the current value of the fundamental period.

[0089] The current value of the fundamental frequency period refers to the actual fundamental frequency period during inverter operation. The current value of the fundamental frequency period can be determined in several ways.

[0090] In one implementation, the current value of the fundamental period is determined based on the frequency of the reference voltage. That is, the controller 20 calculates the current value of the fundamental period according to the current frequency setting of the reference voltage. This method is suitable for situations where the output frequency is given by the controller 20 itself.

[0091] In another embodiment, zero-crossing detection is performed on the AC voltage output by the inverter, and the current value of the fundamental period is determined based on the time interval between two adjacent zero-crossings in the same direction. This method is suitable for situations where the output frequency follows changes in external conditions. When the inverter is operating in grid-connected mode, the current value of the fundamental period can also be determined from the grid frequency output by the phase-locked loop.

[0092] Step S302: Adjust the storage depth of the cache unit according to the current value so that the adjusted storage depth corresponds to half of the current fundamental frequency period.

[0093] Substitute the current value of the fundamental period into equation (17), recalculate the storage depth N, and adjust the number of storage units participating in the cyclic read / write operation in the cache unit according to the recalculated N. Continuing with the previous example, the preset sampling period Ts is 50μs, and N is 200 when the rated fundamental frequency is 50Hz; when the fundamental frequency shifts to 49.5Hz, the current value of the fundamental period is 20.202ms, N = 20.202ms / (2×50μs) ≈ 202, that is, the number of storage units participating in the cyclic read / write operation is adjusted to 202. After the adjustment, the interval between the earliest sampled value written in the cache unit and the current time corresponds to half a fundamental period again, and the averaging operation of equation (10) maintains the accuracy of the fundamental component cancellation.

[0094] It is understandable that within half a fundamental frequency cycle after the storage depth adjustment, some historical sampled values ​​in the cache unit are written at the storage depth before the adjustment. The interval between these values ​​and the current moment, and the adjusted half-fundamental frequency cycle, will deviate from the fundamental frequency cycle offset by no more than the amount of the fundamental frequency cycle offset. This transition phase naturally ends as the cache unit completes a round of writing at the new storage depth. Since the fundamental frequency changes slowly and slightly in practical applications, the offsetting deviation during the transition phase is limited and does not affect the overall suppression effect of the DC component.

[0095] Through steps S301 and S302, even if the fundamental period changes, the time interval of half a fundamental period on which the averaging calculation depends always matches the actual fundamental period, ensuring the elimination effect of the fundamental component in the bus feedforward voltage, and thus ensuring the suppression effect of the output DC component.

[0096] Please see Figure 7 , Figure 7 The inverter control method provided in this application includes a flowchart of step S103 for obtaining the modulation voltage, which includes the following steps.

[0097] Step S401: Obtain the error between the reference voltage and the feedback value of the AC voltage output by the inverter.

[0098] The reference voltage, denoted as Vr, is a given signal used to indicate the target waveform of the AC voltage output by the inverter. The reference voltage is given according to the amplitude and frequency of the target output. For example, when the target output is a sinusoidal voltage with an amplitude of 311V and a frequency of 50Hz, the reference voltage is given as Vr = 311·cos(ωt). The feedback value Uac of the AC voltage is obtained by the controller 20 sampling the AC voltage output by the inverter. Subtracting the feedback value Uac from the reference voltage Vr yields the error, which reflects the degree of deviation of the output AC voltage from the target waveform.

[0099] Step S402: Perform proportional-integral adjustment on the error to obtain the adjustment amount.

[0100] Proportional-integral (PI) regulation refers to the adjustment operation that amplifies the error proportionally and compensates for the cumulative deviation of the error over time through integral calculation. The error is adjusted to obtain the adjustment value, which is used to correct the deviation of the output AC voltage from the target waveform.

[0101] Step S403: Superimpose the adjustment amount with the reference voltage to obtain the modulation voltage.

[0102] The modulation voltage Uc is obtained by adding the adjustment amount to the reference voltage. In this structure, the reference voltage serves as the feedforward main component of the modulation voltage, and the adjustment amount serves as the closed-loop correction amount: the AC voltage output in steady state tracks the target waveform with very small error, and the adjustment amount is correspondingly small. The modulation voltage is mainly composed of the reference voltage, that is, the modulation voltage is approximately equal to the signal in the form of the fundamental frequency. This is consistent with the assumption of equation (1). The modulation voltage is close to the pure fundamental wave, which means that the numerator of equation (9) is basically free of stray harmonic components. This avoids the stray harmonics on the numerator side and the second harmonic components on the denominator side being coupled to generate additional frequency components through division. This, together with the elimination of the fundamental wave component on the denominator side in step S102, ensures that the frequency components of the duty cycle conform to the form on which the aforementioned implementation method is based.

[0103] Please see Figure 3 , Figure 3 A schematic block diagram of the controller provided in an embodiment of this application. (In conjunction with...) Figure 3 The connection relationships and signal flow of the various units within the controller 20 are explained. The controller 20 includes a buffer unit 21, an averaging unit 22, a divider 23, a PWM generator 24, and a PI regulator 25.

[0104] The reference voltage Vr and the feedback value Uac are subtracted by the first addition stage to obtain the error. The error is input to the PI regulator 25. The adjustment amount output by the PI regulator 25 is added to the reference voltage Vr by the second addition stage to obtain the modulation voltage Uc. The current sampled value Ubus(t) of the bus voltage is divided into two paths: one path is directly sent to the averaging unit 22, and the other path is written to the buffer unit 21. The buffer unit 21 outputs the sampled value Ubus(t) from half a fundamental cycle ago. T / 2) is fed into the averaging unit 22, and the averaging unit 22 outputs the bus feedforward voltage Uf according to formula (8); the modulation voltage Uc and the bus feedforward voltage Uf are respectively input to the numerator and denominator of the divider 23, and the divider 23 outputs the duty cycle D according to formula (9); the duty cycle D is input to the PWM generator 24, and the PWM generator 24 outputs the first drive signal PWM1, the second drive signal PWM2, the third drive signal PWM3 and the fourth drive signal PWM4.

[0105] It should be noted that the cache unit 21, the averaging unit 22, the divider 23, the PWM generator 24, and the PI regulator 25 are divisions made according to the functions of the controller 20 for control operations. Each unit can be implemented by the controller 20 executing corresponding program instructions, or it can be implemented by the hardware operation circuit inside the controller 20. The specific implementation form of each unit is not limited in the embodiments of this application.

[0106] In other embodiments, proportional-integral control can be replaced by other closed-loop control methods that can eliminate steady-state errors, such as proportional-integral-derivative control or proportional-resonant control. Accordingly, the PI controller 25 is replaced by a corresponding controller.

[0107] In summary, the inverter control method provided in this application eliminates the fundamental component of the bus voltage to obtain the bus feedforward voltage. This eliminates the fundamental component in the bus feedforward voltage that would cause the duty cycle to generate a DC component through ratio calculation. The DC component in the output AC voltage loses its path to be amplified through the feedforward path, and the mutually reinforcing cycle is cut off. The DC component in the inverter output AC voltage is suppressed, avoiding magnetic saturation, overcurrent, overheating of magnetic components and electrochemical corrosion of batteries and loads caused by the DC component, thus ensuring the safe operation of the transformer, inverter, battery and load.

[0108] Meanwhile, the bus feedforward voltage retains the DC component and second harmonic component in the bus voltage. Changes such as bus voltage drops and rises can still be reflected in the duty cycle in a timely manner and canceled out. The improvement effect of bus voltage feedforward on the inverter's dynamic performance is retained. The elimination of fundamental component is selective, taking into account both DC component suppression and dynamic performance.

[0109] Furthermore, when using averaging to eliminate the fundamental component, only the sampled values ​​of the bus voltage need to be buffered and averaged, without the need for any additional detection hardware. The required historical data is only half a fundamental cycle, and there is no long-term filtering delay in the feedforward channel. This averaging operation can also eliminate all odd-order harmonic components in the bus voltage at the same time. When using fundamental component extraction to eliminate the fundamental component, only one bandpass filter is needed, and the fundamental extraction signal is zero in steady state. The feedforward channel does not introduce any additional effects.

[0110] Please see Figure 10 , Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 900 includes at least one processor 910, at least one network interface 920, and a memory 930 communicatively connected to at least one processor 910. Figure 10 Take the 910 processor as an example.

[0111] Processor 910 is used to execute control calculations for the inverter. Processor 910 can be implemented using processing chips with sampling and computing capabilities, such as digital signal processors, microcontrollers, and field-programmable gate arrays. Network interface 920 is communicatively connected to the corresponding processor 910. Network interface 920 is used to establish communication connections between processor 910 and other external devices, such as communication connections with a host computer, energy management system, or cloud server, in order to monitor and manage the operating status of the inverter. Memory 930 stores instructions that can be executed by at least one processor 910. The instructions are executed by at least one processor 910 to enable at least one processor 910 to execute the inverter control method provided in any of the above embodiments.

[0112] The memory 930, as a non-volatile computer storage medium, can be used to store non-volatile software programs and non-volatile computer executable programs, such as the program instructions corresponding to the inverter control method in the above embodiments. The processor 910 executes the steps of the inverter control method by running the non-volatile software programs and instructions stored in the memory 930. The memory 930 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 930 may also include memory remotely located relative to the processor 910, and these remote memories can be connected to the electronic device 900 via a network.

[0113] The controller 20 in the aforementioned embodiments can be implemented as the electronic device 900 in this embodiment. That is, the controller 20 may include a processor 910 and a memory 930. The inverter control method is stored in the memory 930 in the form of instructions and is executed by the processor 910.

[0114] This application also provides a non-volatile computer storage medium storing computer-executable instructions. These instructions are executed by one or more processors, causing them to perform the inverter control method provided in any of the above embodiments. The non-volatile computer storage medium can be the aforementioned memory 930, or it can be any medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory, magnetic disk, or optical disk.

[0115] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An inverter control method, characterized in that, include: Obtain the inverter's bus voltage; The bus voltage is processed to eliminate the fundamental component, thus obtaining the bus feedforward voltage; Obtain the modulation voltage, which is used to characterize the target waveform of the AC voltage output by the inverter; The duty cycle is determined based on the ratio of the modulation voltage to the bus feedforward voltage; A drive signal is generated based on the duty cycle to drive the switching transistors of the inverter, thereby suppressing the DC component in the AC voltage output by the inverter. Wherein, the fundamental component is the AC component of the bus voltage with a frequency equal to the fundamental frequency, and the fundamental frequency is the frequency of the fundamental wave in the AC voltage output by the inverter; the bus feedforward voltage retains the DC component and the second harmonic component in the bus voltage, and the second harmonic component is the AC component of the bus voltage with a frequency equal to twice the fundamental frequency.

2. The method according to claim 1, characterized in that, The process of eliminating the fundamental component of the bus voltage to obtain the bus feedforward voltage includes: The sampled value of the bus voltage at the current moment and the sampled value of the bus voltage at a moment half a fundamental frequency cycle prior to the current moment are obtained; wherein, the fundamental frequency cycle is the period corresponding to the fundamental frequency. The bus feedforward voltage is calculated using the following formula: Where Uf is the bus feedforward voltage, t is the current time, and Ubus(t) is the sampled value at the current time. T / 2) is the sampled value before half a fundamental frequency period, where T is the fundamental frequency period.

3. The method according to claim 1, characterized in that, Also includes: The bus voltage is sampled according to a preset sampling period, and the sampled values ​​obtained from each sampling are sequentially written into a buffer unit. The storage depth of the buffer unit satisfies the following: Wherein, Ts is the preset sampling period, N is the storage depth, and T is the fundamental frequency period; The step of obtaining the sampled value of the bus voltage at a time half a fundamental cycle prior to the current moment includes: The earliest sampled value written is read from the cache unit and used as the sampled value half a fundamental cycle ago.

4. The method according to claim 3, characterized in that, The cache unit is a circular cache; Within each control cycle, after reading the earliest sampled value at the write time from the target storage location of the circular cache, the sampled value at the current time is written to the target storage location.

5. The method according to claim 1, characterized in that, The process of eliminating the fundamental component of the bus voltage to obtain the bus feedforward voltage includes: The fundamental component of the bus voltage is extracted to obtain the fundamental extracted signal; The bus feedforward voltage is calculated using the following formula: Wherein, Uf is the bus feedforward voltage, Ubus is the bus voltage, and U1 is the fundamental frequency extraction signal.

6. The method according to claim 5, characterized in that, The step of extracting the fundamental component of the bus voltage to obtain the fundamental extracted signal includes: The bus voltage is input to a bandpass filter and filtered to obtain the fundamental frequency extraction signal; wherein the fundamental frequency extraction signal satisfies: Wherein, U1(s) is the frequency domain representation of the fundamental extracted signal, Ubus(s) is the frequency domain representation of the bus voltage, and G1(s) is the transfer function of the bandpass filter.

7. The method according to any one of claims 1-6, characterized in that, Determining the duty cycle based on the ratio of the modulation voltage to the bus feedforward voltage includes: The duty cycle is calculated using the following formula: Wherein, D is the duty cycle, Uc is the modulation voltage, and Uf is the bus feedforward voltage.

8. An inverter, characterized in that, Includes a power circuit and a controller, wherein the power circuit includes a switching transistor; The controller is used to execute the inverter control method as described in any one of claims 1-7 to generate a drive signal to drive the switching transistor.

9. An electronic device, characterized in that, include: At least one processor; At least one network interface, which is communicatively connected to a corresponding processor, and the network interface is used to establish a communication connection between the processor and other external devices; A memory that is communicatively connected to the at least one processor; The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the inverter control method as described in any one of claims 1-7.

10. A non-volatile computer storage medium, characterized in that, The non-volatile computer storage medium stores computer-executable instructions; The computer-executable instructions are executed by one or more processors, causing the one or more processors to perform the inverter control method as described in any one of claims 1-7.

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