T-type three-level inverter, its equalization control method and power conversion device

Abstract

The application relates to the field of power electronics, and discloses a T-type three-level inverter, a balance control method thereof and a power conversion device. The device comprises a T-type three-level inverter circuit, an active midpoint balance circuit and a control circuit; the T-type three-level inverter circuit comprises a direct-current midpoint N formed by a common connection point of a first capacitor C1 and a second capacitor C2; the active midpoint balance circuit comprises M balance branches with the same structure, and the balance branches are staggered in parallel, wherein M is greater than or equal to 2; each balance branch comprises an upper bridge arm switching circuit, a lower bridge arm switching circuit and a balance inductor, and the connection point of the upper bridge arm switching circuit and the lower bridge arm switching circuit is connected to the direct-current midpoint N through the balance inductor; and the control circuit is configured to control the PWM carrier signal phases of the M balance branches to be sequentially different by 360° / M, so as to realize voltage balance regulation of the direct-current midpoint N. The application can realize balance of the midpoint potential, power density of the whole machine and operation efficiency.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a T-type three-level inverter, its equalization control method, and power conversion device. Background Technology

[0002] The T-type three-level converter topology is widely used in energy storage backup power equipment, uninterruptible power supplies (UPS), photovoltaic inverters, and energy storage converters (PCS) due to its low switching voltage stress, high output waveform quality, and excellent system efficiency. Its DC side outputs positive, zero, and negative voltage levels through a voltage divider network, allowing each transistor to withstand only half of the bus voltage. However, under complex operating conditions such as grid-connected charging, off-grid inverter backup power, and unbalanced loads, the DC bus midpoint potential of the T-type three-level converter topology is prone to shift, leading to increased output harmonics, intensified stress on power devices, and accelerated aging of DC-side capacitors.

[0003] Among the existing T-type three-level converter topology midpoint balancing technologies, one is a pure modulation algorithm scheme, which achieves midpoint regulation through SVPWM redundant vector allocation (see Chinese patent CN104702140B) or zero-sequence voltage injection (see Chinese patent CN109687747B). SHEPWM can also be used to perform midpoint balancing control by replacing small vectors (see Chinese patent CN205407622U). However, this type of scheme has limited regulation bandwidth, and the bus capacitor voltage difference exceeds the standard under severe load imbalance or high power impact conditions. Another is a hardware-assisted scheme, which adjusts the midpoint potential by adding an auxiliary switch branch on the DC bus side (see Chinese patent CN122119395A). However, in the existing scheme, the current regulation capability of the adjustment branch is limited by the current rating of a single switch tube, and the single branch bears all the ripple current, requiring a large filter inductor.

[0004] In the field of DC-DC converters, multi-phase interleaved parallel technology has been widely used to reduce single-channel current stress and offset ripple current. However, the midpoint balancing scenario of T-type three-level inverters has its own characteristics: the balancing branch shares the same DC bus with the main converter circuit, and the switching action of the balancing branch may have a coupling effect on the modulation of the main circuit; moreover, the midpoint balancing current needs to be switched bidirectionally in real time according to the potential deviation, which is different from the working mode of unidirectional DC-DC converters.

[0005] Therefore, how to effectively introduce multi-path interleaved parallel equalization technology into a T-type three-level converter topology and achieve coordinated control between the equalization branch and the main converter circuit remains a technical problem that needs to be solved. Summary of the Invention

[0006] To address the aforementioned technical problems, this application provides a T-type three-level inverter, its equalization control method, and a power conversion device.

[0007] Firstly, the T-type three-level inverter provided in this application adopts the following technical solution: A T-type three-level inverter includes a T-type three-level converter circuit, an active neutral point equalization circuit, and a control circuit. The T-type three-level converter circuit includes a first capacitor C1 and a second capacitor C2 connected in series between the positive DC bus and the negative DC bus. The common connection point of the first capacitor C1 and the second capacitor C2 is the DC neutral point N. The active neutral point equalization circuit is connected between the positive DC bus and the negative DC bus and includes M equalization branches with identical structures. The equalization branches are interleaved and connected in parallel, where M ≥ 2. Each equalization branch includes an upper bridge arm switching circuit and a lower bridge arm switching circuit. The system includes a switching circuit and an equalizing inductor. The upper and lower bridge arm switching circuits are connected in series between the positive and negative DC buses. The connection point of the upper and lower bridge arm switching circuits is connected to the DC midpoint N through the equalizing inductor. The control signal output of the control circuit is connected to the control terminals of the T-type three-level converter circuit and the active midpoint equalizing circuit, respectively. The control circuit is configured to control the PWM carrier signals of the M equalizing branches to have a phase difference of 360° / M, thereby achieving voltage equalization adjustment of the DC midpoint N.

[0008] By adopting the above technical solution, this application sets an active midpoint equalization circuit on the DC bus side of the T-type three-level converter circuit. Each equalization branch is connected to the DC midpoint N through an equalization inductor. The control circuit controls the PWM carrier signals of the M equalization branches to be phased by 360° / M, so that the equalization currents of each branch are interleaved and superimposed at the DC midpoint N. Compared with the single-path hardware-assisted solution, the M branches jointly bear the midpoint regulation current, and the equivalent midpoint regulation capacity is increased to M times that of a single path. Each branch only needs to bear 1 / M of the total regulation current, reducing the current stress and conduction loss of the single-path switching device. At the same time, the current ripple of each branch cancels each other out at the DC midpoint N, and the equivalent switching frequency is increased to M times that of a single path, reducing the high-frequency ripple current on the equalization inductor. This allows for the use of a smaller equalization inductor, reducing the inductor size and facilitating high power density integration of the equipment. Compared to pure modulation algorithm solutions, hardware active equalization provides a midpoint current compensation path with large bandwidth and large regulation capacity, which can suppress large shifts in midpoint potential under severe load imbalance or high power surges, thus compensating for the insufficient regulation bandwidth of pure software solutions. Therefore, this application simultaneously achieves a balance between midpoint potential equalization performance and overall power density and operating efficiency.

[0009] Optionally, the power level of each of the equalization branches is lower than the power level of the T-type three-level converter circuit.

[0010] By adopting the above technical solution, the power level of each equalization branch is lower than that of the T-type three-level converter circuit, so that the equalization branch provides auxiliary positioning for the main converter circuit. The equalization branch only needs to use switching devices with lower current rating, which helps to reduce material costs and conduction losses.

[0011] Optionally, the control circuit includes a voltage regulator and a current sharing distributor. The voltage regulator is used to generate a total equalization current command based on the voltage deviation between the first capacitor C1 and the second capacitor C2. The current sharing distributor is used to distribute the total equalization current command to the M equalization branches to generate current commands for each equalization branch.

[0012] By adopting the above technical solution, the control circuit samples the voltage deviation between the first capacitor C1 and the second capacitor C2 in real time through the voltage regulator, forming a voltage closed-loop control. This allows the midpoint potential deviation to directly participate in the regulation as feedback, ensuring that the midpoint potential approaches zero deviation in steady state. The total equalization current command output by the voltage regulator can adaptively adjust according to the magnitude and direction of the midpoint potential deviation. When the deviation increases, the equalization current command is automatically increased to accelerate correction; when the deviation decreases, the equalization current command is automatically decreased to prevent over-adjustment, thus balancing dynamic response speed and steady-state regulation accuracy. The current sharing distributor evenly distributes the total equalization current command to the M equalization branches, ensuring that each branch undertakes the same current regulation task. This provides a unified current reference for the subsequent independent current closed-loop control of each branch, guaranteeing the consistency of the control objectives of each branch under the multi-path interleaved parallel architecture.

[0013] Optionally, the control circuit further includes a current regulator, which is used to collect the current of the equalizing inductor in each equalizing branch, and generate a PWM duty cycle adjustment command signal for the corresponding branch based on the deviation between the current command of each branch and the sampled current of the corresponding equalizing inductor, so as to achieve equal current distribution among the equalizing branches.

[0014] By adopting the above technical solution, the control circuit further introduces a current inner loop on the basis of the voltage outer loop. The actual current of the balancing inductor in each balancing branch is collected in real time by the current regulator and compared with the current command of the corresponding branch. The PWM duty cycle of each branch is adjusted independently according to the deviation value, forming a dual closed-loop control structure of voltage outer loop and current inner loop. The introduction of the current inner loop brings the following technical benefits: First, the response speed of the current inner loop is faster than that of the voltage outer loop. It can quickly track and correct the inductor current of each branch in each PWM switching cycle, so that the actual current of each branch accurately follows the current command, improving the dynamic response performance of the system. Second, since the component parameters of the M equalization branches inevitably vary in actual engineering (such as the inductance deviation of the equalization inductor, the difference in the conduction impedance of the switching devices, etc.), without the current inner loop, the current of each branch will naturally be uneven due to the parameter differences, resulting in some branches being overloaded and others being underloaded. The current inner loop compensates for the influence of component parameter variation by independently adjusting the duty cycle of each branch, realizing accurate current sharing among the equalization branches. Third, the current sharing control makes the conduction loss and heat generation of the power devices in each branch tend to be consistent, avoiding local heat concentration and accelerated aging of devices caused by overcurrent in a single branch, improving the long-term reliability and service life of the system.

[0015] Optionally, the T-type three-level converter circuit operates in space vector pulse width modulation (SVPWM) mode; the control circuit is further configured to: control the M equalization branches to inject or extract equalization current into the DC midpoint N according to the potential deviation of the DC midpoint N, so as to suppress the dynamic potential shift of the DC midpoint N; and adjust the duration of the redundant vector in the SVPWM drive signal according to the potential deviation of the DC midpoint N, so as to reduce the steady-state deviation of the DC midpoint N; wherein, the PWM carrier signal of the M equalization branches and the SVPWM carrier signal of the T-type three-level converter circuit are synchronized based on the same clock source.

[0016] By adopting the above technical solution, the T-type three-level converter circuit operates in SVPWM mode. M equalization branches handle the main equalization adjustment of the midpoint potential (suppressing large offsets), while the SVPWM redundant vectors handle auxiliary fine-tuning (reducing steady-state error). Both are synchronized based on the same clock source, forming a composite control combining hardware active equalization and modulation algorithm fine-tuning. The hardware main equalization provides a large adjustment bandwidth to cope with large offsets, while the software-assisted fine-tuning provides high precision to reduce steady-state error. The two complement each other, achieving precise control of the midpoint potential under all operating conditions.

[0017] Optionally, M=3, and the PWM carrier signals of the three equalization branches are sequentially 120° out of phase.

[0018] By adopting the above technical solution, when M=3, the phase difference of the PWM carrier signals of the three equalization branches is 120°, which achieves three times the equivalent switching frequency and ripple cancellation effect, while taking into account the balance between circuit complexity and performance improvement.

[0019] Optionally, the switching devices in the upper bridge arm switching circuit and the lower bridge arm switching circuit include MOSFETs, HEMTs, or IGBTs.

[0020] By adopting the above technical solutions, the upper and lower bridge arm switching circuits use fully controllable switching devices such as MOSFETs, HEMTs, or IGBTs, which can realize bidirectional current flow and meet the bidirectional adjustment requirements of the equalization branch to inject or extract current to the DC midpoint N, thus adapting to the bidirectional power conversion application scenarios of the integrated energy storage and backup power unit.

[0021] Secondly, the power conversion device provided in this application adopts the following technical solution: A power conversion device includes an energy storage module and a T-type three-level inverter as described in any one of the first aspects; the DC side of the T-type three-level inverter is connected to the energy storage module, and the AC side is used to connect to an AC power grid or a load to achieve bidirectional power conversion.

[0022] By adopting the above technical solution, the power conversion device integrates the energy storage module and the above-mentioned T-type three-level inverter. The DC side is connected to the energy storage module, and the AC side is connected to the AC grid or load. It can realize bidirectional power conversion of grid-connected charging and off-grid inverter backup power. At the same time, it has the function of active equalization regulation of the midpoint potential. It is suitable for power conversion scenarios that require bidirectional power conversion and high-precision control of the midpoint potential, such as integrated energy storage backup power units and energy storage UPS.

[0023] Thirdly, the equalization control method for a T-type three-level inverter provided in this application adopts the following technical solution: A method for equalization control of a T-type three-level inverter, applied to a T-type three-level inverter as described in any of the first aspects; comprising the steps of: S1. Obtain the potential deviation of the DC midpoint N of the T-type three-level converter circuit; S2. Generate the total equalization current command for M equalization branches based on the potential deviation of the DC midpoint N. S3. Distribute the total equalization current command to the M equalization branches and generate the current command for each equalization branch. S4. Based on the current command of each equalization branch, generate PWM drive signals for the upper and lower bridge arm switching circuits in each equalization branch, and the phases of the PWM carrier signals of the M equalization branches are sequentially 360° / M apart.

[0024] By adopting the above technical solution, this application obtains the potential deviation of the DC midpoint N, generates a total equalization current command, and distributes it equally to M equalization branches. Each branch generates a PWM drive signal according to its own current command, and the phase difference of the PWM carrier signals of the M equalization branches is 360° / M. From the control method level, the interleaved parallel operation of the equalization current of each branch and the voltage equalization adjustment of the DC midpoint N are realized, forming a complete software and hardware collaborative solution with the hardware topology.

[0025] Optionally, step S1 specifically includes: sampling the voltage of the first capacitor C1 and the voltage of the second capacitor C2 on the DC side of the T-type three-level converter circuit, and calculating the voltage deviation between the first capacitor C1 and the second capacitor C2 as the potential deviation of the DC midpoint N. Step S2 specifically includes: sending the voltage deviation to the voltage regulator of the control circuit to generate a total equalization current command; Step S4 specifically includes: sampling the current of the equalizing inductor in each equalizing branch, comparing the current command of each equalizing branch with the sampled current of the corresponding equalizing inductor, sending the comparison result to the current regulator of the control circuit, and generating PWM duty cycle adjustment command signals for the upper bridge arm switch circuit and the lower bridge arm switch circuit of each equalizing branch.

[0026] By adopting the above technical solution, the control circuit uses a dual closed-loop control structure of voltage outer loop and current inner loop. The voltage outer loop generates a total equalization current command based on the voltage deviation of C1 and C2, and the current inner loop generates PWM duty cycle adjustment command signals for each branch based on the feedback of the inductor current of each branch. This achieves precise control of the midpoint voltage and rapid tracking of the current of each branch, thereby improving the dynamic response performance and steady-state accuracy of the system.

[0027] In summary, this application includes at least one of the following beneficial technical effects: 1. By setting up M equalization branches connected in parallel to the DC midpoint N, and making the phase difference of the PWM carrier signals of each equalization branch 360° / M, the equalization branches operate in staggered parallel mode. The M equalization branches share the midpoint regulation current, increasing the equivalent midpoint regulation capacity to M times that of a single channel, reducing the current stress and conduction loss of the single-channel switching device. At the same time, the current ripple of each equalization branch cancels each other out at the DC midpoint N, increasing the equivalent switching frequency to M times that of a single channel, reducing the high-frequency ripple current on the equalization inductor, thus allowing the use of a smaller equalization inductor, reducing the inductor size, and facilitating high power density integration of the equipment. 2. Through a dual closed-loop control structure of voltage outer loop and current inner loop, the voltage outer loop adaptively generates a total equalization current command based on the voltage deviation between the first capacitor C1 and the second capacitor C2, achieving precise closed-loop control of the midpoint potential; the current inner loop independently samples the actual current of the equalization inductor in each equalization branch, and independently adjusts the PWM duty cycle of each branch according to the deviation between the current command and the actual current of each branch, compensating for the influence of component parameter dispersion and temperature drift in each branch, and achieving precise equalization of current in each branch; the dual closed-loop collaborative control enables the system to have both fast dynamic response and high steady-state accuracy, while ensuring uniform heating of power devices in each branch, preventing overload of a single branch, and improving the long-term reliability and service life of the system; 3. By controlling M equalization branches to undertake the main equalization adjustment of the midpoint potential to suppress large potential deviations, and using SVPWM redundant vectors to undertake auxiliary fine-tuning to reduce steady-state deviations, and both are based on the same clock source for synchronization, a composite control combining hardware active equalization and modulation algorithm fine-tuning is formed, which takes into account both large adjustment bandwidth and high steady-state accuracy, and achieves precise control of the midpoint potential under all operating conditions. Attached Figure Description

[0028] Figure 1 This is a circuit block diagram of the T-type three-level inverter provided in the embodiments of this application; Figure 2 This is a circuit connection diagram of the T-type three-level converter circuit and the active midpoint equalization circuit provided in the embodiments of this application; Figure 3 This is a circuit connection diagram of another T-type three-level converter circuit and an active midpoint equalization circuit provided in the embodiments of this application; Figure 4 This is a control logic block diagram of the active neutral point equalization branch of a T-type three-level inverter provided in an embodiment of this application; Figure 5 This is a flowchart of the equalization control method for a T-type three-level inverter provided in an embodiment of this application; Figure 6 This is a structural block diagram of the power conversion device provided in the embodiments of this application.

[0029] Explanation of reference numerals in the attached figures: 10. T-type three-level converter circuit; 11. T-type three-level switching network; 12. Bus voltage divider capacitor; 20. Active midpoint equalization circuit; 30. Control circuit; 31. SVPWM drive unit; 32. ADC sampling unit; 33. Bridge arm drive unit; 331. PWM generator; 34. Calculation unit; 341. Voltage regulator; 342. Current sharing distributor; 343. Current regulator; 100. T-type three-level inverter; 200. Energy storage module. Detailed Implementation

[0030] The following is in conjunction with the appendix Figure 1-6 This application will be described in further detail.

[0031] This application discloses a T-type three-level inverter. (Refer to...) Figure 1 The T-type three-level inverter 100 includes a T-type three-level converter circuit 10, an active neutral point equalization circuit 20, and a control circuit 30.

[0032] The T-type three-level converter circuit 10 includes a T-type three-level switching network 11 and a bus voltage divider capacitor 12. The bus voltage divider capacitor 12 consists of a first capacitor C1 and a second capacitor C2 connected in series between the positive DC bus BUS+ and the negative DC bus BUS-. The common connection point of the first capacitor C1 and the second capacitor C2 is the DC midpoint N. The T-type three-level switching network 11 is connected across the positive DC bus BUS+, the DC midpoint N, and the negative DC bus BUS-. It includes an upper bridge arm switch Q7, a lower bridge arm switch Q9, and bidirectional switches Q8 and Q10 forming the middle branch of the T-type bridge arm connected to the midpoint N. The AC side of the T-type three-level switching network 11 is connected to the AC mains or load through an LC filter consisting of an AC side filter inductor L4 and an AC side filter capacitor C3. A fourth current sensor Hal4 is connected in series in the AC side filter inductor L4 branch for sampling the AC side current.

[0033] An active midpoint equalization circuit 20 is connected between the positive DC bus BUS+ and the negative DC bus BUS-, and is used to adjust the potential of the DC midpoint N. The active midpoint equalization circuit 20 includes M equalization branches with identical structures, where M ≥ 2. Each equalization branch includes an upper bridge arm switch circuit, a lower bridge arm switch circuit, and an equalization inductor. The upper and lower bridge arm switch circuits are connected in series between the positive DC bus BUS+ and the negative DC bus BUS-, and the connection point of the upper and lower bridge arm switch circuits is connected to the DC midpoint N through the equalization inductor. In one embodiment, the power rating of each equalization branch is lower than the power rating of the T-type three-level converter circuit 10.

[0034] With the above settings, the active midpoint equalization circuit 20 serves as an auxiliary adjustment unit independent of the T-type three-level converter circuit 10. It does not participate in the main power conversion and is only used for the active adjustment of the DC midpoint N potential. While realizing the midpoint equalization function, it does not affect the energy conversion efficiency of the main circuit.

[0035] The control signal output terminal of the control circuit 30 is connected to the control terminals of the T-type three-level converter circuit 10 and the active neutral point equalization circuit 20, respectively. The control circuit 30 is configured to control the PWM carrier signals of the M equalization branches to have a phase difference of 360° / M between each other, so as to realize the parallel operation of each equalization branch and the voltage equalization regulation of the DC neutral point N.

[0036] It should be noted that the "equalizing branches with the same structure" in the embodiments of this application refer to equalizing branches that have the same circuit topology, but the circuit parameters of each branch (such as the specific inductance value of the equalizing inductor and the specific model of the switching device) may differ within a certain range, as long as each branch can achieve current sharing operation under the control of the control circuit.

[0037] Reference Figure 2 In one embodiment, a circuit connection diagram of an active midpoint equalization circuit 20 is shown, where M=2. The active midpoint equalization circuit 20 includes two identical equalization branches. The first equalization branch includes an upper bridge arm switch circuit Q1, a lower bridge arm switch circuit Q2, and an equalization inductor L1. The upper bridge arm switch circuit Q1 and the lower bridge arm switch circuit Q2 are connected in series between the positive DC bus BUS+ and the negative DC bus BUS-. The connection point of the upper bridge arm switch circuit Q1 and the lower bridge arm switch circuit Q2 is connected to the DC midpoint N through the equalization inductor L1. The second equalization branch includes an upper bridge arm switch circuit Q3, a lower bridge arm switch circuit Q4, and an equalization inductor L2. The upper bridge arm switch circuit Q3 and the lower bridge arm switch circuit Q4 are connected in series between the positive DC bus BUS+ and the negative DC bus BUS-. The connection point of the upper bridge arm switch circuit Q3 and the lower bridge arm switch circuit Q4 is connected to the DC midpoint N through the equalization inductor L2. The PWM carrier signals of the two equalization branches are 180° out of phase. The ADC sampling unit 32 of the control circuit 30 samples the voltage VC1 of the first capacitor C1, the voltage VC2 of the second capacitor C2, and the current IL1 of the equalizing inductor L1 and the current IL2 of the equalizing inductor L2.

[0038] By using the above-mentioned two-way interleaved parallel configuration with M=2, the two balanced branches share the midpoint regulation current, which reduces the current stress on the switching devices by half compared to the single-path scheme; at the same time, the ripple current of the two branches is partially canceled out at the DC midpoint N, which helps to reduce the ripple current on the balanced inductor.

[0039] In one embodiment, the current IL1 of the balancing inductor L1 is acquired by a first current sensor Hal1 connected in series in the branch of the balancing inductor L1, and the current IL2 of the balancing inductor L2 is acquired by a second current sensor Hal2 connected in series in the branch of the balancing inductor L2. In one embodiment, the first current sensor Hal1 and the second current sensor Hal2 are Hall current sensors.

[0040] It is understandable that the type of current sensor is not limited to Hall current sensors. Other current detection methods such as sampling resistors, current transformers, or fluxgate sensors can also be used, as long as the magnitude and direction of the equalizing inductor current can be obtained in real time.

[0041] Reference Figure 3In another embodiment, a circuit connection diagram of another active midpoint equalization circuit 20 is shown, where M=3. The active midpoint equalization circuit 20 includes three identical equalization branches. The first equalization branch includes an upper bridge arm switch circuit Q1, a lower bridge arm switch circuit Q2, and an equalization inductor L1; the second equalization branch includes an upper bridge arm switch circuit Q3, a lower bridge arm switch circuit Q4, and an equalization inductor L2; the third equalization branch includes an upper bridge arm switch circuit Q5, a lower bridge arm switch circuit Q6, and an equalization inductor L3. The connection points of the upper and lower bridge arm switch circuits of the three equalization branches are connected to the DC midpoint N through equalization inductors L1, L2, and L3, respectively. The PWM carrier signals of the three equalization branches are sequentially phase-differentiated by 120°. The ADC sampling unit 32 of the control circuit 30 samples the voltage VC1 of the first capacitor C1, the voltage VC2 of the second capacitor C2, and the currents IL1, IL2, and IL3 of the equalization inductors L1, L2, and L3, respectively. Specifically, the current IL1 of the balancing inductor L1 is collected by the first current sensor Hal1 connected in series in the branch of the balancing inductor L1, the current IL2 of the balancing inductor L2 is collected by the second current sensor Hal2 connected in series in the branch of the balancing inductor L2, and the current IL3 of the balancing inductor L3 is collected by the third current sensor Hal3 connected in series in the branch of the balancing inductor L3.

[0042] Understandably, M=3 is preferred. Through the above three-way interleaved parallel configuration, the three equalizing branches share the midpoint regulation current, and the single-path switching device only needs to bear one-third of the total regulation current, further reducing the current stress of the single-path device; at the same time, the ripple current of the three branches cancels each other out at the DC midpoint N, and the equivalent switching frequency is increased to 3 times that of a single path. The high-frequency ripple current on the equalizing inductor will be further reduced, thus allowing the use of a smaller equalizing inductor, which is beneficial to reducing the inductor size and increasing the overall power density.

[0043] The control circuit 30 is further configured to: sample the voltage VC1 of the first capacitor C1 and the voltage VC2 of the second capacitor C2, and generate a PWM duty cycle adjustment command signal for controlling the M equalization branches based on the voltage deviation ΔV = VC1 - VC2 between the first capacitor C1 and the second capacitor C2. The control circuit 30 also samples the current of the equalization inductor in each equalization branch, and fine-tunes the PWM duty cycle of the corresponding branch based on the deviation of the current in each branch, thereby achieving current equalization among the equalization branches.

[0044] Through the dual closed-loop control consisting of the voltage outer loop and the current inner loop, the voltage outer loop generates a total equalization current command based on the voltage deviation between the first capacitor C1 and the second capacitor C2, determining the total current amount and direction of the midpoint equalization adjustment, ensuring that the potential of the DC midpoint N approaches equilibrium under steady state. The current inner loop independently adjusts the PWM duty cycle of each branch based on the inductor current feedback, ensuring that the actual current of each branch accurately follows the current command, achieving current sharing among the branches. In the dual closed-loop control structure, the voltage outer loop determines "how much to adjust," while the current inner loop determines "how each branch shares the load," with clear division of labor and coordinated cooperation between the two loops. The bandwidth of the voltage outer loop is designed to be lower than that of the current inner loop, enabling the current inner loop to complete current tracking and current sharing adjustment within each adjustment step of the voltage outer loop, ensuring system stability. During transient processes such as load changes or operating condition switching, the outer voltage loop rapidly adjusts the overall equalization current command to cope with significant shifts in the midpoint potential. Simultaneously, the inner current loop precisely distributes the adjusted current command to each branch and tracks it quickly, enabling the M equalization branches to respond collaboratively. This reduces circulating current or overcurrent problems caused by current imbalances in branch current distribution during transient processes. In steady-state operation, the outer voltage loop maintains zero-deviation control of the midpoint potential, while the inner current loop continuously compensates for parameter drift in each branch caused by factors such as temperature changes and device aging, maintaining long-term current balance in each branch.

[0045] It is understood that this application does not limit the specific value of M; M can be 2, 3, 4, or more. The larger the value of M, the smaller the current carried by each branch, and the more significant the ripple cancellation effect, but the circuit complexity also increases accordingly. In practical applications, the value can be flexibly selected according to the power level, size requirements, and cost constraints.

[0046] Reference Figure 1 and Figure 4 The control circuit 30 includes an ADC sampling unit 32, a calculation unit 34, an SVPWM drive unit 31, and a bridge arm drive unit 33.

[0047] The input terminal of the ADC sampling unit 32 is connected to the two ends of the first capacitor C1, the two ends of the second capacitor C2, and the output terminal of the current sensor in each equalization branch. It is used to sample the voltage VC1 of the first capacitor C1, the voltage VC2 of the second capacitor C2, and the current IL_i (i=1,2,M) of each equalization inductor, and then convert the sampled signal into a digital quantity and transmit it to the calculation unit 34.

[0048] The calculation unit 34 includes a voltage regulator 341, a current sharing distributor 342, and a current regulator 343. The voltage regulator 341 generates a total equalization current command I_ref based on the voltage deviation ΔV = VC1 - VC2 between the first capacitor C1 and the second capacitor C2 using a PI calculation. The current sharing distributor 342 distributes the total equalization current command I_ref equally among the M equalization branches, generating a current command I_ref_i = I_ref / M (i = 1, 2, ..., M) for each branch. The current regulator 343 generates a duty cycle adjustment command signal D_i (i = 1, 2, ..., M) for each branch based on the deviation between the current command I_ref_i of each branch and the corresponding equalization inductor sampling current IL_i, using a PI calculation.

[0049] It should be noted that both the voltage regulator 341 and the current regulator 343 can be implemented using a PI (proportional-integral) regulator, or a PR (proportional-resonant) regulator, a PID regulator, or other closed-loop control algorithms. This application does not limit the specific algorithm type of the regulator. The control bandwidth of the voltage regulator 341 is designed to be lower than that of the current regulator 343 to ensure the stability of the dual closed-loop system. In one embodiment, the control bandwidth of the voltage regulator 341 is 1 / 5 to 1 / 10 of the control bandwidth of the current regulator 343, enabling the inner current loop to complete rapid tracking and current sharing regulation of the current in each branch within each regulation cycle of the outer voltage loop.

[0050] The bridge arm drive unit 33 receives the duty cycle adjustment command signals D_i of each branch output by the calculation unit 34. The bridge arm drive unit 33 internally contains a PWM generator 331. The PWM generator 331 compares the duty cycle command D_i of each branch with an internal triangular carrier wave to generate PWM drive signals for the upper and lower bridge arm switching circuits of each balanced branch. The PWM carrier signals of the M balanced branches are sequentially phase-differentiated by 360° / M. Taking M=3 as an example, the PWM carrier signals of the three balanced branches are sequentially phase-differentiated by 120°.

[0051] In one embodiment, the PWM carrier frequency of the bridge arm drive unit 33 and the SVPWM carrier frequency of the SVPWM drive unit 31 can be the same or different, as long as they are phase-synchronized based on the same clock source.

[0052] It is understandable that, through the above-mentioned PWM carrier interleaving setting, the drive signals PWM_i (i=1,2,…,M) of each equalization branch operate alternately in time, so that the output current of each branch is interleaved and superimposed at the DC midpoint N, reducing the fluctuation of the total equalization current, thereby reducing the core loss and winding loss on the equalization inductor.

[0053] The SVPWM driver unit 31 is used to generate the SVPWM drive signal for the T-type three-level switching network 11. The T-type three-level converter circuit 10 operates in space vector pulse width modulation (SVPWM) mode. The PWM carrier of the bridge arm driver unit 33 and the SVPWM carrier of the SVPWM driver unit 31 are synchronized based on the same clock source.

[0054] In one embodiment, synchronization based on the same clock source is achieved as follows: the control circuit 30 adopts a master-slave architecture of DSP and FPGA. The DSP is used to execute control algorithm calculations (including generating the total equalization current command, the current commands of each branch, and the SVPWM redundancy vector adjustment), and the FPGA is used to generate the PWM drive signals of the M equalization branches and the SVPWM drive signals of the T-type three-level converter circuit. The DSP and FPGA transmit synchronization pulse signals through a hardware interface; whenever a sampling operation cycle of the DSP begins, the DSP sends a synchronization pulse to the FPGA, and the FPGA corrects the phase of its internal PWM counter according to the synchronization pulse, so that the PWM drive signal output by the FPGA is synchronized with the sampling operation of the DSP.

[0055] In one embodiment, the DSP and FPGA exchange data via the Xintf interface or the GPIO interface, and the synchronization pulse is transmitted through the GPIO interface; the FPGA corrects its internal PWM counter according to the rising and falling edges of the synchronization pulse to achieve locking of the PWM carrier phase with the SVPWM carrier phase.

[0056] The control circuit 30 is also configured to: inject or extract equalization current into or from the DC midpoint N based on the potential deviation of the DC midpoint N, so as to suppress the dynamic potential shift of the DC midpoint N; and adjust the duration of the redundant vector in the SVPWM drive signal based on the potential deviation of the DC midpoint N, so as to reduce the steady-state deviation of the DC midpoint N. That is, the M equalization branches undertake the main equalization adjustment of the midpoint potential, and the SVPWM redundant vector undertakes auxiliary fine-tuning. Both are synchronized based on the same clock source, forming a composite control combining hardware active equalization and modulation algorithm fine-tuning.

[0057] Specifically, taking M=3 as an example, the process of injecting or extracting balancing current in the balancing branch is as follows: When VC1 > VC2, the potential of the DC midpoint N is biased towards the positive DC bus BUS+. At this time, C1 needs to discharge and C2 needs to charge. Control circuit 30 controls the lower bridge arm switch circuit of the three balancing branches to turn off, and the upper bridge arm switch circuit to conduct at high frequency using PWM. This causes current to flow from BUS+ through the upper bridge arm switch circuit and the balancing inductor to the DC midpoint N, injecting balancing current into the midpoint N. The balancing currents of the three branches converge at the DC midpoint N, causing C2 to charge and C1 to discharge, and the potential of the DC midpoint N to drop back down.

[0058] When VC2 > VC1, the potential of the DC midpoint N is biased towards the negative DC bus BUS- side. At this time, C2 needs to discharge and C1 needs to charge. Correspondingly, control circuit 30 controls the upper bridge arm switch circuit of the three balancing branches to turn off, and the lower bridge arm switch circuit to conduct at high frequency using PWM. This causes current to flow from the midpoint N through the balancing inductor to the lower bridge arm switch circuit, and then back through BUS-, i.e., drawing balancing current from the midpoint N. All three branches draw current from the midpoint N together, causing C2 to discharge and C1 to charge, and the potential of the DC midpoint N to rise again.

[0059] The PWM carrier signals of the three balancing branches are sequentially phased by 120°. Therefore, the upper or lower bridge arm switching circuits of each branch do not operate simultaneously, but rather alternately, causing the balancing currents of each branch to overlap at the DC midpoint N. Taking the case where VC1 > VC2 and current needs to be injected into the midpoint N as an example, the upper bridge arm switching circuit of branch 1 turns on first, the upper bridge arm switching circuit of branch 2 turns on with a 120° delay, and the upper bridge arm switching circuit of branch 3 turns on with a further 120° delay. The balancing currents of each branch arrive at the DC midpoint N alternately in time, significantly reducing the ripple of the total balancing current after convergence, thus achieving smooth current injection.

[0060] Understandably, through the above-mentioned composite control, the hardware main equalizer provides a large adjustment bandwidth to cope with the large potential shift caused by sudden load changes or severe imbalances, while the software-assisted fine-tuning provides high-precision correction to reduce steady-state deviation. The two complement each other, achieving precise control of the midpoint potential.

[0061] In one embodiment, both the upper and lower bridge arm switching circuits can employ fully controllable switching devices such as MOSFETs, HEMTs, or IGBTs to achieve bidirectional current flow. Preferably, both the upper and lower bridge arm switching circuits use SiC MOSFETs as switching devices.

[0062] It should be noted that the "upper bridge arm switch circuit" and "lower bridge arm switch circuit" in the various embodiments of this application are all semiconductor switching devices or combinations thereof with controllable switching capability. Their specific types are not limited to the examples listed in the embodiments of this application. Any switching device that can achieve controlled conduction and shutdown can be applied.

[0063] Reference Figure 4 and Figure 5 This application also discloses an equalization control method for a T-type three-level inverter, applied to the aforementioned T-type three-level inverter 100. The method includes the following steps: S1. Obtain the potential deviation of the DC midpoint N of the T-type three-level converter circuit 10. Specifically, the ADC sampling unit 32 samples the voltage VC1 of the first capacitor C1 and the voltage VC2 of the second capacitor C2, and calculates the voltage deviation ΔV = VC1 - VC2 between the first capacitor C1 and the second capacitor C2 as the potential deviation of the DC midpoint N.

[0064] S2. Based on the potential deviation of the DC midpoint N, generate a total balancing current command for M balancing branches. Specifically, the voltage regulator 341 uses a PI calculation to generate the total balancing current command I_ref from the voltage deviation ΔV = VC1 - VC2.

[0065] S3. Distribute the total equalization current command to the M equalization branches and generate the current command for each equalization branch. Specifically, the current sharing distributor 342 distributes the total equalization current command I_ref equally to the M equalization branches and generates the current command for each branch I_ref_i = I_ref / M.

[0066] S4. Based on the current commands of each balancing branch, generate PWM drive signals for the upper and lower bridge arm switching circuits in each balancing branch, with the PWM carrier signals of the M balancing branches differing in phase by 360° / M. Specifically, the current regulator 343 compares the current command I_ref_i of each branch with the sampled current IL_i of the corresponding balancing inductor, sends the comparison result to the current regulator 343, and generates the duty cycle command D_i of each branch through PI calculation; the PWM generator 331 inside the bridge arm drive unit 33 compares the duty cycle command D_i with the internal triangular carrier to generate the PWM drive signals for the upper and lower bridge arm switching circuits of each balancing branch. Taking M=3 as an example, the PWM carrier signals of the three balancing branches differ in phase by 120°.

[0067] It should be noted that the numbering of steps S1 to S4 above is for ease of description only and is not a strict limitation on the execution order. In actual control, steps S1 to S4 can be executed cyclically, that is, the above steps are executed cyclically with a preset control cycle to achieve real-time continuous adjustment of the DC midpoint N potential.

[0068] In one embodiment, the duty cycle of the PWM drive signal of the M equalization branches can be further corrected according to the temperature feedback of each branch to compensate for the impact of the device on-resistance change caused by temperature difference on the current sharing accuracy.

[0069] The above method steps realize a complete control link from "midpoint potential detection → total current command generation → current sharing distribution in each branch → PWM drive signal generation in each branch". The method is simple, has a fast response speed, and can track midpoint potential changes in real time and make dynamic adjustments.

[0070] Reference Figure 6 This application also discloses a power conversion device, including an energy storage module 200 and the aforementioned T-type three-level inverter 100. The DC side of the T-type three-level inverter 100 is connected to the energy storage module 200, and the AC side of the T-type three-level inverter 100 is used to connect to the AC power grid or load to achieve bidirectional power conversion.

[0071] Understandably, the energy storage module 200 can be any of a lithium battery pack, lead-acid battery pack, or supercapacitor module. The power conversion device can be applied to scenarios requiring bidirectional power conversion, such as integrated energy storage backup power units or energy storage uninterruptible power supplies (UPS).

[0072] Through the above integrated setup, the power conversion device can realize the charging and discharging management of energy storage batteries and the off-grid backup power supply, while also having the function of active equalization regulation of the DC bus midpoint potential, which improves the operational stability of the device and the service life of the capacitor under complex operating conditions.

[0073] The implementation principle of a T-type three-level inverter according to an embodiment of this application is as follows: The control circuit 30 samples the voltage VC1 of the first capacitor C1 and the voltage VC2 of the second capacitor C2 on the DC side in real time through the ADC sampling unit 32, and calculates the deviation between the two as ΔV = VC1 - VC2 as the potential deviation of the DC midpoint N. The voltage regulator 341 in the calculation unit 34 generates a total equalization current command I_ref based on this deviation. The current sharing distributor 342 distributes I_ref equally to M equalization branches, generating the current command I_ref_i for each branch. The current regulator 343 compares the current command I_ref_i of each branch with the corresponding equalization inductor sampling current IL_i fed back by the ADC sampling unit 32, and generates the duty cycle command D_i for each branch through PI calculation. The PWM generator 331 inside the bridge arm drive unit 33 compares the duty cycle command D_i with the internal triangular carrier wave to generate the PWM drive signal for the upper and lower bridge arm switching circuits of each equalization branch. Simultaneously, the SVPWM drive unit 31 generates the SVPWM drive signal for the T-type three-level switching network 11, and the PWM carrier of the bridge arm drive unit 33 and the SVPWM carrier of the SVPWM drive unit 31 are synchronized based on the same clock source. When VC1>VC2, the equalization branch injects current into the midpoint N, discharging C1 and charging C2; when VC2>VC1, the equalization branch draws current from the midpoint N, discharging C2 and charging C1, thereby forcing the voltages of C1 and C2 to remain consistent. The PWM carrier signals of the M equalization branches are sequentially phase-differentiated by 360° / M, and the equalization currents of each branch are interleaved and superimposed at the DC midpoint N, with ripples canceling each other out, thereby reducing the loss on the equalization inductor, allowing for the use of a smaller inductor, which is beneficial to improving the overall power density. Thus, real-time, high-precision active equalization adjustment of the DC bus midpoint potential of the T-type three-level inverter 100 is achieved.

[0074] It should be noted that the "connection" in the embodiments of this application can be a direct electrical connection or an indirect electrical connection through other intermediate components (such as wires, connectors, protection circuits, etc.), as long as signal transmission or power transfer can be achieved. The "circuit" in the embodiments of this application can be a circuit composed of discrete components, a functional circuit inside an integrated chip, or a combination of both.

[0075] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A T-type three-level inverter, characterized in that, include: T-type three-level converter circuit (10), the T-type three-level converter circuit (10) includes a first capacitor C1 and a second capacitor C2 connected in series between the positive DC bus and the negative DC bus, the common connection point of the first capacitor C1 and the second capacitor C2 is the DC midpoint N; An active midpoint equalization circuit (20) is connected between the positive DC bus and the negative DC bus, including M equalization branches with the same structure. The equalization branches are connected in parallel and interleaved, where M≥2. Each equalization branch includes an upper bridge arm switch circuit, a lower bridge arm switch circuit and an equalization inductor. The upper bridge arm switch circuit and the lower bridge arm switch circuit are connected in series between the positive DC bus and the negative DC bus. The connection point of the upper bridge arm switch circuit and the lower bridge arm switch circuit is connected to the DC midpoint N through the equalization inductor. The control circuit (30) is connected to the control terminals of the T-type three-level converter circuit (10) and the active midpoint equalization circuit (20), respectively. The control circuit (30) is configured to control the phase difference of the PWM carrier signals of the M equalization branches by 360° / M in sequence to achieve voltage equalization adjustment of the DC midpoint N.

2. The T-type three-level inverter according to claim 1, characterized in that, The power level of each of the equalization branches is lower than the power level of the T-type three-level converter circuit (10).

3. The T-type three-level inverter according to claim 1, characterized in that, The control circuit (30) includes a voltage regulator (341) and a current sharing distributor (342). The voltage regulator (341) is used to generate a total equalization current command based on the voltage deviation between the first capacitor C1 and the second capacitor C2. The current sharing distributor (342) is used to distribute the total equalization current command to the M equalization branches and generate a current command for each equalization branch.

4. The T-type three-level inverter according to claim 3, characterized in that, The control circuit (30) further includes a current regulator (343), which is used to collect the current of the equalizing inductor in each equalizing branch, and generate a PWM duty cycle adjustment command signal for the corresponding branch according to the deviation between the current command of each branch and the sampled current of the corresponding equalizing inductor, so as to realize the equal distribution of current among each equalizing branch.

5. The T-type three-level inverter according to claim 1, characterized in that, The T-type three-level converter circuit (10) operates in space vector pulse width modulation (SVPWM) mode; the control circuit (30) is also configured to: Based on the potential deviation of the DC midpoint N, control the M equalization branches to inject or extract equalization current into the DC midpoint N to suppress the dynamic potential shift of the DC midpoint N. Furthermore, the duration of the redundant vector in the SVPWM drive signal is adjusted according to the potential deviation of the DC midpoint N in order to reduce the steady-state deviation of the DC midpoint N. Among them, the PWM carrier signal of the M equalization branches is synchronized with the SVPWM carrier signal of the T-type three-level converter circuit (10) based on the same clock source.

6. The T-type three-level inverter according to claim 1, characterized in that, With M=3, the PWM carrier signals of the three balanced branches are sequentially 120° out of phase.

7. The T-type three-level inverter according to claim 1, characterized in that, The switching devices in the upper bridge arm switching circuit and the lower bridge arm switching circuit include MOSFETs, HEMTs, or IGBTs.

8. A power conversion device, characterized in that, include: The energy storage module (200) and the T-type three-level inverter (100) as described in any one of claims 1-7; the DC side of the T-type three-level inverter (100) is connected to the energy storage module (200), and the AC side is used to connect to the AC power grid or load to achieve bidirectional power conversion.

9. A method for equalization control of a T-type three-level inverter, applied to the T-type three-level inverter as described in any one of claims 1-7; characterized in that, Including the following steps: S1. Obtain the potential deviation of the DC midpoint N of the T-type three-level converter circuit (10); S2. Generate the total equalization current command for M equalization branches based on the potential deviation of the DC midpoint N. S3. Distribute the total equalization current command to the M equalization branches and generate the current command for each equalization branch. S4. Based on the current command of each equalization branch, generate PWM drive signals for the upper and lower bridge arm switching circuits in each equalization branch, and the phases of the PWM carrier signals of the M equalization branches are sequentially 360° / M apart.

10. The equalization control method according to claim 9, characterized in that, Step S1 specifically includes: sampling the voltage of the first capacitor C1 and the second capacitor C2 on the DC side of the T-type three-level converter circuit (10), and calculating the voltage deviation between the first capacitor C1 and the second capacitor C2 as the potential deviation of the DC midpoint N; Step S2 specifically includes: sending the voltage deviation to the voltage regulator (341) to generate a total equalization current command; Step S4 specifically includes: sampling the current of the equalizing inductor in each equalizing branch, comparing the current command of each equalizing branch with the sampled current of the corresponding equalizing inductor, sending the comparison result to the current regulator (343), and generating PWM duty cycle adjustment command signals for the upper bridge arm switch circuit and the lower bridge arm switch circuit of each equalizing branch.

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