Integrated circuit driving system of three-phase motor with hall without MCU

Abstract

The application discloses an integrated circuit driving system of a three-phase motor with a Hall without an MCU, which is mainly composed of a three-eight decoder, an inverter, an XOR gate and a gate driver, the three-eight decoder is used for converting a Hall signal into a corresponding binary output, the inverter and the XOR gate are mainly used for logic processing of the binary signal, and the gate driver is mainly used for driving upper and lower power MOS tubes of a three-phase bridge. The three-eight decoder, the inverter, the XOR gate and the gate driver jointly constitute an integrated circuit driving scheme of a three-phase motor with a Hall without an MCU, and provide a simpler driving scheme for a BLDC motor with a Hall sensor, directly use a Hall signal output of the motor itself as a driving signal input, and make the motor work by a six-step commutation mode. The single-chip directly replaces the MCU, reduces complexity, and improves the simplicity of application.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, specifically to an integrated circuit drive system for a Hall effect three-phase motor that does not require an MCU. Background Technology

[0002] BLDC (Brushless Direct Current Motor) drive systems boast extremely high energy conversion efficiency and exceptionally high speed capabilities. The drivers can achieve millisecond-level response times, precisely controlling the motor's speed and torque. Modern BLDC drive chips primarily employ microcontroller units (MCUs) to implement algorithms and require dedicated electronic controllers (drivers) to function, directly increasing system complexity and initial investment costs.

[0003] Conventional BLDC driver solutions primarily employ a combination of an MCU and a gate driver chip. The MCU approach involves complex algorithms and presents significant technical challenges. Therefore, it offers limited advantages for applications such as industrial fans and water pumps. Summary of the Invention

[0004] The purpose of this invention is to provide an integrated circuit drive system for a Hall effect three-phase motor without an MCU, including a 3 / 8 decoder, an inverter, an XOR gate, and a gate driver;

[0005] The 3-to-8 decoder is used to convert Hall signals A, B, and C into binary signals, which are denoted as A0, A1, A2, A3, A4, A5, A6, and A7.

[0006] Inverter B1 flips the binary signal A1 and outputs it to XOR gate C1 and XOR gate C6;

[0007] Inverter B2 flips the binary signal A2 and outputs it to XOR gate C2 and XOR gate C3;

[0008] Inverter B3 flips the binary signal A3 and outputs it to XOR gate C3;

[0009] Inverter B4 flips the binary signal A4 and outputs it to XOR gate C4 and XOR gate C5;

[0010] Inverter B5 flips the binary signal A5 and outputs it to XOR gate C1;

[0011] Inverter B6 flips the binary signal A6 and outputs it to C5;

[0012] XOR gate C1 performs an XOR operation on the outputs of inverters B1 and B5;

[0013] XOR gate C2 performs an XOR operation on the output of inverter B1 and the binary signal A6 output by the 3-8 decoder;

[0014] XOR gate C3 performs an XOR operation on the outputs of inverters B2 and B3;

[0015] XOR gate C4 performs an XOR operation on the output of inverter B4 and the binary signal A5 output by the 3-8 decoder;

[0016] XOR gate C5 performs an XOR operation on the outputs of inverters B4 and B6;

[0017] XOR gate C6 performs an XOR operation on the output of inverter B1 and the binary signal A3 output by the 3-8 decoder;

[0018] The outputs of XOR gates C1 and C2 serve as the inputs of gate driver D1;

[0019] The outputs of XOR gates C3 and C4 serve as the inputs of gate driver D2;

[0020] The outputs of XOR gates C5 and C6 serve as the inputs of gate driver D3;

[0021] The gate drivers D1, D2, and D3 are used to drive the upper and lower power MOSFETs of the three-phase bridge, thereby controlling the on / off state of the three-phase windings of the motor and the energizing sequence.

[0022] Furthermore, the 3-8 decoder has three signal input terminals A, B, and C, which respectively receive Hall signals of different phases.

[0023] Furthermore, the 3-to-8 decoder includes inverters E1, E2, and E3, and three-input NAND gates F0, F1, F2, F3, F4, F5, F6, and F7.

[0024] Furthermore, inverter E1 receives and flips Hall signal A, and outputs the flipped Hall signal A to three-input NAND gates F0, F1, F2, and F3;

[0025] Inverter E2 receives and flips Hall signal B, and outputs the flipped Hall signal B to three-input NAND gates F0, F1, F4, and F5;

[0026] Inverter E3 receives and flips Hall signal C, and outputs the flipped Hall signal C to three-input NAND gates F0, F1, F3, and F5;

[0027] The three-input NAND gate F0 performs NAND operations on the outputs of inverters E1, E2, and E3, and the output is a binary signal A0.

[0028] The three-input NAND gate F1 performs NAND operations on the outputs of inverters E1 and E2 and the Hall signal C, and the output is a binary signal A1.

[0029] The three-input NAND gate F2 performs NAND operations on the outputs of inverters E1 and E3 and the Hall signal B, and the output is a binary signal A2.

[0030] The three-input NAND gate F3 performs NAND operations on the output of inverter E1 and Hall signals B and C, and the output is binary signal A3.

[0031] The three-input NAND gate F4 performs NAND operations on the outputs of inverters E2 and E3 and the Hall signal A, and the output is a binary signal A4.

[0032] The three-input NAND gate F5 performs NAND operations on the output of inverter E2 and Hall signals A and C, and the output is binary signal A5.

[0033] The three-input NAND gate F6 performs NAND operations on the output of inverter E3 and Hall signals A and B, and the output is binary signal A6.

[0034] The three-input NAND gate F7 performs NAND operations on Hall signals A, B, and C, and outputs a binary signal A7.

[0035] Furthermore, when the Hall signal received by the 3-to-8 decoder is [0,0,0], the output of the 3-to-8 decoder is [0,1,1,1,1,1,1,1].

[0036] When the Hall signal received by the 3-8 decoder is [0,0,1], the output of the 3-8 decoder is [1,0,1,1,1,1,1,1].

[0037] When the Hall signal received by the 3-8 decoder is [0,1,0], the output of the 3-8 decoder is [1,1,0,1,1,1,1,1].

[0038] When the Hall signal received by the 3-8 decoder is [0,1,1], the output of the 3-8 decoder is [1,1,1,0,1,1,1,1].

[0039] When the Hall signal received by the 3-8 decoder is [1,0,0], the output of the 3-8 decoder is [1,1,1,1,0,1,1,1].

[0040] When the Hall signal received by the 3-8 decoder is [1,0,1], the output of the 3-8 decoder is [1,1,1,1,1,0,1,1].

[0041] When the Hall signal received by the 3-8 decoder is [1,1,0], the output of the 3-8 decoder is [1,1,1,1,1,1,0,1].

[0042] When the Hall signal received by the 3-8 decoder is [1,1,1], the output of the 3-8 decoder is [1,1,1,1,1,1,1,0].

[0043] Furthermore, the XOR gate includes multiple two-input NAND gates G1, G2, G3, and G4.

[0044] Furthermore, the two-input NAND gate G1 performs an NAND operation on the input signal and then outputs it to G2 and G3;

[0045] The two-input NAND gate G2 performs a NAND operation on an input signal and the output of G1, and then outputs the signal to G4.

[0046] The two-input NAND gate G3 performs a NAND operation on the other input signal and the output of G1, and then outputs the result to G4.

[0047] The two-input NAND gate G4 performs a NAND operation on the outputs of G2 and G3 to obtain the output.

[0048] Furthermore, the gate driver adopts a push-pull structure for output, thereby driving the U, V, W three-phase bridge composed of power MOS.

[0049] Furthermore, the outputs of XOR gates C1, C3, and C5 determine the on / off state of the high-power MOSFETs in the three-phase bridge.

[0050] Furthermore, the outputs of XOR gates C2, C4, and C6 determine the on / off state of the lower power MOSFETs in the three-phase bridge.

[0051] This invention uses a 3 / 8 decoder, inverter, XOR gate, and gate driver to output a large current that can directly drive the power MOSFETs of a three-phase bridge without the need for an additional gate driver chip.

[0052] The driving scheme in this invention has a simple structure and small package size, which can provide a simpler application method for driving BLDC motors and reduce costs. Attached Figure Description

[0053] Figure 1 This is a block diagram of an integrated circuit driving scheme for a Hall effect three-phase motor without an MCU.

[0054] Figure 2 Here is a block diagram of a 3 / 8 decoder;

[0055] Figure 3 Here is a block diagram of an XOR gate;

[0056] Figure 4 Block diagram of the gate drive circuit;

[0057] Figure 5 The simulation results of the logic function of the 38 decoder are shown in the figure.

[0058] Figure 6 The diagram shows the simulation results of the inverter's logic function.

[0059] Figure 7 The simulation results of the XOR gate logic function are shown in the figure.

[0060] Figure 8 The simulation results of the two-input NAND gate logic function are shown in the figure.

[0061] Figure 9 The simulation results of the three-input NAND gate logic function are shown in the figure.

[0062] Figure 10 The diagram shows the functional simulation results of an integrated circuit drive scheme for a Hall effect three-phase motor without an MCU. Detailed Implementation

[0063] The present invention will be further described below with reference to embodiments, but it should not be construed that the scope of the present invention is limited to the following embodiments. Various substitutions and modifications made based on ordinary technical knowledge and common practices in the art without departing from the above-described technical concept of the present invention should be included within the scope of protection of the present invention.

[0064] Example 1:

[0065] See Figures 1-10 An integrated circuit drive system for a Hall effect three-phase motor without an MCU, comprising a 3 / 8 decoder, an inverter, an XOR gate, and a gate driver;

[0066] The 3-to-8 decoder is used to convert Hall signals A, B, and C into binary signals, which are denoted as A0, A1, A2, A3, A4, A5, A6, and A7.

[0067] Inverter B1 flips the binary signal A1 and outputs it to XOR gate C1 and XOR gate C6;

[0068] Inverter B2 flips the binary signal A2 and outputs it to XOR gate C2 and XOR gate C3;

[0069] Inverter B3 flips the binary signal A3 and outputs it to XOR gate C3;

[0070] Inverter B4 flips the binary signal A4 and outputs it to XOR gate C4 and XOR gate C5;

[0071] Inverter B5 flips the binary signal A5 and outputs it to XOR gate C1;

[0072] Inverter B6 flips the binary signal A6 and outputs it to C5;

[0073] XOR gate C1 performs an XOR operation on the outputs of inverters B1 and B5;

[0074] XOR gate C2 performs an XOR operation on the output of inverter B1 and the binary signal A6 output by the 3-8 decoder;

[0075] XOR gate C3 performs an XOR operation on the outputs of inverters B2 and B3;

[0076] XOR gate C4 performs an XOR operation on the output of inverter B4 and the binary signal A5 output by the 3-8 decoder;

[0077] XOR gate C5 performs an XOR operation on the outputs of inverters B4 and B6;

[0078] XOR gate C6 performs an XOR operation on the output of inverter B1 and the binary signal A3 output by the 3-8 decoder;

[0079] The outputs of XOR gates C1 and C2 serve as the inputs of gate driver D1;

[0080] The outputs of XOR gates C3 and C4 serve as the inputs of gate driver D2;

[0081] The outputs of XOR gates C5 and C6 serve as the inputs of gate driver D3;

[0082] The gate drivers D1, D2, and D3 are used to drive the upper and lower power MOSFETs of the three-phase bridge, thereby controlling the on / off state of the three-phase windings of the motor and the energizing sequence.

[0083] Example 2:

[0084] An integrated circuit drive system for a three-phase motor with Hall effect without an MCU is provided. The technical content is the same as in Embodiment 1. Furthermore, the 3-to-8 decoder has three signal input terminals A, B, and C, which respectively receive Hall signals of different phases.

[0085] Example 3:

[0086] An integrated circuit drive system for a Hall effect three-phase motor without an MCU is provided, with the same technical content as any one of embodiments 1-2. Further, the 3-8 decoder includes inverters E1, E2, E3 and three-input NAND gates F0, F1, F2, F3, F4, F5, F6, F7.

[0087] Example 4:

[0088] An integrated circuit drive system for a Hall effect three-phase motor without an MCU, with the same technical content as any one of embodiments 1-3, further wherein the inverter E1 receives and flips the Hall signal A, and outputs the flipped Hall signal A to the three-input NAND gates F0, F1, F2, and F3;

[0089] Inverter E2 receives and flips Hall signal B, and outputs the flipped Hall signal B to three-input NAND gates F0, F1, F4, and F5;

[0090] Inverter E3 receives and flips Hall signal C, and outputs the flipped Hall signal C to three-input NAND gates F0, F1, F3, and F5;

[0091] The three-input NAND gate F0 performs NAND operations on the outputs of inverters E1, E2, and E3, and the output is a binary signal A0.

[0092] The three-input NAND gate F1 performs NAND operations on the outputs of inverters E1 and E2 and the Hall signal C, and the output is a binary signal A1.

[0093] The three-input NAND gate F2 performs NAND operations on the outputs of inverters E1 and E3 and the Hall signal B, and the output is a binary signal A2.

[0094] The three-input NAND gate F3 performs NAND operations on the output of inverter E1 and Hall signals B and C, and the output is binary signal A3.

[0095] The three-input NAND gate F4 performs NAND operations on the outputs of inverters E2 and E3 and the Hall signal A, and the output is a binary signal A4.

[0096] The three-input NAND gate F5 performs NAND operations on the output of inverter E2 and Hall signals A and C, and the output is binary signal A5.

[0097] The three-input NAND gate F6 performs NAND operations on the output of inverter E3 and Hall signals A and B, and the output is binary signal A6.

[0098] The three-input NAND gate F7 performs NAND operations on Hall signals A, B, and C, and outputs a binary signal A7.

[0099] Example 5:

[0100] An integrated circuit drive system for a Hall effect three-phase motor without an MCU, the technical content of which is the same as any one of embodiments 1-4, further wherein when the Hall signal received by the 3-8 decoder is [0,0,0], the output of the 3-8 decoder is [0,1,1,1,1,1,1,1];

[0101] When the Hall signal received by the 3-8 decoder is [0,0,1], the output of the 3-8 decoder is [1,0,1,1,1,1,1,1].

[0102] When the Hall signal received by the 3-8 decoder is [0,1,0], the output of the 3-8 decoder is [1,1,0,1,1,1,1,1].

[0103] When the Hall signal received by the 3-8 decoder is [0,1,1], the output of the 3-8 decoder is [1,1,1,0,1,1,1,1].

[0104] When the Hall signal received by the 3-8 decoder is [1,0,0], the output of the 3-8 decoder is [1,1,1,1,0,1,1,1].

[0105] When the Hall signal received by the 3-8 decoder is [1,0,1], the output of the 3-8 decoder is [1,1,1,1,1,0,1,1].

[0106] When the Hall signal received by the 3-8 decoder is [1,1,0], the output of the 3-8 decoder is [1,1,1,1,1,1,0,1].

[0107] When the Hall signal received by the 3-8 decoder is [1,1,1], the output of the 3-8 decoder is [1,1,1,1,1,1,1,0].

[0108] Example 6:

[0109] An integrated circuit drive system for a three-phase motor with Hall effect without an MCU is provided. The technical content is the same as any one of embodiments 1-5. Further, the XOR gate includes multiple two-input NAND gates G1, G2, G3, and G4.

[0110] Example 7:

[0111] An integrated circuit drive system for a Hall effect three-phase motor without an MCU, with the same technical content as any one of embodiments 1-6, further wherein the two-input NAND gate G1 performs NAND operation on the input signal and outputs it to G2 and G3;

[0112] The two-input NAND gate G2 performs a NAND operation on an input signal and the output of G1, and then outputs the signal to G4.

[0113] The two-input NAND gate G3 performs a NAND operation on the other input signal and the output of G1, and then outputs the result to G4.

[0114] The two-input NAND gate G4 performs a NAND operation on the outputs of G2 and G3 to obtain the output.

[0115] Example 8:

[0116] An integrated circuit driving system for a three-phase motor with Hall effect without an MCU is provided. The technical content is the same as any one of embodiments 1-7. Furthermore, the gate driver adopts a push-pull structure output to drive the U, V, W three-phase bridge composed of power MOS.

[0117] Example 9:

[0118] An integrated circuit drive system for a three-phase motor with Hall effect without an MCU is provided. The technical content is the same as any one of embodiments 1-8. Furthermore, the outputs of XOR gates C1, C3, and C5 determine the on / off state of the high-power MOSFETs of the three-phase bridge.

[0119] Example 10:

[0120] An integrated circuit drive system for a three-phase motor with Hall effect without an MCU is provided. The technical content is the same as any one of embodiments 1-9. Furthermore, the outputs of XOR gates C2, C4, and C6 determine the on / off state of the lower power MOSFETs of the three-phase bridge.

[0121] Example 11:

[0122] A 3-to-8 decoder, six inverters, six XOR gates, and three gate drivers constitute an integrated circuit drive scheme for a Hall effect three-phase motor without an MCU.

[0123] Working mechanism of the invention: Figure 2 As shown, the 3-to-8 decoder A1 has three input signal terminals A, B, and C, which receive Hall signals. The 3-to-8 decoder mainly consists of three inverters E1, E2, and E3, and six three-input NAND gates F0, F1, F2, F3, F4, F5, F6, and F7. The 3-to-8 decoder converts three-bit binary inputs into corresponding outputs. The truth table is as follows:

[0124] A B C Output 0 0 0 A0=0, all other outputs are 1. 0 0 1 A1=0, all other outputs are 1. 0 1 0 A2=0, all other outputs are 1. 0 1 1 A3=0, all other outputs are 1. 1 0 0 A4=0, all other outputs are 1. 1 0 1 A5=0, all other outputs are 1. 1 1 0 A6=0, all other outputs are 1. 1 1 1 A7=0, all other outputs are 1.

[0125] The simulation results are as follows Figure 5 As shown, the output is active low, which satisfies the truth table.

[0126] like Figure 6 The image shows the functional simulation results of the inverter, which achieves the flipping of the input logic signal. The expression is:

[0127]

[0128] The truth table is as follows:

[0129] IN1 OUT1 0 1 1 0

[0130] like Figure 3 The structure is composed of XOR gates, consisting of four two-input NAND gates. Figure 7 The following shows the functional simulation results of the XOR gate, expressed as:

[0131] OUT2=INA1⨁INA2

[0132] The truth table is as follows:

[0133] INA1 INA2 OUT2 0 0 1 0 1 1 1 0 1 1 1 0

[0134] like Figure 8 The following shows the simulation results of a two-input NAND gate function, expressed as:

[0135] ,

[0136] The truth table is as follows:

[0137] INA3 INA4 OUT3 0 0 1 0 1 1 1 0 1 1 1 0

[0138] like Figure 9 The following shows the simulation results of a three-input NAND gate function. The expression is:

[0139]

[0140] The truth table is as follows:

[0141] INA5 INA6 INA7 OUT4 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 0

[0142] like Figure 4 The diagram shows the gate driver circuit structure, which implements the toggling of the input logic signal. The expression is:

[0143]

[0144] The truth table is as follows:

[0145] INA OUTA 0 1 1 0

[0146] Gate drivers can be broadly divided into two stages: the input stage and the output stage. The input stage uses high-voltage NMOS transistors as trigger switches to provide sufficient response speed, and an inverter is used to achieve hysteresis. The output stage uses registerable latched signals to avoid signal phase errors, and the internal design avoids dead time. The output adopts a complementary push-pull output structure with upper PMOS and lower NMOS transistors. The transistor design area is large enough to provide a drive current of more than 1A to drive the power MOS transistors of the three-phase bridge.

[0147] like Figure 10 The following shows the simulation results of an integrated circuit drive scheme for a three-phase motor with Hall effect without an MCU. UP represents the upper logic of phase U, UN represents the lower logic of phase U, VP represents the upper logic of phase V, VN represents the lower logic of phase V, WP represents the upper logic of phase W, and WN represents the lower logic of phase W. The truth table is as follows:

[0148] A B C UP UN VP VN WP WN 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 0 0 1 1 0 1 0 1 1 0 0 1 0 0 1 1 0 0 1 0 0 1 0

[0149] Three Hall sensors are typically installed at 120° electrical angles apart. When the rotor poles (N or S) sweep across the sensors, the Hall values ​​Ha, Hb, and Hc output a high level (1) or a low level (0). These three signals combine to form a representation of the rotor's current position. The core principle of the six-step commutation of a brushless DC motor (BLDC) with Hall sensors is to use three Hall sensors (A, B, C) to detect the position of the rotor poles in real time, and determine the energizing sequence of the motor's three-phase windings (U, V, W) based on the six different combinations of their output states, thereby generating a continuously rotating magnetic field to drive the rotor and rotate the motor. The main steps of the six-step commutation are as follows:

[0150] Hall effect values ​​(Ha, Hb, Hc) Corresponding electrical angle range Commutation steps Conducting phase (current path) 101 0°-60° Step 1 UP, VN 100 60°-120° Step 2 UP, WN 110 120°-180° Step 3 VP, WN 010 180°-240° Step 4 VP, UN 011 240°-300° Step 5 WP, UN 001 300°-360° Step 6 WP, VN

[0151] In this invention, when using a 3x8 decoder to convert the Hall output of a BLDC motor, Ha is connected to the C input terminal of the 3x8 decoder, Hb is connected to the B input terminal, and Hc is connected to the A input terminal to achieve six-step commutation. Considering the abnormal states of the Hall output (all logic 0s if damaged, all logic 1s if short-circuited), the subsequent logic of the 3x8 decoder does not use all logic 0s or all logic 1s output states, indirectly providing effective protection for the BLDC motor.

[0152] This invention does not integrate the three-phase bridge section, mainly considering the flexibility of use. The gate driver can be matched with power MOSFETs that adapt to different voltages or currents. At the same time, the power supply is separated, and the motor speed can be adjusted by the current. In addition, it adopts an independent three-terminal input, which can be flexibly used as a high-speed, high-current power MOSFET driver. It provides a microcontroller or MCU with an external square wave signal for flexible control, enabling more complex and precise designs, and enhancing scalability and reusability.

[0153] The above examples are merely implementation methods of the present invention. The present invention is not limited to the above implementation methods. Any modifications, equivalent substitutions, improvements, etc., made within the ideas, principles, and rules of the present invention shall be deemed to be within the protection scope of the present invention.

Claims

1. An integrated circuit drive system for a three-phase motor with Hall effect without an MCU, characterized in that: This includes a 3 / 8 decoder, an inverter, an XOR gate, and a gate driver; The 3-to-8 decoder is used to convert Hall signals A, B, and C into binary signals, which are denoted as A0, A1, A2, A3, A4, A5, A6, and A7. Inverter B1 flips the binary signal A1 and outputs it to XOR gate C1 and XOR gate C6; Inverter B2 flips the binary signal A2 and outputs it to XOR gate C2 and XOR gate C3; Inverter B3 flips the binary signal A3 and outputs it to XOR gate C3; Inverter B4 flips the binary signal A4 and outputs it to XOR gate C4 and XOR gate C5; Inverter B5 flips the binary signal A5 and outputs it to XOR gate C1; Inverter B6 flips the binary signal A6 and outputs it to C5; XOR gate C1 performs an XOR operation on the outputs of inverters B1 and B5; XOR gate C2 performs an XOR operation on the output of inverter B1 and the binary signal A6 output by the 3-8 decoder; XOR gate C3 performs an XOR operation on the outputs of inverters B2 and B3; XOR gate C4 performs an XOR operation on the output of inverter B4 and the binary signal A5 output by the 3-8 decoder; XOR gate C5 performs an XOR operation on the outputs of inverters B4 and B6; XOR gate C6 performs an XOR operation on the output of inverter B1 and the binary signal A3 output by the 3-8 decoder; The outputs of XOR gates C1 and C2 serve as the inputs of gate driver D1; The outputs of XOR gates C3 and C4 serve as the inputs of gate driver D2; The outputs of XOR gates C5 and C6 serve as the inputs of gate driver D3; The gate drivers D1, D2, and D3 are used to drive the upper and lower power MOSFETs of the three-phase bridge, thereby controlling the on / off state of the three-phase windings of the motor and the energizing sequence.

2. The integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 1, characterized in that: The 3-to-8 decoder has three signal input terminals A, B, and C, which receive Hall signals of different phases respectively.

3. The integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 1, characterized in that: The 3-to-8 decoder includes inverters E1, E2, and E3, and three-input NAND gates F0, F1, F2, F3, F4, F5, F6, and F7.

4. The integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 3, characterized in that: Inverter E1 receives and flips Hall signal A, and outputs the flipped Hall signal A to three-input NAND gates F0, F1, F2, and F3; Inverter E2 receives and flips Hall signal B, and outputs the flipped Hall signal B to three-input NAND gates F0, F1, F4, and F5; Inverter E3 receives and flips Hall signal C, and outputs the flipped Hall signal C to three-input NAND gates F0, F1, F3, and F5; The three-input NAND gate F0 performs NAND operations on the outputs of inverters E1, E2, and E3, and the output is a binary signal A0. The three-input NAND gate F1 performs NAND operations on the outputs of inverters E1 and E2 and the Hall signal C, and the output is a binary signal A1. The three-input NAND gate F2 performs NAND operations on the outputs of inverters E1 and E3 and the Hall signal B, and the output is a binary signal A2. The three-input NAND gate F3 performs NAND operations on the output of inverter E1 and Hall signals B and C, and the output is binary signal A3. The three-input NAND gate F4 performs NAND operations on the outputs of inverters E2 and E3 and the Hall signal A, and the output is a binary signal A4. The three-input NAND gate F5 performs NAND operations on the output of inverter E2 and Hall signals A and C, and the output is binary signal A5. The three-input NAND gate F6 performs NAND operations on the output of inverter E3 and Hall signals A and B, and the output is binary signal A6. The three-input NAND gate F7 performs NAND operations on Hall signals A, B, and C, and outputs a binary signal A7.

5. An integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 3, characterized in that: When the Hall signal received by the 3-8 decoder is [0,0,0], the output of the 3-8 decoder is [0,1,1,1,1,1,1,1]. When the Hall signal received by the 3-8 decoder is [0,0,1], the output of the 3-8 decoder is [1,0,1,1,1,1,1,1]. When the Hall signal received by the 3-8 decoder is [0,1,0], the output of the 3-8 decoder is [1,1,0,1,1,1,1,1]. When the Hall signal received by the 3-8 decoder is [0,1,1], the output of the 3-8 decoder is [1,1,1,0,1,1,1,1]. When the Hall signal received by the 3-8 decoder is [1,0,0], the output of the 3-8 decoder is [1,1,1,1,0,1,1,1]. When the Hall signal received by the 3-8 decoder is [1,0,1], the output of the 3-8 decoder is [1,1,1,1,1,0,1,1]. When the Hall signal received by the 3-8 decoder is [1,1,0], the output of the 3-8 decoder is [1,1,1,1,1,1,0,1]. When the Hall signal received by the 3-8 decoder is [1,1,1], the output of the 3-8 decoder is [1,1,1,1,1,1,1,0].

6. The integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 1, characterized in that: The XOR gate includes multiple two-input NAND gates G1, G2, G3, and G4.

7. An integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 6, characterized in that: The two-input NAND gate G1 performs an NAND operation on the input signal and outputs it to G2 and G3. The two-input NAND gate G2 performs a NAND operation on an input signal and the output of G1, and then outputs the signal to G4. The two-input NAND gate G3 performs a NAND operation on the other input signal and the output of G1, and then outputs the result to G4. The two-input NAND gate G4 performs a NAND operation on the outputs of G2 and G3 to obtain the output.

8. The integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 1, characterized in that: The gate driver uses a push-pull structure to drive the U, V, W three-phase bridge composed of power MOS.

9. An integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 1, characterized in that: The outputs of XOR gates C1, C3, and C5 determine the on / off state of the high-power MOSFETs in the three-phase bridge.

10. An integrated circuit drive system for a Hall effect three-phase motor without an MCU according to claim 1, characterized in that: The outputs of XOR gates C2, C4, and C6 determine the on / off state of the lower power MOSFETs in the three-phase bridge.

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