Low phase noise signal generation circuitry

Abstract

The present disclosure relates to low phase noise signal generation circuitry. The present disclosure relates to signal generation circuitry comprising first square wave conversion circuitry comprising a first input and a first output, and second square wave conversion circuitry comprising a second input and a second output. The second output is coupled to the first input of the first square wave conversion circuitry, and the square wave conversion circuitry is configured to generate a first square wave based on a first oscillation signal received at the second input. The first square wave and a second oscillation signal are combined to produce a combined signal, and wherein the first square wave conversion circuitry is configured to generate a second square wave based on the combined signal.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to signal generation circuit systems, including signal generation circuit systems for generating square waves using square wave conversion circuit systems. Background Technology

[0002] Modern applications for wireless signal transmission / reception, such as mobile telecommunications, radio, or radar, typically require low phase noise in the generation of clock or local oscillator (LO) signals to achieve superior signal-to-noise ratio (SNR) specifications. Radio frequency (RF) oscillators are commonly used in phase-locked loops (PLLs) and are usually supplied with a low-frequency reference signal. This reference signal is typically provided in square wave form. Summary of the Invention

[0003] Various exemplary embodiments are presented below. Some simplifications and omissions may have been made in the following examples to highlight and illustrate some aspects of the various exemplary embodiments, rather than to limit the scope.

[0004] In an example embodiment, the signal generation circuit system includes: an oscillator circuit system configured to generate a first oscillation signal at a first node and a second oscillation signal at a second node; a first square wave conversion circuit system having a first input coupled to the second node and a first output coupled to the output of the signal generation circuit system; and a second square wave conversion circuit system having a second input coupled to the first node and a second output coupled to the second node, the second square wave conversion circuit system being configured to generate a first square wave based on the first oscillation signal. The first square wave and the second oscillation signal are combined at the second node to generate a combined signal. The first square wave conversion circuit system is configured to generate a second square wave based on the combined signal.

[0005] In one or more embodiments, the first square wave conversion circuit system includes a first resistive feedback inverter coupled to a second node via a first capacitor in AC.

[0006] In one or more embodiments, the second square wave conversion circuit system includes a second resistive feedback inverter coupled to the first node via a second capacitor AC.

[0007] In one or more embodiments, the second square wave conversion circuit system is coupled to the second node via a third capacitor AC.

[0008] In one or more embodiments, the oscillator circuit system includes a resonator coupled between a first node and a second node, a first capacitor coupled between the first node and a reference node, a second capacitor coupled between the second node and the reference node, a first transistor having a gate terminal connected to the first node and a drain terminal connected to the second node, and a resistor coupled between the first node and the second node.

[0009] In one or more embodiments, the oscillator circuitry is arranged as a Pierce oscillator.

[0010] In one or more embodiments, the oscillator circuit system further includes a bias circuit system connected to the second node, the bias circuit system comprising: a current mirror including a second transistor and a third transistor; a current source coupled to the second transistor; and a low-pass filter coupled between the second transistor and the third transistor. The third transistor is connected to the second node.

[0011] In one or more embodiments, the output of the signal generation circuit system is coupled to a phase-locked loop (PLL), and a second square wave is provided to the PLL as a reference clock signal for the PLL.

[0012] In an example embodiment, a method includes generating a first oscillation signal and a second oscillation signal through an oscillator circuit system, generating a first square wave based on the first oscillation signal through a second square wave conversion circuit system, and generating a second square wave based on the first square wave and the second oscillation signal through the first square wave conversion circuit system.

[0013] In one or more embodiments, the method further includes combining a first square wave and a second oscillation signal at the input of a first square wave conversion circuit system to generate a combined signal. Generating a second square wave includes generating a second square wave based on the combined signal via the first square wave conversion circuit system.

[0014] In one or more embodiments, the first square wave conversion circuit system includes a first resistive feedback inverter that is AC coupled to the oscillator circuit system.

[0015] In one or more embodiments, the second square wave conversion circuit system includes a second resistive feedback inverter, which is AC coupled to both the oscillator circuit system and the first square wave conversion circuit system.

[0016] In one or more embodiments, the first oscillation signal and the second oscillation signal are generated simultaneously.

[0017] In one or more embodiments, the oscillator circuit system includes a Pierce oscillator.

[0018] In an example embodiment, the signal generation circuit system includes a first square wave conversion circuit system and a second square wave conversion circuit system. The first square wave conversion circuit system includes a first input and a first output. The second square wave conversion circuit system includes a second input and a second output. The second output is coupled to the first input of the first square wave conversion circuit system, and the second square wave conversion circuit system is configured to generate a first square wave based on a first oscillation signal received at the second input. The first square wave and the second oscillation signal are combined to generate a combined signal. The first square wave conversion circuit system is configured to generate a second square wave based on the combined signal.

[0019] In one or more embodiments, the signal generation circuit system includes an oscillator circuit system configured to generate a first oscillation signal at a first node coupled to a second input of the second square wave generation circuit system, and simultaneously generate a second oscillation signal at a second node coupled to the first input of the first square wave generation circuit system.

[0020] In one or more embodiments, the first square wave conversion circuit system includes a first resistive feedback inverter coupled to a second node via a first capacitor (AC), and the second square wave conversion circuit system includes a second resistive feedback inverter coupled to the first node via a second capacitor (AC). The second square wave conversion circuit system is coupled to the second node via a third capacitor (AC).

[0021] In one or more embodiments, the oscillator circuit system includes a resonator coupled between a first node and a second node, a first capacitor coupled between the first node and a reference node, a second capacitor coupled between the second node and the reference node, a first transistor having a gate terminal connected to the first node and a drain terminal connected to the second node, and a resistor coupled between the first node and the second node.

[0022] In one or more embodiments, the oscillator circuit system further includes a bias circuit system connected to the second node, the bias circuit system comprising: a current mirror including a second transistor and a third transistor; a current source coupled to the second transistor; and a low-pass filter coupled between the second transistor and the third transistor. The third transistor is connected to the second node.

[0023] In one or more embodiments, the output of the signal generation circuit system is coupled to a phase-locked loop (PLL), and a second square wave is provided to the PLL as a reference clock signal for the PLL. Attached Figure Description

[0024] A more complete understanding of the subject matter can be derived by considering the following figures and referring to the specific embodiments and claims. The same appendages throughout the figures refer to similar elements. Elements in the figures are shown for simplicity and clarity, and are not necessarily drawn to scale. The figures, together with the specific embodiments, are incorporated in and form a part of this specification, and are used to further illustrate examples, embodiments, etc., and to explain various principles and advantages according to this disclosure. In the figures:

[0025] Figure 1 Illustrative circuit diagrams are shown according to various embodiments, including a signal generation circuit system configured to generate and provide a square wave;

[0026] Figure 2 An illustrative graph is shown representing a signal generated by a signal generation circuit system having only a single set of square wave conversion circuitry, the signal including the input and output signals of the square wave conversion circuitry system;

[0027] Figure 3 The representation shown according to various embodiments is provided by, for example, Figure 1 An illustrative graph of a signal generated by a signal generation circuit system, including an input signal provided at the input of a first square wave conversion circuit system, a first square wave output by a second square wave conversion circuit system, and a second square wave output by the first square wave conversion circuit system; and

[0028] Figure 4 The diagram illustrates, according to various embodiments, a first square wave signal generated by a signal generation circuit system having only a single set of square wave conversion circuitry and a signal generation circuit system having two sets of square wave conversion circuitry (such as...). Figure 1 An illustrative graph showing the relationship between the phase noise and relative frequency offset of the second square wave signal generated by the signal generation circuit system. Detailed Implementation

[0029] The following detailed descriptions are merely illustrative in nature and are not intended to limit the use of the embodiments described herein or such embodiments. Furthermore, they are not intended to be construed as being bound by any explicit or implicit theory presented in the foregoing technical fields, background information, or the appended detailed descriptions.

[0030] For the sake of simplicity and clarity, the drawings illustrate a general construction. Descriptions and details of well-known features and techniques may be omitted from the following detailed description to avoid unnecessarily obscuring this disclosure. For example, the dimensions of some elements or areas in the drawings may be exaggerated relative to other elements or areas to aid in understanding the embodiments described herein.

[0031] The terms “first,” “second,” “third,” “fourth,” etc. (if present) used in the detailed description and claims are used to distinguish similar elements and are not necessarily used to describe a particular sequence or time order. It should be understood that the terms thus used are interchangeable where appropriate, allowing the embodiments described herein (e.g.) to operate in sequences other than those described or otherwise. Furthermore, the terms “comprise,” “include,” “have,” and any variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to such a process, method, article, or apparatus. As used herein, the terms “generally,” “approximately,” “substantially,” and “largely” mean sufficient to practically achieve the stated purpose, and minor defects (if present) are not important to the stated purpose.

[0032] In accordance with these principles, when used to refer to measurable quantities (including, but not limited to, dimensions), these terms mean that the quantity is equal to the stated value, subject to acceptable tolerances of any method or apparatus chosen for manufacturing the described structure or measuring the described quantity or dimension. Unless otherwise stated, directional references, such as “top,” “bottom,” “left,” “right,” “above,” “below,” etc., are not intended to require any preferred orientation, but are for illustrative purposes and refer to the orientation of one or more corresponding figures. As used herein, the terms “exemplary” and “example” mean “serving as an example, case study, or illustration.” Any embodiment described herein as exemplary or illustrative is not necessarily to be construed as preferred or advantageous over other embodiments. Additionally, certain terms may also be used herein for illustrative purposes only and are therefore not intended to be restrictive.

[0033] In this document, elements, nodes, or features are sometimes referred to as “connected” or “coupled” together. As used herein, unless explicitly stated otherwise, “connected” means that one element is directly engaged to (or in direct communication with) another element in an electrical or non-electrical manner, and not necessarily mechanically engaged. Similarly, unless explicitly stated otherwise, “coupled” means that one element is directly or indirectly engaged to (or in direct or indirect communication with) another element in an electrical or non-electrical manner, and not necessarily mechanically engaged. Therefore, although the schematic diagrams shown in the figures depict exemplary arrangements of elements, additional intervening elements, devices, features, or components may be present in one or more embodiments of the depicted subject matter.

[0034] The various embodiments described herein relate to signal generation circuit systems for generating square waves with low phase noise, which can be used as reference signals (e.g., reference clock signals) in applications where low phase noise is desired or required. The signal generation circuit system may have an output, an oscillator circuit system, a first square wave conversion circuit system (sometimes referred to herein as the "first conversion circuit system"), and a second square wave conversion circuit system (sometimes referred to herein as the "second conversion circuit system"). The second conversion circuit system is coupled in parallel with the oscillator circuit system (e.g., coupled in parallel with its resonator), generates the first square wave based on the oscillation signal output from the oscillator circuit system, and provides the first square wave to the first conversion circuit system. The first conversion circuit system receives the oscillation signal from the oscillator circuit system and the first square wave from the second conversion circuit system, generates the second square wave, and provides the second square wave at the output of the signal generation circuit system. The first square wave output by the second conversion circuit system cancels the kickback effect of the first conversion circuit system on the resonator of the oscillator circuit system, while also reducing phase noise.

[0035] Conventional signal generation circuitry systems that generate square wave reference signals typically consist of only a single square wave converter circuit directly connected between the oscillator and the output of the signal generation circuitry system. In such a conventional arrangement, the limiting factor for phase noise performance is often the square wave converter circuitry. In modern radio frequency (RF) applications such as wireless communication and radar, low phase noise is generally desired.

[0036] The embodiments described herein address these challenges by implementing a combination of a first square wave conversion circuit system that provides a square wave at the output of a signal generation circuit system and an additional (“second”) square wave conversion circuit system coupled in parallel with a resonator of an oscillator circuit system (e.g., a “piezoelectric resonator,” a “crystal oscillator,” or a “quartz crystal,” as non-limiting examples). The second conversion circuit system generates a square wave based on a first oscillation signal provided by the oscillator circuit system and combines the square wave with a second oscillation signal provided by the oscillator circuit system at the input of the first conversion circuit system. In this way, the second conversion circuit system increases the slope (i.e., increases the steepness of the slope) of the oscillation signal provided by the oscillator circuit system without overloading the resonator (i.e., increasing the load capacitance of the resonator). The phase noise of the output signal (i.e., the square wave) provided by the first conversion circuit system is inversely proportional to the steepness of the input signal provided to the input of the first conversion circuit system. Therefore, by using the second conversion circuit system to increase the steepness of the oscillation signal, the phase noise in the square wave signal output by the signal generation circuit system is advantageously reduced.

[0037] In one or more embodiments, the signal generation circuit system includes an oscillator circuit system, a first square wave conversion circuit system (“first conversion circuit system”), a second square wave conversion circuit system (“second conversion circuit system”), and an output node. The first conversion circuit system may be coupled between the first node of the oscillator circuit system and the output node of the signal generation circuit system. The second conversion circuit system may be coupled between the first node of the oscillator circuit system and the second node of the oscillator circuit system.

[0038] In one or more embodiments, the oscillator circuit system may include a Pierce oscillator circuit system. In one or more embodiments, the oscillator circuit system may include a resonator such as a crystal oscillator, a first capacitor and a second capacitor, a transistor, a resistor, and a bias circuit system. The resonator may have a first terminal connected to a first node and a second terminal connected to a second node. The first capacitor may be connected between the first node and a reference node. The second capacitor may be connected between the second node and the reference node. The resistor may be connected between the first node and the second node. The transistor may have a gate terminal connected to the first node, a source terminal connected to the reference node, and a drain terminal connected to the second node. The bias circuit system may be connected to the second node. The bias circuit system may include a current mirror comprising a pair of transistors, wherein the gate terminals of the pair of transistors are connected via a low-pass filter.

[0039] In one or more embodiments, the first conversion circuit system and the second conversion circuit system may each include an input node, an intermediate node, an output node, a capacitor connected between the intermediate node and the input node, a resistor connected between the intermediate node and the output node, a first transistor having a source terminal coupled to a voltage source, a gate terminal connected to the intermediate node, and a drain terminal connected to the output node, and a second transistor having a source terminal connected to a reference node, a gate terminal connected to the intermediate node, and a drain terminal connected to the output node. The first transistor and the second transistor may be arranged as inverters. In one or more embodiments, the size of the transistor in the inverter of the first conversion circuit system may differ from the size of the transistor in the inverter of the second conversion circuit system.

[0040] In one or more embodiments, a first conversion circuit system can convert an input oscillating signal into a square wave (e.g., generate a square wave based on the oscillating signal). A second conversion circuit system can convert the input oscillating signal into a square wave. The input oscillating signal provided at the input of the second conversion circuit system can be a first oscillating signal generated by the oscillator circuit system. The input oscillating signal provided at the input of the first conversion circuit system can be the sum of a second oscillating signal generated by the oscillator circuit system and a square wave provided by the second conversion circuit system. In this way, combining the square wave generated by the second conversion circuit system with the second oscillating signal generated by the oscillator circuit system at the input of the first conversion circuit system cancels out the recoil effect of the first conversion circuit system on the resonator of the oscillator circuit system, while also reducing phase noise.

[0041] Figure 1 An illustrative circuit diagram is shown representing a signal generation circuit system 100, which can be configured to generate signals with low phase noise (e.g., as a non-limiting example, less than -150 dBc / Hz for an oscillation frequency of 40 MHz). Figure 4 (An additional example is shown in the diagram) a square wave (e.g., a square wave reference signal or a clock signal). As shown, the signal generation circuit system 100 includes an oscillator circuit system 102, a first square wave conversion circuit system 104 (sometimes referred to herein as "first conversion circuit system 104"), a second square wave conversion circuit system 106 (sometimes referred to herein as "second conversion circuit system 106"), a buffer circuit system 110, and an output node 108.

[0042] Oscillator circuit system 102 may include resonator 112, capacitors 114 and 116, transistor 120, resistor 122, nodes 124 and 126, and bias circuit system 128. Resonator 112 may be a piezoelectric resonator, such as a crystal oscillator. Resonator 112 may have a first end coupled to node 124 and a second end coupled to node 126. Capacitor 114 may be connected between node 124 and reference node 118. In this document, according to various embodiments, a "reference node" refers to a node where a reference voltage, ground voltage, or common voltage is supplied. Capacitor 116 may be connected between node 126 and reference node 118. Transistor 120 may have a gate terminal connected to node 124, a source terminal coupled to reference node 118, and a drain terminal connected to node 126. Resistor 122 may be connected between the gate and drain terminals of transistor 120 (e.g., between nodes 124 and 126) such that transistor 120 can be biased via resistor 122.

[0043] Bias circuitry 128 can be configured to provide DC bias to transistor 120. Bias circuitry 128 may include a variable current source 130 and a current mirror, as well as a low-pass filter 138. The current mirror includes transistors 134 and 136. Transistor 134 is a diode-connected transistor with its gate connected to its drain. Transistor 134 includes a source terminal coupled to voltage source 132. The drain terminal of transistor 134 is connected to the variable current source 130. Transistor 136 includes a source terminal coupled to voltage source 132 and a drain terminal coupled to node 126. Low-pass filter 138 may be coupled between the gate terminals of transistors 134 and 136. In one or more embodiments, low-pass filter 138 may have a cutoff frequency of approximately 1 kHz. Inserting a low-pass filter 138 between the gates of transistors 134 and 136 in this manner can block or mitigate noise from the variable current source 130 (e.g., high, medium, and relatively low frequency noise), which could otherwise adversely affect the quality of the oscillation waveform provided by the oscillator circuitry 102 at nodes 124 and 126.

[0044] Due to the current mirror arrangement of transistors 134 and 136, the current at the drain terminal of transistor 136 can be proportional to the current at the drain terminal of transistor 134. In this way, the current supplied by transistor 136 to the rest of the oscillator circuit system 102 via node 126 can be controlled, for example, by a variable current source 130.

[0045] In one or more embodiments, transistors 134 and 136 may be p-type metal-oxide-semiconductor field-effect transistors (MOSFETs). In one or more embodiments, transistor 120 may be an n-type MOSFET. It should be understood that the depiction of transistors 120, 134, and 136 as MOSFETs in this example is intended for illustrative purposes and not for limitation, such that in one or more other embodiments, other transistor types (e.g., bipolar junction transistors (BJTs)) may be used to implement one or more of transistors 120, 134, and 136.

[0046] The arrangement of resonator 112, capacitors 114 and 116, transistor 120, and resistor 122 can correspond to the arrangement of a Pierce oscillator. Resonator 112 can be driven to oscillate when current (e.g., DC current) is supplied from bias circuitry 128 via node 126. Resonator 112, along with capacitors 114 and 116, can form a π-type network bandpass filter (e.g., where resonator 112 acts as an inductor), which provides a phase shift between nodes 124 and 126. In this way, oscillator circuitry 102 can generate a first oscillation signal at node 124 and a second oscillation signal at node 126, wherein the first and second oscillation signals are out of phase by 180 degrees or approximately 180 degrees. Oscillator circuitry 102 can generate the first oscillation signal at node 124 while simultaneously generating the second oscillation signal at node 126. That is, the first and second oscillation signals can be generated simultaneously.

[0047] The first conversion circuit system 104 can be implemented as a first AC-coupled resistive feedback inverter. For example, the first conversion circuit system 104 may include a capacitor 140, an inverter 142, and a resistor 144. Capacitor 140 provides AC coupling between the input of inverter 142 and node 126 (i.e., between the input of inverter 142 and oscillator circuit system 102). The input of inverter 142 may be connected to node 141. This AC coupling prevents an increase in the drive level of resonator 112, an increase that could otherwise be caused by the first conversion circuit system 104 and the second conversion circuit system 106. Resistor 144 is coupled between the output of inverter 142 and the input of inverter 142. Resistor 144 can provide resistive feedback between the output of inverter 142 and the input of inverter 142.

[0048] The second conversion circuit system 106 can be implemented as a second AC-coupled resistive feedback inverter. For example, the second conversion circuit system 106 may include a capacitor 146, an inverter 148, and a resistor 150. Capacitor 146 provides AC coupling between the input of inverter 148 and node 124, such that the output of the second conversion circuit system is AC-coupled to the input of inverter 148 and AC-coupled to the oscillator circuit system 102. This AC coupling prevents an increase in the drive level of resonator 112, which could otherwise be caused by the second conversion circuit system 106. Resistor 150 is coupled between the output of inverter 148 and the input of inverter 148. Resistor 150 can provide resistive feedback between the output of inverter 148 and the input of inverter 148. An additional capacitor 174 can be coupled between the output of inverter 148 of the second conversion circuit system 106 and node 141 (i.e., the input of inverter 142). The additional capacitor 174 can provide AC coupling between the output of the second conversion circuit system 106 and the input of the first conversion circuit system 104 and the oscillator circuit system 102, which can mitigate or avoid the unwanted load effect of the second conversion circuit system 106 on the resonator 112.

[0049] Circuit system 152 represents an exemplary embodiment of a first conversion circuit system 104, a second conversion circuit system 106, or both. For example, circuit system 152 includes an input terminal 156, an output terminal 158, a capacitor 160, an intermediate node 162, a resistor 164, a transistor 166, and a transistor 168. Capacitor 160 is connected between input terminal 156 and intermediate node 162. Intermediate node 162 may correspond to the input of an inverter implemented by transistors 166 and 168. Resistor is connected between intermediate node 162 and output terminal 168. Transistor 166 includes a source terminal coupled to voltage source 154, a gate terminal connected to intermediate node 162, and a drain terminal connected to output terminal 158. Capacitor 170 represents the gate-drain capacitance of transistor 166. Transistor 168 includes a source terminal coupled to reference node 118, a gate terminal connected to intermediate node 162, and a drain terminal connected to output terminal 158. Capacitor 172 represents the gate-drain capacitance of transistor 168. In one or more embodiments, transistor 166 is a p-type MOSFET. In one or more embodiments, transistor 168 is an n-type MOSFET. It should be understood that the description of transistors 166 and 168 as MOSFETs in this example is intended for illustrative purposes and not for limitation, such that in one or more other embodiments, one or both of transistors 166 and 168 may be implemented using other transistor types (e.g., bipolar junction transistors (BJTs)).

[0050] In one or more embodiments of implementing the first conversion circuit system 104 using circuit system 152, node 141 may correspond to node 162, resistor 144 may be implemented as resistor 164, capacitor 140 may be implemented as capacitor 160, and the corresponding pull-up transistor and pull-down transistor of inverter 142 may be implemented as transistors 166 and 168. In one or more embodiments of implementing the second conversion circuit system 106 using circuit system 152, resistor 150 may be implemented as resistor 164, capacitor 146 may be implemented as capacitor 160, and the corresponding pull-up transistor and pull-down transistor of inverter 148 may be implemented as transistors 166 and 168.

[0051] In one or more embodiments, both the first conversion circuit system 104 and the second conversion circuit system 106 are implemented using the same circuit system arrangement (e.g., the circuit system arrangement of circuit system 152), wherein the transistors for implementing the inverter 142 of the first conversion circuit system 104 may have different sizes (e.g., as a non-limiting example, different total widths and the same or similar gate lengths) compared to the transistors for implementing the inverter 148 of the second conversion circuit system 106.

[0052] The second conversion circuit system 106 can receive a first oscillation signal provided by the oscillator circuit system 102 via node 124. The second conversion circuit system 106 can convert the first oscillation signal into a first square wave. The first square wave can be 180 degrees out of phase with the first oscillation signal (e.g., due to inverter 148). The second conversion circuit system 106 can provide the first square wave to node 141 via capacitor 174. The first square wave can be combined with a second oscillation signal at node 126 to form a combined signal, and the combined signal can be provided to the input of the first conversion circuit system 104. The first conversion circuit system 104 can receive the combined signal via node 126 and can convert the combined signal into a second square wave (e.g., thereby generating a second square wave). The second square wave can be 180 degrees out of phase with the combined signal (e.g., due to inverter 142). The first conversion circuit system 104 can provide the second square wave to the output node 108 of the signal generation circuit system 100 via buffer circuit system 110.

[0053] In this way, the combination of the first square wave generated by the second conversion circuit system 106 (e.g., generated) at the input of the first conversion circuit system 104 with the second oscillation signal generated by the oscillator circuit system reduces the recoil effect of the first conversion circuit system 104 on the input signal provided to the first conversion circuit system (e.g., which would otherwise cause flattening at the crossover point, as further described below), thereby reducing phase noise.

[0054] In one or more embodiments, output node 108 may be coupled to a phase-locked loop (PLL), such as an all-digital PLL (ADPLL). In one or more such embodiments, a second square wave provided by the first conversion circuit system 104 via output node 108 may serve as a reference signal for the PLL, such as a clock signal.

[0055] Figure 2 A graph 200 shows the input signal 202 and output signal 204 of a square wave conversion circuit system included in a reference signal generation circuit system, which comprises only a single square wave conversion circuit system between the oscillator circuit system and the output of the reference signal generation circuit system. As shown, the input signal 202 is generally sinusoidal, except for flattening that occurs at crossover points (e.g., the time points at or near the crossover of input signal 202 and output signal 204), where the pull-up and pull-down transistors of the inverter in the square wave conversion circuit system operate in their respective saturation regions to provide maximum voltage gain. A magnified view 206 further illustrates the flattening of the input signal 202. This flattening of the input signal 202 is likely caused by the recoil effect of the high input capacitance of the square wave conversion circuit system. Because the phase noise at the output of the inverter is inversely proportional to the steepness of its input signal, the flattening of the input signal 202 unduly limits the overall signal quality of the output signal 204. The input capacitance of the square wave conversion circuit system can be defined in the context of the Miller effect, as shown in Equation 1:

[0056] C in = (C gd,p + C gd,n ) × (1+|A v |)(Equation 1)

[0057] In equation 1, C in C represents the equivalent input capacitance of the square wave conversion circuit system. gd,p C represents the gate-drain capacitance of the pull-up transistor in an inverter. gd,n This represents the gate-drain capacitance of the pull-down transistor in the inverter, and A v This represents the gain of the square wave conversion circuit system. Gain A v It is often relatively large, especially for applications involving the generation of reference clock signals, which typically require square waves with steep edges.

[0058] Although minimizing the lengths of the pull-up and pull-down transistors of the inverter in a square wave converter circuit system would reduce C gd,p and C gd,nHowever, such solutions are typically only suitable for applications insensitive to phase noise. This is because flicker noise from the pull-up and pull-down transistors of the inverter contributes to the overall phase noise, and minimizing the size of these transistors would result in excessive flicker noise contribution. Alternatively, embodiments of this paper provide a second square wave conversion circuit system coupled between the oscillator circuit system and the first square wave conversion circuit system (e.g., ...). Figure 1 The square wave conversion circuit system 106 is used to alleviate the flattening of the input signal shown in this example, wherein the square wave signal output by the second square wave conversion circuit system is combined with the signal output by the oscillator circuit system to increase the steepness of the rising and falling edges of the input signal provided at the input of the first square wave conversion circuit system.

[0059] Figure 3 The diagram shows the representation by Figure 1 A graph 300 of the signal generated by an example embodiment of the signal generation circuit system 100 is shown, and reference is made herein. Figure 1 The components of the signal generation circuit system 100 are described. The graph 300 includes an input signal 302 provided at the input of the first conversion circuit system 104, a first square wave 304 output by the second conversion circuit system 106, and an output signal 306 (sometimes referred to as "second square wave 306") output by the first conversion circuit system 104.

[0060] The input signal 302 can be provided to the input of the first conversion circuit system 104 via node 126. The input signal 302 can be a combination of an oscillating signal (e.g., a sine wave) output from the oscillator circuit system 102 and a first square wave 304 output from the second conversion circuit system 106. Figure 2 Compared to the input signal 202, at least in part due to the first square wave 304, the input signal 302 has a steeper slope at its rising and falling edges. Enlarged view 308 shows the flattening caused by the recoil effect relative to... Figure 2 The flattening of the input signal 202 is reduced. Furthermore, the reduced flattening of the input signal 302 does not occur at the intersection points where the input signal 302 intersects with the output signal 306. In fact, the reduced flattening of the input signal 302 is offset from these intersection points (relative to time). In this way, by providing a first square wave 304 to be combined with the oscillating signal output by the oscillator circuit system 102 to generate the input signal 302, phase noise in the output signal 306 is advantageously reduced.

[0061] Figure 4Figure 400 illustrates the relationship between phase noise and a relative frequency (e.g., relative to the oscillation frequency), sometimes referred to as the "offset frequency." A first curve 402 represents the phase noise performance of the output signal (e.g., the output square wave) of a first signal generation circuit system having only a single set of square wave conversion circuitry, and a second curve 404 represents the phase noise performance of a first signal generation circuit system having two sets of square wave conversion circuitry arranged according to the embodiments described herein (e.g., ...). Figure 1 The second signal generation circuit system (e.g., the first conversion circuit system 104 and the second conversion circuit system 106) Figure 1 The phase noise performance of the output signal (e.g., output square wave) of the signal generation circuit system 100 is compared. The phase noise comparison shown in Figure 400 is simulated using a 40 MHz crystal oscillator as the resonant element in each of the first and second signal generation circuit systems, and takes into account noise and bias current from the low dropout (LDO) regulator.

[0062] As shown, from approximately 6 kHz to approximately 4 MHz, the phase noise performance of the first signal generation circuit system, represented by curve 402, is worse than that of the second signal generation circuit system, represented by curve 404, in terms of relative frequency. For example, at 100 kHz, the phase noise of the output signal of the second signal generation circuit system is about 5 dB smaller than that of the first signal generation circuit system. For example, at 1 MHz, the phase noise of the output signal of the second signal generation circuit system is about 2 dB smaller than that of the first signal generation circuit system.

[0063] As used herein, the terms “circuit” and “circuit system,” including the term “processing circuit system” and related terms, refer to any suitable combination of analog or digital circuit elements, hardware, firmware, software, etc.; including but not limited to application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), microcontrollers, and microprocessors. It should be understood that the term “circuit system” encompasses both non-volatile and volatile memory devices, including but not limited to random access memory (RAM), read-only memory (ROM), etc., which can be implemented using any suitable means, such as SRAM, DRAM, or magnetic storage devices as examples of non-limiting examples.

[0064] While at least one exemplary embodiment has been presented in the foregoing detailed descriptions, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed descriptions will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. A signal generation circuit system, characterized in that, include: The oscillator circuit system is configured as follows: A first oscillation signal is generated at the first node; as well as A second oscillation signal is generated at the second node; A first square wave conversion circuit system has a first input coupled to the second node and a first output coupled to the output of the signal generation circuit system; as well as A second square wave conversion circuit system, having a second input coupled to the first node and a second output coupled to the second node, is configured to generate a first square wave based on the first oscillation signal. The first square wave and the second oscillation signal are combined at the second node to generate a combined signal, and the first square wave conversion circuit system is configured to generate a second square wave based on the combined signal.

2. The signal generation circuit system according to claim 1, characterized in that, The first square wave conversion circuit system includes a first resistor feedback inverter, which is AC coupled to the second node via a first capacitor.

3. The signal generation circuit system according to claim 1, characterized in that, The oscillator circuit system includes: A resonator coupled between the first node and the second node; A first capacitor is coupled between the first node and the reference node; A second capacitor is coupled between the second node and the reference node; A first transistor having a gate terminal connected to the first node and a drain terminal connected to the second node; and A resistor is coupled between the first node and the second node.

4. The signal generation circuit system according to claim 3, characterized in that, The oscillator circuit system further includes a bias circuit system connected to the second node, the bias circuit system comprising: A current mirror, comprising a second transistor and a third transistor; A current source, coupled to the second transistor; and A low-pass filter is coupled between the second transistor and the third transistor, wherein the third transistor is connected to the second node.

5. A method, characterized in that, include: The first oscillation signal and the second oscillation signal are generated by the oscillator circuit system; The first square wave is generated based on the first oscillation signal by the second square wave conversion circuit system; as well as The first square wave conversion circuit system generates a second square wave based on the first square wave and the second oscillation signal.

6. The method according to claim 5, characterized in that, Also includes: At the input of the first square wave conversion circuit system, the first square wave and the second oscillation signal are combined to generate a combined signal, wherein generating the second square wave includes: The second square wave is generated by the first square wave conversion circuit system based on the combined signal.

7. A signal generation circuit system, characterized in that, include: A first square wave conversion circuit system includes a first input and a first output; as well as A second square wave conversion circuit system includes a second input and a second output, the second output being coupled to the first input of the first square wave conversion circuit system, and the second square wave conversion circuit system being configured to generate a first square wave based on a first oscillation signal received at the second input. The first square wave and the second oscillation signal are combined to generate a combined signal, and the first square wave conversion circuit system is configured to generate the second square wave based on the combined signal.

8. The signal generation circuit system according to claim 7, characterized in that, Also includes: An oscillator circuit system is configured to generate the first oscillation signal at a first node coupled to the second input of the second square wave generation circuit system, and simultaneously generate the second oscillation signal at a second node coupled to the first input of the first square wave generation circuit system.

9. The signal generation circuit system according to claim 8, characterized in that, The oscillator circuit system includes: A resonator coupled between the first node and the second node; A first capacitor is coupled between the first node and the reference node; A second capacitor is coupled between the second node and the reference node; A first transistor having a gate terminal connected to the first node and a drain terminal connected to the second node; and A resistor is coupled between the first node and the second node.

10. The signal generation circuit system according to claim 9, characterized in that, The oscillator circuit system further includes a bias circuit system connected to the second node, the bias circuit system comprising: A current mirror, comprising a second transistor and a third transistor; A current source, coupled to the second transistor; and A low-pass filter is coupled between the second transistor and the third transistor, wherein the third transistor is connected to the second node.

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