Electronic device
Patent Information
- Application Number
- CN202510562724.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-21
- Filing Date
- 2025-04-30
- Publication Date
- 2026-09-22
AI Technical Summary
[0004]如上述的电子装置，第二晶体管的控制端接收的最高电压相等于第三晶体管的临界电压的绝对值。
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Figure CN122801910A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to electronic devices, and in particular to common-source cascode amplifiers. Background Technology
[0002] Common cascode amplifiers include normally-off (E-mode) transistors and normally-on (D-mode) transistors. The normally-on transistor is electrically connected between the drive voltage and the normally-off transistor. The normally-off transistor is electrically connected between the normally-on transistor and ground. The gate of the normally-on transistor is electrically connected to ground. The gate of the normally-off transistor receives the control signal. However, when the gate voltage of the normally-off transistor is 0V, the normally-on transistor will repeatedly turn on or off due to voltage oscillations at the source of the normally-off transistor. Summary of the Invention
[0003] An electronic device according to an embodiment of this disclosure includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal, a second terminal, and a control terminal. The second terminal of the first transistor is electrically connected to a ground terminal. The control terminal of the first transistor receives a control signal. The second transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor receives a driving voltage. The second terminal of the second transistor is electrically connected to the first terminal of the first transistor. The third transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor is electrically connected to the control terminal of the first transistor. The second terminal of the third transistor is electrically connected to the control terminal of the second transistor. The control terminal of the third transistor is electrically connected to a ground terminal. The threshold voltage of the first transistor is greater than zero, and the threshold voltages of both the second and third transistors are less than zero.
[0004] In the electronic device described above, the highest voltage received at the control terminal of the second transistor is equal to the absolute value of the threshold voltage of the third transistor.
[0005] In the electronic device described above, the rated voltage of the first transistor is equal to the absolute value of the critical voltage of the second transistor plus the first voltage. The first voltage is between 10V and 15V.
[0006] In the electronic device described above, when the first transistor and the second transistor are turned on simultaneously, the second transistor reduces the on-resistance formed when the first transistor and the second transistor are turned on.
[0007] In the electronic device described above, when the driving voltage is higher than the second voltage, the third transistor suppresses the voltage oscillation at the first terminal of the first transistor.
[0008] In the electronic device described above, the second voltage is equal to 10V.
[0009] In the electronic device described above, the first transistor, the second transistor, and the third transistor are packaged in a chip using semiconductor packaging technology.
[0010] The electronic device described above is a common-source, common-gate amplifier.
[0011] An electronic device according to an embodiment of this disclosure includes a first transistor, a second transistor, and a third transistor. The first transistor includes a first terminal, a second terminal, and a control terminal. The second terminal of the first transistor is electrically connected to a ground terminal. The control terminal of the first transistor receives a control signal. The second transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the second transistor receives a driving voltage. The second terminal of the second transistor is electrically connected to the first terminal of the first transistor. The third transistor includes a first terminal, a second terminal, and a control terminal. The first terminal of the third transistor is electrically connected to a ground terminal. The second terminal of the third transistor is electrically connected to the control terminal of the second transistor. The control terminal of the third transistor is electrically connected to the control terminal of the first transistor. The threshold voltage of the first transistor is greater than zero, and the threshold voltages of the second and third transistors are both less than zero.
[0012] In the electronic device described above, when the control terminal of the first transistor is 0V and the first transistor is off, the third transistor prevents the second transistor from repeatedly turning on or off due to voltage oscillations at the second terminal of the first transistor.
[0013] In the electronic device described above, the first transistor, the second transistor, and the third transistor are packaged in a chip using semiconductor packaging technology.
[0014] The electronic device described above is a common-source, common-gate amplifier. Attached Figure Description
[0015] Figure 1 This is a schematic diagram of an electronic device 100 according to an embodiment of the present disclosure.
[0016] Figure 2 This is a schematic diagram of an electronic device 200 according to an embodiment of the present disclosure.
[0017] Figure 3 This is a schematic diagram of the layout, packaging, and wire bonding of an electronic device 300 according to an embodiment of this disclosure.
[0018] Figure 4 This is a schematic diagram of the layout, packaging, and wire bonding of an electronic device 400 according to an embodiment of the present disclosure.
[0019] [Symbol Explanation]
[0020] 100: Electronic devices
[0021] Q1: First transistor
[0022] Q2: Second transistor
[0023] Q3: Third transistor
[0024] D1: Drain of the first transistor
[0025] D2: Drain of the second transistor
[0026] D3: Drain of the third transistor
[0027] S1: Source of the first transistor
[0028] S2: Source of the second transistor
[0029] S3: Source of the third transistor
[0030] G1: Gate of the first transistor
[0031] G2: Gate of the second transistor
[0032] G3: Gate of the third transistor
[0033] HV: Drive voltage
[0034] RF: Control signal
[0035] GND: Ground terminal
[0036] A, B: Nodes
[0037] 200: Electronic devices
[0038] 300: Electronic devices
[0039] 302, 304, 306: solder pads
[0040] 308: Chip
[0041] 310: Gate drive circuit
[0042] 400: Electronic Devices
[0043] 402, 404, 406: solder pads
[0044] 408: Chip
[0045] 410: Gate drive circuit Detailed Implementation
[0046] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the drawings. Wherever possible, the same component symbols are used in the drawings and description to denote the same or similar parts.
[0047] Throughout this specification and the appended claims, certain terms are used to refer to specific components. Those skilled in the art will understand that electronic device manufacturers may use different names to refer to the same components. This document is not intended to distinguish between components that function identically but have different names. In the following specification and claims, words such as "covering," "containing," and "comprising" are open-ended terms and should therefore be interpreted as "containing but not limited to...".
[0048] The terms “approximately,” “equal to,” “equivalent to,” “same,” “substantially,” or “proximately” are generally interpreted as being within 20% of a given value or range, or as being within 10%, 5%, 3%, 2%, 1%, or 0.5% of a given value or range.
[0049] The ordinal numbers used in the specification and claims, such as "first" and "second," to modify components do not inherently imply any prior ordinal number for that component, nor do they represent the order of one component with another, or the order of manufacturing processes. These ordinal numbers are used solely to clearly distinguish one named component from another with the same name. The claims and specification may not use the same terminology; therefore, a first component in the specification may be a second component in the claims.
[0050] The electrical connections or couplings described in this disclosure can refer to direct connections or indirect connections. In the case of a direct connection, the endpoints of the components on two circuits are directly connected or connected to each other by conductor segments. In the case of an indirect connection, the endpoints of the components on two circuits are connected by a switch, diode, capacitor, inductor, resistor, other suitable components, or combinations of the above components, but are not limited thereto.
[0051] In this disclosure, the thickness, length, and width can be measured using an optical microscope, while the thickness or width can be measured from a cross-sectional image in an electron microscope, but are not limited thereto. Furthermore, any two values or directions used for comparison may have a certain degree of error. Additionally, the terms "equal to," "equivalent to," "identical," "substantially," or "approximately" used in this disclosure generally mean falling within 10% of a given value or range. Moreover, the phrases "given range is from a first value to a second value" and "given range falls within the range of the first value to the second value" indicate that the given range includes the first value, the second value, and other values in between.
[0052] It should be understood that the features described below can be replaced, recombined, or mixed in several different embodiments to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and matched as long as they do not violate the spirit of the disclosure or conflict with it.
[0053] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that such terms, as defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in embodiments of this disclosure.
[0054] Figure 1 This is a schematic diagram of an electronic device 100 according to an embodiment of this disclosure. Figure 1 As shown, the electronic device 100 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3. In some embodiments, the electronic device 100 is a common-source common-gate amplifier used to amplify a control signal RF, and the amplified control signal RF is output from node B. The first transistor Q1 includes a drain D1 and a source S1 connected to a gate G1. The source S1 is electrically connected to ground GND. The gate G1 receives the control signal RF. The second transistor Q2 includes a drain D2 and a source S2 connected to a gate G2. The drain D2 receives a drive voltage HV. The source S2 is electrically connected to the drain D1 of the first transistor Q1.
[0055] The third transistor Q3 includes a drain D3, a source S3, and a gate G3. The drain D3 is electrically connected to the gate G1 of the first transistor Q1. The source S3 is electrically connected to the gate G2 of the first transistor Q1. The gate G3 is electrically connected to ground GND. That is, the gate G3 is also electrically connected to the source S1 of the first transistor Q1. The threshold voltage of the first transistor Q1 is greater than 0. The threshold voltages of the second transistor Q2 and the third transistor Q3 are both less than 0. In other words, the first transistor Q1 is a normally off transistor. The second transistor Q2 and the third transistor Q3 are normally on transistors.
[0056] In some implementations, a normally-off transistor (NOT) is in the off state when no gate voltage is applied, and a sufficiently positive voltage must be applied to turn it on. This sufficiently positive voltage is called the threshold voltage. Conversely, a normally-on transistor (NOT) must be applied with a sufficiently negative voltage to turn it off. In some embodiments, the first transistor Q1 is a low-voltage NOT transistor. The second transistor Q2 and the third transistor Q3 are high-voltage NOT transistors. In some embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all N-type transistors, but this disclosure is not limited thereto.
[0057] In some embodiments, the highest voltage (i.e., its withstand voltage) received by the gate G2 of the second transistor Q2 is equal to the absolute value of the threshold voltage of the third transistor Q3. In some embodiments, the rated voltage of the first transistor Q1 is equal to the absolute value of the threshold voltage of the second transistor Q2 plus a first voltage. The first voltage may be, for example, between 10V and 15V, but this disclosure is not limited thereto.
[0058] In some embodiments, when the first transistor Q1 and the second transistor Q2 are simultaneously turned on, the second transistor Q2 can reduce the on-resistance Ron formed when the first transistor Q1 and the second transistor Q2 are turned on. When the on-resistance Ron is reduced, the drive current flowing from the drive voltage HV through the first transistor Q1 and the second transistor Q2 to the ground terminal GND can be correspondingly increased to increase the power gain of the electronic device 100. For example, compared with the cascode amplifier in the prior art, the electronic device 100 of this disclosure can reduce the on-resistance Ron from 299mΩ to 283mΩ (a reduction of about 5%), thereby increasing the drive current from 16A to 17A (an increase of about 5%).
[0059] In some embodiments, when the drive voltage HV is higher than the second voltage, the third transistor Q3 can suppress voltage oscillations on the drain D1 of the first transistor Q1. That is, the third transistor Q3 can suppress high-voltage oscillations on node B. The second voltage may be, for example, 10V, but this disclosure is not limited thereto. The drive voltage HV is the voltage across node A and ground GND. In some embodiments, voltage oscillations on node B can cause the second transistor Q2 to turn on or off incorrectly. The voltage on node B is the voltage across node B and ground GND. In some embodiments, the high-voltage oscillations on node B are caused by the coupling between parasitic inductance and parasitic capacitance in the path of the second transistor Q2.
[0060] Figure 2 This is a schematic diagram of an electronic device 200 according to an embodiment of the present disclosure. Figure 2As shown, the electronic device 200 includes a first transistor Q1, a second transistor Q2, and a third transistor Q3. In some embodiments, the electronic device 200 is a common-source common-gate amplifier used to amplify a control signal RF, and the amplified control signal RF is output from the source S2 of the second transistor Q2. The first transistor Q1 includes a drain D1 and a source S1 connected to a gate G1. The source S1 is electrically connected to ground GND. The gate G1 receives the control signal RF. The second transistor Q2 includes a drain D2 and a source S2 connected to a gate G2. The drain D2 receives a drive voltage HV. The source S2 is electrically connected to the drain D1 of the first transistor Q1.
[0061] The third transistor Q3 includes a drain D3 and a source S3, connected to a gate G3. The drain D3 is electrically connected to ground GND. That is, the drain D3 is electrically connected to the source S1 of the first transistor Q1. The source S3 is electrically connected to the gate G2 of the second transistor Q2. The gate G3 is electrically connected to the gate G1 of the first transistor Q1. In other words, the gate G3 of the third transistor Q3 is the same as the gate G1 of the first transistor Q1, and it also receives a control signal RF and controls the turning on or off of the third transistor Q3 and the first transistor Q1 respectively according to the control signal RF. The threshold voltage of the first transistor Q1 is greater than 0. The threshold voltages of the second transistor Q2 and the third transistor Q3 are both less than 0.
[0062] In some embodiments, the first transistor Q1 is a normally off transistor. The second transistor Q2 and the third transistor Q3 are normally on transistors. The second transistor Q2 and the third transistor Q3 are high-voltage normally on transistors. In some embodiments, the first transistor Q1, the second transistor Q2, and the third transistor Q3 are all N-type transistors, but this disclosure is not limited thereto.
[0063] In some embodiments, when the first transistor Q1 and the second transistor Q2 are simultaneously turned on, the second transistor Q2 can reduce the on-resistance Ron formed when the first transistor Q1 and the second transistor Q2 are turned on. When the on-resistance Ron is reduced, the drive current flowing from the drive voltage HV through the first transistor Q1 and the second transistor Q2 to the ground terminal GND can be increased accordingly, thereby increasing the power gain of the electronic device 200.
[0064] In some embodiments, when the control terminal of the first transistor is 0V and the first transistor Q1 is off, the third transistor Q3 prevents the second transistor Q2 from repeatedly turning on or off due to voltage oscillations at the source S1 of the first transistor Q1.
[0065] Figure 3 This is a schematic diagram illustrating the layout, packaging, and wire bonding of the electronic device 300 according to an embodiment of this disclosure. Figure 3As shown, the electronic device 300 includes a gate drive circuit 310, solder pads 302, 304, and 306, and a chip 308. In some embodiments, Figure 1 The first transistor Q1, the second transistor Q2, and the third transistor Q3 in the electronic device 100 are packaged in a chip 308 using semiconductor packaging technology. Figure 3 In this embodiment, chip 308 includes eight pins, but this disclosure is not limited thereto. Gate drive circuit 310 is electrically connected to pad 302. Pad 302 is electrically connected to the gate G1 of first transistor Q1 and the drain D3 of third transistor Q3. The gate G1 of first transistor Q1 is electrically connected to pad 302 via a single pin and wire bonding. The drain D3 of third transistor Q3 is electrically connected to pad 302 via a single pin and wire bonding. Pad 302 is used to receive control signal RF.
[0066] Pad 304 is electrically connected to ground (GND). Pad 304 is electrically connected to the source (S1) of the first transistor Q1 via two pins and wire bonding. Pad 306 receives the drive voltage HV. Pad 306 is electrically connected to the drain (D2) of the second transistor via four pins. The drain (D1) of the first transistor Q1 is electrically connected to the source (S2) of the second transistor Q2 via wire bonding. The source (S1) of the first transistor Q1 is electrically connected to the gate (G3) of the third transistor Q3 via wire bonding. The source (S3) of the third transistor Q3 is electrically connected to the gate (S2) of the second transistor Q2 via wire bonding. The gate drive circuit 310 is used to output a control signal RF to the chip 308.
[0067] In some embodiments, when the user does not use the third transistor Q3, the user can disconnect the diagonal portion of the pad 302 from the body of the pad 302, or change the shape of the pad 302 so that the pad 302 is not connected to the drain D3 of the third transistor Q3. In this way, the chip 308 can also be used in the older cascode amplifier architecture.
[0068] Figure 4 This is a schematic diagram illustrating the layout, packaging, and wire bonding of the electronic device 400 according to an embodiment of this disclosure. Figure 4 As shown, the electronic device 400 includes a gate drive circuit 410, solder pads 402, 404, and 406, and a chip 408. In some embodiments, Figure 2 The first transistor Q1, the second transistor Q2, and the third transistor Q3 in the electronic device 200 are packaged in a chip 408 using semiconductor packaging technology. Figure 4 In this embodiment, chip 408 includes eight pins, but this disclosure is not limited thereto. Gate drive circuit 410 is electrically connected to pad 402. Pad 402 is electrically connected to the gate G1 of first transistor Q1 and the gate G3 of third transistor Q3 via a single pin and wire bonding. Pad 402 receives control signal RF.
[0069] Pad 404 is electrically connected to ground (GND). Pad 404 is electrically connected to the drain (D3) of the third transistor Q3 via a single pin and wire bonding. Pad 404 is electrically connected to the source (S1) of the first transistor Q1 via a two-pin connection and wire bonding. Pad 406 receives the drive voltage HV. Pad 406 is electrically connected to the drain (D2) of the second transistor Q2 via four pins and wire bonding. The gate (G2) of the second transistor Q2 is electrically connected to the source (S3) of the third transistor Q3 via wire bonding. The gate drive circuit 410 outputs a control signal RF to chip 408.
[0070] In some embodiments, when the user does not use the third transistor Q3, the user can disconnect the diagonal portion of the pad 404 from the body of the pad 404, or change the shape of the pad 404 so that the pad 404 is not connected to the drain D3 of the third transistor Q3. In this way, the chip 408 can also be used in the older cascode amplifier architecture.
[0071] The electronic devices 100 and 200 of this disclosure maintain the high-voltage withstand capability of the second transistor Q2. By using a common-gate structure to increase the voltage and turn on the second transistor Q2, the on-resistance of the second transistor Q2 can be further reduced, thereby increasing the on-current. The electronic devices 100 and 200 of this disclosure prevent high-voltage interference from the second transistor Q2 through the connection of the third transistor Q3.
[0072] While embodiments of this disclosure are as described above, it should be understood that what is presented above is merely exemplary and not limiting. Many modifications to the exemplary embodiments described above can be made without departing from the spirit and scope of the disclosure. Therefore, the breadth and scope of this disclosure should not be limited by the embodiments described above. Rather, the scope of this disclosure should be defined by the following claims and their equivalents. Although the above disclosure has been illustrated and depicted by one or more related embodiments, equivalent changes and modifications will be conceived by others skilled in the art based on the above specifications and drawings. Furthermore, although particular features of this disclosure have been demonstrated by one of the related embodiments, such features may be combined with one or more other features to meet the needs and facilitate any known or particular application.
[0073] The technical terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be a limitation of this disclosure. Unless the context clearly indicates otherwise, the singular form used herein, as well as the plural form, also includes the plural form. Furthermore, the terms "comprising," "including," "(having)," "equipped with," or variations thereof are used either as a detailed description or as part of the scope of the claims. The foregoing terms mean "comprising" and are, to some extent, equivalent to the term "comprising." Unless otherwise defined, all terms used herein (including technical or scientific terms) are to be understood by one of ordinary skill in the art as described above. It should be further understood that the foregoing terms, as defined in commonly used dictionaries, should be interpreted in the context of the relevant art. Unless expressly defined herein, the foregoing terms are not to be interpreted as idealized or overly formal.
Claims
1. An electronic device comprising: The first transistor includes a first terminal, a second terminal, and a control terminal; wherein the second terminal is electrically connected to the ground terminal, and the control terminal receives a control signal. The second transistor includes a first terminal, a second terminal, and a control terminal; wherein the first terminal receives a driving voltage, and the second terminal is electrically connected to the first terminal of the first transistor. The third transistor includes a first terminal, a second terminal, and a control terminal; wherein the first terminal is electrically connected to the control terminal of the first transistor, the second terminal is electrically connected to the control terminal of the second transistor, and the control terminal is electrically connected to the ground terminal. The first transistor has a threshold voltage greater than zero, while the second and third transistors both have threshold voltages less than zero.
2. The electronic device as claimed in claim 1, wherein, The highest voltage received at the control terminal of the second transistor is equal to the absolute value of the threshold voltage of the third transistor.
3. The electronic device as claimed in claim 1, wherein, The rated voltage of the first transistor is equal to the absolute value of the critical voltage of the second transistor plus the first voltage; the first voltage is between 10V and 15V.
4. The electronic device as claimed in claim 1, wherein, When the first transistor and the second transistor are both turned on, the second transistor reduces the on-resistance formed when the first transistor and the second transistor are turned on.
5. The electronic device as claimed in claim 1, wherein, When the driving voltage is higher than the second voltage, the third transistor suppresses the voltage oscillation at the first terminal of the first transistor.
6. The electronic device as claimed in claim 5, wherein, The second voltage is equal to 10V.
7. The electronic device as claimed in claim 1, wherein, The first transistor, the second transistor, and the third transistor are packaged in a chip using semiconductor packaging technology.
8. The electronic device as claimed in claim 1, wherein, The electronic device is a common-source, common-gate amplifier.
9. An electronic device comprising: The first transistor includes a first terminal, a second terminal, and a control terminal; wherein the second terminal is electrically connected to the ground terminal, and the control terminal receives a control signal. The second transistor includes a first terminal, a second terminal, and a control terminal; wherein the first terminal receives a driving voltage, and the second terminal is electrically connected to the first terminal of the first transistor. The third transistor includes a first terminal, a second terminal, and a control terminal; wherein the first terminal is electrically connected to the ground terminal, the second terminal is electrically connected to the control terminal of the second transistor, and the control terminal is electrically connected to the control terminal of the first transistor. The first transistor has a threshold voltage greater than zero, while the second and third transistors both have threshold voltages less than zero.
10. The electronic device of claim 9, wherein, When the control terminal of the first transistor is 0V and the first transistor is off, the third transistor prevents the second transistor from repeatedly turning on or off due to voltage oscillations at the second terminal of the first transistor.
11. The electronic device as claimed in claim 9, wherein, The first transistor, the second transistor, and the third transistor are packaged in a chip using semiconductor packaging technology.
12. The electronic device as claimed in claim 9, wherein, The electronic device is a common-source, common-gate amplifier.